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You are on page 1of 3

COE-202 – Fundamentals of Computer Engineering

Assignment # 2: Due Sunday January 4th, 2008 – in class.

Problem 1) (20 points) Simplify the following Boolean functions to the form of sum-of-

products by finding all prime implicants and essential prime implicants and applying the

selection rule:

a) F(W,X,Y,Z) = Σm(0,1,2,6,8,9,10,13)

b) F(A,B,C,D) = ΠM(1,3,5,6,7,9,10,11,14)

Problem 2) (20 points) Simplify the following expressions in (1) sum-of-products and

(2) product-of-sums forms. Use the K-map method for the simplification:

a) AC’ + B’D + A’CD + ABCD

b) (A’ + B’ + D) (A’ + D’) (A + B + D’) (A + B’ + C + D)

Problem 3) (30 points) It is required to implement a 4-bit ripple carry adder using

LogiSim:

a) Implement the full adder circuit explained in class and shown in Figure P3a. Make this

as an “FA” circuit added to your project.

b) Add another circuit called “4-bit Ripple Carry Adder”. Use the FA block to construct

the 4-bit carry adder. Test your new circuit with few examples and verify that it is

performing the required function.

Provide screenshots for part (a) and part (b).

Hint: follow the instructions given in class and illustrated in

http://ozark.hendrix.edu/~burch/logisim/docs/2.1.0/guide/subcirc/using.html

Half adder

Ai Bi

Ai Half adder

Bi Si

Ci+1 Ci

FA

Ci

Ci+1 Si

Figure P3a: Full adder circuit. Figure P3b: Full adder block

diagram.

(CLA) using LogiSim:

a) Implement the partial adder circuit explained in class and shown in Figure P4a. Make

this as a “PA” circuit added to your project.

b) Add another circuit called “4-bit Carry Lookahead Adder”. Use the PA block to

construct the 4-bit carry look ahead adder plus the required logic (AND and OR gates) to

HW_2_coe_081_202_02.doc Page 1 of 3

Dr. Ashraf S. Hasan Mahmoud Dec 14th, 2008

generate the required carry signals. The construction procedure is as explained in class

notes, and as shown in Figure P4c. Test your new circuit with few examples and verify

that it is performing the required function.

Provide screenshots for part (a) and part (b).

Ai Si

Ai Bi

Bi

Pi

Gi Ci

Ci Ci

Ci+1 Pi PA

PA: Partial Adder Gi

Si

FA: Full Adder

Figure 4a: Partial adder logic. Figure 4a: Partial adder block.

A3 B3 A2 B2 A1 B1 A0 B0

G3 G2 G1 G0

C4 C3 C2 C1 C0

P3 PA P2 PA P1 PA P0 PA

S3 S2 S1 S0

C1 = G0 + P0C0

C2 = G1 + P1G0 + P1P0C0

C3 = G2 + P2G1+ P2P1G0 + P2P1P0C0

C4 = G3 + P3G2 + P3P2G1+ P3P2P1G0 + P3P2P1P0C0

the subtraction X-Y for the two unsigned numbers, X=X3-X0, and Y=Y3-Y0.

a) (25 points) Design a 1-bit full subtractor. The 1-bit full subtractor performs the

following operation: D = X – bin – Y. Where D is the output, X, bin (borrow in), and Y

are the input. Plot the truth table, and design the required circuit. Using a block diagram

show how it can be used to construct the 4-bit ripple-borrow subtractor.

b) (25 points) Implement the 4-bit ripple-borrow subtractor in LogiSim and verify its

operation. Provide several printouts displaying the required operation with selected

examples of subtracting 4-bit numbers.

Problem 6) (50 points) Design a combinational circuit that receives a 4-bit signed

number in 2’s complement representation and returns the absolute value of the number

i.e., the output returned should be 3-bit. Show all steps of design and implement your

design in LogiSim. Submit several printouts displaying the function of your design.

Problem 7) (20 points) Construction of a 4-to-16 line decoder with enable input using

five 2-to-4 line decoders with enable inputs. Do not use other logic gates.

HW_2_coe_081_202_02.doc Page 2 of 3

Dr. Ashraf S. Hasan Mahmoud Dec 14th, 2008

a) Construct a 15-to-1 line multiplexer with two 8-to-1 line multiplexers. The

corresponding figure depicts the multiplexer block and its functional table. Minimize the

added logic required to have selection codes 0000 through 1110.

b) Use LogiSim to construct an 8-to-1 line multiplexer. Save the block under the name

8x1MUX. Use two of such blocks plus added logic gates to implement the final 15-to-1

line multiplexer using LogiSim. Submit both the designs for the 8-to-1 block and the 15-

to-1 line multiplexer. Highlight on the submitted screen shots the operation of the 15-to-1

multiplexer

15-to-1 8-to-1

S1 line multiplexer S0, S1, S2, and S3 are the four S1 line multiplexer

S2 select lines for the 15-to-1 line S2

S3 multiplexer, and O is the output

line. I0, I1, …, I14 are the 15

I0 O input lines to select from. I0 O

I1 I1

S0 S1 S2 S3 O

0 0 0 0 I0

0 0 0 1 I1

0 0 1 0 I2

I14 0 0 1 1 I3 I7

0 1 0 0 I4

0 1 0 1 I5

0 1 1 0 I6

0 1 1 1 I7

1 0 0 0 I8

1 0 0 1 I9

1 0 1 0 I10

1 0 1 1 I11

1 1 0 0 I12

1 1 0 1 I13

1 1 1 0 I14

Figure P8a: 15-to-1 line Figure P8b: 15-to-1 line Figure P8c: 8-to-1 line

multiplexer block. multiplexer functional table. multiplexer block.

HW_2_coe_081_202_02.doc Page 3 of 3

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