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1.Magnitude comparator

2.How to design a 4-bit comparator

Definition

A magnitude comparator is a combinational circuit that compares two numbers A & B to

determine whether:

A > B, or

A = B, or

A<B

Inputs

First n-bit number A

Second n-bit number B

Outputs

3 output signals (GT, EQ, LT), where:

1. GT = 1 IFF A > B

2. EQ = 1 IFF A = B

3. LT = 1 IFF A < B

Note: Exactly One of these 3 outputs equals 1, while the other 2 outputs are 0`s

Inputs: 8-bits (A ⇒ 4-bits , B ⇒ 4-bits)

A and B are two 4-bit numbers

Let A = A3A2A1A0 , and

Let B = B3B2B1B0

Inputs have 28 (256) possible combinations

Not easy to design using conventional techniques

The circuit possesses certain amount of regularity ⇒ can be designed algorithmically.

Define Xi = (Ai Bi)+ (Ai / Bi /)

Xi = 0 IFF Ai ≠ Bi

Condition for A= B

EQ=1 (i.e., A=B) IFF

1. A3=B3 → (X3 = 1), and

2. A2=B2 → (X2 = 1), and

3. A1=B1 → (X1 = 1), and

4. A0=B0 → (X0 = 1).

If A3 > B3, then A > B (GT=1) irrespective of the relative values of the other bits of A &

B. Consider, for example, A = 1000 and B = 0111 where A > B.

This can be stated as GT=1 if A3 B3/ =1

If A3 = B3 (X3 = 1), we compare the next significant pair of bits (A2 & B2).

If A2 > B2 then A > B (GT=1) irrespective of the relative values of the other bits of A &

B. Consider, for example, A = 0100 and B = 0011 where A > B.

This can be stated as GT=1 if X3A2 B2/ =1

If A3 = B3 (X3 = 1) and A2 = B2 (X2 = 1), we compare the next significant pair of bits (A1

& B1).

If A1 > B1 then A > B (GT=1) irrespective of the relative values of the remaining bits A0

& B0. Consider, for example, A = 0010 and B = 0001 where A > B

This can be stated as GT=1 if X3 X2A1 B1/ =1

If A3 = B3 (X3 = 1) and A2 = B2 (X2 = 1) and A1 = B1 (X1 = 1), we compare the next pair

of bits (A0 & B0).

If A0 > B0 then A > B (GT=1). This can be stated as GT=1 if X3X2X1A0B0/=1

1. A3 B3/ =1, or

2. X3A2 B2/ =1, or

3. X3 X2A1 B1/ = 1, or

4. X3X2X1A0B0/ =1

In other words, GT = A3 B3/ + X3A2 B2/ + X3 X2A1 B1/ + X3X2X1A0B0/

In the same manner as above, we can derive the expression of the LT (A < B) output

LT = B3 A3/ + X3B2 A2/ + X3 X2B1 A1/ + X3X2X1B0A0/

The gate implementation of the three output variables (EQ, GT & LT) is shown in the

figure below.

A3

B3

A2

B2

A1 A<B

B1

A0

A>B

B0

A=B

Modification to the Design

The hardware in the comparator can be reduced by implementing only two outputs, and

the third output can be obtained using these two outputs.

For example, if we have the LT and GT outputs, then the EQ output can be obtained by

using only a NOR gate, as shown in the figure below.

Thus, when both the GT and LT outputs are zeros, then the 3rd one (i.e. EQ) is a ‘1’

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