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DATA SHEET

MOS FIELD EFFECT POWER TRANSISTORS

2SJ494
SWITCHING P-CHANNEL POWER MOS FET INDUSTRIAL USE

PACKAGE DIMENSIONS

DESCRIPTION

(in millimeter)

This product is P-Channel MOS Field Effect Transistor
designed for high current switching applications.

4.5±0.2

10.0±0.3

3.2±0.2

3±0.1
4±0.2

• Super Low On-State Resistance
RDS(on)1 = 50 m: Max. (VGS = –10 V, ID = –10 A)
RDS(on)2 = 88 m: Max. (VGS = –4 V, ID = –10 A)
• Low Ciss

12.0±0.2

FEATURES

13.5 MIN.

15.0±0.3

2.7±0.2

Ciss = 2360 pF Typ.

• Built-in Gate Protection Diode

0.7±0.1
2.54

ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
Drain to Source Voltage

VDSS

Gate to Source Voltage*

VGSS (AC)

Gate to Source Voltage

VGSS (DC)

Drain Current (DC)

ID (DC)

Drain Current (pulse)**

ID (pulse)

1.3±0.2
1.5±0.2
2.54

–60

+20

V

–20, 0

+20

V


+80

A

1. Gate
2. Drain
3. Source

V
A

Total Power Dissipation (TC = 25 °C)

PT

35

W

Total Power Dissipation (TA = 25 °C)

PT

2.0

W

Channel Temperature

Tch

150

°C

Storage Temperature

Tstg

–55 to +150

°C

2.5±0.1
0.65±0.1

1 2 3

ISOLATED TO-220 (MP-45F)

Drain

Body
Diode

Gate

* f = 20 kHz, Duty Cycle d 10% (+Side)
** PW d 10 Ps, Duty Cycle d 1%

Gate Protection
Diode
Source

THERMAL RESISTANCE
Channel to Case

Rth (ch-C)

3.57 °C/W

Channel to Ambient

Rth (ch-A)

62.5 °C/W

The diode connected between the gate and source of the transistor serves as a protector against ESD. When this
device actually used, an additional protection circuit is externally required if a voltage exceeding the rated voltage
may be applied to this device.

Document No. D11266EJ2V0DS00 (2nd edition)
Date Published January 1998 N CP(K)
Printed in Japan

©

1998

0 V Forward Transfer Admittance | yfs | VDS = –10 V.U. ID = –10 A 61 88 m: Gate to Source Cutoff Voltage VGS (off) VDS = –10 V. ID = –10 A 8. VGS = 0 1.5 –2.5 Test Circuit 2 Gate Charge D. 90 % 90 % ID I D Wave Form t t = 1 µs Duty Cycle ≤ 1 % V 0 10 % 10 % td (on) tr ton RL 90 % 0 VDD ID VGS 0 1. 2 TYP. ID = –10 A 39 50 m: RDS(on)2 VGS = –4 V.2SJ494 ELECTRICAL CHARACTERISTICS (TA = 25 °C) CHARACTERISTICS SYMBOL Drain to Source On-state Resistance TEST CONDITIONS MIN.0 Reverse Recovery Time trr IF = 20 A.T.0 –1. RG RG = 10 Ω D.U.0 15 Drain Leakage Current IDSS VDS = –60 V. VDS = 0 +10 PA Input Capacitance Ciss VDS = –10 V 2360 pF Output Capacitance Coss VGS = 0 1060 pF 350 pF f = 1 MHz S Reverse Transfer Capacitance Crss Turn-On Delay Time td(on) ID = –10 A 25 ns tr VGS(on) = –10 V 160 ns 310 ns 240 ns ID = –20 A 74 nC VDD = –48 V 12 nC 16 nC Rise Time Turn-Off Delay Time td(off) Fall Time tf Total Gate Charge QG Gate to Source Charge QGS VDD = –30 V RG = 10 : VGS = –10 V Gate to Drain Charge QGD Body Diode Forward Voltage VF(S-D) IF = 20 A. UNIT RDS(on)1 VGS = –10 V. VGS = 0 –10 PA Gate to Source Leakage Current IGSS VGS = +20 V.T. td (off) tf toff 50 Ω VDD . IG = 2 mA VGS VGS 10 % Wave Form VGS (on) PG. MAX. VGS = 0 130 ns Reverse Recovery Charge Qrr di/dt = 100 A/Ps 290 nC Test Circuit 1 Switching Time RL PG. ID = –1 mA –1.

˚C FORWARD BIAS SAFE OPERATING AREA DRAIN CURRENT vs.˚C TC .1 ite VGS= –10 V –60 –40 VGS = –4 V –20 DC Lim –80 d –1 –10 –100 VDS .V 3 .Total Power Dissipation .2SJ494 DERATING FACTOR OF FORWARD BIAS SAFE OPERATING AREA TOTAL POWER DISSIPATION vs.Case Temperature .V 0 –4 –8 –12 –16 VDS .Drain Current .Percentage of Rated Power .Gate to Source Voltage . CASE TEMPERATURE PT .% 35 100 80 60 40 20 0 20 40 60 80 30 25 20 15 10 5 0 100 120 140 160 20 40 60 80 100 120 140 160 TC .Drain to Source Voltage .A 50 0 s ID(pulse) –100 30 0 1 ID(DC) m s 10 Po –10 s µ d ite ) im )L 0V on =1 ( S S RD t VG (a µ ID .A –100 10 we 0 rD m s m s iss ipa tio n Tc = 25 ˚C Single Pulse –1 –0.Case Temperature .W dT .A –1 000 Pulsed Tch = –25 ˚C 25 ˚C 125 ˚C –100 –10 –1 0 –5 –10 VDS = –10 V –15 VGS .Drain Current . DRAIN TO SOURCE VOLTAGE –1000 Pulsed ID .V FORWARD TRANSFER CHARACTERISTICS ID .Drain Current .Drain to Source Voltage .

Pulse Width .V GATE TO SOURCE CUTOFF VOLTAGE vs.mΩ PW . DRAIN CURRENT RDS(on) .001 10 µ 100 µ 1m 10 m 100 m 1 10 100 1 000 100 10 VDS = –10 V Pulsed Tch = –25 ˚C 25 ˚C 75 ˚C 125 ˚C 1 0. PULSE WIDTH rth(t) .5 0 –50 0 50 100 150 Tch .5 ˚C/W 100 10 Rth(ch-c) = 3.s DRAIN TO SOURCE ON-STATE RESISTANCE vs.V | yfs | .Transient Thermal Resistance .0 –0.57 ˚C/W 1 0.0 –1.1 –0.Drain Current .5 –1.Gate to Source Cutoff Voltage .A DRAIN TO SOURCE ON-STATE RESISTANCE vs.˚C/W 1 000 Rth(ch-a) = 62.01 Single Pulse 0.A 4 –100 VGS(off) .S FORWARD TRANSFER ADMITTANCE vs. GATE TO SOURCE VOLTAGE 150 Pulsed 100 ID = –20 A 50 0 –5 –10 –20 VGS .Gate to Source Voltage .mΩ ID .0 –100 RDS(on) .1 0.˚C .2SJ494 TRANSIENT THERMAL RESISTANCE vs.Drain to Source On-State Resistance . DRAIN CURRENT Pulsed 150 100 VGS = –4 V VGS = –10 V 50 0 –1 –10 ID .Drain to Source On-State Resistance .1 –10 –1.Channel Temperature .Forward Transfer Admittance .Drain Current . CHANNEL TEMPERATURE VDS = –10 V ID = –1 mA –2.

Diode Forward Current .Switching Time .1 –1 –10 –100 td(off) tf 100 tr 10 100 10 –10 IF . td(off).A –100 120 80 VGS = –4 V 40 VGS = –10 V VGS = –4 V –10 VGS = 0 –1 –0. Coss.1 ID = –10 A 0 –50 0 50 100 0 150 CAPACITANCE vs.0 VSD .A –100 VDS .A REVERSE RECOVERY TIME vs.˚C DYNAMIC INPUT/OUTPUT CHARACTERISTICS –80 ID = –20 A –14 VGS –60 –12 –40 –10 VDD = –48 V –24 V –12 V –8 –6 –4 –20 –2 VDS 0 20 40 60 80 0 VGS .0 1 000 td(on).ns –1. CHANNEL TEMPERATURE Pulsed 160 ISD .V 1000 –3.Reverse Recovery Time . DRAIN CURRENT 1 –0.Drain Current . DRAIN TO SOURCE VOLTAGE SWITCHING CHARACTERISTICS VGS = 0 f = 1 MHz Ciss 1 000 Coss Crss 100 10 –0.1 VDS . Crss .mΩ 2SJ494 QG .V Tch .0 –2.V di/dt = 50 A/µ s VGS = 0 –1 VDD = –30 V VGS = –10 V RG = 10 Ω –10 –100 –1 ID .Capacitance .ns Ciss. tf . tr.Gate to Source Voltage .Drain to Source Voltage .Gate Charge .SOURCE TO DRAIN DIODE FORWARD VOLTAGE DRAIN TO SOURCE ON-STATE RESISTANCE vs.nC 5 .V RDS(on) .Channel Temperature .1 td(on) 1 –0.pF 10 000 trr .Diode Current .Drain to Source On-State Resistance .Drain to Source Voltage .Source to Drain Voltage .

NEC semiconductor device reliability/quality control system C11745E Power MOS FET features and application to switching power supply D12971E Application circuits using Power MOS FET TEA-1035 Safe operating area of Power MOS FET TEA-1037 Guide to prevent damage for semiconductor devices by electrostatic discharge (EDS) C11892E .2SJ494 Document Name 6 Document No.

2SJ494 [MEMO] 7 .

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