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Debugger Basics - Training

TRACE32 Online Help


TRACE32 Directory
TRACE32 Index
TRACE32 Training ............................................................................................................................

Debugger Training ........................................................................................................................

Debugger Basics - Training .......................................................................................................

System Concept ......................................................................................................................

On-chip Debug Interface

Debug Features

TRACE32 Tools

On-chip Debug Interface plus On-chip Trace Buffer


On-chip Trace Features

11
11

On-chip Debug Interface plus Trace Port

12

Trace Features

12

TRACE32 Tools

13

NEXUS

15

NEXUS Features

15

TRACE32 Tools (parallel NEXUS port)

16

TRACE32 Tools (serial AURORA NEXUS port)

18

Starting a TRACE32 PowerView Instance .............................................................................


Basic TRACE32 PowerView Parameters

19
19

Configuration File

19

Standard Parameters

20

Examples for Configuration Files

21

Additional Parameters

24

Application Properties (Windows only)

25

Configuration via T32Start (Windows only)

26

About TRACE32

27

Version Information

27

Prepare Full Information for a Support Email

28

Establish your Debug Session ...............................................................................................


Key TRACE32 Set-up Commands

29
29

The PER.view/PER.Set Command

30

The Data.LOAD Command

31

Debug Scenarios

35

Establish the Debug Communication ....................................................................................

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Debugger Basics - Training

37

Debug Scenario 1 ....................................................................................................................


NOR Flash Programming

43
44

The Flash Programming File

44

On-chip Flash Programming

45

Off-chip Flash Programming

48

Configure the TRACE32 OS-Awareness

59

Debug Scenario 2 ....................................................................................................................

60

Typical Boot Sequence

60

Flash Programming (NAND/Serial/eMMC)

65

The Flash Programming File and the Debug Symbol File

65

NAND Flash Programming (non-generic NAND Flash Controller)

66

eMMC Flash Programming

78

Establish the Communication

79

Load the Debug Symbols

79

Debug Scenario 3 ....................................................................................................................

80

Run the Boot Loader

81

Load Application (and/or OS) Code and Debug Symbols

82

Load Debug Symbols only

82

Configure the TRACE32 OS-Awareness

82

Complete Set-up Example

82

Debug Scenario 4 ....................................................................................................................

83

Write a Script to Configure the Target

84

Load Application (and/or OS) Code and Debug Symbols

84

Configure the TRACE32 OS-Awareness

84

Generate a Start-Up Script .....................................................................................................

85

Write a Start-Up Script

85

Run a Start-up Script

86

Automated Start-up Scripts

87

TRACE32 PowerView ..............................................................................................................

88

Overview

89

Main Menu Bar and Accelerators

90

Main Tool Bar

92

Window Area

94

Command Line

97

Command Structure

97

Command Examples

98

The Online Help for a Specific Command

99

Standard Parameter Syntax

100

Message Line

101

Softkeys

102

State Line

103
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Debugger Basics - Training

Registers ..................................................................................................................................
Display the Core Registers

104
104

Colored Display of Changed Registers

105

Modify the Contents of a Core Register

106

Display the Special Function Registers

107

Tree Display

107

Full Display

108

Details about a Single Configuration Register

110

The PER Definition File

111

Modify a Special Function Register

112

Memory Display and Modification .........................................................................................


The Data.dump Window

113
114

Basics

114

Modify the Memory Contents

119

Run-time Memory Access

120

Colored Display of Changed Memory Contents

129

The List Window

130

Displays the Source Listing Around the PC

130

Displays the Source Listing of a Selected Function

131

Breakpoints ..............................................................................................................................
Breakpoint Implementations

133
133

Software Breakpoints in RAM (Program)

133

Software Breakpoints in FLASH (Program)

134

Onchip Breakpoints in NOR Flash (Program)

135

Onchip Breakpoints (Read/Write)

138

ETM Breakpoints (Read/Write) for ARM or Cortex-A/-R

152

Breakpoint Types

155

Program Breakpoints

156

Read/Write Breakpoints

157

Breakpoint Handling ...............................................................................................................

159

Breakpoint Setting at Run-time

159

Real-time Breakpoints vs. Intrusive Breakpoints

160

Break.Set Dialog Box

162

The HLL Check Box

163

Implementations

165

Actions

166

Options

169

DATA Breakpoints

171

Advanced Breakpoints

174

TASK-aware Breakpoints

175

Intrusive TASK-aware Breakpoint

175

Real-time TASK-aware Breakpoint

179

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Counter

180

CONDition

184

CMD

187

memory/register/var

190

Display a List of all Set Breakpoints

195

Delete Breakpoints

196

Enable/Disable Breakpoints

196

Store Breakpoint Settings

197

Debugging ................................................................................................................................
Basic Debug Control

198
198

Sample-based Profiling ..........................................................................................................

201

Introduction

201

Standard Approach

202

Details

205

In-depth Result

205

(other)

206

Document your Results ..........................................................................................................

207

Print your Results

207

Save your Results to a File

209

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Debugger Basics - Training

Debugger Basics - Training


Version June, 11 2013

System Concept
A single-core processor/multi-core chip can provide:

An on-chip debug interface

An on-chip debug interface plus an on-chip trace buffer

An on-chip debug interface plus an off-chip trace port

A NEXUS interface including an on-chip debug interface

Depending on the debug resources different debug features can be provided and different TRACE32 tools
are offered.

1989-2013 Lauterbach GmbH

Debugger Basics - Training

System Concept

On-chip Debug Interface


The TRACE32 debugger allows you to test your embedded hardware and software by using the on-chip
debug interface of the single-core processor/multi-core chip. The most common on-chip debug interface is
JTAG.
A single on-chip debug interface can be used to debug all cores of a multi-core chip.

Debug Features
Depending on the single-core processor/multi-core chip different debug features are available.
Debug features provided by all single-core processors/multi-core chips:

Read/write access to registers

Read/write access to memories

Start/stop of program execution

Debug features specific for each single-core processor/multi-core chip:

Number of on-chip breakpoints

Read/write access to memory while the program execution is running

Additional features as benchmark counters, triggers etc.

1989-2013 Lauterbach GmbH

Debugger Basics - Training

System Concept

TRACE32 Tools
The TRACE32 debugger hardware always consists of:

Universal debugger hardware

Debug cable specific to the processor architecture

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Debugger Basics - Training

System Concept

POWER DEBUG INTERFACE / USB 2

Debug controller with:

304 DMIPS

200 MHz

USB 2.0 as host interfaces

PC

Target

Debug Cable

USB
Cable

PODBUS IN

POWER DEBUG INTERFACE / USB2

POWER

DEBUG CABLE

USB
POWER
7-9 V

LAUTERBACH

SELECT
EMULATE

DEBUG CABLE

TRIG

PODBUS OUT

JTAG
Connector

LAUTERBACH

POWER DEBUG INTERFACE / USB 2

AC/DC Adapter

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Debugger Basics - Training

System Concept

POWER DEBUG / ETHERNET

Debug controller with:

304 DMIPS

200 MHz

100 MBit ethernet or USB 2.x as host interface

Upgradable to a POWER TRACE / ETHERNET

HUB

PC or
Workstation

100 MBit Ethernet

Target

Debug Cable
PODBUS IN

POWER DEBUG / ETHERNET


LAUTERBACH

POWER

COLLISION

DEBUG CABLE

ETHERNET

CON ERR

RECEIVE
POWER
7-9 V

LAUTERBACH

TRIGGER

TRANSMIT

DEBUG CABLE

USB

EMULATE

RESERVED FOR POWER TRACE

SELECT

RECORDING

PODBUS OUT

JTAG
Connector

TRIG

Ethernet
Cable

POWER DEBUG / ETHERNET


AC/DC Adapter

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Debugger Basics - Training

System Concept

POWER DEBUG II

Debug controller with:

1000 DMIPS

500 MHz

1 GBit ethernet or USB 2.0 as host interface

Expandable with POWER TRACE II module

HUB

PC or
Workstation

1 GBit Ethernet

Target
PODBUS SYNC

Debug Cable

POWER DEBUG II

POWER
SELECT

ACTIVITY
ETHERNET
POWER
7-9 V

PODBUS OUT

LAUTERBACH

DEBUG CABLE

DEBUG CABLE

LINK

LAUTERBACH

RUNNING

USB

Ethernet
Cable

PODBUS EXPRESS OUT

JTAG
Connector

TRIG

POWER DEBUG II

AC/DC Adapter

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Debugger Basics - Training

10

System Concept

On-chip Debug Interface plus On-chip Trace Buffer


A number of single-core processors/multi-core chips offer in addition to the on-chip debug interface an onchip trace buffer.

On-chip Trace Features


The on-chip trace buffer can store information:

On the executed instructions.

On task/process switches.

On load/store operations if supported by the trace generation hardware.

In order to analyze and display the trace information the debug cable needs to provide a Trace License. The
name of the Trace License:

<core>-TRACE e.g. ARM-TRACE

or <core>-MCDS) e.g. TriCore-MCDS

The display and the evaluation of the trace information is described in the following documents:

ARM-ETM Training (training_arm_etm.pdf).

Hexagon-ETM Training (training_hexagon_etm.pdf).

Nexus Training (training_nexus.pdf).

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System Concept

On-chip Debug Interface plus Trace Port


A number of single-core processors/multi-core chips offer in addition to the on-chip debug interface a socalled trace port. The most common trace port is the TPIU for the ARM/Cortex architecture.

Trace Features
The trace port exports in real-time trace information:

On the executed instructions.

On task/process switches.

On load/store operations if supported by the trace generation logic.

The display and the evaluation of the trace information is described in the following documents:

ARM-ETM Training (training_arm_etm.pdf)

Hexagon-ETM Training (training_hexagon_etm.pdf)

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System Concept

TRACE32 Tools
For tracing the TRACE32 debugger has to be extended by:

An universal trace hardware

A preprocessor specific to the processor architecture

POWER TRACE / ETHERNET

Trace memory with a depth of 512 MByte.

HUB

PC or
Workstation

100 MBit Ethernet

Target

Debug Cable
PODBUS IN

POWER TRACE / ETHERNET

POWER
TRIG

POWER
7-9 V

COLLISION

PODBUS OUT

LAUTERBACH

JTAG
Connector

ETHERNET

CON ERR

RECEIVE

DEBUG CABLE

TRIGGER

TRANSMIT

LAUTERBACH

LOGIC ANALYZER PROBE

USB

EMULATE
RECORDING

DEBUG CABLE

SELECT

Ethernet
Cable

Trace
Connector

POWER TRACE / ETHERNET

Preprocessor

AC/DC Adapter

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Debugger Basics - Training

13

System Concept

POWER DEBUG II and POWER TRACE II

POWER DEBUG II can be extended by a POWER TRACE II with 1 GByte, 2 GByte or 4 GByte trace
memory.

HUB

PC or
Workstation

1 GBit Ethernet

Target

Debug Cable
PODBUS SYNC

POWER DEBUG II

POWER
TRIG

JTAG
Connector

SELECT

ACTIVITY
ETHERNET

POWER
7-9 V

PODBUS OUT

PODBUS IN

LAUTERBACH

POWER TRACE II

DEBUG CABLE

DEBUG CABLE

LINK

LAUTERBACH

RUNNING

USB

Ethernet
Cable

PODBUS EXPRESS OUT

PODBUS EXPRESS IN

LAUTERBACH
POWER

RECORD
RUNNING

LOGIC ANALYZER PROBE

POWER
7-9V

PREPROCESSOR / NEXUS

SELECT

Trace
Connector

PODBUS OUT

PODBUS EXPRESS OUT

POWER DEBUG II
POWER TRACE II

Preprocessor

AC/DC Adapter

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Debugger Basics - Training

14

System Concept

NEXUS
NEXUS is a standardized interface for on-chip debugging and real-time trace especially for the automotive
industry.

NEXUS Features
Debug features provided by all single-core processors/multi-core chips:

Read/write access to the registers

Read/write access to all memories

Start/stop of program execution

Read/write access to memory while the program execution is running

Debug features specific for single-core processor/multi-core chip:

Number of on-chip breakpoints

Benchmark counters, triggers etc.

Trace features provided by all single-core processors/multi-core chips:

Information on the executed instructions.

Information on task/process switches.

Trace features specific for the single-core processor/multi-core chip:

Information on load/store operations if supported by the trace generation logic.

The display and the evaluation of the trace information is described in Nexus Training
(training_nexus.pdf).

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Debugger Basics - Training

15

System Concept

TRACE32 Tools (parallel NEXUS port)


The TRACE32 hardware consists of:

A universal debugger and trace hardware

A NEXUS adapter specific to the processor architecture

POWER TRACE / ETHERNET for NEXUS

Trace memory with a depth of 512 MByte.

HUB

PC or
Workstation

100 MBit Ethernet

Target
PODBUS IN

POWER TRACE / ETHERNET

NEXUS Adapter

POWER
TRIG

SELECT

DEBUG CABLE

LOGIC ANALYZER PROBE

EMULATE

USB

RECORDING
TRIGGER
ETHERNET

Ethernet
Cable

CON ERR
TRANSMIT
RECEIVE
COLLISION

PODBUS OUT

LAUTERBACH

POWER TRACE / ETHERNET

NEXUS
Connector

POWER
7-9 V

AC/DC Adapter

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Debugger Basics - Training

16

System Concept

POWER DEBUG II and POWER TRACE II for NEXUS

POWER DEBUG II can be extended by a POWER TRACE II for NEXUS with 1 GByte, 2 GByte or 4 GByte
trace memory.

HUB

PC or
Workstation

1 GBit Ethernet

PODBUS SYNC

POWER DEBUG II

POWER
TRIG

SELECT
RUNNING

USB

Target

DEBUG CABLE

LINK
ACTIVITY
ETHERNET

Ethernet
Cable

POWER
7-9 V

PODBUS OUT

PODBUS IN

LAUTERBACH

POWER TRACE II

PODBUS EXPRESS OUT

PODBUS EXPRESS IN

LAUTERBACH
POWER

RECORD
RUNNING

LOGIC ANALYZER PROBE

POWER
7-9V

PREPROCESSOR / NEXUS

SELECT

NEXUS
Connector

NEXUS Adapter

PODBUS OUT

PODBUS EXPRESS OUT

POWER DEBUG II
POWER TRACE II

AC/DC Adapter

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Debugger Basics - Training

17

System Concept

TRACE32 Tools (serial AURORA NEXUS port)


For tracing the TRACE32 debugger has to be extended by:

An universal trace hardware

A serial preprocessor specific to the processor architecture

POWER DEBUG II and POWER TRACE II for NEXUS

POWER DEBUG II can be extended by a POWER TRACE II for NEXUS with 1 GByte, 2 GByte or 4 GByte
trace memory.

HUB

PC or
Workstation

1 GBit Ethernet

Target

Debug Cable
PODBUS SYNC

POWER DEBUG II

POWER
TRIG

ACTIVITY
ETHERNET

POWER
7-9 V

PODBUS OUT

PODBUS IN

LAUTERBACH

POWER TRACE II

DEBUG CABLE

DEBUG CABLE

LINK

LAUTERBACH

RUNNING

USB

Ethernet
Cable

JTAG
Connector

SELECT

PODBUS EXPRESS OUT

PODBUS EXPRESS IN

LAUTERBACH
POWER

LOGIC ANALYZER PROBE

RECORD
RUNNING

PREPROCESSOR / NEXUS

SELECT
POWER
7-9V

Trace
Connector

PODBUS OUT

PODBUS EXPRESS OUT

POWER DEBUG II
POWER TRACE II

Preprocessor

AC/DC Adapter

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Debugger Basics - Training

18

System Concept

Starting a TRACE32 PowerView Instance

Basic TRACE32 PowerView Parameters


This chapter describes the basic parameters required to start a TRACE32 PowerView instance.
The parameters are defined in the configuration file. By default the configuration file is named config.t32. It
is located in the TRACE32 system directory (parameter SYS).

Configuration File
Open the file config.t32 from the system directory ( default c:\T32\config.t32) with any ASCII editor.

The following rules apply to the configuration file:

Parameters are defined paragraph by paragraph.

The first line/headline defines the parameter type.

Each parameter definition ends with an empty line.

If no parameter is defined, the default parameter will be used.

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19

Starting a TRACE32 PowerView Instance

Standard Parameters

Parameter

Syntax

Description

Host interface

PBI=
<host_interface>

Host interface type of TRACE32 tool


hardware (USB or ethernet)

Environment
variables

OS=
ID=<identifier>
TMP=<temp_directory>
SYS=<system_directory>
HELP=<help_directory>

(ID) Prefix for all files which are saved by


the TRACE32 PowerView instance into the
TMP directory
(TMP) Temporary directory used by the
TRACE32 PowerView instance (*)
(SYS) System directory for all TRACE32
files
(HELP) Directory for the TRACE32 help
PDFs (**)

Printer
definition

PRINTER=WINDOWS

All standard Windows printer can be used


from TRACE32 PowerView

License file

LICENSE=<license_directory>

Directory for the TRACE32 license file


(not required for new tools)

(*) In order to display source code information TRACE32 PowerView creates a


copy of all loaded source files and saves them into the TMP directory.
(**) The TRACE32 on-line help is PDF-based.

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Debugger Basics - Training

20

Starting a TRACE32 PowerView Instance

Examples for Configuration Files


Configuration File for USB

Single PowerDebug / PowerTrace connected via USB:


; Host interface
PBI=
USB
; Environment variables
OS=
ID=T32
TMP=C:\temp
SYS=d:\t32\usb
HELP=C:\T32_MPC\pdf
; Printer settings
PRINTER=WINDOWS

; temporary directory for TRACE32


; system directory for TRACE32
; help directory for TRACE32

; all standard windows printer can be


; used from the TRACE32 user interface

Multiple PowerDebug / PowerTrace connected via USB:


; Host interface
PBI=
USB
NODE=training1

; NODE name of TRACE32

; Environment variables
OS=
ID=T32
TMP=C:\temp
SYS=d:\t32\usb
HELP=C:\T32_MPC\pdf

; temporary directory for TRACE32


; system directory for TRACE32
; help directory for TRACE32

; Printer settings
PRINTER=WINDOWS

; all standard windows printer can be


; used from the TRACE32 user interface

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21

Starting a TRACE32 PowerView Instance

Use the IFCONFIG command to assign a NODE name to PowerDebug / PowerTrace.

Enter NODE name

Save NODE name to


PowerDebug / PowerTrace

IFCONFIG

Assign USB NODE name

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22

Starting a TRACE32 PowerView Instance

Configuration File for Ethernet

; Host interface
PBI=
NET
NODE=training1
; Environment variables
OS=
ID=T32
TMP=C:\temp
SYS=d:\t32\eth

; temp directory for TRACE32


; system directory for TRACE32

; Printer settings
PRINTER=WINDOWS

; all standard windows printer can be


; used from the TRACE32 user interface

Ethernet Configuration and Operation Profile

IFCONFIG

Display and change information for the Ethernet interface

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23

Starting a TRACE32 PowerView Instance

Additional Parameters
Changing the font size can be helpful for a more comfortable display of TRACE32 windows.
; Screen settings
SCREEN=
FONT=SMALL

; Use small fonts

Display with normal font:


:

Display with small font:

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Debugger Basics - Training

24

Starting a TRACE32 PowerView Instance

Application Properties (Windows only)


The properties window allows you to configure some basic settings for the TRACE32 software.

Configuration File
Working Directory
Window Size

Definition of the Configuration File


By default the configuration file config.t32 in the TRACE32 system directory (parameter SYS) is used. The
option -c allows you to define your own location and name for the configuration file.
C:\T32_ARM\bin\windows\t32marm.exe -c j:\and\config.t32

Definition of a Working Directory


After its start TRACE32 PowerView is using the specified working directory. It is recommended not to work in
the system directory.
PWD

TRACE32 command to display the current working directory

Definition of the Window Size for TRACE32 PowerView


You can choose between Normal window, Minimized and Maximized.

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Debugger Basics - Training

25

Starting a TRACE32 PowerView Instance

Configuration via T32Start (Windows only)


The basic parameters can also be set-up in an intuitive way via T32Start.
A detailed online help for t32start.exe is available via the Help button or in T32Start (app_t32start.pdf).

Parameters

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Debugger Basics - Training

26

Starting a TRACE32 PowerView Instance

About TRACE32
If you want to contact your local Lauterbach support, it might be helpful to provide some basis information
about your TRACE32 tool.

Version Information

The VERSION window informs you about:


1.

The version of the TRACE32 software

2.

The debug licenses programmed into the debug cable and the expiration date of your software
guarantee respectively the expiration date of your software maintenance.

3.

The serial number of the debug cable.

VERSION.view

Display the VERSION window.

VERSION.HARDWARE

Display more details about the TRACE32 hardware modules.

VERSION.SOFTWARE

Display more details about the TRACE32 software.

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Debugger Basics - Training

27

Starting a TRACE32 PowerView Instance

Prepare Full Information for a Support Email


Be sure to include detailed system information about your TRACE32 configuration.
1.

To generate a system information report, choose Help > Support > Systeminfo.

2.

Preferred: click Save to File, and send the system information as an attachment to your e-mail.

3.

Click Save to Clipboard, and then paste the system information into your e-mail.

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28

Starting a TRACE32 PowerView Instance

Establish your Debug Session


Before you can start debugging, the debug environment has to be set-up. The necessary set-up depends
crucially on the debug scenario.

Key TRACE32 Set-up Commands

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Debugger Basics - Training

29

Establish your Debug Session

The PER.view/PER.Set Command


A debug set-up requires various configurations in core/chip related configuration registers.
The main commands to perform these changes are:

PER.Set.simple <address>|<range> [<%format>] <string>

Modify configuration register/onchip peripheral

Data.Set <address>|<range> [<%format>] <string>

Modify memory-mapped
configuration register/on-chip
peripheral

The main command to inspect the changes is:

PER.view <filename> [<tree-search-item>] /SpotLight

Display the configuration registers/onchip peripherals, highlight changes

Example: Disable Watchdog


; Display Watchdog Timer configuration registers, highlight changes
; a comma is used instead of the <filename>
PER.view , "Watchdog Timer" /SpotLight

; Disable Watchdog timer by configuring Watchdog Timer Control Register


; (WTCON)
PER.Set.simple 0x53000000 %Long 0x0

A in-depth introduction to the PER command group is given on page 104.

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30

Establish your Debug Session

The Data.LOAD Command


A debug set-up requires to load the code to be debugged and to load the debug symbols. TRACE32
PowerView supports a wide range of compilers and compiler output formats.
To get a list of all compilers supported for your core proceed as follows:
1.

Open the Processor Architecture Manual for your core.

2.

Refer to the compiler list provided by this manual. The Option column lists the supported output
formats.

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31

Establish your Debug Session

The most important commands to load the code to be debugged and the debug symbols are:

Data.LOAD.<subcommand> <file> </option>

Load code and debug symbols

Data.LOAD.Binary <file> </option>

Load only code

Data.LOAD.<subcommand> <file> /NoCODE </option>

Load only debug symbols

Data.LOAD.Elf arm-flash.elf

; Load code and debug symbols from


; ELF file

Data.LOAD.AIF demo.axf

; Load code and debug symbols from


; AIF file

Data.LOAD.Elf *

; Load code and debug symbols from


; ELF file
; open file browser to select file

Data.LOAD.Elf arm.elf /NoCODE

; Load debug symbols from ELF file

Data.LOAD.Binary my_app.bin

; Load code from binary file

A in-depth introduction to the Data.LOAD command is given in the chapter Load the Application Program
in training_hll.pdf.

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32

Establish your Debug Session

The TASK.CONFIG Command


Today most applications use an operating system. TRACE32 PowerView includes a configurable target-OS
debugger to provide symbolic debugging of operating systems.
Lauterbach provides ready-to-run configuration files for most common available OSes.
To get the appropriate information on your OS, proceed as follows:
1.

Open the on-line help and deactivate the help filter.

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33

Establish your Debug Session

2.

Open the TRACE32 manual for your operating system (RTOS Debugger).

If your OS is compiled with symbol and debug information, the adaptation to your OS can be activated in
most cases as follows:
TASK.CONFIG <file>

Configures the OS debugger using a configuration file provided by


Lauterbach

MENU.ReProgram <file>

Program a ready-to-run OS menu

HELP.FILTER.Add <filter>

Add the help information for the OS debugger

All necessary files can be found on the TRACE32 software DVD under:

\demo\<architecture>\kernel\<OS>

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Debugger Basics - Training

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Establish your Debug Session

Debug Scenarios
The necessary set-up for your debug session depends crucially on the debug scenario. The graphic below
shows you that there are mainly four debug scenarios.

Establish the communication between


the debugger and core(s)

YES

YES

Is the software
running out of
NOR flash?

Debug
Scenario 1

Is the software
running out of flash?

NO

NO

Debug
Scenario 2

YES

Debug
Scenario 3

Is a boot loader
available?

NO

Debug
Scenario 4

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35

Establish your Debug Session

After the communication between the debugger and the core(s) is established, there a four debug
scenarios. Each debug scenario requires a different set-up.

Debug Scenario 1
The boot loader or the application (and/or the operating system) under debug is running out of
NOR flash.

Debug Scenario 2
The boot loader under debug is running out of a flash e.g. a NAND or serial flash.

Debug Scenario 3
The application (and/or the operating system) under debug are running out of RAM and a readyto-run boot loader configures the target system and especially the RAM for this debug scenario.

Debug Scenario 4
The application (and/or the operating system) under debug are running out of RAM. The target
configuration, especially the RAM configuration has to be done by TRACE32 commands,
because there is no ready-to-run boot loader.

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Establish your Debug Session

Establish the Debug Communication

1. Select the core

2. Adjust the JTAG clock if required

3. Set the required options for your


core

4. Establish the communication

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Establish the Debug Communication

1.

Select the target core/chip

Inform the debugger about the core/chip on your target, if an automatic detection of the core/chip is
not possible. Wild card symbols * or ? are allowed.

SYStem.DETECT CPU

Auto detection of CPU

SYStem.CPU <cpu>

Select the CPU/chip

SYStem.CPU CortexR5

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Establish the Debug Communication

2.

Adjust the JTAG clock


The debugger uses a default JTAG clock of 10 MHz. Adjusting the JTAG clock might be necessary:
-

if a fixed relation between the core clock and the JTAG clock is specified. E.g. for the Power
1
4

Architecture MPC55xx: JTAGclock --- coreclock


-

if RTCK has to be used as JTAG clock for an ARM core.

SYStem.JtagClock <frequency>

Select the JTAG clock

SYStem.JtagClock 1.MHz
SYStem.JtagClock 100.kHz
SYStem.JtagClock RTCK

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Establish the Debug Communication

3.

Set the required options for your core/chip


Some cores/chips require additional settings before the communication can be established.

Additional settings

For details refer to the Processor Architecture Manual.

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Establish the Debug Communication

4.

Establish the communication


The most common way to establish the communication between the debugger and the core is Up.

If Up is selected, the following steps are performed:


-

Reset of the core

Initialization of the communication between the debugger and the core

Stop of the core at the reset vector

SYStem.Up

Establish the communication between the debugger and the


core(s)

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Establish the Debug Communication

A second useful way to establish the communication between the debugger and the core/chip is
Attach. Attach allows to connect the debugger to an already running core/chip.

If Attach is selected, the following step is performed:


1. Initialization of the communication between the debugger and the core.
No target reset is executed.

SYStem.Mode Attach

Establish the communication between the debugger and the


target core/chip (without reset)

SYStem.Mode Attach
Break

; stop the program execution

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Establish the Debug Communication

Debug Scenario 1
The boot loader or the application (and/or the operating system) under debug is running out of NOR flash.

Establish the debug communication

Program the software to NOR flash


(this includes the loading of the debug
symbols)

YES

Is an OS used?

NO

Configure the TRACE32


OS-awareness for your OS

* Ready for debug

*Considering the circumstance that a process has to be started manually e.g. via a TERMinal window

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Debug Scenario 1

NOR Flash Programming


The debugger supports the programming of on-chip and off-chip NOR flash devices.

NOTE:

Flash programming requires that data cache is disabled for the address range
covered by the FLASH device.

The Flash Programming File


On-chip and off-chip NOR flash programming allows to load any output file generated by your compiler.

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Debug Scenario 1

On-chip Flash Programming


Ready to run scripts for most on-chip flashs can be found on the TRACE32 software DVD under:

\demo\<architecture>\flash\<CPU>.cmm
e.g. \demo\arm\flash\at91sam7s.cmm
e.g. \demo\powerpc\flash\jpc564xl.cmm

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Debug Scenario 1

To program the software to the on-chip flash of your processor/chip proceed as follows:
1.

Start the script appropriate for your processor/chip.

2.

TRACE32 PowerView informs you when all preparations are done. Please confirm that you are
ready to choose the boot loader or the application to be programmed.

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Debug Scenario 1

3.

Please select the boot loader or application to be programmed.

TRACE32 PowerView informs you, that the programming is done.

If the boot loader/application is compiled with debug symbols they are automatically loaded into TRACE32
PowerView with the flash programming.

For details on the on-chip flash programming open the flash programming script.
; ~~ represents the TRACE32 installation directory
PEDIT ~~\demo\powerpc\flash\jpc564xl.cmm

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Debug Scenario 1

Off-chip Flash Programming


TRACE32 PowerView provides two methods to program off-chip flash:
1.

Tool-based programming
Tool-based programming means that the flash programming algorithm is part of the TRACE32
software. Tool-based programming is easy to configure but slow.

2.

Target-controlled programming
Target-controlled flash programming means that the underlying flash programming algorithm is
detached from the TRACE32 software. Target-controlled flash programming works as follows:
1. The flash algorithm is downloaded to the target RAM.
2. The programming data are downloaded to the target RAM.
3. The flash algorithm running in the target RAM programs the data to the flash devices.
Target-controlled flash programming minimizes the communication between the host and the
debugger hardware. This makes target-controlled flash programming fast.

NOTE:

It is recommended to start with tool-based flash programming. If this works properly


you can switch to target-controlled flash programming.

Programming off-chip NOR flash requires the following steps (see next page):

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Debug Scenario 1

Establish the debug communication

NO

Is the watchdog
disabled?

YES

Disable watchdog

NO

Is the data cache


disabled?

YES

Disable data caches

Make sure that the core has write


access to the flash

NO

Do you want to use targetcontrolled programming?

NO

YES

Has the core


access to RAM?

YES

Enable RAM access

Program flash

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Debug Scenario 1

1.

Disable Internal and External Watchdog

Example
; Display Watchdog Timer configuration registers, highlight changes
PER.view , "Watchdog Timer" /SpotLight

; Disable Watchdog timer by configuring Watchdog Timer Control Register


; (WTCON)
PER.Set.simple 0x53000000 %Long 0x0

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Debug Scenario 1

2.

Disable Data Cache

The data cache has to be disabled for the address ranges of all flash devices to enable TRACE32
PowerView to read the flash status information.
Example
; Display the memory management configuration registers
; highlight changes
PER.view , "Core Registers,Memory Management Unit" /SpotLight

; Disable Data Cache by configuring the control register SCTLR


PER.Set.simple C15:0x1 %LONG 0x550078

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Debug Scenario 1

3.

Make sure that the core has write access to the flash

NOR flash programming requires that the core has write access to the flash device(s).
The following settings in the bus configuration have to be done for each NOR flash device:

Definition of the base address of the NOR flash device

Definition of the size of the NOR flash device

Definition of the bus size that is used to access the NOR flash device

The write access has to be enabled for the NOR flash device

Definition of the timing (number of wait states for the write access to the NOR flash device)

Use the PER.view command to check the settings in the bus configuration registers.

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Debug Scenario 1

Example for ColdFire


Bus configuration after reset:

In order to have write access to the used off-chip NOR flash device the Address Region 0 has to be
configured for the following characteristics:

Base address 0xa0000000

Size 16 MByte

Bus size 16 bit

PER.Set <address> %<format> <value>


Data.Set <address> %<format> <value>

PER.view , /SpotLight

; Highlight all changed


; configuration registers

PER.Set 0xf0000080 %Long 0xA0000031

; ADDSEL0

PER.Set 0xf00000c0 %Long 0x00508637

; BUSCON0

Correct bus configuration for NOR flash programming.

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Debug Scenario 1

Framework for Tool-based Flash Programming

FLASH.RESet

Reset the FLASH declaration table

FLASH.CFI <start_address> <data_bus_width>

Generate a FLASH declaration by evaluating the


Common Flash Interface description inside the
FLASH device.
The command FLASH.CFI requires the definition
of

the <start_address> of the FLASH device

the <data_bus_width> that is used by the


core to access the FLASH device

FLASH.List

List the FLASH declaration table

FLASH.UNLOCK ALL

Unlock the FLASH sectors

FLASH.ReProgram ALL | OFF

Enable/disable the FLASH programming

Data.LOAD.<subcommand> <file> </option>

Load code and debug symbols

More details on the concepts of the TRACE32 NOR flash programming can be found in NOR FLASH
Programming Users Guide (norflash.pdf).
If your FLASH device doesnt provide CFI please refer to NOR FLASH Programming Users Guide
(norflash.pdf) for details on the FLASH programming procedure.

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Debug Scenario 1

Example
FLASH.RESet

; Reset the FLASH declaration table

FLASH.CFI 0xa0000000 Word

; Generate a FLASH declaration via


; CFI

FLASH.List

; Display the FLASH declaration


; table

FLASH.UNLOCK ALL

;
;
;
;

FLASH.ReProgram ALL

; Enable the FLASH for programming

Data.LOAD.Elf demo.elf

; Specify the file that contains


; the code and the debug symbols

FLASH.ReProgram OFF

; Program FLASH and disable


; the FLASH programming afterwards

Data.LOAD.Elf demo.elf /DIFF

; Verify the FLASH programming

Unlock the FLASH device if


required
e.g. some FLASH devices are
locked after power on

IF FOUND()
PRINT "Verify error after FLASH programming"
ELSE
PRINT "FLASH programming completed successfully"

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Debug Scenario 1

Framework for Target-controlled Flash Programming

FLASH.RESet

Reset the FLASH declaration table

FLASH.CFI <start_address> <bus_width> /TARGET <code_range> <data_range>


Generate a FLASH declaration by evaluating the
Common Flash Interface description inside the
FLASH device.
The command FLASH.CFI requires the definition
of

the <start_address> of the FLASH device

the <data_bus_width> that is used by the


core to access the FLASH device

the target RAM location <code_range> for


the flash programming algorithm

the target RAM location <data_range> for


the flash programming data
FLASH.List

List the FLASH declaration table

FLASH.UNLOCK ALL

Unlock the FLASH sectors

FLASH.ReProgram ALL | OFF

Enable/disable the FLASH programming

Data.LOAD.<subcommand> <file> </option>

Load code and debug symbols

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Debug Scenario 1

Details on <code_range>
Required size for the code is size_of(file) + 32 byte
Flash programming algorithm

Memory mapping for the <code_range>

32 byte
Details on <data_range>
The parameter <data_range> specifies the RAM location for the data, especially

the <data_buffer_size> for the programming data. Recommended buffer size is 4 KByte, smaller
buffer sizes are also possible. The max. buffer size is 16 KByte

the argument buffer for the communication between TRACE32 PowerView and the programming
algorithm

the stack

<data_buffer_size> =
size_of(<data_range>) - 64 byte argument buffer - 256 byte stack
64 byte argument buffer

Memory mapping for the <data_range>

Data buffer for data transfer


between TRACE32 and
flash programming algorithm
<buffer_size> calculated as
described above
256 byte stack

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Debug Scenario 1

4.

Enable RAM Access

Target-controlled Flash Programming requires, that the core has access to the RAM locations specified for
<code_range> and <data_range>.
If this is not the case the following settings in the bus configuration have to be done for an off-chip RAM:

Definition of the base address of the RAM

Definition of the size of the RAM

Definition of the bus size that is used to access the RAM

Definition of the timing (number of wait states for the RAM access)

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Debug Scenario 1

Example
; reset the FLASH declaration table
FLASH.RESet
; set-up the FLASH declaration for target-controlled programming
; target RAM at address 0x20000000
FLASH.CFI 0x0 Word /TARGET 0x20000000++0xfff 0x20001000++0xfff
; display FLASH declaration table
FLASH.List
; unlock the FLASH device if required for a power-up locked device
; FLASH.UNLOCK ALL
; enable the programming for all declared FLASH devices
FLASH.ReProgram ALL
; specify the file that contains the code and the debug symbols
Data.LOAD.Elf demo.elf
; program the file and disable the FLASH programming afterwards
FLASH.ReProgram OFF
; verify the FLASH contents
Data.LOAD.Elf demo.elf /DIFF
IF FOUND()
PRINT "Verify error after FLASH programming"
ELSE
PRINT "FLASH programming completed successfully"
...

Configure the TRACE32 OS-Awareness


Refer to page 33 for details.

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Debug Scenario 1

Debug Scenario 2
The boot loader under debug is running out of a flash e.g. a NAND flash.
In contrast to NOR flash, code can not be executed out of NAND or serial flash. The code has always to be
copied to RAM before it can be executed.

Typical Boot Sequence


Before the set-up for debug scenario 2 is described, it might be useful to have a look at a typical boot
sequence. If the boot loader is running out of flash the system start-up might include the following steps:

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Debug Scenario 2

1.

Reset
At RESET the boot loader is copied from the flash to an on-chip SRAM, which is mapped to the reset
vector. The boot loader starts afterwards.
Please be aware, that some core(s) require a correct ECC for this copy procedure.

Chip

Boot loader (max. 4 kByte)

0x0

On-chip SRAM
SDRAM

Copied by hardware
at RESET

Boot loader (max. 4 kByte)


boot.bin
Second stage boot loader

Kernel image
(compressed)

kernel.bin

Flash

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Debug Scenario 2

2.

Boot loader is running


The main task of the boot loader is to initialize the SDRAM and to copy the second stage boot loader
to SDRAM. When this is done the control is passed to the second stage boot loader.

Second stage boot loader

Chip

Boot loader (max. 4 kByte)


On-chip SRAM
SDRAM

Boot loader (max. 4 kByte)


boot.bin
Second stage boot loader

kernel.bin

Copied by boot loader


to SDRAM

Kernel image
(compressed)

Flash

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Debug Scenario 2

3.

Second stage boot loader is running


The main task of the second stage boot loader is to copy the kernel image to SDRAM. When this is
done the control is passed to the kernel.

Second stage boot loader

Chip

Kernel image
Boot loader (max. 4 kByte)
On-chip SRAM
SDRAM

Boot loader (max. 4 kByte)


boot.bin
Second stage boot loader

kernel.bin

Kernel image
(compressed)

Copied by second stage


boot loader to SDRAM

Flash

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Debug Scenario 2

Set-up for Debug Scenario 2

NO

Is the boot loader


already in the
flash?

YES

Program boot loader


code to flash

Establish the debug communication

Load the debug symbols for the boot


loader into TRACE32 PowerView

Ready for debug

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Debug Scenario 2

Flash Programming (NAND/Serial/eMMC)

NOTE:

Flash programming requires that data cache and MMU is disabled.

The Flash Programming File and the Debug Symbol File


Flash programming can only program binary files. Therefore two output files have to be generated by the
compiler:

A binary file (e.g. boot.bin)

A file containing the debug symbols (e.g. boot.elf)

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Debug Scenario 2

NAND Flash Programming (non-generic NAND Flash Controller)


Ready-to-run flash programming scripts for most processors/chips can be found on the TRACE32 software
DVD under

/demo/<architecture>/flash
Name scheme:
/demo/<architecture>/flash/<cpu_name>-<nand_flash_code>.cmm

Get <cpu_name> from the CPU column of the list of Supported NAND/Serial Flash Controller on the
Lauterbach home page (www.lauterbach.com) if the CONTROLLER column does not indicate generic.

If the CONTROLLER column indicates generic refer to page 69.

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Debug Scenario 2

Get <nand_flash_code> from the CODE column of the list of Supported Flash Devices on the
Lauterbach home page (www.lauterbach.com).

Name of flash programming script here \demo\arm\flash\imx31-nand2g08.cmm

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Debug Scenario 2

To program the code to flash proceed as follows:


1.

Start the script appropriate for your processor/chip and appropriate for your flash device.

2.

TRACE32 PowerView informs you when all preparations are done. Please confirm that you are
ready to choose the boot loader binary to be programmed.

3.

Please select the boot loader to be programmed.

Detail on NAND flash programming can be found in NAND FLASH Programming Users Guide
(nandflash.pdf).

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Debug Scenario 2

NAND Flash Programming (generic NAND Flash Controller)


The CONTROLLER column of the list of Supported NAND/Serial Flash Controller on the Lauterbach
home page (www.lauterbach.com) indicates generic, if a processor/chip has a generic NAND flash
controller.

Programming script for generic NAND flash controller have to be written by the user.

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Debug Scenario 2

Programming a flash device with the help of a generic NAND flash controller requires the following steps:

Establish the debug communication

Prepare flash controller and flash for


programming

NO

Has the core


access to RAM?

YES

Enable RAM access

NO

Is the watchdog
disabled?

YES

Disable watchdog

Program flash

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Debug Scenario 2

1.

Prepare the NAND FLASH Controller and the NAND FLASH for Programming

Programming a flash device requires a proper initialization of the flash controller and the bus interface. The
following settings might be necessary:

Power-up the flash clock domain.

Enable the flash controller or bus.

Configure the communication signals (clock, timing, etc.).

Inform the flash controller about the flash device (large/small page, ECC, spare, etc.).

Configure the flash pins if they are muxed with other functions of the processor/chip.

Disable the write protection for the flash.

Use the PER.Set/PER.view commands for this set-up.

Example for s3c2410X (ARM920T):


PER.view , "NAND Flash Controller" /SpotLight

; enable and configure NAND flash controller


PER.Set 0x4E000000 %Long 0xE030

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Debug Scenario 2

2.

Enable RAM Access

TRACE32 PowerView runs the flash programming algorithm in target RAM. It requires at least 16 KByte of
RAM for this purpose.
This requires that the core has access to target RAM.
If the core has no access to target RAM, the access to target RAM has to be set-up.
Correct settings in the bus configuration registers are key for the RAM access. The following settings in the
bus configuration have to be done:

Definition of the RAM base address

Definition of the RAM size

Definition of the bus size that is used to access the RAM

The write access has to be enabled for the RAM

Definition of the timing (number of wait states for the write access to the RAM)

Use the PER.Set/PER.view commands for this set-up.

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Debug Scenario 2

Example SDRAM configuration on an s3c2410X (ARM920T):


Bus configuration after reset:

Per.Set 0x48000000 %Long 0x2222D222


Per.Set 0x48000004 %Long 0x00000700
Per.Set 0x48000008 %Long 0x00007ff0
Per.Set 0x4800000C %Long 0x00000700
Per.Set 0x48000010 %Long 0x00001F4C
Per.Set 0x48000014 %Long 0x00000700
Per.Set 0x48000018 %Long 0x00000700
Per.Set 0x4800001C %Long 0x00018005
Per.Set 0x48000020 %Long 0x00018005
Per.Set 0x48000024 %Long 0x008e0459
Per.Set 0x48000028 %Long 0x00000032
Per..Set 0x4800002C %Long 0x00000030
Per..Set 0x48000030 %Long 0x00000030
Per..Set 0x53000030 %Long 0x00000000

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Debug Scenario 2

Correct bus configuration for SDRAM usage:

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Debug Scenario 2

3.

Disable internal and external watchdog

Example (ARM920T):
; Display Watchdog Timer configuration registers, highlight changes
PER.view , "Watchdog Timer" /SpotLight

; Disable Watchdog timer by configuring Watchdog Timer Control Register


; (WTCON)
PER.Set.simple 0x53000000 %Long 0x0

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Debug Scenario 2

Generic NAND Flash Programming Framework

The following commands are useful, if a generic NAND flash controller is used to program a flash. For details
refer to NAND FLASH Programming Users Guide (nandflash.pdf).

FLASHFILE.RESet

Reset NAND flash programming to


default.

FLASHFILE.CONFIG <cmd_reg> <addr_reg> <io_reg>

Inform TRACE32 PowerView on the


NAND flash registers

FLASHFILE.TARGET <code_range> <data_range> <file>

Inform TRACE32 PowerView on all


details about flash programming
algorithm.

FLASHFILE.Erase <range>

Erase NAND flash.

FLASHFILE.LOAD <file> <address>

Program binary file to NAND flash.

More details on the FLASHFILE.TARGET command:


The name of the flash programming algorithm depends on the NAND flash to be programmed (e.g.
nand5608.bin for the K9F5608 NAND flash from Samsung).

Its location on the TRACE32 software DVD is defined by the number of data I/O pins between the NAND
flash controller and the flash device. E.g. is there are 8 data I/O pins between the NAND flash controller and
the flash device the algorithm can be found under:
/demo/<architecture>/flash/byte/<nand_flash_code>.bin

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Debug Scenario 2

This flash programming algorithm is downloaded to a target RAM when flash programming is performed.
Therefore TRACE32 PowerView needs to be informed about an appropriate RAM location by the
<code_range> parameter of the FLASH.TARGET program
required size for the code is size_of(file) + 32 byte
FLASH algorithm

Memory mapping for the <code_range>

32 byte
The parameter <data_range> specifies the RAM location for the data, especially

the <data_buffer_size> for the programming data. Recommended buffer size is 4 KByte, smaller
buffer sizes are also possible. The max. buffer size is 16 KByte

the argument buffer for the communication between TRACE32 PowerView and the programming
algorithm

the stack

<data_buffer_size> =
size_of(<data_range>) - 64 byte argument buffer - 256 byte stack
64 byte argument buffer

Memory mapping for the <data_range>

Data buffer for data transfer


between TRACE32 and
NAND FLASH algorithm
<buffer_size> calculated as
described above
256 byte stack

Example
FLASHFILE.RESet
FLASHFILE.CONFIG 0x4E000004 0x4E000008 0x4E00000C
FLASHFILE.TARGET 0x30000000++0x1FFF 0x30002000++0x3FFF
~~\demo\arm\flash\byte\nand5608.bin
FLASHFILE.Erase 0x0--0x1FFFF
FLASHFILE.LOAD boot.bin 0x0

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Debug Scenario 2

eMMC Flash Programming


Name scheme:
/demo/<architecture>/flash/<cpu_name>-emmc.cmm

Get <cpu_name> from the CPU column of the list of Supported NAND/Serial Flash Controller on the
Lauterbach home page (www.lauterbach.com).

Name of flash programming script here


/demo/arm/flash/pxa920-emmc.cmm
Detail on eMMC flash programming can be found in eMMC FLASH Programming Users Guide
(emmcflash.pdf).

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Debug Scenario 2

Establish the Communication


It is required to establish the communication between the debugger and the core by SYStem.Up. This
advise the processor/chip to reset before the communication is established (details can be found on page 1).

Load the Debug Symbols


; load debug symbols for boot loader and second stage boot loader
; address of boot loader:
0x0--0x3fff
; address of second stage boot loader:
0x33f80000++0x3ffff
; symbol mapping has to be accordingly
Data.LOAD.Elf boot.elf /NOCODE

If you want to debug only the second stage boot loader you can set an on-chip breakpoint to its start
address:
Break.Set start_boot2 /Onchip

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Debug Scenario 2

Debug Scenario 3
The application (and/or the operating system) under debug are running out of RAM and a ready-to-run boot
loader configures the target system and especially the RAM for this debug scenario.

Establish the debug communication

Run the boot loader until the target


configuration is done

YES

Does the boot loader


load the application
(and/or the OS)
to RAM?

Load application (and/or OS)


code to RAM
(this includes the loading of
the debug symbols)

Load debug symbols


for application (and/or OS)

YES

NO

Is an OS used?

NO

Configure the TRACE32


OS-awareness for your OS

* Ready for debug

*Considering the circumstance that a process has to be started manually e.g. via a TERMinal window
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Debug Scenario 3

Run the Boot Loader


The most important command to run the boot loader are:

Go

Start program execution

Break

Stop program execution

WAIT <time>

Wait the defined time (for scripts only)

Go <address>

Run the program until the specified address is reached

Break.Set <address>

Set a breakpoint to the specified address

Example 1
Go

; start the program execution

Break

; stop the program execution after


; the target initialization is done

Example 2

; script example

Go

; start the program execution

WAIT 0.5s

; wait 500. ms

Break

; stop the program execution

; continue with other set-ups

Example 3
Go 0xc0001000

; run the program until the


; complete set-up is done

Example 4
Break.Set 0xc0001000

; set a breakpoint to the end


; of the boot loader

Go

; start the program execution

WAIT !STATE.RUN()

; wait until the program stops


; at the end of the boot loader

; continue with other set-ups


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Debug Scenario 3

Load Application (and/or OS) Code and Debug Symbols


If the boot loader does not load the application (and/or OS) you can perform the loading by the following
command:
Data.LOAD.Elf my_app.elf

Load Debug Symbols only


If the boot loader loads the application (and/or OS) code to RAM you need only to load the debug symbols.
Data.LOAD.Elf my_app.elf /NOCODE

Configure the TRACE32 OS-Awareness


Refer to page 33 for details.

Complete Set-up Example


Example for a boot loader that loads the application to RAM.
SYStem.CPU
SYStem.Up
Go

; start the program execution

WAIT 0.5s

; wait 500. ms

Break

; stop the program execution

Data.LOAD.Elf my_app /NOCODE

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Debug Scenario 3

Debug Scenario 4
The application (and the operating system) under debug are running out of RAM. The target configuration,
especially the RAM configuration has to be done by TRACE32 commands, because there is no ready-to-run
boot loader.

Establish the debug communication

Use TRACE32 commands to configure


the target, especially the target RAM and
the UART

Load application (and OS) code to RAM


(this includes the loading of the debug
symbols)

YES

Is an OS used?

NO

Configure the TRACE32


OS-awareness for your OS

* Ready for debug

*Considering the circumstance that a process has to be started manually e.g. via a TERMinal window

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Debug Scenario 4

Write a Script to Configure the Target


A minimum target configuration has to configure all used memories and the serial interface.
Use the PER.Set/PER.view commands for this set-up.

Load Application (and/or OS) Code and Debug Symbols


Data.LOAD.Elf my_app.elf

Configure the TRACE32 OS-Awareness


Refer to page 33 for details.

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Debug Scenario 4

Generate a Start-Up Script


It is strongly recommended to summarize the commands, that are used to set-up the debug environment, in
a start-up script. The script language PRACTICE is provided for this purpose.
The standard extension for a script file is .cmm.

Write a Start-Up Script


The debugger provides an ASCII editor, that allows to write, to run and to debug a start-up script.
PEDIT <file>

Open <file> with the script editor

PEDIT my_startup

The debugger provides two commands, that allow you to convert debugger configuration information to a
script.
STOre <file> [<item>]

Generate a script that allows to reproduce the current settings

ClipSTOre [<item>]

Generate a command list in the clip-text that allows to reproduce the


current settings

STOre system_settings SYStem

; Generate a script that allows you


; to reproduce the settings of the
; SYStem window at any time

PEDIT system_settings

; Open the file system_settings

ClipSTOre SYStem

;
;
;
;
;
;

Generate a command list that


allows you to reproduce the
settings of the SYStem window
at any time
The generated command list can be
pasted in any editor

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Generate a Start-Up Script

Run a Start-up Script

DO <filename>

Run a start-up script

DO my_startup

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Generate a Start-Up Script

Automated Start-up Scripts


There a 3 ways to define a start-up script, that is automatically started, when the debugger is started.

1.

Define start-up script in conjunction with the executable


The debugger-executable can be started with the config file and the start-up script as parameters.
c:\t32\t32arm.exe -c c:\t32\config_usb.t32 -s g:\and\arm\start.cmm

2.

Use T32start to define an automated start-up script


If you use T32start to start the debugger, an automated start-up script can be defined.

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Generate a Start-Up Script

TRACE32 PowerView

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TRACE32 PowerView

Overview
Main Menu Bar
Main Tool Bar
Local Buttons

Local Menu

The structure and functionality of TRACE32 PowerView is defined by the file


t32.men which is located in the TRACE32 system directory.
TRACE32 allows you to modify the GUI so it will better fit to your requirements.
Refer to Training Menu (training_menu.pdf).

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TRACE32 PowerView

Main Menu Bar and Accelerators


The main menu bar provides all important TRACE32 functions sorted by groups.
For often used commands accelerators are defined.

Accelerators

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TRACE32 PowerView

A user specific menu can be defined very easily:


MENU.AddMenu <name> <command>

Add a user menu

MENU.RESet

Reset menu to default

Menu.AddMenu "Set PC to main" "Register.Set pc main"


; user menu with accelerator
Menu.AddMenu "Set PC to main, ALT+F10" "Register.Set pc main"

User Menu

For more complex changes to the main menu bar refer to Training Menu
(training_menu.pdf).

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TRACE32 PowerView

Main Tool Bar


The main tool bar provides fast access to often used commands.
The user can add his own buttons very easily:
MENU.AddTool <tooltip text> <tool image> <command>

Add a button to the toolbar

MENU.RESet

Reset menu to default

MENU.AddTool "Set PC to main" "PM,X" "Register.Set PC main"

User specific
button

Information on the <tool image> can be found in Help -> Contents


TRACE32 Documents -> IDE User Interface -> IDE Reference Guide -> MENU -> Programming
Commands -> TOOLITEM.

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TRACE32 PowerView

All predefined TRACE32 icons can be inspected as follows:

ChDir.DO ~~/demo/menu/internal_icons.cmm

The predefined icons can easily be used to create new icons.


; overprint the icon colorpurple with the character v in White color
Menu.AddTool "Set PC to main" "v,W,colorpurple" "Register.Set PC main"

For more complex changes to the main tool bar refer to Training Menu
(training_menu.pdf).

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TRACE32 PowerView

Window Area
Save Page Layout
No information about the page layout is saved when you exit TRACE32 PowerView. To save the window
layout use the Store Window to command in the Window menu.

Store Windows to generates a batchfile, that


allows you to reactivate the window-configuration
at any time.

// andT32_1000003 Sat Jul 21 16:59:55 2012


B::
TOOLBAR ON
STATUSBAR ON
FRAMEPOS 68.0 5.2857 107. 45.
WINPAGE.RESET
WINCLEAR
WINPOS 0.0 0.0 80. 16. 15. 1. W000
WINTABS 10. 10. 25. 62.
List
WINPOS 0.0 21.643 80. 5. 25. 1. W001
WINTABS 13. 0. 0. 0. 0. 0. 0.
Break.List
WINPAGE.SELECT P000
ENDDO

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TRACE32 PowerView

Run the batchfile to reactivate the stored


window-configuration

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TRACE32 PowerView

Modify Window

The Window Header


displays the command
which was executed to
open the window

By clicking with the right


mouse button to the window
header, the command which
was executed to open the
window is re-displayed in the
command line and can be
modified there

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TRACE32 PowerView

Command Line

Command line

Command Structure
Device Prompt

Selects the command set used by the TRACE32:


no device prompt

TRACE32-IDE

B::

command set for Debugger (BDM)

E::

command set for TRACE32-ICE

F::

command set for TRACE32-FIRE


(RISC Emulator)

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TRACE32 PowerView

Command Examples

Data

Command group to display, modify memory

Data.dump

Displays a hex dump

Data.Set

Modify memory

Data.LOAD.auto

Loads code to the target memory

Break

Command group to set, list, delete breakpoints

Break.Set

Sets a breakpoint

Break.List

Lists all set breakpoint

Break.Delete

Deletes a breakpoint

Each command can be abbreviated. The significant letters are always written in upper case letters.

Data.dump 0x1000--0x2000 /Byte

Option
Parameter
Subcommand
Command group

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TRACE32 PowerView

The Online Help for a Specific Command

Enter the command to the command line.


Add one blank.
Push F1 to get the on-line help for the specified command.

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TRACE32 PowerView

Standard Parameter Syntax


RADIX.<mode>

Define parameter syntax

The RADIX defines the input format for numeric values.


RADIX.Decimal

Number base is decimal and C-like operators are used

RADIX.Hex

Number base is hex and C-like operators are used (default)

Examples:
Decimal

Hex

Data.dump 100

100d

100h

Data.dump 100.

100d

100d

Data.dump 0x100

100h

100h

To see the currently used parameter syntax, enter RADIX. to the command line.

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TRACE32 PowerView

Message Line

Message Area

Message Line

Message line for system and error messages

Message Area window for the display of the last system and error messages

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TRACE32 PowerView

Softkeys
The softkey line allows to enter a specific command step by step.

Select the command group

Select the subcommand

Angle brackets request an entry from the user.


Here e.g. the entry of an <address> or a <range>.

Get a display of all options

Select an option

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TRACE32 PowerView

State Line

Symbolic and absolute


address at the cursor

Debug mode

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TRACE32 PowerView

Registers

Display the Core Registers

Register.view

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Registers

Colored Display of Changed Registers


Register.view /SpotLight

; The registers changed by the last


; step are marked in dark red.
; The registers changed by the
; step before the last step are
; marked a little bit lighter.
; This works up to a level of 4.

Establish /SpotLight as default setting

SETUP.Var %SpotLight

Establish the option SpotLight as default setting for


- all Variable windows
- Register window
- PERipheral window
- the HLL Stack Frame
- Data.dump window

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Registers

Modify the Contents of a Core Register

By double clicking to the register contents


a Register.Set command is automatically displayed
in the command line.
Enter the new value and press Return to modify the
register contents.

Register.Set <register> <value>

Modify register

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Registers

Display the Special Function Registers


TRACE32 supports a free configurable window to display/manipulate configuration registers and the on-chip
peripheral registers at a logical level. Predefined peripheral files are available for most standard processors/
chips.

Tree Display
The individual configuration registers/on-chip peripherals are organized by TRACE32 PowerView in a tree
structure. On demand, details about a selected register can be displayed.

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Registers

Full Display
Sometimes it might be useful to expand the tree structure from the start.

Use the right mouse and


select Show all

Useful commands:
; Display the functional unit "Display_Controller" in expanded mode
; "Display_Controller" is first level unit
PER.view , "Display_Controller"
; Display the functional unit "Memory Management Unit" in expanded mode
; "Memory Management Unit" is second level unit
PER.view , "Core Registers,Memory Management Unit"
; Display all functional units in expanded mode
PER.View , "*"

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Registers

The following command sequence can be used to save the contents of all configuration registers/on-chip
peripheral registers to a file.
PRinTer.FileType ASCIIE

; Select ASCII ENHANCED as output


; format

PRinTer.FILE Per.lst

; Define Per.lst as output file

WinPrint.Per.view , "*"

;
;
;
;

Save contents of all


configuration registers/on-chip
periperal registers to the
specified file

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Registers

Details about a Single Configuration Register

The access class, address, bit position and the full name of the selected item are
displayed in the state line; the full name of the selected item is taken from the
processor/chip manual.

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Registers

The PER Definition File


The layout of the PER window is described by a PER definition file.
The definition can be changed to fit to your requirements using the PER command group.
The path and the version of the actual PER definition file can be displayed by using:
VERSION.SOFTWARE

PER.view <filename> [<tree-search-item>]

Display the configuration registers/on-chip peripherals

PER.view C:\T32\perarm9t.per

; Display the peripheral file


; perarm9t.per instead of the default
; PER definition file

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Registers

Modify a Special Function Register


You can modify the contents of a configuration/on-chip peripheral register:

By pressing the right mouse button and selecting one of the predefined values from the pulldown menu.

By a double-click to a numeric value. A PER.Set command to change the contents of the


selected register is displayed in the command line. Enter the new value and confirm it with return.

PER.Set.simple <address>|<range> [<%format>] <string>

Modify configuration register/onchip peripheral

Data.Set <address>|<range> [<%format>] <string>

Modify memory

PER.Set.simple D:0xF87FFF10 %Long 0x00000b02

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Registers

Memory Display and Modification


This training section introduces the most often used methods to display and modify memory:

The Data.dump window, that displays a hex dump of a memory area, and
the Data.Set command that allows to modify the contents of a memory address.

The List (former Data.List) window, that displays the memory contents as source code listing.

A so-called access class is always displayed together with a memory address. The following access
classes are available for all processor architectures:
P:1000

Program address 0x1000

D:6814

Data address 0x6814

For additional access classes provided by your processor architecture refer to your Processor Architecture
Manual.

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Memory Display and Modification

The Data.dump Window


Basics

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Memory Display and Modification

Use an Address to Specify the Start Address for the Data.dump Window

Please be aware, that TRACE32 permanently updates all windows. The default
update rate is 10 times per second.

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Memory Display and Modification

Use an Address Range to Specify the Addresses for the Data.dump Window

If you enter an address range, only data for the specified address range are displayed. This is useful if a
memory area close to memory-mapped I/O registers should be displayed and you do not want TRACE32
PowerView to generate read cycles for the I/O registers.
Conventions for address ranges:

<start address>--<end address>

<start address>..<end address>

<start address>++<offset_in_byte>

<start address>++<offset_in_word> (for DSPs)

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Memory Display and Modification

Use a Symbol to Specify the Start Address for the Data.dump Window

Use i to select any symbol name or label known to TRACE32 PowerView.

By default an oriented display


is used (line break at 2x).
A small arrow indicates
the specified dump address.

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Memory Display and Modification

Data.dump <address> | <range> [/<option]

Display a hex dump of the memory

Data.dump 0x6814

; Display a hex dump starting at


; address 0x6814

Data.dump 0x6814--0x6820

; Display a hex dump of the


; specified address range

Data.dump 0x6814..0x6820

; Display a hex dump of the


; specified address range

Data.dump 0x6814++0x8

; Display a hex dump of the


; specified address range

Data.dump ast

; Display a hex dump starting at


; the address of the label ast

Data.dump ast /Byte

; Display a hex dump starting at


; the address of the label ast in
; byte format

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Memory Display and Modification

Modify the Memory Contents

By a left mouse double-click to the memory contents


a Data.Set command is automatically
displayed in the command line,
you can enter the new value and
confirm it with Return.

Data.Set <address>|<range> [%<format>] [/<option>]

Modify the memory contents

Data.Set 0x6814 0x0000aaaa

; Write 0x0000aaaa to the address


; 0x6814

Data.Set 0x6814 %Long 0xaaaa

; Write 0xaaaa as a 32 bit value to


; the address 0x6814, add the
; leading zeros automatically

Data.Set 0x6814 %LE %Long 0xaaaa

; Write 0xaaaa as a 32 bit value to


; the address 0x6814, add the
; leading zeros automatically
; Use Little Endian mode

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Memory Display and Modification

Run-time Memory Access


TRACE32 PowerView updates the displayed memory contents by default only if the core is stopped.

A hatched window frame


indicates that the
information display is
frozen because the core
is executing the program.

The plain window frame


indicates that the
information is updated,
because the program
execution is stopped.

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Memory Display and Modification

Non-intrusive Run-time Memory Access

Various cores allow a debugger to read and write physical memory (not cache) while the core is executing
the program. The debugger has in most cases direct access to the processor/chip internal bus, so no extra
load for the core is generated by this feature.
Open the SYStem window in order to check if your processor architecture allows a debugger to read/write
memory while the core is executing the program:

MemAccess CPU/NEXUS/DAP
indicates, that the core allows
the debugger to read/write the
memory while the core is
executing the program.

For more information on the non-intrusive run-time memory access refer to the description of the command
SYStem.MemAccess in your Processor Architecture Manual.

The usage of the non-intrusive run-time memory access has to be configured explicitly. Two methods are
provided:

Configure the run-time memory access for a specific memory area.

Configure run-time memory access for all windows that display memory contents (not available
for all processor architectures).

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Memory Display and Modification

Configure the run-time memory access for a specific memory area:


Enable the E check box to switch
the run-time memory access to ON

A plain window frame


indicates that the
information is updated
while the core is
executing the program

If the E check box is enabled, the attribute E is added to the memory class:
EP:1000

Program address 0x1000 with run-time memory access

ED:6814

Data address 0x6814 with run-time memory access

Write accesses to the memory work correspondingly:

Data.Set via run-time


memory access
(attribute E)

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Memory Display and Modification

SYStem.MemAccess CPU

; Enable the non-intrusive


; run-time memory access

Go

; Start program execution

Data.dump E:0x6814

; Display a hex dump starting at


; address 0x6814 via run-time
; memory access

Data.Set E:0x6814 0xAA

; Write 0xAA to the address


; 0x6814 via run-time memory
; access

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Memory Display and Modification

Configure the run-time memory access for all windows that display memory (not available for all
cores):

If MemAccess CPU/NEXUS/DAP is
selected and DUALPORT is selected,
run-time memory is configured for
all windows that display memory

All windows that display memory


have a plain window frame,
because they are updated while
the core is executing the program

Write access is possible for all


memories while the core is
executing the program

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Memory Display and Modification

SYStem.MemAccess CPU

; Enable the non-intrusive


; run-time memory access

SYStem.Option DUALPORT ON

; Activate the run-time memory


; access for all windows that
; display memory

Go

; Start program execution

Data.dump 0x6814

; Display a hex dump starting at


; address 0x6814 via run-time
; memory access

Data.Set 0x6814 0xAA

; Write 0xAA to the address


; 0x6814 via run-time memory
; access

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Memory Display and Modification

Intrusive Run-Time Memory Access

If your processor architecture doesnt allow a debugger to read or write memory while the core is executing
the program, you can activate an intrusive run-time memory access if required.

CpuAccess Enable allows an


intrusive run-time memory access

If an intrusive run-time memory access is activated, TRACE32 stops the program execution periodically to
read/write the specified memory area. Each update takes at least 50 us.

core(s) is
executing the program

core(s) is stopped to allow


TRACE32 PowerView to read/write
the specified memory

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Memory Display and Modification

An intrusive run-time memory access is only possible for a specific memory area.
Enable the E check box to switch
the run-time memory access to ON

A plain window frame


indicates that the
information is updated
while the core(s) is
executing the program

A red S in the state line indicates, that a TRACE32 feature is


activated, that requires short-time stops of the program execution

Write accesses to the memory work correspondingly:

Data.Set via run-time


memory access with short
stop of the program
execution

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Memory Display and Modification

SYStem.CpuAccess Enable

; Enable the intrusive


; run-time memory access

Go

; Start program execution

Data.dump E:0x6814

; Display a hex dump starting at


; address 0x6814 via an intrusive
; run-time memory access

Data.Set E:0x6814 0xAA

; Write 0xAA to the address


; 0x6814 via an intrusive
; run-time memory access

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Memory Display and Modification

Colored Display of Changed Memory Contents

Enable the option SpotLight to mark the


memory contents changed by the last
4 single steps in rubiginous becoming lighter

Data.dump flags /SpotLight

; Display a hex dump starting at


; the address of the label flags
; Mark changes

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Memory Display and Modification

The List Window


Displays the Source Listing Around the PC

If MIX mode is selected for


debugging, assembler and hll
information is displayed

If HLL mode is selected for


debugging, only hll
information is displayed
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Memory Display and Modification

Displays the Source Listing of a Selected Function

Select the function you


want to display

List [<address>] [/<option>]

Display source listing

Data.List [<address>] [/<option>]

Display source listing

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Memory Display and Modification

List

; Display a source listing


; around the PC

List E:

; Display a source listing


; around the PC via run-time
; memory access

List *

; Open the symbol browser to


; select a function for display

List func17

; Display a source listing of


; func17

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Memory Display and Modification

Breakpoints

Breakpoint Implementations
A debugger has two methods to realize breakpoints: Software breakpoints and Onchip Breakpoints.

Software Breakpoints in RAM (Program)


The default implementation for breakpoints on instructions is a Software breakpoint. If a Software breakpoint
is set the original instruction at the breakpoint address is patched by a special instruction (usually TRAP) to
stop the program and return the control to the debugger.
The number of software breakpoints is unlimited.
.

Please be aware that TRACE32 PowerView always tries to set an Onchip


breakpoint, when the setting of a Software Breakpoint fails.

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Breakpoints

Software Breakpoints in FLASH (Program)


TRACE32 allows to set software breakpoints to FLASH. Refer to the section Software Breakpoints in
FLASH in NOR FLASH Programming Users Guide (norflash.pdf).

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Breakpoints

Onchip Breakpoints in NOR Flash (Program)


Most core(s) provide a small number of on-chip breakpoints in form of breakpoint registers. These on-chip
breakpoints can be used to set breakpoints to instructions in read-only memory like NOR FLASH, EEPROM
or ROM.

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Breakpoints

Since Software breakpoints are used by default for Program breakpoints, TRACE32 PowerView has to be
informed explicitly where to use Onchip breakpoints. Depending on your memory layout, the following
methods are provided:
1.

If the code is completely located in read-only memory, the default implementation for the
Program breakpoints can be changed.

Change the implementation of Program breakpoints to Onchip

Break.IMPLementation Program Onchip

Advise TRACE32 PowerView to


implement Program breakpoints always as
Onchip breakpoints

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Breakpoints

2.

If the code is located in RAM and NOR FLASH/EEPROM/ROM you can define code ranges
where Onchip breakpoints are used.

MAP.BOnchip <range>

Advise TRACE32 PowerView to implement Program


breakpoints as Onchip breakpoints within the defined
memory range

MAP.List

Check your settings

MAP.BOnchip 0x0++0x1FFF
MAp.BOnchip 0xA0000000++0x1FFFFF

Check your settings as follows:

For the specified address ranges Program breakpoints are


implemented as Onchip breakpoints. For all other memory areas
Software breakpoints are used.

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Breakpoints

Onchip Breakpoints (Read/Write)


Onchip breakpoints can be used to stop the core at a read or write access to a memory location.

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Breakpoints

Onchip Breakpoints by Processor Architecture


The list on the next page gives an overview of the availability and the usage of the on-chip breakpoints.
The following notations are used:

On-chip breakpoints: Total amount of available on-chip breakpoints.

Program breakpoints: Number of on-chip breakpoints that can be used to set Program breakpoints into FLASH/EEPROM/ROM.

Read/Write breakpoints: Number of on-chip breakpoints that stop the program when a read or
write to a certain address happens.

Data value breakpoint: Number of on-chip data breakpoints that stop the program when a specific data value is written to an address or when a specific data value is read from an address.

Single address/address ranges/bit masks


For some processor architectures on-chip breakpoints can only mark single addresses (e.g ARM11).
Most processor architectures allow to mark address ranges with on-chip breakpoints. It is very common
that one on-chip breakpoint marks the start address of the address range while the second on-chip
breakpoint marks the end address (e.g. MPC55xx).

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Breakpoints

A number of processor architectures provide only bit masks to mark an address range with on-chip
breakpoints. In this case the address range is always enlarged to the smallest bit mask that includes the
address range. It is recommended to control which addresses are actually marked with breakpoints by using
the Break.List /Onchip command:
Breakpoint setting:
Var.Break.Set flags
Break.List

Break.List /Onchip

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Breakpoints

RISC/CISC Processors

Family

On-chip
Breakpoints

Instruction
Breakpoints

Read/Write
Breakpoint

Data Value
Breakpoints

68k
6833x
6834x
68360

68HC12
68HC12A

up to 2

up to 2 single
address

up to 2 single
address

68HC16

78K0R

1 single address

1 single address

Andes

08

up to 8

up to 8
range as bit mask

up to 8

APS

3 instruction

3 single address

ARM7
ARM9
Janus

2 or
(1 if software
breakpoints are
used)

up to 2
range as bit mask

up to 2
range as bit mask

ARM10/
ARM11

2 16 instruction
2 16 read/write

2 16
single address

2 16
single address

ARMv8

2 16 instruction
2 16 read/write

2 16
single address

2 16
single address

ATOM

4
single address

4
single address or
very small ranges

AVR32

6 instruction
2 read/write

6
range as bit mask

2
range as bit mask

C166SV2

up to 4

up to 4 write
up to 1 read

up to 4 write
up to 1 read

Cortex-A5

3 instruction
2 read/write

3
single address

2
range as bit
mask, break
before make

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Breakpoints

On-chip
Breakpoints

Instruction
Breakpoints

Read/Write
Breakpoint

Data Value
Breakpoints

Cortex-A8

6 instruction
2 read/write

6
range as bit mask

2
range as bit
mask, break
before make

Cortex-A7/
A9/A15

6 instruction
4 read/write

6
single address

4
range as bit
mask, break
before make

Cortex-M0/
M0+

1-4 (by BU Breakpoint Unit)


1-2 (by DW - Data
Wachtpoint unit)

1-4 (BU)
single address
(onchip flash only)
and
1-2 (DW unit)
range as bit mask

1-2 (DW unit)


range as bit mask

Cortex-M1

2/4 (by BPU Breakpoint Unit)


1/2 (by DW - Data
Wachtpoint unit)

2 or 4 (BPU)
single address
(onchip flash only)
and
1 or 2 (DW unit)
range as bit mask

1 or 2 (DW unit)
range as bit mask

Cortex-M3

6 (by FPB - Flash


Patch and
Breakpoint unit)
4 (by DWT - Data
Wachtpoint and
Trace unit)

6 (FPB)
single address
(onchip flash only)
and
4 (DWT)
range as bit mask

4 (DWT)
range as bit mask

1
needs two
DWT
comparators

Cortex-M4

2/6 (by FPB Flash Patch and


Breakpoint unit)
1/4 (by DWT Data Wachtpoint
and Trace unit)

2 or 6 (FPB)
single address
(onchip flash only)
and
1 or 4 (DWT)
range as bit mask

1 or 4 (DWT)
range as bit mask

0 or 1
needs two
DWT
comparators

Cortex-R4/
R5

2-8 instruction
1-8 read/write

2-8
range as bit mask

1-8
range as bit
mask, break
before make

Cortex-R7

6 instruction
4 read/write

6
single address

4
range as bit
mask, break
before make

Family

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Breakpoints

On-chip
Breakpoints

Instruction
Breakpoints

Read/Write
Breakpoint

Data Value
Breakpoints

ColdFire

4 instruction,
2 read/write

3 single address,
1 bit mask

2 single address
or 2 ranges

eTPU

up to 2 single
address

up to 2 read/write
range as bitmask

2
(only with write
breakpoints)

H8S

up to 2

up to 2
range as bit mask

GTM
(only MPC)

up to 4

up to 4

up to 4

H8SX

up to 4

up to 4
range as bit mask

M32R

4 instruction
2 read/write

4 single address

2 single address
or
2 ranges

MCORE

2 single address
or
1 range as bit
mask

2
range as bit mask

MCS8

up to 2 single
address

up to 2 single
address
(reduced to 1 if
combined with
data)

MCS12
MCS12C

up to 3

up to 3 single
address

up to 3 single
address

MCS12X

up to 4 single
address or 2
address ranges

up to 4 single
address or 2
address ranges

MGT5100

1 instruction
(No on-chip
breakpoint,
if software
breakpoints are
used)
1 read/write

1/0 single
address

1single address

Family

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Breakpoints

On-chip
Breakpoints

Instruction
Breakpoints

Read/Write
Breakpoint

Data Value
Breakpoints

MIPS32
MIPS64

up to 15
instruction
up to 15
read/write

up to 15
range as bit mask

up to 15
range as bit mask

up to 15

MPC500
MPC800

4 instruction,
2 read/write

4 single address
or 2 breakpoint
ranges

2 single address
or 1 breakpoint
range

MPC5200

2 instruction
(reduced to 1 if
software
breakpoints are
used)
2 read/write

2/1
2 single address
or 1 breakpoint
range

2
2 single address
or 1 breakpoint
range

MPC55xx

4 instruction
2 read/write

4 single address
or 2 breakpoint
ranges

2 single address
or 1 breakpoint
range

MPC563x

4 instruction
2 read/write

4 single address
or 2 breakpoint
ranges

2 single address
or 1 breakpoint
range

MPC564x
MPC567x

8 instruction
2 read/write

8 single address
or
4 single address
and 2 breakpoint
ranges

2 single address
or 1 breakpoint
range

MPC74xx
MPC86xx

1 instruction
(No on-chip
breakpoint,
if software
breakpoints are
used)
1 read/write

1/0 single
address

1 single address

MPC8240
MPC8245
MPC825x
MPC826x
(PQ2)

1 instruction
(No on-chip
breakpoint, if
software
breakpoints are
used)

1/0 single
address

Family

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Breakpoints

On-chip
Breakpoints

Instruction
Breakpoints

Read/Write
Breakpoint

Data Value
Breakpoints

2 instruction
(reduced to 1 if
software
breakpoints are
used)
2 read/write

2/1
2 single address
or
1 breakpoint
range

2
2 single address
or 1 breakpoint
range

MPC85xx
(PQ3)

2 instruction
(reduced to 1 if
software
breakpoints are
used)
2 read/write

2/1
2 single address
or 1 breakpoint
range

2
2 single address
or 1 breakpoint
range

MSP430

28

28
ranges require
2 breakpoints

28
ranges require
2 ...4 breakpoints

28

PPC401
PPC403

2 instruction,
2 read/write

2 single address
or 2 ranges

2 single address
or 2 ranges

PPC405
PPC44x

4 instruction,
2 read/write

4 single address
or 2 address
ranges

2 single address
or 1 address
range

PPC600

1 instruction
(no on-chip
breakpoint,
if software
breakpoints are
used)

1/0 single
address

PPC740
PPC750

1 instruction
(No on-chip
breakpoint,
if software
breakpoints are
used)
1 read/write

1/0 single
address

1 single address

PWRficient

2 instruction,
2 read/write

2 single address
or 1 breakpoint
range

2 single address
or 1 breakpoint
range

Family
MPC8247
MPC8248
MPC827x
MPC8280
(PQ27)
MPC83xx
(PQ2 Pro)

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Breakpoints

On-chip
Breakpoints

Instruction
Breakpoints

Read/Write
Breakpoint

Data Value
Breakpoints

QORIQ

2 instruction,
2 read/write

2 single addr.,
or 1 large range,
or 2 ranges up to
4 kB,
or 1 single
address and 1
range up to 4 kB

2 single addr.,
or 1 large range,
or 2 ranges up to
4 kB,
or 1 single
address and 1
range up to 4 kB

RH850

12

12
range as bit mask

12
range as bit mask

12

RX

8 instruction
4 read/write

8
range as bit mask

4
1 breakpoint
range
others range as
bit mask

SH2A
ST4A

10

up to 10

up to 10
range as bit mask

SH3

up to 2

up to 2
range as bit mask

SH4
ST40

up to 6

up to 6
range as bit mask

SH7047
SH7144/45

up to 1

up to 1

SH7058

12

up to 12

up to 12
range as bit mask

up to 12

Super10

up to 8

up to 8

up to 8

TriCore

up to 4 instruction
up to 4 read/write

up to 4 single
address or
up to 2 ranges

up to 4 single
address or
up to 2 ranges

V850E1

4 or 8 single
address

2 single address
or 1 range

4
range as bit mask

Family

4 or 8 instruction
(onchip flash only)

V850E2

2 single address
or 1 range

8 single address

8 instruction
(onchip flash only)

4
range as bit mask

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Breakpoints

On-chip
Breakpoints

Instruction
Breakpoints

Read/Write
Breakpoint

Data Value
Breakpoints

XC2000/
XE16x

up to 4

up to 4 write
up to 1 read

up to 4 write
up to 1 read

XC800

up to 4
up to 1 range
(2 single needed)

up to 1 single
address read or
address range
up to 1 single
address write or
address range

XSCALE

2 instruction/
2 read/write

2 single address

2 single address
or
1 range as bit
mask

Family

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Breakpoints

DSP Processors

On-chip
Breakpoints

Instruction
Breakpoints

Read/Write
Breakpoints

Data Value
Breakpoints

Blackfin

6 instruction
2 read/write

6 single address
or
3 ranges

2 single address
or
1 range

CEVA-X

4 instruction
4 read/write

4 single address

4 single address
or range

2
1

2
1

2
1

DSP
56300
56800E

up to 2 single
address

up to 1 single
address

MMDSP

2 instruction
1 read/write

2 single address

1 single address

OAK
TeakLite
TeakLite II
Teak

3 instruction
1 read/write

3 single address

1 single address
or
range as bit mask

StarCore

12

up to 12 single
address or up to 6
ranges

up to 6 single
address or
up to 3 ranges

STN8810
STN8815
STN8820

up to 2

up to 2

TeakLite III

2 instruction
1 read/write

2 single address

2 single address
or 1 range

TMS320
C28x

2 single address

TMS320
C54x

2 single address

TMS320
C55x

up to 4 single
address

up to 3 data,
1 breakpoint
range and 2 bit
masks

up to 3

Family

DSP56K
56k/56300/
56800
56100

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Breakpoints

On-chip
Breakpoints

Instruction
Breakpoints

Read/Write
Breakpoints

Data Value
Breakpoints

TMS320
C62x

1 single address

TMS320
C64x

up to 4

up to 4 single
address

TMS320
C67x

1 single address

ZSP400

ZSP500

up to 4 single
address

up to 1
range as bit mask

Family

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Breakpoints

Softcores

Family

On-chip
Breakpoints

Instruction
Breakpoints

Read/Write
Breakpoint

Data Value
Breakpoints

MicroBlaze

0 4 instruction
0 4 read/write

04
range as bit mask

04
range as bit mask

NIOS2

0/4/8
(configurable)

up to 4

up to 4 single
address or
2 ranges

up to 4

On-chip
Breakpoints

Instruction
Breakpoints

Read/Write
Breakpoint

Data Value
Breakpoints

0/2/4/8

up to 0/2/4/8
range as bit mask

up to 0/2/4/8
range as bit mask

up to 0/1/2/4
only writes,
only in full
mode

Configurable Cores

Family
ARC
600/700
ARC-EM

range as bit
mask
ARC
tangentA4

0/2/4/8

up to 0/2/4/8
range requires
2 breakpoints

up to 0/2/4/8
write only
range requires
2 breakpoints

ARC
tangentA5
Beyond
BA22

up to 0/1/2/4
only writes,
only in full
mode
range requires
2 breakpoints

up to 8

up to 8
range requires
2 breakpoints

up to 8
range requires
2 breakpoints

up to 8
range requires
2 breakpoints

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Breakpoints

On-chip
Breakpoints

Instruction
Breakpoints

Read/Write
Breakpoint

Data Value
Breakpoints

Diamond
Cores

up to 2
range as bit mask

up to 2
range as bit mask

M8051EW

0, 1, 2 or 4

up to 4

up to 4 single
addresses for
read or write
range requires
2 breakpoints
or
2 single address
read/write,
max 1 read/write
range

same as
read/write
breakpoints

Family

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Breakpoints

ETM Breakpoints (Read/Write) for ARM or Cortex-A/-R


The on-chip breakpoints offered by ARM and Cortex-A/-R cores provide sometimes restricted functionality
on Read/Write breakpoints:

Breakpoints on address ranges are implemented as bit masks.

Breakpoints on address ranges are not supported at all.

No data value can be specified for a Read/Write breakpoint.

In most cases better feature can be provided, if ETM breakpoints are added to the Onchip breakpoints.
TRACE32 PowerView supports the usage of two ETM breakpoints.

ETM breakpoints can only be used by the TRACE32 debugger, if the ETM
provides address information on load/store operations (data address
information). For details refer to the chapter ETM Features and Settings in
training_arm_etm.pdf.
Since the ETM is configured via the JTAG interface, Read and Write
breakpoints from the ETM can be used by the TRACE32 debugger even if no
ETM AutoFocus preprocessor is connected.

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Breakpoints

Settings to Enable the Use of ETM Breakpoints

ReadWriteBreak ON

Use 2 ETM address comparators first when a Read or Write breakpoint is


set. Data comparators can also be used, if they are available.
AComp: Number of available address comparators.
DComp: Number of available data comparators.

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Breakpoints

One ETM address comparator


is now used by the debugger

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Breakpoints

Breakpoint Types
TRACE32 PowerView provides the following breakpoint types for standard debugging.

Breakpoint Types

Possible Implementations

Program

Software (Default)
Onchip

Read, Write,
ReadWrite

Onchip (Default)

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Breakpoints

Program Breakpoints

Set a Program breakpoint


by a left mouse
double-click
to the instruction

The red program breakpoint indicator marks all code lines for which a Program breakpoint is set.

The program stops before the instruction marked by the breakpoint is executed (break before make).

Disable the Program


breakpoint by a
left mouse double-click
to the red program
breakpoint indicator.
The program breakpoint
indicator becomes grey.

Break.Set <address> /Program [/DISable]

Set a Program breakpoint to the specified address.


The Program breakpoint can be disabled if required.

Break.Set 0xA34f /Program


Break.Set main /Program
Break.Set func17 /Program /DISable
Break.List

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Breakpoints

Read/Write Breakpoints

Core stops at
a read access
to the variable

Core stops at
a write access
to the variable

On most core(s) the program stops after the read or write access (break after make).

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Breakpoints

If a hll variable is displayed,


a small red breakpoint indicator
marks an active Read/Write breakpoint.
A small grey breakpoint indicator
marks a disabled Read/Write breakpoint.

Break.Set <address> | <range> /Read | /Write | /ReadWrite [/DISable]


; allow hll expression to specify breakpoint
Var.Break.Set <hll-expression> /Read | /Write | /ReadWrite [/DISable]

Break.Set 0x0B56 /Read


Break.Set ast /Write
Break.Set vpchar+5 /ReadWrite /DISable
Var.Break.Set flags /Write
Var.Break.Set flags[3] /Read
Var.Break.Set ast->count /ReadWrite /DISable
Break.List

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Breakpoints

Breakpoint Handling

Breakpoint Setting at Run-time

Software breakpoints

If MemAccess is CPU/NEXUS/DAP or CPUAccess is Enable, Software breakpoints can be set


while the core(s) is executing the program. If the breakpoint is set via CPUAccess the realtime
behavior is influenced.

If MemAccess and CPUAccess is Denied Software breakpoints can only be set when the
program execution is stopped.

The behavior of Onchip breakpoints is core dependent. E.g. on all ARM/Cortex cores Onchip breakpoints
can be set while the program execution is running.

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Breakpoint Handling

Real-time Breakpoints vs. Intrusive Breakpoints


TRACE32 PowerView offers in addition to the basic breakpoints (Program/Read/Write) also complex
breakpoints. Whenever possible these breakpoints are implemented as real-time breakpoints.
Real-time breakpoints do not disturb the real-time program execution on the core(s), but they require a
complex on-chip breakpoint logic.
If the on-chip breakpoint logic of a core does not provide the required features or if Software breakpoints are
used, TRACE32 has to implement an intrusive breakpoint.
Intrusive breakpoints
The usage of these breakpoints influence the real-time behavior. Intrusive breakpoint perform as follows:

Program restart
Program execution

Breakpoint hit

Perform
check

Check not ok

Check ok

Stop

Each stop to perform the check suspends the program execution for at least 1 ms.

The (short-time) display of a red S in the state line indicates that an intrusive breakpoint was hit.

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Breakpoint Handling

Intrusive breakpoints are marked special breakpoint indicator:

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Breakpoint Handling

Break.Set Dialog Box


There are two standard ways to open a Break.Set dialog.

or

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Breakpoint Handling

The HLL Check Box

(asm breakpoint)

The entered address/label is marked by the selected breakpoint.

HLL

The address range used by the entered hll expression is marked


by the selected breakpoint.

Single Address

HLL check box OFF ->


breakpoint is set to
specified address/label

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Breakpoint Handling

Complete Variable

HLL check box ON ->


breakpoint is set to the
address range used
by the entered
variable/function

HLL-Expression

HLL check box ON ->


breakpoint is set to the
address range used by
the entered hll expression

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Breakpoint Handling

Implementations

Implementation

Implementation
auto

Use breakpoint implementation predefined in TRACE32 PowerView.

SOFT

Implement breakpoint as Software breakpoint.

Onchip

Implement breakpoint as Onchip breakpoint.

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Breakpoint Handling

Actions

By default the program execution is stopped when a breakpoint is hit (action stop). TRACE32 PowerView
provides the following additional reactions on a breakpoint hit:
Action (debugger)
Spot

The program execution is stopped shortly at a breakpoint hit to update the


screen. As soon as the screen is updated, the program execution continues.

Alpha

Set an Alpha breakpoint.

Beta

Set a Beta breakpoint.

Charly

Set a Charly breakpoint.

Delta

Set a Delta breakpoint.

Echo

Set an Echo breakpoint.

WATCH

Trigger the debug pin at the specified event (not available for all processor
architectures).

Alpha, Beta, Charly, Delta and Echo breakpoint are only used in very special cases. For this reason no
description is given in the general part of the training material.

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Breakpoint Handling

Action (on-chip or off-chip trace)


TraceEnable

Advise on-chip trace logic to generate trace information on the specified event.

TraceON

Advise on-chip trace logic to start with the generation of trace information at the
specified event.

TraceOFF

Advise on-chip trace logic to stop with the generation of trace information at the
specified event.

TraceTrigger

Advise on-chip trace logic to generate a trigger at the specified event.


TRACE32 PowerView stops the recording of trace information when a trigger is
detected.

A detailed description for the Actions (on-chip and off-chip trace) can be found in the following manuals:

ARM-ETM Training (training_arm_etm.pdf).

Hexagon-ETM Training (training_hexagon_etm.pdf).

Nexus Training (training_nexus.pdf).

or with the description of the Break.Set command.

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Breakpoint Handling

Example for the Action Spot


The information displayed within TRACE32 PowerView is by default only updated, when the core(s) stops
the program execution.
The action Spot can be used to turn a breakpoint into a watchpoint. The core stops the program execution at
the watchpoint, updates the screen and restarts the program execution automatically. Each stop takes
50 100 ms depending on the speed of the debug interface and the amount of information displayed on
the screen.
Example: Update the screen whenever the program executes the instruction sieve\11.

spotted indicates an active Spot breakpoint

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Breakpoint Handling

Options

Options

Temporary

OFF: Set a permanent breakpoint (default).


ON: Set a temporary breakpoint. All temporary breakpoints are deleted
the next time the core(s) stops the program execution.

DISable

OFF: Breakpoint is enabled (default).


ON: Set breakpoint, but disabled.

DISableHIT

ON: Disable the breakpoint after the breakpoint was hit.

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Breakpoint Handling

Example for the Option Temporary

Sets a temporary breakpoint

Start the program execution with Go

All temporary breakpoints are automatically deleted after


the next program stop

Break <address> | <label> [/<type>] [/<implem.>]


Var.Break <hll-expression> [/<type>] [/<implem.>]

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Breakpoint Handling

DATA Breakpoints
The DATA field offers the possibility to combine a Read/Write breakpoint with a specific data value.
Data breakpoints are implemented as real-time breakpoints if the core supports Data Value Breakpoints
(for details on your core refer to page 139). Otherwise an intrusive breakpoint is used (for details on the
intrusive DATA breakpoints refer to page 160)

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Breakpoint Handling

Example: Stop the program execution if a 1 is written to flags[3].

If TRACE32 PowerView had to use an intrusive breakpoint to realize


a DATA breakpoint, a (short-time) red S in the state line indicates that
the breakpoint was hit

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Breakpoint Handling

If a hll expression is used TRACE32 PowerView gets the information if the data is written via a byte, word or
long access from the symbol information.
If an address or symbol is used the user has to specify the access width.

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Breakpoint Handling

Advanced Breakpoints

If the advanced button is pushed


additional input fields are appened
to the Break.Set dialog box to provide
advanced breakpoint features

Advanced breakpoint input fields

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Breakpoint Handling

TASK-aware Breakpoints
TASK-aware breakpoints allow to stop the program execution at a breakpoint if the specified task/process is
running.
TASK-aware breakpoints are implemented on most cores as intrusive breakpoints. A few cores support realtime TASK-aware breakpoints (e.g. ARM/Cortex). For details on the real-time TASK-aware breakpoints refer
to the description of the Break.Set command.
Intrusive TASK-aware Breakpoint

Processing:

Program execution stops at TASK-aware


breakpoint

Specified
task
running?

No

Continue with program


execution

Yes

Keep stop of program execution

Each stop at the TASK-aware breakpoint takes at least 1.ms. This is why the red S is displayed in the
TRACE32 PowerView state line whenever the breakpoint is hit.

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Breakpoint Handling

Example: Stop the program execution at the entry to the function Func_2 only if the task/process main is
running.

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Breakpoint Handling

The red S indicates,


that an intrusive
breakpoint is used

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Breakpoint Handling

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Breakpoint Handling

Real-time TASK-aware Breakpoint

Example for ARM9: Stop the program execution at the entry to the function Func_2 only if main is running
(Onchip breakpoint).

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Breakpoint Handling

Counter
Allows to stop the program execution on the n th hit of a breakpoint.

Software Counter

If the on-chip breakpoint logic of the core does not provide counters, counters are implemented as software
counters.
Processing:

Program execution stops at Counter


breakpoint

Increment
counter

Counter
reached final
value?

No

Continue with program


execution

Yes

Keep stop of program execution

Each stop at a Counter breakpoint takes at least 1.ms. This is why the red S is displayed in the TRACE32
PowerView state line whenever the breakpoint is hit.

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Breakpoint Handling

Example: Stop the program execution after the function sieve was entered 1000. times.

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Breakpoint Handling

The current counter


value is displayed
in the Break.List
window

The red S indicates an


intrusive breakpoint

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Breakpoint Handling

On-chip Counter

The on-chip breakpoint logic of some cores e.g. MPC8xx, MPC5xx, MPC55xx, StarCore provides counters.
They are used together with Onchip breakpoints.
Example: Stop the program execution after the function sieve was entered 1000. times.

The counters run completely in real-time. No current counter value can be displayed while the program
execution is running. As soon as the counter reached its final value, the program execution is stopped.

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Breakpoint Handling

CONDition
The program execution is stopped at the breakpoint only if the defined condition is true.
CONDition breakpoints are always intrusive.
Processing:

Program execution stops at a


CONDition breakpoint

Evaluate
condition

Condition
is
true?

No

Continue with program


execution

Yes

Keep stop of program execution

Each stop at a CONDition breakpoint takes at least 1.ms. This is why the red S is displayed in the TRACE32
PowerView state line whenever the breakpoint is hit.

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Breakpoint Handling

Example: Stop the program execution on a write to flags[3] only if flags[12] is equal to 0 when the
breakpoint is hit.

The red S indicates


an intrusive breakpoint

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Breakpoint Handling

Conditions not in HLL Syntax

It is also possible to write register-based or memory-based conditions.


Examples: Stop the program executions on a write to address flags if Register R11 is equal to 1.

Switch HLL OFF ->


TRACE32 syntax can be used
to set the breakpoint

; stop the program execution at a write to the address flags if the


; register R11 is equal to 1
Break.Set flags /Write /CONDition Register(R11)==0x1
; stop program execution at a write to the address flags if the long
; at address D:0x1000 is larger then 0x12345
Break.Set flags /Write /CONDition Data.Long(D:0x1000)>0x12345

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Breakpoint Handling

CMD
The field CMD allows to specify one or more commands that are executed when the breakpoint is hit.

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Breakpoint Handling

Example: Write the contents of flags[12] to a file whenever the write breakpoint at flags[12] is hit.
;open the file for writing

OPEN #1 outflags.txt /Create

The specified command(s) is executed


whenever the breakpoint is hit. With RESUME
ON the program execution will continue after
the execution of the command(s) is finished.

The cmd field in the Break.List window


informs the user which command(s) is
associated with the breakpoint. R indicates
that RESUME is ON.

It is recommended to set RESUME to OFF, if CMD

starts a PRACTICE script with the command DO

commands are used that open processing windows like


Trace.STATistic.Func, Trace.Chart.sYmbol or CTS.List

because the program execution is restarted before these commands are finished.

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Breakpoint Handling

The state of the debugger toggles between


going and stopped

; close the file when you are done

close #1

Display the result:

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Breakpoint Handling

memory/register/var
The on-chip breakpoint logic of some CPUs allows to combine data accesses and instructions to form a
complex breakpoint (e.g. ARM or PowerArchitecture).
Preconditions

Harvard architecture.

The on-chip breakpoint logic supports a logical AND between Program and Read/Write
breakpoints.

Advantageous

Program breakpoints on address ranges are possible.

Read/Write breakpoints on address ranges are possible.

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Breakpoint Handling

Example: Stop the program execution when the function sieve writes a 1 to flags[3].

1. Define the address (range) of the


instruction here
2. Select MemoryWrite
3. Define the address (range) for the
MemoryWrite access
4. Define the data value for the
MemoryWrite access

If your core does not support this feature, the radio buttons (MemoryWrite, MemoryRead etc.) are grey.

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Breakpoint Handling

Exclude

(Advanced users only, not available on all cores)


The breakpoint is inverted.

by the inverting logic of the on-chip breakpoint logic

by setting the specified breakpoint type to the following


2 address ranges
0x0--(start_of_breakpoint_range-1)
(end_of_breakpoint_range+1)--end_of_memory

The EXclude option applies only to Onchip breakpoints.


If the on-chip breakpoint logic does not provide an inverting logic, the
core has to provide the facility to set the specified breakpoint type on
2 address ranges.

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Breakpoint Handling

Example for the Option EXclude


Stop the program execution when code outside of the function sieve writes 1 to the variable flags[3].

The function sieve is marked with Exclude memoryWrite breakpoints

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Breakpoint Handling

Inverting logic of the onchip trigger unit

Two address range breakpoints

If your TRACE32 PowerView does not accept the option EXclude, delete all other on-chip breakpoints, to
make sure that enough resources are available.

Break.Set <address>|<address range> [/<type>] [/<implem.>] [/DISable]

Set a breakpoint

Var.Break.Set <hll-expression> [/<type>] [/<implem.>] [/DISable]

Set a breakpoint in hll


syntax

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Breakpoint Handling

Display a List of all Set Breakpoints

address

Address of the breakpoint

types

Type of the breakpoint

impl

Implementation of the breakpoint or disabled

action

Action selected for the breakpoint (if not stop)

options

Option defined for the breakpoint

data

Data value that has to be read/written to stop the program execution by


the breakpoint

count

Current value/final value of the counter that is combined with a


breakpoint

condition

Condition that has to be true to stop the program execution by the


breakpoint

cmd (command)
R (resume)

Commands that should be executed after the breakpoint hit


R ON: continue the program execution after the defined commands
were executed

task

Name of the task for a task-aware breakpoint


Symbolic address of the breakpoint

Break.List [/<option>]

List all breakpoints

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Breakpoint Handling

Delete Breakpoints

Break.Delete <address>|<address range> [/<type>] [/<implem.>] [/<option>]

Delete breakpoint

Var.Break.Delete <hll-expression> [/<type>] [/<implem.>] [/<option>]

Delete hll breakpoint

Enable/Disable Breakpoints

Break.ENable [<address>|<address range>] [/<option>]

Enable breakpoint

Break.DISable [<address>|<address range>] [/<option>]

Disable breakpoint

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Breakpoint Handling

Store Breakpoint Settings

// AndT32 Fri Jul 04 13:17:41 2003


B::
BREAK.RESET
B.S
func4 /P /DISABLEHIT
B.S
sieve /P
V.B.S \\diabp555\Global\flags[3]; /W /DATA.BYTE 0x1;
ENDDO

STOre <filename> Break

Generate a batch for breakpoint settings

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Breakpoint Handling

Debugging

Basic Debug Control


There are local buttons in the Data.List window for all basic debug commands

Step

Single stepping e.g. Step 10.

Over

Step over the call.

Next

Next sets a temporary breakpoint to the next assembler or hll line and starts the
program execution. This command is useful to overstep a subroutine call or to
leave a loop.

Program Counter

With Next a temporary


breakpoint is set to the
next written code line,
here e.g. to leave the loop

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Debugging

Return

Return sets a temporary breakpoint to the last instruction of a function and then
starts the program execution.

After pressing
Return the program
execution is stopped
at the last instruction
of the function

Up

This command is used to return to the function that called the current function.
For this a temporary breakpoint is set at the instruction directly after the function
call.

Press Up to return
to the function that
called the current
function

Display the hll stack to


see the function nesting

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Debugging

Step <count>

Single step

Step.Change <expression>

Step until <expression> changes

Step.Till <boolean _expression>

Step until <boolean _expression> becomes true

Var.Step.Change <hll_expression>

Step until <hll_expression> changes

Var.Step.Till <boolean _hll_expression>

Step until <boolean _hll_expression> becomes


true

Step.Over

Step over call

Go [<address>|<label>]

Start program execution

Go.Next

Run program until the next code line is reached

Go.Return

Run program until the end of the hll function is


reached

Go.Up [<level>|<address>]

Run program until it returns to the caller function

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Debugging

Sample-based Profiling

Introduction
Task: get the percentage of time used by a high-level language function.

Measurement procedure: The Program Counter is sampled periodically. This is implemented in two ways.

Snoop: Processor architecture allows to read the Program Counter while the program execution
is running.

StopAndGo: The program execution is stopped shortly in order to read the Program Counter.

The command group for sample-based profiling is PERF.<subcommand>.

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Sample-based Profiling

Standard Approach
Steps to be taken:
1.

Open the PERF configuration window.

PERF.state

Display PERF configuration window

The PERF METHOD Snoop is automatically selected, if the processor architecture supports reading
the Program Counter while the program execution is running. The default METHOD for all other
processor architectures is StopAndGo.

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Sample-based Profiling

2.

Enable the sample-based profiling by selecting the OFF state.

PERF.OFF

3.

Enable the sample-based profiling

Open a result window by pushing the ListFunc button.

PERF.ListFunc

Open a HLL function profiling window

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Sample-based Profiling

4.

Start the program execution and the sampling.

Remarks on the StopAndGo method


The target processor is stopped periodically in order to get the actual Program Counter. Such a stop
can take more than 1 ms in a worst case scenario.

The display of a red S in the TRACE32 state line indicates, that the program execution is periodically
interrupted by the sample-based profiling.
TRACE32 tunes the sampling rate so that more the 99% of the run-time is retained for the actual program
run (runtime). The smallest possible sampling rate is nevertheless 10 (snoops/s).

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Sample-based Profiling

Details
In-depth Result
Push the Detailed button, to get more detailed information on the result.

PERF.ListFunc ALL

Open a detailed HLL function profiling window

Name

Function name

WatchTIme

Time the function is observed

Ratio

Ratio of time spent by the function in percent

DRatio

Similar to Ratio, but only for the last second

Address

Functions address range

Hits

Number of samples taken for the function

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Sample-based Profiling

(other)
TRACE32 assigns all samples that can not be assigned to a high-level language function to (other).
Especially if the ratio for (other) is quite high, it might be interesting what code is running there. In this case
pushing the button ListLABEL is recommended.

PERF.ListLABEL

Open a window for label-based profiling

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Sample-based Profiling

Document your Results

Print your Results


Requires a printer configuration in the file config.t32.
E.g. for Windows
PRINTER=WINDOWS
For other host platform refer to the host platform specific section of the Installation Guide.

Print a Hardcopy of the TRACE32 Application Window

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Document your Results

Print the Contents of a Specific Window


Select the Print item in the window manager menu to print the window contents.

Print any Result


To print more complex results e.g over several pages:
WinPrint.<command>

Pre-command for complex outputs

WinPrint.Data.dump 0x1000--0x1fff
WinPrint.Trace.List (-1000.)--(-500.)

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Document your Results

Save your Results to a File


Select the Output Format for the File

Switch the File


radio button to ON

PRinTer.FileType <format>

Select file format

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Document your Results

Open the File for Printing


Print 1 output to 1 file

WinPrint.Data.dump 0x1000++0xfff

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Document your Results

Print n outputs to n files

If the file name includes a number, this number is automatically incremented after each output.

WinPrint.Data.dump 0x1000++0xfff

Go
Break
WinPrint.Data.dump 0x1000++0xfff

The number within the file name


is automatically incremented

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Document your Results

Print n outputs to 1 file

PRinTer.OPEN [<filename>]

Open permanent output file for results

PRinTer.CLOSE

Close permanent output file for results

PRinTer.OPEN outpd
WinPrint.Data.dump 0x1000++0xfff
Go
Break
WinPrint.Data.dump 0x1000++0xfff
PRinTer.CLOSE

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Document your Results

Reset Output to Printer

Switch the Printer


radio button to ON

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Document your Results