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ary Gloss

A
Accept operation. Operation on a mailbox that is similar to the pend operation, except that if no clataare available, the task retums immediately from the call with a condition code rather than susPending. Access time. The interval between when data are requestedfrom the memory cell and when they are actually available. Accumulator. An anonymous register used in certain computer instructions. Activity packet. A special token passed between the processors in a dataflow architecture. Each token contains an opcode, operand count, operands,and a list of for destination addresses the result of the computation. parameter. The named variable passedto a procedure or subroutine. Actual Address bus. The collection of wires neededto accessindividual memory addresses' Alpha testing. software. ALU. A type ofvalidation consisting ofinternal distribution and exerciseofthe

See arithmetic logic unit' Anatog-to-digital conversion. The processof convertingcontinuous(analog; signals into discrete (digital) ones. Anonymous variable. A hidden variable createdby the compiler to facilitate call-byvalue parameterpassing. Application programs" Programs users write to solve specific problems. Arithmetic logic unit. operations. The CPU intemal device that performs arithmetic and logical

Assemblers. Software that translatesassemblylanguage to machine code. Assembly language. The set of symbolic equivalents to the macroinstruction set. 327

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I Glossary Associative memory. Memory organizedso that it can be searchedaccordingto its contents. Asynchronous event. An event that is not synchronous. Atomic instruction. An instructionthat cannotbe intenupted.

B
systems. in Background. Non-interruptdriven processes foreground/background BAM. See binary angularmeasurement. used to preventdeadlocksituations. Banker's algorithm. A techniquesometimes most that in hardwarecomponents Bathtub curve. A graphdescribingthe phenomenon believe errorsoccur either very early or very late in the life of the component.Some that it is applicableto software. rule, increasing that in the FIFO pagereplacement Belady's Anomaly. The observation the number of pagesin memory may not reducethe number of page faults. of Beta testing. A type of systemtestwherepreliminaryversions validatedsoftwareare under actual use. distributedto friendly customerswho test the software Binary angular measurement. An n-bit scalednumber where the least significantbit is 2"-' .180. that can take on one of two values. Binary semaphore. A semaphore Binary tree. A collectionof n nodes,one of which is a specialone calledthe root. The remaining n - 1 nodesform at most two subtrees. Black box testing. A testingmethodologywhereonly the inputs and outputsof the unit inside the unit is ignored. How the outputsare generated are considered. of by Blocked. The condition experienced tasksthat are waiting for the occurrence an event. a Broadcast communication. In statecharts, techniquethat allows for transitionsto occur in more than one orthogonalsystemsimultaneously. Buffer. A temporary data storage area used to interface between, for example, a fa^st device and a slower processservicingthat device. early in the life to Burn-in testing. Testingthat seeks flush out thosefailuresthat appear of the part and thus improve the reliability of the delivered product. The time over which data are being passedinto a buffer. Bus arbitration. The processof ensuringthat only one device at a time can place data on the bus. Bus contention. Condition in which two or more devicesattemptto gain control of the - -main memory bus simultaneously. Burst period. Bus cycle. Memory fetch. Bus grant. A signal provided by the DMA controller to a device indicating that it has exclusiverights to the bus. Bus time-out. A condition whereby a device making a DMA requestdoes not receive a bus grant before some specifiedtime. the Busy wait. In polled loop systems, processof testing the flag without success.

I Glossary

329

C
Call-by-address. See call-by-reference. Call-by-reference. The processin which the address the parameter passed the of is by calling routine to the called procedureso that it can be alteredthere. Call-by-value. Parameter passingmethodin which the value of the actualparamerer in the subroutineor function call is copied into the procedure's formal parameter. Calling trees. See structurechart. CASE. Computer-aded softwareengineering. Catastrophic error. CCR An error that rendersthe svstemuseless. See condition code register.

Cellular automata. A computationalparadigm for an efficient descriptionof SIMD massivelyparallel systems. Chain reaction. In statecharts, group of sequentialevents where the nth event is a triggeredby the (n - l)th event. 'Code Checkpoints. that outputs intermediateresults to allow an external Drocessto monitor the efficacy of the processin questronChecksum. A simple binary addition of all program code memory locationsused ro verify the contents. Circular queu€. See ring buffer. Seecomplexinstruction computer. set Class definitions. Object declarations along with the methodsassociated with thern. Clear box testing. See white box testing. Code inspection. See group walkthrough. Collision. Condition in which a device already has control of the bus and another obtainsaccess. Also, simultaneous use of a critical resource. C-ompaction. The processof compressing fragmentedmemory so that it is no lon-eer fragmented. Also called coalescing. Softwarerhat translares high-orderlanguageprogramsinto assembll,code Complex instruction set computers. Architecturescharacterized a larse. micrr.bv coded instruetionset with numerousaddressing modes. Composition. An operationappliedto a reliability matrix that determines marin-iuir the reliability betweenprocessors. Compute-bound. Computationsin which the number of operationsis laree in ;,r:--parisonto the number of I/O instructions. Condition code register. Intemal CPU register used to implemenr a .Lrr.,i::1.-:.;. transfer. Conditional transfer. A changeof the program counterbasedon the resuk .ri : !3>: Content.addressablememory. See associatrve memory. context. The minimum informationthat is needed order to sa'e a curienrlr .\e.-urrns in task so that it can be resumed. Context switching. The processof saving and restorine suft-rcient information for a real-time task so that it can be resumedafter beins intem-rpred. Compiler. CISC.

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I Glossary Continguous firleallocation. The processof forcing all allocatedfile sectorsto follow one anotheron the disk. iontinuous random variable. A random variablewith a continuoussamplespace. to Control flow diagram. A real-timeextension dataflowdiagramsthat showsthe flow of control signalsthrough the system. Control specifications. In dataflow diagrams,a finite state automatonin diagrammatic and tabularrepresentation. cycle. the Control unit. CPU internal device that synchronizes fetch-execute are multitasking system. A scheme in which two or more processes Cooperative Calls to a central by determined a finite stateautomaton. or divided into states phases, dispatcher are made after each phase is complete. set. CPU used to extendthe macroinstruction Coprocessor. A secondspecialized multitaskingsystem. Coroutine system. See cooperative Correlated data. See time-relativedata. that can take on two or more values. Counting semaphore. A semaphore unit. CPU. Centralprocessing code. CRC. See cyclic redundancY Critical region. Code that interactswith a serially reusableresource. CU. See control unit. the precludes CPU from accessing the Cycle stealing. A situationin which DMA access bus. Cyclic redundancy code. A method for checking ROM memory that is superior to checksum.See Chapter 11. Cycling. The processwhereby all tasks are being appropriately scheduled(although no cyciomatic complexity. is actualprocessing occurring). A measureof a system reliability devised by McCabe.

D
Daemon. A device serverthat doesnot run explicitly but rather lies dormant waiting for some condition(s) to occur. Dangerous allocation. Any memory allocation that can preplude system determinrsm. Data bus. Bus used to carry data between the various componentsin the system. Dataflow architectures. A multiprocessing system that uses a large number of speciai processors,and computation is performed by passing activiti packs between them. Dataflow diagrams. A structured analysis tool for modeling software systems. Dead code. See unreachablecode. Deadlock. A catastrophicsituation that can arise when tasksare cornpetingfor the sarne set of two or more serially reusableresources. Deadly embrace. See deadlock. Death spiral. Stack overflow causedby repeatedspurious interrupts. Decode. The processof isolating the opcodeTieldof a macroinstructionand determin-:ne the addressin micromemory of the programming correspondingto it'

I Glossary

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Defect. The preferred term for an error in requirement,design, or code. See also fault, failure. are Demand page system. Techniquewhere program segments permittedto be loaded in memory as they are requested fixed-sizechunks. noncontiguous in Density. In computermemory, the number of bits per unit area. that are De-referencing. The processin which the actual locationsof the parameters passedusing call-by-valueare determined' the Derivative of f at x. Represents slope of the function/ at point x. Deterministic system. A systemwhere for each possiblestate.and each Setof inputs, a unique set of outputsand next stateof the systemcan be determined. Digital-to-analog conversion. The processof convertingdiscrete(digital) signalsinto continuous(analog)ones. Direct memory access. A scheme in which accessto the computer's memory is affordedto other devicesin the systemwithout the intervcntionof the CPU' Direct mode instruction. Instructionin which the operandis the data containedat the field of the instruction. address specifiedin the address Discrete random variable. A random variabledrawn from a discretesamplespace. Discrete signals. Logic lines used to control devices. Dispatcher. The part of the kernel that performs the necessarybookkeeping to start 3 task. Distributed real.time systems. A collection of interconnectedself-containedprocessofs. See direct memory access. controller. Device that performsbus arbitration. DMA as block model, a statethat is best described a TCB Dormant state. ln the task-control belonging to a task that is unavailableto the operatingsystem. Double-buffering. A techniqueusing two buffers where one is tllled while the data ir the other is being used. DMA. memory. DRAM. Dynamic random access Drive line. In core memory,a wire usedto induce a magneticfield in a toroid-shrpe; magnet. The orientation of the field representseither a 1 or a 0' Dynamic memory. Memory that usesa capacitorto storelogic 1s and 0s. and thet ::-.: periodicallyto restorethe chargelost due to capacitivedischarse be refreshed Dynamic priority system. A system in which the priorities of tasks ca: ;:i::: Contrast with fixed priority system'

E
metrics (seeChapter 11)' One of Halstead's harClare .l';;:.:: :: ---e Software used to conffol speci.alized Embedded system. computer system. I --: '-i:l EncapSulation. A condition that ariseswhen a classof objecis;n.j ilre rrFEri'.and implementation' can be performedon are isolatedin both access Effort.

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Event. Any occurrence that resultsin a changein the stateof a system.

I Glossary

Event determinism. When the next states and outputsof the systemare known for each set of inputs that trigger events. Event flag. Synchronization mechanismprovided by certain languages. Exception. Error or other specialcondition that arisesduring program execution. Exception handler. Code used to processexceptlons. Execute. Processof sequencing througli the stepsin micromemorycorresponding a to particular macroinstruction. Executing state. In the task-controlblock model, a task that is currently running. Exccutive. See kernel. Extennal fragmentation. When main memory becomescheckeredwith unused but availablepartitions,as in Figure 8.-5.

F
Failed system. A systemthai cannotsatisfyone or more of the requirements listedin the formal systemspecification. Failure. A fault that causes softwaresystemto fail to meet one of its requirements. the See also defect. A function describingthe probability that a systemfails at time r. Fault. The appearanceof a defect during the operation of a software system; synonymouswith error or bug. See also failure. Failure function. Fault tolerance. The ability of the systemto continue to function in the presence of hardwareor softwarefailures. Fetch. The processof retrieving a macroinstruction from main memory and placing it in the instructionregister. Fetch-execute cycle. The process continuouslyfetchingand executingmacroinstrucof tions from main memory. File fragmentation. Analogous to memory fragmentationbut occurring within files, problems. with the sameassociated Finite state automaton. A mathematical technique usedto represent systems with finite input and output spaces. Also known as a finite statemachine. Firing. In Petri netsor in certainmultiprocessor architectures, when a process block or processperformsits prescribedfunction. Firm real-time system. A systemwith hard deadlineswhere some low missing a deadlinecan be tolerated. of

Fixed priority system. A system in which the task priorities cannot be changed. Contrast with dynamic priority system. Fixed-rate system. A systemin which intemrptsoccui only at fixed rates. Flip-flop. A bistablelogic device. Flow chart. Graphical algorithm representation. Flush. In pipelined architectures, the act of emptying the pipeline when branching occurs.

I Glossary

333

Foreground. A collectionof interrupt driven or real-timeprocesses. Formal parameter. The dummy variable used in the description of a procedure or subroutine. FSA. Seefinite stateautomaton. FSM. See finite state automaton. Function points. A widely used metric set in nonembeddedenvironments; they form Function points measurethe the basis of many commercial software analysispackages. in betweenmodulesand subsystems programsor systems. number of interfaces Functional requirements. Those system features that can be directly tested br executing the program.

G
but Garbage. Memory that hasbeenallocated is no longerbeing usedby a task (that is. the task has "lost track of it"). General register. CPU intemal memory that is addressablein the address field of certainmacroinstructtons. General semaphore. See counting semaphore. polynomial in CRC. General polynomial. The modulo-2 divisor of the message Granularity. See scale factor.

inspect Group walkthrough. A kind of white box testingin which a numberof persons the code line-by-line with the unit author.

H 1 -Hamming code. A coding technique used to detect and correct errors in computer memory. Hard error. Physical damageto memory cell.

time constraints leads Hard real-time system. Systemswherefailure to meet response to system failure. Hybrid system. A system in which interrupts occur both at fixed frequencies and sporadically. Hypercube processor. A processor configuration that is similar to the linear arrar' processorexcept that each processorelement communicatesdata along a number of other higher dimensional pathways.

I
ICE. See in-circuit emulation.

Immediate mode instruction. An instructionin which the operandis an intege: Implied mode instruction. An instruction involving one or more specitk nnern\a{ locations or registers that are implicitly defined in the operation pert-urrri trt instruction. Incidence matrix. A realiability matrix in which the enries are eitlrer I or 0.

334

I Glossary In-circuit emulation. A devicethat usesspecialhardwarein conjunctionwith software to emulatethe targetCPU for debuggingpurposes. Indirect mode instruction. Instructionwhere the operandfield is a memory location containing the addressof the addressof the operand. Induction variable. A variablein a loop that is incremented decremented some or by constant. Information hiding. The processof isolating highly changeable sectionsof code. Inheritance. In object-oriented programming, inheritance allows the programmer to define new objects in terms of other objects that inherit their characteristics. In-line patch. A patch that fits into the memory spaceallocatedto the code to be changed. Input space. The set of all possibleinput combinationsto a system. Instruction register. CPU intemal register that holds the instruction pointed to by the contents of the program counter. Integration. The processof uniting modules from different sourcesto form the overall system. Internal fragmentation. Condition that occurs in fixed-partition schemeswhen, for example, a processrequires I kilobyte of memory, while the only 2-kilobyte partitions are available. Interrupt. A hardware signal that initiates an event. Interrupt handler. Specialcode usedto respondto intemrpts.Also called an interrupt service routine. Interrupt-handler location. Memory location containing the starting address of an interrupt-handlerroutine. The program counter is automatically loaded with its address when an interrupt occurs. Interrupt latency. The delay between when an intemrpt occurs and when the CPU begins reacting to it. Interrupt register. Register containing a bit map of all pending (latched) interrupts. Interrupt return location. Memory location where the contentsof the program counter is saved when an intemrpt is processedby the CPU. Register that contains the identity of the highest-priority intemrpt A macro where the actual function call is replaced by in-line

Interrupt vector. request. Intrinsic function. code.

J
Jackson Chart. A form of structure chart that provides for conditional branchins.

K
Kalrnan filter. A mathematical construct used to combine measurements the same of quantity from different sources. Kernel. The smallestportion of the operating system that provides for task scheduling, dispatching, and intertask communication.

I Glossary

335

polnts that providespreemptlon Kernel preemption. A methodusedin real-timeUNIX to be intemrpted' in cails to kemel functionsto allow them usedto protect a critical region' Key. In a mailbox, the data that are passedas a flag

L
Leaf. Any node in a tree with no subtrees' algorithm' pagereplacement Least recently used rule. The best nonpredictive a diagramat a finer level of Leveling. [n dataflow diagrams.the processof redrawing detail. of so organized that multiple instructions the same Linear array processor. A processor type can be executedin Parallel' Linker.Softwarethatpreparesrelocatableobjectcodeforexecutton' in numberof customers average Little,s law. Rule trom queuingtheory statingthat the

aqueuingSystem,N"',isequaltotheaverageanivalrateofthecustomerstoth ta"' system,ru,, times the averagetime spentin that system' in the program' Live variable. A variablethat can be used subsequently Livelock. Another term for process starvatron' the machine' Load module. Code that can be readily loaded into if you examine a list of recently executed Locality-of-ret'erence. The notion that you will seethat most of the instructions are progiu* instructions on a logic analyzer, instructtons' iocalized to within a small number of ineffective' Lock-up. When a systementersin which it is rendered

Look-uptable.Anintegerarithmetictechniquethatusestablesandrelieson functions quickly' mathematicaldefinition of the derivative to compute outsidea loop that computations Loop invariant optimization. The processof placing do not need to be performed within the loop' Looselycoupledsystem.Asystemthatcanrunonotherhardwarewiththerewri certainmodul:s LRU. See leastrecentyusedrule'

M

computer operations'Also called Machine code. Binary instructions that affect specific machine language. Macrocode. See macroinstruction' Binary program code stored in the main memory of the computer' Macroinstruction. Also called macrocode. 'i of a memory locatlon in'J ArMailbox, An intertask communication device consi,sting it' operations-post and pend-that can be performed on by the CPU' Main memory. Memory that is directly addressable in of repeatingprocesses c1'ciicor pencrltc i\ ilsl'l'ls Major cycle. The largestsequence MAR. See memory addressregister' enabling or di'abling sFecric Mask register. A register that contains a bit map either intemrPts.

336

I Glossary configuration' in Master processor. The on-line processor a master/slave MDR. SeememorYdata register. of the memory Memory address register (or MAR). Registerthat holds the address location to be acted on. written to or that Memory data register (or MDR). Registerthat holds the data to be location held in the MAR' is read fiom the memory of Memory-loading. The percentage usablememory that is being used' parts of a Memory locking. In a real-timesystem,the processof locking all or certain involved in paging, and thus make the processlnro memory to reducefhe <lverhead executiontimes more predictable. configurationthat is similar to the linear array processor Mesh processor. A processor data north and south' elementalso communicates that eachprocessor "^a"pt Messageexchange' See mailbox. Messagepolynomial. Used in CRC (seeChapter 11)' functionsthat can be performedon objects. systems, Methods. In object-oriented MFT. Multiprogrammingwith a fixed number of tasks' particular macroof Microcode. A sequence binary instructionscorrespondingto a instruction.Also called microinstructions' via Microcontroller. A computersystemthat is programmable microcode. Microinstructions. See microcode. Micro-kerne|.Anano-kemelthatalsoprovidesfortaskscheduling. to corresponding Micromemory. cPU intemal memory that holds the binary codes macroinstructions. of Microprogram. Sequence microcodestoredin micromemory' in of Minor cycle. A sequence repeatingprocesses cyclic or periodic systems' combinesthe high-orderlanguageinstructionwith the Mixed listing. A printout that equivalentassemblylanguagecode' frequencies and Mixed system. A system in which interrupts occur both at fixed sporadically" with highMultimedia computing. Computing that involves computer systems CD-ROM drives, mice, high-performancesound cards, and resolution graphics, multitasking operating systemsthat support these devices' Multip|exer.Adeviceusedtoroutemultiplelinesontofewerlines. than one Multiprocessing operating system. An operating system in which more to provide for simultaneity; contrastwith multitasking operating processoris available sysrcm. functionMultitasking operating system. An operating systemthat provides sufficient single processor so that the illusion of ality to aiow multiple programs to run on a simultaneity is created; contrast with multiprocessing operating system. Mutex. A common name for a semaphorevariable' MUX. MVT. See multiPlexer' Muftiprogramming with a variable number of tasks'

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N
Nano-kernel. Code that provides simple thread-of-execution(same as "flow-ofcontrol") management;essentiallyprovides only one of the three servicesprovided by a kernel-that is, it providesfor task dispatching. Nonfunctional requirements. System requirementsthat cannot be tested easily by program executron. upon removing povl'er. Nonvolatile menory. Memory whose contentsare preserved that doesnot use the storedprogram, Non-von Neumann architecture. An architecture cycle. serial fetch-execute No-op. A macroinstruction that does not changethe state of the computer. problem for NP-complete problem, A decisionproblem that is a seeminglyintractable which the only known solutions are exponentialfunctions of the problem size; compare with NP-hard. NP-hard. A decision problem that is similar to an NP-completeproblem (exceptthat for the NP-hard problem not even an exponential time solution can be found). nth Order reliability matrix. The composition of a reliability matrix with itself (n - l) trmes. N-version programming. A techniqueusedto reducethe likelihood of systemlock-up each running software that has been coded to the same by using redundantprocessors, by different teams. specifications Nucleus. See kernel.

o
Object code. A specific collection of machine instructions. Object-oriented language. A languagethat provides constructsthat encouragea high degree of information hiding and data abstraction. Opcode. Starting addressof the microcode program stored in micromemory. programs. Operating system. A unique collection of systems system. A system that is not embedded. Organic Orthogonal process. In statecharts,the combined functionalit.v of t set of orrhogonal processes. processes r'Jn that that depictsconcrurent a Orthogonal product. In statecharts. process in isolation. Ostrich algorithm. A techniquethat advisesthat the problem of deadlockbe ignored. This solution is viable only in noncritical s\stems. Output space. The set of all possibleoutput combilations ior a s)'stem' Overlay. Dependentcode and data sections used in overlaf i,ng. Overlaying. A technique that allows a srngle program to be larger than the allowable user space. Oversized patch. A patch that requires more memor)- than is curendy occupied by the code to be replaced.

338

I

Glossary

P
Page. Fixed-sizechunk used in demand-paged systems. Page fault. An exceptionthat occurs when a memory referenceis made to a location within a page not loaded in marn memory. Page-frame. Seepage. Page stealing. When a page is to be loaded into main memory, and no free pagesare found, then a page frame must be written out or swappedto disk to make room. Page table. A collectionof pointersto pagesusedto allow noncontiguous allocationof page frames in demandpaging. Parnas partitioning. See information hiding. Partial order relation. In processscheduling,an indicator that any processcan call itself (reflexivity); if processA calls process B, then the reverse is not possible (antisymmetry), A and if process calls processB and processB calls processC, then processA can call processC (transitivity). Patching. The processof correctingerrors in the code directly on the targetmachine. PC. PDL. See program counter. See program design language.

Peepholeoptimization. An optimizationtechniquewhere a small window of assembly langageor machinecode is comparedagainstknown pattemsthat yield optimization opportunltles. Pend operation. Operationof removing datafrom a mailbox. If data are not available, itself until the data becomeavailable. the processperforming the pend suspects Petri net. A mathematical/pictorial systemdescriptiontechnique. Phase-driven code. See state-driven code. Ping-pongbuffering. Seedouble-buffering. Pipeline. An intertaskcommunicationmechanismprovided in UNIX. Pipelining. A techniqueused to speedprocessor executionthat relies on the fact that fetching the instruction is only one part of the fetch-execute cycle, and that it can overlap with different parts of the fetch-execute cycle for other instructions. Polled loop system. A real-timesystemin which a single and repetitivetest instruction is used to test a flag that indicates that some event has occurred. Polymorphism. In object-oriented programming, polymorphism allows the prograrnmerto createa single function that operateson different objects dependingon the type of object involved. Post operation. Operationthat placesdata in a mailbox. Power bus. The collectionof wires usedto distributeDowerto the variouscomponents of the computersystem. a Pragma. In certainprogramminglanguages, pseudo-opthat allows assemblycode to be placed in-line with the high-order language code. Preempt. task. A condition that occurs when a higher-priority task interrupts a lower-priority

Preemptive priority system. A systemthat usespreemptionschemes insteadof roundscheduling. robin or first-come/first-serve

.."-:--:<]

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Glossary

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Primary memory. See main memory. to Priority ceiling protocol. A method used in interruptdriven systems avoid priority inversion;dictatesthat a task blocking a higher priority task inheritsthe higherpriority for the duration of that task. Priority inversion. A condition that occurs becausea noncritical task with a high execution rate will have a higher priority than a critical task with a low execution rate. used to calculatethe overall systemreliability. Processblocks. Subsysterrs systemsuch as a in Processingelements. The individual processors a multiprocessing systolic or wavefiont architecture. Program counter. The CPU internal register that holds the address of the next instructionto be executed. Program design language. A type of abstracthigh-order languageused in sYstem specification. Propagation delay. The contributionto interruptlatencydue to limitation in switching of speeds digital devicesand in the transit time of electronsacrosswires. Prototype. A mock-up of a softwaresystemoften used during the designphase. Pseudocode. A type of program design language.

R
such asC. Raise. Mechanismused to initiate a softwareinterrupt in certain languages RAM scrubbing. A technique used in memory configurations that include error the which reduces chanceof multiple bit detectionand correctionchips.The technique, memory effors are corrected in because someconfigurations errorsoccuring,is needed memory datathen needto be written on the bus and not in mernoryitself. The corrected back to rnemory. Random variable. A function mapping elements of the sample space into a real number. Rate-monotonic system. A fixed-rate,preemptive,prioritized real-time systemshere the priorities are assignedso that the higher the executionfrequency,the higher the priority. Reactive system. A systemthat has some ongoing interactionwith its enrironment. Read/write line. Logic line that is set to logic 0 during memory-u'rite and to logr. I during memory read. Ready state. In the task-controlblock model, the stateof those thsksthat are r:::i :.run, but not running. Real-time system. A system that must satisf;- explicit tbcundea' :eirrcrit ll=.1 or constraints it will fail. Recovery block. Sectionof code that terminate.in che.-\pr.int. lf the lire:r:. beginningof a recoren bir-t-k. processing can resumeat the ihat can Recursion. A methoduherebya procedure be self-relerentiiri. ls. l[ !-allin\\-hi(call) itself.

340

I Glossary Reduced instruction set cornputer. Architecture usually characterized by a small instruction set with limited addressing modes and hard-wired (as opposed to microcoded)instructlons. Reduction in strength. Optimization techniquethat usesthe fastestmacroinstruction possibleto accomplisha given calculation. Re-entrant procedure. A procedurethat can be usedby severalconcurrentlyrunning tasksin a multitaskingsystem. Register direct mode instruction. Instruction in which the operand field is a reglster. Register indirect mode instruction. Instructionin which the operandaddress kept in is a registernamed in the operandfield of the instruction. Regressiontesting. A test methodologyused to validate updatedsoftu,areagainstan old set of test casesthat have alreadybeen passed. Reliability matrix. In a multiprocessing system,a matrix that denotesthe reliability of the connections betweenprocessors. Responsetime. The time between the presentation a set of inputs to a software of systemand the appearance all the associated of outputs. ReversePolish notation. The result of building a binary parsetree with operands the at leavesand operations the roots, and then traversingit in post-orderfashion. at Ring buffer. A first-in/first-outlist in which simultaneous input and output to the list is achievedby keepinghead and tail pointers.Data are loaded at the tail and read from the head. RISC. See reducedinstructionset computer. Root. In overlaying memory management,the portion of memory containing the overlay managerand code common to all overlay segments, such as math libraries. Round-robin system. A systemin which several processes executed are sequentially to completion,often in conjunctionwith a cyclic executive. Round-robin system with time-slicing. A system in which each executabletask is assigned fixed time quantumcalled a time slice in which to execute. clock is used a A to initate an interrupt at a rate correspondingto the time slice.

S
Sample space. The set of outcomesto some experiment. Sampling rate. The rate at which an analog signal is converted to digital form. Scale factor. A technique used to simulate floating point operations by assigning an implicit noninteger value to the least significant bit of an integer. sccs. Source code control system for managementof system code; typical for UNIX operatingsystems. Schedualability formance. analysis. The compile time prediction of execution time per-

Scheduler. The part of the kernel that determineswhich task will run. Scratch pad memory. CPU intemal memory used for intermediate results.

311 I Glossary Screen signature. The CRC of a screenmemory'

Secondarymemory.Memorythatischaracterizedbylong-termstoragedevicesSucha tapes,disks, and cards'

S e l f - m o d i f y i n g c o d e ' C o d e t h a t c a n a c t u a l l y c h a n g e i t s e lmay r e x a m p lonlyyone i n g f ; f o differ by e ' b t a k of certain initructions advantageof tn" tu",iiat the opcodes type used for protectrng critical regions' Semaphore. A special variable on a semaphor' two operations that can be performed Semaphore primitives' The namelY,wait and signal' coupled system' Semidetachedsystem' See loosely bit.

S e n s e l i n e . l n c o r e m e m o r y a w i r e t h a t i s u s e d t o . . r e isd ' ' tise m egeneratedin e n d sense t h a h m o r y . D e p the i n g o n in the core, a pulse or not orientation of the magnetrcfield at a time and that can only be usedby one task resource Serialty reusable resource. A that must be used to comPletion' line.

Server.Aprocessusedtomanagemultiplerequeststoaseriallyreusableresource SEU. Seesingleevent upset' such as C' mechanismprovided by certainlanguages' Signal. Exception-handling

Signaloperation.op",uti-ononasemaphorethatessentiallyreleasesthereso semaPhore' ProtectedbY the

Single.eventupset.Alterationofmemorycontentsduetochargedparticlesprese event' Jpu"", ot in the presenceof a nuclear S|aveprocessor.Theoff-line,processorinamaster/slaveconfiguration. of the contents of memory' Soft eiror. Repairable alteration

Softreal-timesystem.Asysteminwhichperformancersdegradedbynotdestroye failure to meet responsetime constrarnts' Software. A collection of macroinstructlons'

Softwarereliability.Theprobabilitythatasoftwaresystemwillnotfailbeforesom time t. software' involving redundant hardware or Spatiat fault tolerance' Methods

S p e c u l a t i v e e x e c u t i o n . I n m u l t i p r o c e s s i n g s y s t e m s , aini tthe tnexttprocessbirrrr' e n i code s u a i o n h a t i n v o l r ' e s :> optimislcailv and predictivelyexecuting processor longasthereisnodepend"ncyinthatprocessblockoncodethatcouidberu:il-:. other Processors' the wait semaphoreoperatlon' Spin lock. Another name for with all interruptsocculrlng sporadicarir' Sporadic system. A system by an interrupt that occursapen'rir'i'i Sporadic task. A task driven

Spuriousinterrupts.Extraneousandunwantedintemlptsih":,:,:'.']::..].. loading. memory' SRAM. Static random-access structure' Stack. A first-inAast-out data

Stackmachines.ComputerarchitectureinuhichLtelnst.';---::i3r=;en:ir3.J stack' and an accurtuial"t intemal memory store called a

342

I Glossary Starvation. A condition that occurs when a task is not being serviced frequently enough. State-driven code. Programcode basedon a finite stateautomaton. Static memory. Memory that does not rely on capacitivechargeto storebinary data. Statistically based testing. Techniquethat usesan underlyingprobability distribution random test cases. function for each systeminput to generate that containsthe value of the Status register. A registerinvolved in interuptprocessing lowest interrupt that will presentlybe honored. to Stresstesting. A type of testingwherein the systemis subjected a large disturbance of interupts), foilowed by smallerdisturbances in the inputs(for example,a largeburst spreadout over a longer period of time. Structure chart. Graphicaldesign tool usedto partition systemfunctionality. Suspendedstate. In the task-controlblock model, those tasks that are waiting on a particularresource,and thus are not ready.Also called the blocked state. Swapping. The simplest schemethat allows the operating system to aliocate main simultaneously. memory to two processes physical phenomenonthat an eiectricai signal cannot instanfaSwitch bounce. The neouslychangefrom its logical false condition. Synchronous data. See time-relativedata. Synchronous event. Event that occursat predictabletimes in the flow-of-control. Syndrome bits. The extra bits neededto implementa Hamming code. System. An entity that when presentedwith a set of inputs produces outputs. of System programs. Softwareused to managethe resources the computer. System unification. A process consisting of linking together the testing software modulesin an orderly fashron. Systotic processors. Multiprocessingarchitecturethat consistsof a large number of in connected an array topology. uniform processors

T
Task-control block. A collection of data associatedwith a task including processcode (or a pointer to it), and other infonnation. TCB. See task control block. Telepresence. A form of virtual reality in which a human operatorcan remotely control robots or other devicesas if the operatorwere physically present. time for eachset of Temporal determinism. A conditionthat occurswhen the response outputsis known in a deterministicsystem. that allow for toleratingmisseddeadlines. Temporal fault tolerance. Techniques that can atomically test and then set a Test-and-setinstruction. A macroinstruction to panicular memory address some value. Test probe. A checkpointused only during testing' Test suite. A collection of test cases.

I

Glossary

343 Very high paging activity.

Thrashing.

Throughput. A measureof the number of macroinstructions secondthat can be per processed basedon some predetermined instructionmix. Time-loading. The percentageof "useful" processingthe computer is doing. Also known as the utilization factor. Time overloaded. A systemthat is l00oloor more time-loaded. Time-relative data. A iollection of data that must be time correlated, Time-slice. A fixed time quantum used to limit execution time in round-robin systems. Transceivers. A transmitheceive hybrid device. Tiansputer. A fully self-sufficient, multiple instruction set, von Neumann processor, designedto be connected other transputers. to Trap. Internal interrupt causedby the execution of a certain instruction. A high-impedancestate that, in effect, disconnectsa device from the bus. Tri-state.

U
Unit. A softwaremodule. Unreachable code. Code that can never be reachedin the normal flow-of-control. User space. Memory not required by the operating system. Utilization facator. See time-loadine.

v
Vector processor. See linear iuray processor. Version control software. A systemthat managesthe accessto the various components of the system from the software library. Volatile memory. Memory in which the contents will be lost if power is removed. von Neumann bottleneck. A situation in which the serial fetch and execution of instructions limits overall execution speed.

w
Wait and hold condition. The situation in which a task acquires a resourceand then does not relinquish it until it can acquire another resource. Wait operation. Operation on a semaphore that essentiallylocks the resourceprotected by the semaphore,or prevents the requestingtask from proceeding if the resourceis already locked. Wait state. Clock cycle used to synchronizemacroinsEuctionexecution with the access time of memory. Watchdog timer. issued. A device that must be reset periodically or a discrete signal is

I Glossary Wavefront processor. A multiprocessing architecture that consists of an array of identical processors, each with its own local memory and connected in a nearestneighbor topology. White box testing. Logic-driven testing-designedto exercise all paths in the module.

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Manual. series in computer [i51] Spivey, J., The Z Notation: A Reference Science.EnglewoodCliffs, N.J.: Prentice-Hall,1989. Systems-A [152] Stankovic, J., and Krithi Ramamritham.Hard Real-Time (IEEE), 1988' D.C': ComputerSciencePress Tutorial. Washington, C.Bttazzo. [153] Stankovic,JohnA., Maro Spuri, Marco Di Natale and Giorgio systems.IEEE Implications of classicalschedulingresults for real-time 6 Computer,2, (June1995):16-25. of Can the advantages RISC be utilized A., [154] Steininger, and H. Schweinzer. '91 Workshop Realon of Proceedings the Euronticro in real-timesystems? (1991):30-35. Paris TimeSystem.s. systems.New York: McGrawSaul. Real-TimeData-Processing [155] Stimler, Hill, 1969. languages, of [156] Stoyenko, A. D. Evolution and state-of-the-art real-time 18 (Apr'. 1992):6l-84' and Software Journal of Systems and E. Kligerman. Real-Time Euclid: A languagefor [157] Stoyenko,A. D., reliable real-time systems.IEEE Transactionson sofnvare Engineering SE-12(Sept.1986):940-949. N.J.: IEEE [158] Tripp, Leonard L. IEEE Standardscollection, Piscataway, Press,1994. Borland Interll59l Turbo C User's Guide Version2.0. Scotts Valley, Calif.: national,1988. for [160] Walpole,RonaldE., and RaymondH. Myers. Probability and Statistics Engineers and scientists. 2nd ed. New York: Macmillan Publishing, t978. [161] [162] of Warnier,J. D. Logical Construction Programs.New York: Van Nostrand Reinhold, 1974. Washabaugh,Douglas M., and Dennis Kafura. Incremental garbage collection of concurrentobjects for real-time applicationS. Proceedingsof the llth Real-Time systemssymposium.Lake Buena vista, Fla. (Dec. 1 9 9 0 )2 1 - 3 0 . : Wheeden,Richard L., and Antoni Zygmund. Measureand Integral. New York: Marcel Dekker, 1977. Wirth, Niklaus. Programmingin Modula-2.2nd ed. New York: SpringerVerlag,1983. Wulf, W., and Mary Shaw.Global variablesconsideredharmful. SIGPLAN Natices L 2 {J973); 28-34'

[163] [i64] [165]

lndex
Binary ree, definition, 28 Bit failures, 277 Black box testing,264-5 Blocked tasks, 181 BRANCH instructions, 38 Broadcastcommunication,133' 135 Buffer size calculation, 245-8 maximum, 248 M[\4/1 queue' 251 variable, 246-8 Buffering data,170-2 Buffering sYstem' 245 B u g s ,2 5 5 - 6 Built-in-softwaretest (BIST), 271 Built-in{est software(BITS)' 271' 2'16 Burn-in testing,267 Burst petiod, 245,248 Bursting of events, 146 Bursts of data,245-6 Bus,2 arbitration, 50 contention, 50 cycles,21-2 grant signal' 50 interface unit (BIU), 318 time-out signal, 51 transfer mechanisms, 2-3 Byzantine Generals' Problem' 286 Calling trees, 113-i4 CASE (comPuter-aidedsoftware engineering),110 Central processing unit (CPU), 2,

A
-3 0-address architecture, 25 I 3 1-3 1-addressarchitecture, 2-addressarchitecture, 33-5 3-addressarchitecture, 35 machine, instruction set' 26 O-address l-address machine, instruction set, 32 2-addressmachine' instruction set' 34 3-addressmachine, instruction set' 36 0-addressmachine, Programmlng'

20-r
oPeration, 4-7 structure,4 tesrifig, 27 l-2 throughput, 13 Chain reaction, i35 CheckPoints, 269-70 Checksum, 272 CICS (Customer Information 148 Control SYStem), queue (ring buffer), 171 Circular CISC (comPlex instruction sdt comPuters) architecture' 4 1-3 Class definitions' 70 Cleanroom testing, 268 cMS-2, l7 Code generation, 83-4 Code insPections,266 COHESION environment, 95 Collision,50' 175 COM variables, 63 COMMON variables, 63 Compaction' 200 Compare instructions,35-8 Compiler optimization techmques' 224-i2 combination effects' 233-4 common subexPresston elimination, 225 constant folding, 226 constant ProPagation' 229 crossjumP eliminadon' Ii:-l dead-storeeliminanon' ll9 dead-vanable ellmlnarex'- l-tr' fl ow-of-codlFoi r'OtrruDi:-ir- -li intrinsic runcc:'is- lit lmP Lr':uc-.-r :--::-rroYItF: .rtr: L\:r-.$l: -;:::f-::g.:":6 -:--:r-;g"ft-f'Ii^'tl]i i-{--

28-3r
Absract data tYPing' 68-71 Accumulator, 22 Activity Packets,292 Ada, 17,60, 61, 63, 65, 66, 11' 80-1, 150, 182,324 Ada-95, 8r-2, 324' 325 Ada++, 70 Address bus, 2 Addressingmodes,21-5 ALGOL-60, 63, 66 ALGOL-W 63 Alpha testing, 267 Analog+o-digital (A/D) circuitry, 53 ANSI-C, 78, 181 Aiplication Programs, 7 Adthmetic logic unit (ALU)' 4 Arithmetic oPerations,27 Assemblers, 8 21,82-3' lI2' AssemblYlanguages, 324 Asynchronous events, 12 Automatic teller machine, 118-20

c
C language,l'1, 60, 61, 65, 66"13' 75-8,83, 324,326 disadvantages,78 excePtion handling, 77-8 special variable tYPes,75-6 C++ language,70,78, 324' 326 Caches,227 Call-by-address,61-2 Call-bY-name, 63 Call-bY-reference,6 1-2 Call-bY-value' 61-2 Call-bY-value-result-63

B
Background, 156 Background Processing, 157-8 Banker's algorithm, 185-6 B A S I C , 1 7 , 6 0 , 6 3 , 6 5 , ' 1 3 , ' 7 4 '1 9 7 Bathtub curve, 257 Beta testing, 267 BinarY angular measurement (BAM), t?1-?

lll-:

-t<-s

356
Compiler optimization techniques \cont.) reduction in strength, 225 removal of dead or unreachable code,22'7-8 short-circuiting Boolean code, 230 speculative execulion, 234 use of arithmetic identities, 225 use of registers and caches,22'7 Compilers,8, 83-4 315-16 Complex systems, multimedia, 323 Computer architecturc, 2 Computer architectules, systems, multiprocessing Data flow architectures,292-4 Data flow diagrams, 120-4,133, 286,294 conventions,121 DeMarco's rules for, i21 for navigation system, 122 for nuclear plant, 123 Hatley and Pribhai's extensions,
1 a A

Index DRAGOON,70 65 Dynamicallocation, systems, 154 Dynamic-priority

E
Electropically erasable programmable read-only memory (EEPROM),47-8 Embedded data processor (EDP), 318 Embedded distribution systems, 283 Embedded systems, 10 Enable priority interrupt (EPI), 38-9 Enumerated types, 69 Erlang's loss formula, 253-4 ESTEREL, 60 Euclid, 326 Even parity checker, ll7 Event determinism, 12 Event flags, 181-3 Event signals,181-3 Events, 12, 144 bursting of, 146 Exception handling, 68 C language, 77-8 Executive, 143 Exponential distribution, 242, 243 Extemal fragmentation memory, 199

282-3
Computer hardware, 19-58 history, 17 prototypes/simulators,307 Computer hardware/software integration,301-13 Condition code registers (CCRs), 37 Conditional branching, 114 Conditional transfer, 37 Context, 150 Context-saving rule, 151 Context swirching, 150-l Contiguous file allocation, 204 Continuousprobability distribution. 242 Continuous random variable, 242 Continuous real-valued function, 222-3 Control flow diagram, 124 Control specifications, 124 contrbl unit (cU), 4 Cooperative multitasking systems, 148-50 Coprocessors,40-l Core memory, 44 Coroutines,148-50, 157 responsetime, 208 Counting semaphores,178-9 Critical regions, 175 Cross jump elimination, 231-2 CSML,60 Customers, 248 Cycle stealing, 46 Cyclic executive system, 149 Cycl ic redundancycode (CRC), 272-4 Cycling, 307 eychmatic c-or[plexiry, 260

Data flow processors,system specification, 293-4 Data Item Descriptions (DIDs), 99-100 Data strobe (DST), 2-3 Data transfer timing diagram, 3 Databases applications, 3 17-19 construction,3l7-18 design,317 Deadlock, 183-5 avoidance, 185-6 conditions necessaryfor, 183-4 detection of, 185-7 recovery 186-7 Death spiral, 277 DEBUG, 228 Debuggers, 307 Defects,255-6 Dernand paging, 201-3 DeMarco's rules for data flow diagrams,121 Descrete random variable, 243-4 Design, 109-40 Detailed design document, 9l Determinism,l2-13 Digital-to-analog (D/A) circuitry, 53 Direct memory access(DMA), 50-1,218,27',7 acknowledge signal (DMACK),

F
Failed system, definition, 9 Failure function, 257 Failures, 255-6 FALSE state, 3 Fault tolerance, 269 Faults, 255-6 Fetch-execute cycle, 5 Fiber Distributed Data Interface

50
controller, 50-l memory, 235 request signal (DMARQ,

50 transfer timing diagram, 51 Direct mode instructions, 22 Disable priority interrupt (DPI), 38-9 Discrete random variable, 241 Discrite signal, 3 Dispatcher, 142,149 Distributed systems, 283-91 reliability in, 286-91 DOD-STD-2I674 (ME-STD-

(FDDr), 318
204 File fragmentation, (FSA), 117, Finite stateautomata t33-4,146-:7 (FSMs),117 Finitq statemachines (FIFO),202 First-in/first-out 153-4 systems, Fixed-priority 150 Fixed-rate systems, Flash memory,48 Flip-flop, zt4-5 39, Floatingpoint instructions, 214, 215 Flow-of-control optimization,228 Flowcharts,ll2-13, ll4 156 Foreground,

D
Daemons, 175 Data bus, 2

2167A),99-rc4
Double buffering, 170 Double indirect mode addressing, 24-5

Index

357
Input/output (I/O) inteirupt driven, 48, 52 memory-mapped, 49-50, 235 m e t h o d s ,, 3 , 4 8 - 5 2 2 perfcrrmance, 239 programmed, 48-9 Input space,8 Inputs, 8 Instructioncounting.213-16 Instructionexecutiontime s i m u l a t o r s2 1 7 - l l i , Instructionregister,4 Integration,30l Internal fragmentation memory, 199 Interpolation,geometric interprctation, 222-3 Interpreter, 74 Irrterrupt, definition, 6 Interrupt controllers,54-5 Interrupt disabling,211 Interrupt driven I/O, 48, 52 Interrupt driven systems,150-6 Interrupt handlers,6, 182, 191, 195 Interrupt handling,5J, 311 timing sequence, 55 Intenupt latency, 21O-12 low priority interrupts high priority,212 Interrupt register 6 Interrupt retum location, 6 Interrupt systems,144-6 response1ime, 209 Intenupt vector, 6 Intertaskcommunication,169-88 Intrinsic functions, 226 ISO Standard9000, 103-4

Foreground,ibackground systems, l 56-60 initialization, 158 major drawback, 160 real-timeoperation,158-9 response times, 160 Formal program proving, 266-1 FORTRAN, 16, 1'7 60, 61, 63_6, . t 3 - 5 . 1 1 2 ,1 9 7 ,2 1 1 ,3 2 4 Freedomspacestation,318 Function points, 263 Fusible-linkROMs, 46 Fusible links, 46-7

L
Languagefeatures,59-85 comparison of, 74 see also specific languap,esand specific language features Least recently used (LRU) method 202 L e v e l i n g ,l 2 l Linkers, 8 Little's law, 253 Livelock,183 LOAD instruction,25, 28, 63 Load module, 302 Local area networks (LANs), 43, 315 Locality-of-reference method, 203*4 Locksup,271 Logic analyzer, 213, 304-5 Longmp,77 Look-up tables,222-4 Loop induction elimination, 227 Loop invariant optimization, 226 Loop jamming, 231 Loop unrolling, 230-l Loosely coupled system, 10 LSB (least significantbir,220

G
Garbagecollection,204 Gaussian(or normal) distribtion, 242 Gaussianprobability function, 243 Generalregisters, 4 Generator poly nomial, 272 Global variables,63-4 reuse,238 GOTO statemenr, 112, 113 Granularity, 220-1 Graphicaltechniques, design precautions, l38 Group walkthrou ghs, 266

H
Halstead'smetrics, 261-3 Hamming code error detection and cotection,274 Hard, enor,2'72 Harells statecharts, 136-7 Heisenberg uncertainty pnnciple, 307,310-12 Hybrid systems,150, 156

M
McCabe's metric, 260 Machine language,20, 83 Macrocode, 5 Macroinstruction execution times, 211 Macroinstructions, 5 Mailboxes, 173-5 and semaphores,177 implementation,173-4 queues,174-5 Major cycles, 155-6 Mask registeq 6 Mathematicalspecification,11l-12 Matrix multiplication, 65 Maximum stack size, 193 Mealy FSA, 117-18 Memory, 2, 43-8 analysisof requirementsi3-1-dangerousallocation- i !-r DMA,235 'ii i--: .l d y n a m i ca l l o c a l r . - r . extemal frasm3n-'rror-- ^, fragmei--:::::. l-'i l|]le;nal lnlSneri::]:.. -+. icckine. l0-r manasement schernes-l-1nonvolatile.43

J
Jacksonchart, 113 Java language, 326 JOVIAL, 17 Jump instructions,35-8 conditional and unconditional, 37-8 "Jump-to-self instruction, 150 Jump unconditional absolute (JUA),

I
IEEE 830-1993, 104 rEEE 1003 1-1990, 164-5 IEEE standards,106 If-then structure, 147 Image processin 319-24 g, Immediate mode instructions, 22 Implied mode instructions, 22 Incidence matrix,287 In-circuit emulation (ICE), 305-6 In-circuit emulator block diagram, 308 Indexed loop construct, 132-3 Indirect memory instructions, 23 Induction v ariable, 22'7 Inertial measurementunit (IMU), 10 Information hiding, 7l Inheritance, 70

38

K
Kalman filter, 269 Kemels build or buy?, 164 definitions, 142-3 design strategies, 141-67 hierarchy. 143 role of. 142

358
Memory (cont ) primary or main, 3 program arca,236 RAM area, 236 secondary,3 stack area, 236 static schemes,205 rcsiLn|,272 volatile, 43 Memory addressregister (MAR), 4 Memory data register (MDR), 4 Memory-loading,201, 312 rcducing,237-8 variable selection-23r Memory-loading f actot, 236-:7 Memory management, 189-205 Memory managementmodel, 196 Memory map,234-5 Memory-mapped l/o, 49 -50, 235 Messageexchanges, 173 Message polynomia| 2'12 Methods, 70 MFT (multiprogramming with a fixed number of tasks), 198-200 Microcode, 5 Microcontroller, 20 Microinstructions, 5 Micro-kemal, 143 Micromemory,4 Microprogram, 5 Mil-Std-15538 bus standard, 52-3 Mil-Std-2167A (DOD-STD-21674'), 99-100 MIMD archiiecture, 283 Minor cycles, 155-6 MISD architecture, 282 Mismatched COMMON overlays, 64 Missed intemrpts, 276-7 Mixed listing, 214 MMll queae,249-52 buffer size calculation, 251 real-time systems, 252 Modeling techniques, advantages and disadvantages,138 M o d u l a - 2 ,l ' 7 , 6 3 , 6 5 , 6 6 , 7 1 , 79-80, 150,183 Modularity, 7l-3 MODULE,71,79 Moore finite state automaton, 117 MSB (most significant bit),22A-1 MULT1,65 MULr2, 65 Multi Bus tr, 318 Multimedia architecture, 323 Multimedia systems,321-4 Multimeters, 304 Multiple stack anangements, 193 Multiplexer, 52 Multiplexer/demul tiplexer (MDM) units,318 Multiprocessingsystems, 124, 2, 129, r7 5, 260, 281-99, 3t5 classification of computer architectures,282-3 Multiprogramming, 129 Multitasking systems,79, 124, 146, 169, r',]5.260 Mutex, 177 MUX transceivers,52-3 MVT (multiprogramming with a variable number of tasks), 200-1

Index

P
Package,7 l-2 P a g ef a u l t , 2 0 1 Page frames, 201 Page stealing,201 Page table, 201 Parallel subsystems,equivalent reliability, 258 Parameterpassing, 60-73 Pamas partitioninE, 92-4, ll0, 265 Partial transition table, 120 P a s c a l ,1 7 , 6 0 , 6 I , 6 5 , 6 6 , ' 1 3 , 78-9, 83 Patching,308, 309-10 PEARL,326 Peephole optimization, 225 Petri nets, 124-9 examples,129 firing, 125 flowchart analogs,127 systolic array, 296-7 Phase-driven code, 146-8, l5'7, 208 Ping-pong buffering, 170 Pipelining, 39-40 Poissonprocess,244, 252 Polled loop systems, 144 response time, 146,208 with inrerrupts, 144-6 Polymorphism, 70 POP instruction, 27 POSIX standard,164-5, 318 Power bus, 2 keemption, 212 Preemptive priority systems, 153-5 Priority ceiling protocol (PCP), 155 Priority inversion, 155 Probability density function, 242 Probability distribution function, 241-3,248 Probe effect, 311 Process, 142 Processblocks, 258 hocessing elements, 294 Program counter (PC), 4 Program design languages (PDLs), I l5-16 Programmable logic arrays (PLAs), 46 hogrammable read-only memories (PROMs),46-7 Programmed I/O,48-9 Programming languages,324-6 Project Whirlwind, 316-17 Propagation delays, 211 Pseudocode,115-16 PUSH instruction, 28 -PUSH operation, 27

N
Nano-kemel, 143 Natural languages, 110-11 Nearest neighbor topolo1y, 294 Network interface unit (NIU), 318 No-op (no-operation), 5 Non-von Nuemann multiprocessing architectures, 21, 291-8 NP-completeproblems,218-19 NP-hard problem, 219 N-version programming, 271

o
Object-oriented programming, 70 Occam, 60 Occam-2,325 Odd parity checker, 118 Opcode (operation code), 5 Operating system, 8, 143 Operational concept document, 89 Optimization basic theory,223-32 peephole,225 techryqaes,224-32 Orbital replaceable units (ORU), 318 Qrganic distributed processing system,283 Organic systems, l0 Orthogonalstates,284 Orthogonality, 134 OS/2 PresentationManager, 148 Oscilloscope, 304 Ostrich algorithm, 186 Output space, 8 0utputs, 8 Overlaying, 198

Index

359
second-order,289 third-order, 290 Resource allocation, 185 Resourcesharing, 175 Resourcetable, 174 Response time,9,207 calculation,208-10 coroutines,208 interrupt systems, 209 modelling, 252 phase-driven code, 208 polled loops, 208 reducing,219-34 Restoreroutine, 191-2 Retum from interrupt (RI), 38 RETURN instruction, 38 Retum location,38 Reverse Polish notation, 28 Ring buffers, 171-2 RISC (reduced instruction set computer) architectures,4 1-3, 282,315 Round-robin systems, 152 Run-time ring buffer, 193 Run-time stack, 190 Single-event upset (SEU), 158 protection mechanisms, 277-8 Single-processing system,2 Slowest cycle computation, 220 Smalltalk, 70 Soft enor, 272 Software concepts, 7-8 d e s i g n ,i 1 0 Heisenberg uncertainty principle, 311 history, 17 reliability, 256-63 definition, 256 simulators, 306 testing,311-12 watchdog timers, 56, I57,276, 2',77 Software Design Descriptions (SDDs), 104 Software life cycle, 87-107 concept phase, 89 designphase,91-4 functional requirements, 90 maintenancephase, 96 nonfunctional requirements,90-l nontemporal transitions, 96-8 Pamas partitioning, 92-4 phases,activities and byproducts, 88-96 programming phase, 94-5 requirements phase, 89-91 rules for requirements and design documents, 91 standards, 99-107 test phase,95-6 version control software, 94 Spacestation,Freedom,318 SPARC (Special Application of RISC) series,42 Spatial fault tolerance, 269 Specification, 109-40 mathematical,111-12 Speculative execution, 234 Spin lock, 177 Spiral software model, 98

o
Queues,mailboxes,i74-5 Queuing models, 241-54 Queuing system, components, 249 Queuing theory,248-52 buffer calculations, 25 1 service and production rates, 250-7

R
Raise operation,181 Random-accessmemory (RAM), 43 corraplion,2T2 dynamic (DRAM),43 scrubbing,157-8, 274-5 static (SRAM), 43 testing,274-6 Randomvariable, 241 Rate-monotonic analysis (RMA), 155 Rate-monotonic systems, 154 Reactive systems, 10 Read-only mernory (ROM), 43 conuption,272 testing,272-4 Read/write line, 3 Real-time computing, 16 Real-time languages.See Language features and under specific languages Real-time systems, 1 applications,3l5-26 basic cpncepts,1-18 definition, 9 design issues,14 examples,14-16 full-featured, 160-3 history, 16-17 Mlivl/l queue, 252 significant development events, 16 use of term, 10-11 Recovery blocks, 270 Recursion, 64-5 Re-entrant procedures, 65 Register direct mode instnrctions,

S
SABRE, 16 Sample space, 241 Sampling rate, 53 Save routine, 191-2 Scale factor, 220 Scaled arithmetic, 220-l Schedualability analysis, 84 Scheduler, 142 Scheduling, NP-complete, 2 18-l 9 Scratch pad memory, 4 Screen signature, 274 Second-orderreliability matrix, 289 Self-modifying code, 238 Semaphores, 175-80 and mailboxes, 177 counting, 178-9 primitives, 176 problems with, 179 Semiconductor memory. 44-6 Semidetachedsystem, 10 Senseline, 44 Serially reusable resources, 175 Series subsystems,equivalent reliability, 259 Servers172,248 , Setjmp, 77 Signal library function call. 182 Signal operation. 176 SIMD architectures,282

24
Register indirect instructions, 24 Registers, 227 Regression testing, 267 Reliability, 256-63 characterizations,256 in distributed systems, 286-91 Reliability functions, 256-8 Reliability manix;.287-9 hiiher-order, 290-1 maximum,29l

sPool-, 175
Sporadicsystems.150 Sporadic tasks, 150 Spurious interrups. 276-l Stack, 38 architecture. 15 area.136 managemen.- 190-molel. i51 operations. 21 overflos.277

360
Standards,software develoPment' Task-controlblock (TCB), 161-3 model, 161, 190, l96J state transitions, 162 task management, 163 task states,161 Task resource request table, 173-4 Task synchronization, 169-88 Temporal determinism, 13 Temporal fault tolerance, 269 Test-and-setinstruction, 180 Test instructions, 37 Tesr log, 303 Test probe, 269-?0 Test tools, 303-7 Testing, 263-9 black box, 264-5 cleanroom, 268 TRUE state, 2 Type definition, 69 Typing, 66-8

Index

99-r07
Starvation,154, 183 State counters, 149 State-driven code, 146-9 133-8, 284 Statecharts, depth, 134 orthogonality, 134 Statistiqally based testing, 267-8 Status register, 6

U
Ultraviolet read-onlY memory

(uvRoM),47 UNIT,73
Universal asynchronousrelaY terminal (UART), 52

25, sToRE, 63
Stress, tesring, 269 Strong typing,66 Structurechans, 113-14 Analysis, 110, 120 Structured SUBROUTINE, 65, 73 Subroutine instructions, 35-8 Subsystems,reliabilities, 259 Swapping, 198 Switch bounce, 1zl4 Synchronous events, 12 Syndrome,274 System, definition, 8 Systembus, 2 System concePts,8-9 System integration backoff method, 308-9 establishing a baseline, 307-8 goals, 302-3 methodology, 307-10 System-level testing, 267 Systernperformanceanalysis,207-23 System programs, 7 System reliability, 258-63 284-6 System specification, data flow processors,293-4 for wavefront Processors,298 System test suite, 267 System unifrcation, 302 System validation, 303 Systolic anay for convolution, 295 in nearest neighbor toPologY' 295 peti net,296-:1 ots, 294-7 Systolic process . Systolic systems, specification, 297

3r8,324 uNrx, 143,
User space,198 Utilization factor, definition, 13

cPu,27r-2
goal of,263 memory,272 planning, 263-9 RAM, 274-6 ROM,272-4 software,311-12 statistically based, 267-8 stress,269 systemJevel, 267 unit level, 264-:7 white box, 265-6 Thrashing, 201 Threat-managementsystems, 154 Time-loading, 2O7 312 , and its measuremettt,212-18 deterministic Performance,218 instruction counting, 2 13-1 6 instruction execution time simulators,217-18 logic analYzer,2l3 pictorial representation,2 16-17 definition, 13 reducing,219-34 Time-overloaded sYstem, 13, 250 Time-relative buffering, 170-1 Time slice, 152 Timing code, 305 Timing instructions, 304-5 Transceiver,52 Transitibn Table, 118 Transputen, 298 Traps,7, 182 Tri-state condition, 50

V
Version control software, 94 Virtual reality (VR) systems, 320-l VLSL292,295 Von Neumann bottleneck, 39 Von Neumann computer architectures,20, j9, 282

W
Wait and hold condition, 185 Wait operation, 176 Wamier-Orr notation, 129-33 examples,tr31-2 Watchdog timer (WDT), 56, 157, 276,2"t7 Waterfall, 88 Wavefront processors,297-8 system specification for, 298 Weak typing, 66-8 Weibull distribu tion, 243 Weibull probabilitY densitY funcrtion, 243 -. Whirlwinil computer, 316-17 White box, testing, 265-6 Wide area networks (WANs), 315 Working sets, 203-4 World Wide Web, 113, 133

T
fable-driven code, 148 Task, 142

z
Z notation,110