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Homework 6 -Solution

Spring 2008

Problem 1

A NOR CMOS gate with the device/parasitic parameters below must drive (output to) the inputs of 3

NAND gates (one input on each gate) with the same MOSEFT gate dimensions as the NOR gate.

VDD = 2.0V, Cox = 2fF/m2, CDBp = 1fF, CDBn = 0. 5fF

(W/L)p= 4/0.5, kp =100A/V2, |Vtp| = 0.5V,

(W/L)n= 2/0.5, kn =250A/V2, Vtn = 0.6V,

a)

b)

c)

d)

What is the total parasitic capacitance at the output of the NOR gate?

What is the total load capacitance contributed by the 3 NAND gates?

What is the total capacitance at the output of the NOR gate?

What is the effective resistance between the output and VDD when the NOR gate pulls the output

high? Use the general formula for channel resistance.

e) Combining results from (c) and (d), what is the output RC time constant?

solution

a) A NOR gate has 1 pMOS and 2 NMOS drains at the output node.

Thus, Cpara = CDp + 2CDn

CDp = CGDp + CDBp AGp Cox + CDBp = (4*0.5)(2) + 1 = 3 fF

CDn = CGDn + CDBn AGn Cox + CDBn = (2*0.5)(2) + 0.5 = 1.5 fF

Cpara = 3 + 2(1.5) = 6 fF

b) Each input of a NAND gate goes to 1 pMOS and 1 nMOS transistor. The capacitive load

generated by gate (input) node of these transistors is just CGp + CGn.

Thus, CL = 3 (CGp + CGn) = 3 Cox (AGp + AGn) = 3 (2) (4*0.5 + 2*0.5)

CL = 18fF

c) Cout = Cpara + CL = 6 + 18 = 24fF

d) When the NOR gate pulls its output high, both series pMOS must be on.

Thus, Reff = 2 Rp,

Rp = [p(VDD-|Vtp|)]-1, p = kp (W/L) = 100 (4/0.5) = 800uA/V2

Rp = [800u(2.0-|0.5|)]-1 = 833

e) = Rp Cout = 833 (24f) = 20,000x10-15 = 20x10-12 = 20psec

Problem 2

For the problems below assume the following process parameters and constants: kn = 100 A/V2, kp =

40A/V2, Vtn=|Vtp|=0.5V, VSB = 0V and VDD = 2.5V. Ignore channel length modulation and other

secondary effects.

a) Use a computer (e.g., Excel, Matlab) to plot the I-V curve (ID vs. VD) for an nMOS transistor with

W=1.5m and L=0.6m, VS = 0V at VG = 1V. Plot ID vs. VD from 0V to 2.5V with at least 10

steps. Be sure to properly account for transitions between the triode and saturation (active) regions.

b) Repeat (a) at VG = 2V and VG = 2.5V. Include all three curves on the same plot.

p. 1

c) Repeat (a) and (b) for a pMOS device with W=3m, L=0.6m and VS = 2.5V and VG values of 2V,

1V, and 0V. Notice that to plot ID vs. VD, you will need to be careful how you represent the term

VSD. Done correctly, your plot should be similar to the one shown in HW4 solutions.

Solution

a & b)

Vds

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

2.2

2.4

2.5

Vg=1

0.0

20.0

30.0

31.3

31.3

31.3

31.3

31.3

31.3

31.3

31.3

31.3

31.3

31.3

Vg=2

0.0

70.0

130.0

180.0

220.0

250.0

270.0

280.0

281.3

281.3

281.3

281.3

281.3

281.3

c)

Vg=2.5

0.0

95.0

180.0

255.0

320.0

375.0

420.0

455.0

480.0

495.0

500.0

500.0

500.0

500.0

Vsd

2.5

2.3

2.1

1.9

1.7

1.5

1.3

1

0.8

0.6

0.4

0.2

0

0

1

Vg=1

12.5

12.5

12.5

12.5

12.5

12.5

12.5

12.5

12.5

12.5

12.0

8.0

0.0

0.0

2

Vg=2

112.5

112.5

112.5

112.5

112.5

112.5

112.5

100.0

88.0

72.0

52.0

28.0

0.0

0.0

2.5

Vg=2.5

200.0

200.0

200.0

199.5

195.5

187.5

175.5

150.0

128.0

102.0

72.0

38.0

0.0

0.0

250.0

600.0

Vg=1

Vg=1

500.0

200.0

Vg=2

Vg=2.5

Vg=2

Vg=2.5

150.0

ID (uA)

400.0

ID (uA)

Vds

0

0.2

0.4

0.6

0.8

1

1.2

1.5

1.7

1.9

2.1

2.3

2.5

2.5

300.0

200.0

100.0

50.0

100.0

0.0

0

0.0

0

0.5

1.5

2.5

0.5

1.5

-50.0

VD (V)

VD (V)

Problem 3

This problem deals with a CMOS inverter with the following parameters: VDD = 3V, Vtn = 0.6V, Vtp = 0.82V, kn = 100A/V2, n = 2.2p.

Solution

a) Determine the beta ratio,

1.3V.

n/ p,

p. 2

2.5

Problem 4

A CMOS inverter with minimum sized transistors has n =0.2mA/V2, p = 0.1mA/V2 and

Vtn=|Vtp|=0.6V.Assume VDD = 3.3V.

a) What is the inverter gate switching threshold (midpoint) voltage VM?

b) What is the resistance for each transistors using our general expression for MOSFET resistance in

saturation?

c) What are the rise and fall times of this circuit if the parasitic capacitance at the output is 9fF?

d) If a load capacitance, CL = 25fF is added to the output, what are the new rise and fall times?

e) What are the propagation delays for this circuit considering both parasitic and load capacitances?

Solution

a) VM =

1+

= 1.47V

1+ 2

1

= 1.85k

n (VDD Vtn ) (0.2)(2.7)

1

1

Rp =

=

= 3.7 k

p (VDD Vtp ) (0.1)(2.7)

b) Rn =

n

p

n

p

d) Here, Cout = 25+9 = 34fF, so

t HL = 2.2 Rn Cout = 2.2(1.85k)(34 fF ) = 138.5 ps

e) t HL = ln(2) Rn Cout = ln(2)(1.85k)(34 fF ) = 43.6 ps

Problem 5

A CMOS inverter is designed with p = 80A/V2, n =0.25mA/V2, Vtn=|Vtp|=0.5V and VDD = 2.5V.

The total capacitance at the output is 50fF

a) Using our general expression for MOSFET resistance in saturation, what is the resistance for each

transistor?

b) What is the rise time of this circuit?

c) What is the fall time of this circuit?

d) What is the high-to-low propagation delay for this inverter?

e) What is the low-to-high propagation delay for this inverter?

f) Do the relative results (rise vs. fall time, high-to-low vs. low-to-high propagation delay) make sense

considering the relative pMOS and nMOS beta values? Briefly explain why or why not.

Solution:

1

= 2.0k

n (VDD Vtn ) (0.25 10 )(2.5 0.5)

1

1

Rp =

=

= 6.25k

3

p (VDD Vtp ) (0.08 10 )(2.5 0.5)

a) Rn =

p. 3

c) t f = 2.2 Rn Cout = 2.2(2k)(50 fF ) = 220 ps

d) t HL = ln(2) Rn Cout = ln(2)(2k)(50 fF ) = 69.3 ps

e) t LH = ln(2) R p C out = ln(2)(6.25k)(50 fF ) = 217 ps

f) Because bn > bp, we should expect the fall time and high-to-low delay to be

lower (faster) than the rise time and low-to-high delay. Calculation results confirm.

Problem 6

A clever ECE410 student has noticed that the simulated worst-case rise time of a CMOS NAND gate is

actually slower than the worst-case fall time, contrary to calculations based on the models give in class.

The student proposes that a more accurate model of the NAND gate worst-case rise time should include

an additional parameter.

a) Specify the input transition sequence that would produce the worst-case rise time. Refer to your results

from Lab 4 if necessary. Format your response like AB CD, where the first number represents the

input to the series transistor that is connected to the output.

b) Sketch an RC model of the NAND gate during this transition including all parasitic capacitances and

resistances for all transistors that are turned on.

c) Derive an improved equation for the worst-case rise time based on your RC model. You should see

that an additional term is necessary to more accurately model this transition.

d) Based on this improved mode, will the worst-case rise time always be longer than the worst-case fall

time? Briefly explain.

Solution

a) The worst-case rise time occurs when 11 10, turning off the

nMOS connected to ground but leaving the nMOS connected to the

output turned on. Only one pMOS is turned on to pull the output

high.

b) The RC model shown here includes the resistance of the nMOS

transistor that remains on during the 1110 transition and is

connected to the output which is changed from low to high during

this input transition.

VDD

Rp

Cout

Rn

Cx

c) For the RC circuit shown here there are two time constants,

RpCout, and (Rp+Rn)Cx. The rise time is thus,

tr = 2.2 (RpCout + (Rp+Rn)Cx)

d) No, it wont always be longer. The rise and fall times are given by

tr = 2.2 (RpCout + (Rp+Rn)Cx)

tf = 2.2 (2RnCout + RnCx)

Depending on the ratio Cout/Cx and the ratio Rp/Rn, the fall time could be longer than the

rise time. For example, if Rp<2Rn and Cout>>Cx the fall time will be longer. Thus, the size

of the transistors and the output load capacitance will determine which output transition

is slowest. This is a feature of the NAND gate, which has very similar rise and fall

characteristics, unlike the NOR gate where there is an obvious distinction and the fall

time is always faster than the rise time.

p. 4

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