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- 1 Introduction MSP430

You are on page 1of 35

Computer

computer

Different computers have different

instruction sets

instruction sets

2.1 Introduction

Instruction Set

Simplified implementation

instruction sets

Chapter 2 Instructions: Language of the Computer 2

Stanford MIPS commercialized by MIPS

Technologies (www.mips.com)

Large share of embedded core market

equipment, cameras, printers,

Appendixes B and E

add a, b, c # a gets b + c

All arithmetic operations have this form

Design Principle 1: Simplicity favours

regularity

Arithmetic Operations

Simplicity enables higher performance at

lower cost

Chapter 2 Instructions: Language of the Computer 4

Arithmetic Example

C code:

f = (g + h) - (i + j);

add t0, g, h

add t1, i, j

sub f, t0, t1

# temp t0 = g + h

# temp t1 = i + j

# f = t0 - t1

operands

MIPS has a 32 32-bit register file

Assembler names

Numbered 0 to 31

32-bit data called a word

$t0, $t1, , $t9 for temporary values

$s0, $s1, , $s7 for saved variables

Register Operands

C code:

f = (g + h) - (i + j);

f, , j in $s0, , $s4

add $t0, $s1, $s2

add $t1, $s3, $s4

sub $s0, $t0, $t1

Memory Operands

Store result from register to memory

c.f. Little Endian: least-significant byte at least address

Chapter 2 Instructions: Language of the Computer 8

C code:

g = h + A[8];

g in $s1, h in $s2, base address of A in $s3

lw $t0, 32($s3)

add $s1, $s2, $t0

offset

# load word

base register

C code:

A[12] = h + A[8];

h in $s2, base address of A in $s3

Index 8 requires offset of 32

lw $t0, 32($s3)

# load word

add $t0, $s2, $t0

sw $t0, 48($s3)

# store word

memory

Operating on memory data requires loads

and stores

as much as possible

variables

Register optimization is important!

Chapter 2 Instructions: Language of the Computer 11

Immediate Operands

addi $s3, $s3, 4

addi $s2, $s1, -1

case fast

Immediate operand avoids a load instruction

Chapter 2 Instructions: Language of the Computer 12

Cannot be overwritten

add $t2, $s1, $zero

n 1

x = x n1 2

+ x n2 2

+ L + x1 2 + x 0 2

Range: 0 to +2n 1

Example

n2

= 0 + + 123 + 022 +121 +120

= 0 + + 8 + 0 + 2 + 1 = 1110

Using 32 bits

0 to +4,294,967,295

Chapter 2 Instructions: Language of the Computer 14

n 1

x = x n1 2

+ x n2 2

+ L + x1 2 + x 0 2

Range: 2n 1 to +2n 1 1

Example

n2

= 1231 + 1230 + + 122 +021 +020

= 2,147,483,648 + 2,147,483,644 = 410

Using 32 bits

2,147,483,648 to +2,147,483,647

Chapter 2 Instructions: Language of the Computer 15

0 for non-negative numbers

Non-negative numbers have the same unsigned

and 2s-complement representation

Some specific numbers

1: 1111 1111 1111

Most-negative: 1000 0000 0000

Most-positive: 0111 1111 1111

Signed Negation

Complement means 1 0, 0 1

x + x = 1111...1112 = 1

x + 1 = x

Example: negate +2

2 = 1111 1111 11012 + 1

= 1111 1111 11102

Chapter 2 Instructions: Language of the Computer 17

Sign Extension

lb, lh: extend loaded byte/halfword

beq, bne: extend the displacement

2: 1111 1110 => 1111 1111 1111 1110

Chapter 2 Instructions: Language of the Computer 18

MIPS instructions

Encoded as 32-bit instruction words

Small number of formats encoding operation code

(opcode), register numbers,

Regularity!

Register numbers

$t8 $t9 are regs 24 25

$s0 $s7 are regs 16 23

Representing Instructions

op

rs

rt

rd

shamt

funct

6 bits

5 bits

5 bits

5 bits

5 bits

6 bits

Instruction fields

rs: first source register number

rt: second source register number

rd: destination register number

shamt: shift amount (00000 for now)

funct: function code (extends opcode)

Chapter 2 Instructions: Language of the Computer 20

R-format Example

op

rs

rt

rd

shamt

funct

6 bits

5 bits

5 bits

5 bits

5 bits

6 bits

special

$s1

$s2

$t0

add

17

18

32

000000

10001

10010

01000

00000

100000

000000100011001001000000001000002 = 0232402016

Chapter 2 Instructions: Language of the Computer 21

Hexadecimal

Base 16

0

1

2

3

4 bits per hex digit

0000

0001

0010

0011

4

5

6

7

0100

0101

0110

0111

8

9

a

b

1000

1001

1010

1011

c

d

e

f

1100

1101

1110

1111

Chapter 2 Instructions: Language of the Computer 22

rs

rt

constant or address

6 bits

5 bits

5 bits

16 bits

op

Constant: 215 to +215 1

Address: offset added to base address in rs

compromises

instructions uniformly

Keep formats as similar as possible

Chapter 2 Instructions: Language of the Computer 23

The BIG Picture

Instructions represented in

binary, just like data

Instructions and data stored

in memory

Programs can operate on

programs

compiled programs to work

on different computers

Standardized ISAs

Operation

Java

MIPS

Shift left

<<

<<

sll

Shift right

>>

>>>

srl

Bitwise AND

&

&

and, andi

Bitwise OR

or, ori

Bitwise NOT

nor

Logical Operations

groups of bits in a word

Chapter 2 Instructions: Language of the Computer 25

Shift Operations

rs

rt

rd

shamt

funct

6 bits

5 bits

5 bits

5 bits

5 bits

6 bits

Shift left logical

op

sll by i bits multiplies by 2i

srl by i bits divides by 2i (unsigned only)

Chapter 2 Instructions: Language of the Computer 26

AND Operations

$t2

$t1

$t0

OR Operations

$t2

$t1

$t0

NOT Operations

Change 0 to 1, and 1 to 0

a NOR b == NOT ( a OR b )

Register 0: always

read as zero

$t1

$t0

condition is true

Conditional Operations

j L1

Compiling If Statements

C code:

if (i==j) f = g+h;

else f = g-h;

f, g, in $s0, $s1,

bne

add

j

Else: sub

Exit:

$s0, $s1, $s2

Exit

$s0, $s1, $s2

Assembler calculates addresses

Chapter 2 Instructions: Language of the Computer 31

C code:

while (save[i] == k) i += 1;

Loop: sll

add

lw

bne

addi

j

Exit:

$t1,

$t1,

$t0,

$t0,

$s3,

Loop

$s3, 2

$t1, $s6

0($t1)

$s5, Exit

$s3, 1

Basic Blocks

with

No branch targets (except at beginning)

blocks for optimization

An advanced processor

can accelerate execution

of basic blocks

Otherwise, set to 0

slt $t0, $s1, $s2

bne $t0, $zero, L

#

branch to L

Hardware for <, , slower than =,

per instruction, requiring a slower clock

All instructions penalized!

This is a good design compromise

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