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High Voltage Synchronous Rectified Dual-Channel Buck
MOSFET Driver for Notebook Computer
General Description


The RT9627A is a high frequency, dual-channel driver
specifically designed to drive two power N-MOSFETs in
each channel of a synchronous-rectified Buck converter
topology. It is especially suited for mobile computing
applications that require high efficiency and excellent
thermal performance. This driver, combined with Richtek's
series of multi-phase Buck PWM controllers, provides a
complete core voltage regulator solution for advanced

The drivers are capable of driving a 3nF load with fast
rising/falling time and fast propagation delay. This device
implements bootstrapping on the upper gates with only a
single external capacitor. This reduces implementation
complexity and allows the use of higher performance, cost
effective, N-MOSFETs. Adaptive shoot through protection
is integrated to prevent both MOSFETs from conducting

Dual-Channel Driver
Each Channel Drives Two N-MOSFETs
Adaptive Shoot-Through Protection
Ω On-Resistance, 4A Sink Current Capability
Supports High Switching Frequency
Tri-State PWM Input for Power Stage Shutdown
Output Disable Function
Integrated Boost Switch
Low Bias Supply Current
VCC POR Feature Integrated
RoHS Compliant and Halogen Free


Core Voltage Supplies for Intel ® / AMD ® Mobile
High Frequency Low Profile DC/DC Converters
High Current Low Output Voltage DC/DC Converters
High Input Voltage DC/DC Converters

Simplified Application Circuit



























Copyright © 2014 Richtek Technology Corporation. All rights reserved.

DS9627A-02 August 2014


is a registered trademark of Richtek Technology Corporation.

All rights reserved. LGATE1 Low Side Gate Drive Outputs. DS9627A-02 August 2014 . PWM2 Control Inputs for Drivers. Connect to the Gates of high side power UGATE2 N-MOSFETs. both UGATEx and LGATEx are driven low and the normal operation is disabled. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. These pins provide return paths for the high side gate drivers. The PWM signal can enter three distinct states during operation. BOOT2 Bootstrap Supply for High Side Gate Drives. www. PHASE1 Switch Nodes. 5 10 Copyright © 2014 Richtek Technology Corporation. 12 PHASE2. Connect these pins to the PWM outputs of the controller. The bootstrap capacitors provide the charge to turn on the high side MOSFETs. EN Enable Control Input. 11 LGATE2. Place a high quality bypass capacitor from this pin to GND. VCC Supply Voltage Input. Connect this pin to a 5V bias 2 is a registered trademark of Richtek Technology Corporation. Marking Information 0H= : Product Code 0H=YM DNN YMDNN : Date Code Functional Pin Description Pin No. Connect these pins to the Sources of the high side MOSFETs and the Drains of the low side MOSFETs. Connect the bootstrap capacitors between these pins and the PHASEx pins. High Side Gate Drive Outputs.RT9627A Ordering Information Pin Configurations Package Type QW : WDFN-12L 3x3 (W-Type) (Exposed Pad-Option 1) Lead Plating System G : Green (Halogen Free and Pb Free) UGATE1 BOOT1 PWM1 PWM2 EN BOOT2 1 2 3 4 5 6 GND (TOP VIEW) RT9627A 13 12 11 10 9 8 7 PHASE1 LGATE1 VCC LGATE2 PHASE2 UGATE2 WDFN-12L 3x3 Note : Richtek products are :  RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. Connect to the Gates of the low side power N-MOSFETs. 1. 9. 8.richtek. 4 PWM1.  Suitable for use in SnPb or Pb-free soldering processes. When pulling low. 7 Pin Name Pin Function UGATE1. 3. 2. 13 (Exposed Pad) GND Ground. 6 BOOT1.

If PWMx input is within the shutdown window. both UGATEx and LGATEx will be pulled to low. Thus. Copyright © 2014 Richtek Technology Corporation. All rights reserved. low side MOSFET can be turned on only after high side MOSFET is effectively turned off. the POR pin output voltage (POR output) is high.richtek. both UGATEx and LGATEx outputs are low. DS9627A-02 August 2014 Shoot-Through Protection Shoot-through protection block implements the dead-time when both high side and low side MOSFETs are turned off. and shutdown state. UGATEx and LGATEx can be controlled by PWMx input voltage.1V or phase voltage below 2V. If the POR pin voltage is low. When PWMx input is higher than its rising threshold. When the POR pin voltage is high.RT9627A Function Block Diagram VCC BOOT1 POR UGATE1 EN Control Logic VCC Shoot-Through Protection PHASE1 VCC R LGATE1 Tri-State Detect PWM1 GND R BOOT2 UGATE2 VCC Control Logic R Shoot-Through Protection VCC Tri-State Detect PWM2 PHASE2 R LGATE2 Operation POR (Power On Reset) Control Logic POR block detects the voltage at the VCC pin. When the VCC pin voltage is higher than POR rising threshold. UGATEx is low and LGATEx is high. There are three PWMx input modes which are 3 . With shoot-through protection block. UGATEx is high and LGATEx is low. is a registered trademark of Richtek Technology Corporation. shoot-through between high side and low side MOSFETs is prevented. UGATEx and LGATEx can be controlled by PWMx input. www. POR output is low when VCC is not higher than POR rising threshold. When PWMx input is lower than its falling threshold. Tri-State Detect When both POR output and ENx pin voltages are high. Control logic block detects whether high side MOSFET is turned off by monitoring (UGATEx − PHASEx) voltages below 1. high side and low side MOSFETs are never turned on simultaneously. To prevent the overlap of the gate drives during the UGATEx pull low and the LGATEx pull high. low.

richtek. PD @ TA = 25°C WDFN-12L 3x3 ------------------------------------------------------------------------------------------------------------ Package Thermal Resistance (Note 2) WDFN-12L 3x3.5V −0. 10 sec.3V to 6V −0.28W 30. TA = 25°C. θJA ------------------------------------------------------------------------------------------------------WDFN-12L 3x3. www.3V to 6V −5V to 7. VCC ----------------------------------------------------------------------------------------------------Ambient Temperature Range -------------------------------------------------------------------------------------------Junction Temperature Range -------------------------------------------------------------------------------------------- 4. θJC ------------------------------------------------------------------------------------------------------ Junction Temperature ---------------------------------------------------------------------------------------------------- Lead Temperature (Soldering.1 V VPORL VCC POR Falling 3.5V −40°C to 85°C −40°C to 125°C Electrical Characteristics (VCC = 5V.RT9627A Absolute Maximum Ratings (Note 1) Supply Voltage. VEN = 3.) ------------------------------------------------------------------------------ Storage Temperature Range ------------------------------------------------------------------------------------------- ESD Susceptibility (Note 3) HBM (Human Body Model) ---------------------------------------------------------------------------------------------  Recommended Operating Conditions     −0.4 3. PWM = 0V -- 0 5 A VPORH VCC POR Rising -- 3. EN to GND ----------------------------------------------------------------------------------------------------- Power Dissipation.5°C/W 150°C 260°C −65°C to 150°C 2kV (Note 4) Input Voltage. All rights reserved.5°C/W 7. 10mA -- -- 80  VCC Power On Reset (POR) Internal BOOT Switch Internal Boot Switch On Resistance Copyright © 2014 Richtek Technology Corporation.5V to 26V 4.5V to 7. DS9627A-02 August 2014 .3V -- 120 -- A Shutdown Current ISHDN VEN = 0V.5V to 5.85 4.3V to 6V −0.65 -- V VPORHYS Hysteresis -- 200 -- mV RBOOT VCC to BOOT. unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit VCC Supply Current Quiescent Current IQ PW M Pin Floating.3V to 6V 3.5V − 4 is a registered trademark of Richtek Technology Corporation.3V to 6V −2. VCC ----------------------------------------------------------------------------------------------------BOOTx to PHASEx ------------------------------------------------------------------------------------------------------ PHASEx to GND DC ----------------------------------------------------------------------------------------------------------------------------< 20ns ---------------------------------------------------------------------------------------------------------------------- UGATEx to PHASEx DC ----------------------------------------------------------------------------------------------------------------------------< 20ns ---------------------------------------------------------------------------------------------------------------------- LGATEx to GND DC ----------------------------------------------------------------------------------------------------------------------------< 20ns ---------------------------------------------------------------------------------------------------------------------- PWMx.3V to 32V −8V to 38V −0. VIN --------------------------------------------------------------------------------------------------------Supply Voltage.

Note 3.5 --  LGATEx Driver Sink Current ILGATEsk VLGATE = 2.RT9627A Parameter Symbol Test Conditions Min Typ Max Unit VPWM = 5V -- 174 -- VPWM = 0V -- 174 -- A PWMx Input Input Current IPWM PWMx Tri-State Rising Threshold VPWMH 3. The device is not guaranteed to function outside its operating conditions.5V -- 4 -- A Note 5 .richtek. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. Note 4. θJC is measured at the exposed pad of the package.1 V PWMx Tri-State Falling Threshold VPWML 0. and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied.7 1 1.5V -- 2 -- A UGATEx Driver Sink Resistance RUGATEsk 100mA Sink Current -- 1 --  UGATEx Driver Sink Current IUGATEsk VUGATE VPHASE = 2. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. Devices are ESD sensitive. Handling precaution recommended. These are stress ratings only.8 4.3 V Tri-State Shutdown Hold-off Time tSHD_Tri 100 175 250 ns EN Input EN Input Voltage Logic-High VENH 2 -- -- Logic-Low VENL -- -- 0. Exposure to absolute maximum rating conditions may affect device reliability.5 3.5V -- 2 -- A LGATEx Driver Source Resistance RLGATEsr 100mA Source Current -- 1 --  LGATEx Driver Source Current ILGATEsr VLGATE = 2. The human body mode is a 100pF capacitor is charged through a 1. All rights reserved.5 V Switching Time UGATEx Rise Time tUGATEr 3nF load -- 8 -- ns UGATEx Fall Time tUGATEf 3nF load -- 8 -- ns LGATEx Rise Time tLGATEr 3nF load -- 8 -- ns LGATEx Fall Time UGATEx Turn-Off Propagation Delay LGATEx Turn-Off Propagation Delay UGATEx Turn-On Propagation Delay LGATEx Turn-On Propagation Delay UGATEx/LGATEx Tri-State Propagation Delay Output tLGATEf 3nF load -- 4 -- ns tPDLU Outputs Unloaded -- 35 -- ns tPDLL Outputs Unloaded -- 35 -- ns tPDHU Outputs Unloaded -- 20 -- ns tPDHL Outputs Unloaded -- 20 -- ns tPTS Outputs Unloaded -- 35 -- ns UGATEx Driver Source Resistance RUGATEsr 100mA Source Current -- 1 --  UGATEx Driver Source Current IUGATEsr VUGATE VPHASE = 2. Copyright © 2014 Richtek Technology Corporation.5V -- 2 -- A LGATEx Driver Sink Resistance RLGATEsk 100mA Sink Current -- 0. Note 2. DS9627A-02 August 2014 is a registered trademark of Richtek Technology Corporation. www.5kΩ resistor into each pin.

DS9627A-02 August 2014 .3nF R8 2.2µH VIN VBAT C8 C9 C10 C11 C12 C13 C2 1µF R2 2 BOOT1 R1 R3 1 10 VCC UGATE1 C1 RT9627A 1µF 12 PHASE1 VCC Enable 5 EN PWM1 3 PWM1 LGATE1 PWM2 13 (Exposed Pad) 11 R4 7 R6 QUG1 L2 1µH VCORE C3 3.richtek.2 Timing Diagram PWM tPDLL 90% tPDLU LGATE 1.5V tPDHU Copyright © 2014 Richtek Technology Corporation. All rights reserved.5V 1.RT9627A Typical Application Circuit L1 2.2 VIN UGATE2 4 C14 PWM2 BOOT2 6 8 PHASE2 QUG2 R5 C15 1µF L3 1µH GND LGATE2 9 R7 QLG2 C16 3.5V 90% UGATE 1. www.3nF QLG1 C4 C5 C6 C7 R5 6 1.5V tPDHL is a registered trademark of Richtek Technology Corporation.

RT9627A Typical Operating Characteristics Driver Enable Driver Disable UGATE (50V/Div) UGATE (50V/Div) PHASE (20V/Div) PHASE (20V/Div) LGATE (10V/Div) LGATE (10V/Div) EN (10V/Div) EN (10V/Div) VIN = 19V. DS9627A-02 August 2014 Full Load Time (20ns/Div) is a registered trademark of Richtek Technology Corporation. 7 .richtek. No Load Time (2μs/Div) Time (2μs/Div) PWM Rising Edge PWM Falling Edge PWM (10V/Div) PWM (10V/Div) UGATE (20V/Div) UGATE (20V/Div) PHASE (20V/Div) PHASE (20V/Div) LGATE (5V/Div) LGATE (5V/Div) Time (20ns/Div) Time (20ns/Div) Dead Time Dead Time (5V/Div) UGATE UGATE PHASE PHASE LGATE (5V/Div) LGATE Full Load Time (20ns/Div) Copyright © 2012 2014 Richtek Technology Corporation. All rights reserved. No Load VIN = 19V.

RT9627A Dead Time Dead Time UGATE UGATE PHASE PHASE (5V/Div) (5V/Div) LGATE LGATE No Load No Load Time (20ns/Div) Time (20ns/Div) Short Pulse UGATE UGATE .richtek. All rights reserved.PHASE PHASE LGATE (5V/Div) No Load Time (20ns/Div) Copyright © 2014 Richtek Technology 8 is a registered trademark of Richtek Technology Corporation. www. DS9627A-02 August 2014 .

The required gate drive currents are calculated as follows. In contrast. LGATEx signal is then allowed to go high. The Power On Reset (POR) circuit monitors the supply voltage at the VCC pin. the PWMx signal takes over the control. Enable and Disable The RT9627A includes an EN pin for sequence control. the non-overlap circuit monitors the LGATEx voltage. By Copyright © 2014 Richtek Technology Corporation. waiting for the voltages of the PHASEx pin and high side gate drive to fall below their threshold.RT9627A Application Information Supply Voltage and Power On Reset The RT9627A is designed to drive two sets of both high side and low side N-MOSFETs through two externally input PWMx control signals. UGATEx is allowed to go high. When LGATEx go below 9 . Equivalent Circuit and Associated Waveforms is a registered trademark of Richtek Technology Corporation. It is also required to switch Drain current on and off with the required speed. D1 Three State PWM Input After initialization. A minimum 1μF ceramic capacitor is recommended to bypass the supply voltage. the non-overlap protection circuit ensures that UGATEx is low before LGATEx pulls high. the current could be negligible. Thus. Non-overlap Control To prevent the overlap of the gate drives during the UGATEx pull low and the LGATEx pull high. the RT9627A begins a new initialization and follows the PWMx command to control the UGATEx and LGATEx. the controller resets and prepares for operation. Also to prevent the overlap of the gate drives during LGATEx pull low and UGATEx pull high. However. www. The rising PWMx signal first forces the LGATEx signal low and then allows the UGATEx signal to go high right after a non-overlapping time to avoid shoot-through current.1V. the non-overlap circuit monitors the voltages at the PHASEx node and high side gate drive (UGATEx − PHASEx). Place the bypassing capacitor physically near the IC. When the PWMx input signal goes low. the nonoverlap protection circuit ensures that the monitored (UGATEx − PHASEx) voltages have gone below 1. LGATEx begins to turn high. Before LGATEx can pull high. UGATEx and LGATEx are held low before VCC is above the POR rising threshold.richtek. If VCC exceeds the POR rising threshold voltage. UGATEx begins to pull low (after propagation delay). Driving Power MOSFETs The DC input impedance of the power MOSFET is extremely high. the falling PWMx signal first forces UGATEx to go low. The gate draws the current only for few nano-amperes. When the EN pin rises above the VENH trip point.1V or phase voltage is below 2V. the capacitance at the Gate to Source terminal should be considered. Once the monitored voltages fall below the threshold. It requires relatively large currents to drive the Gate up and down rapidly. When the EN pin falls below the VENL trip point. DS9627A-02 August 2014 d1 s1 PHASEx VIN L VOUT Cgs1 Cgd1 Cgd2 Igs1 Igd1 Ig1 g1 d2 Ig2 Igd2 g2 D2 Igs2 Cgs2 s2 GND Vg1 VPHASEx +5V t Vg2 5V t Figure1. once the gate has been driven up to “ON” level. the RT9627A shuts down and keeps UGATEx and LGATEx low. Connect 5V to VCC to power on the RT9627A. All rights reserved. When the UGATEx or PHASEx signal reach a predetermined low level.

367 (A) (6) RT9627A. respectively. from the equation (1) and (2) we can obtain : Igs2  1660 x 10-12 x 5 14 x 10-9 2200 x 10-12 x 5 30 x 10-9 Igd2  380 x 10-12 x 5 14 x 10-9  0.richtek. the Cgd2 have been charged to VIN. tr1 and tr2 are the rising time of the high side and the low side power MOSFETs respectively. Crss = 500pF and tr = 30ns. Thus. It is recommended to adopt a ceramic or tantalum capacitor. Cgs1 and Cgs2. The VCB (the voltage difference between BOOTx and PHASEx on RT9627A) provides a voltage to the Gate of the high side power MOSFET. Select the Bootstrap Capacitor Figure 2 shows part of the bootstrap circuit of the Cgs1 x 5 Before driving the Gate of the high side MOSFET up to 5V. to minimize the risk of overcharging and to reduce the ripple on VCB.283 (A) (8) the total current required from the gate driving source can be calculated as following equations : Ig1  Igs1  Igd1   0. It is determined by following constraints. Vg1 = Vg2 = 5V. www.367  0. Assume a synchronous rectified Buck converter. This supply needs to be ensured that the MOSFET can be driven. the low side MOSFET has to be off.729 (A) (9) Ig2  Igs2  Igd2   0. (3) and (4) Copyright © 2014 Richtek Technology Corporation.65 (A) (10) By a similar calculation. as Cgd2 reverses its polarity and g2 is charged up to 5V. the bootstrap capacitor should not be smaller than 0. Cgd1 and Cgd2 are the capacitors from Gate to Drain of the high side and the low side power MOSFETs. a low value capacitor CB will lead to the over charging that could damage the IC. The high side MOSFET is PHB83N03LT whose Ciss = 1660pF.136 (A) 500 x 10-12 x 12 + 5  30 x 10-9 (7)  0. In general design.RT9627A In Figure 1. the Cgs1 and C gs2 are referred as “Ciss” which are the input capacitors. the high side MOSFET is turned off before the low side is turned on. and tr = 14ns. the capacitance C B has to be selected properly.593 (A) (5)  0.593  0. For this. the required current Igs1 and Igs2.1μF. All rights reserved. the current Ig1 and Ig2 are required to move the gate up to 5V. Cgd2 . and the larger the better. dV 5 Igd1  Cgd1  Cgd1 (3) dt tr1 Igs1  Igd1   0. The operation consists of charging Cgd1. In general data sheets. VIN BOOTx UGATEx PHASEx CB + VCB - VCC LGATEx GND Figure 2. Cgs1 and Cgs2 are the capacitors from Gate to Source of the high side and the low side power MOSFETs. we can also get the sink current required from the turned off MOSFET. the body diode “D2” had been turned on before high side MOSFETs turned on. using 1μF can provide better 10 is a registered trademark of Richtek Technology Corporation.136   0. DS9627A-02 August 2014 . From Figure 1. Part of Bootstrap Circuit of RT9627A In practice. Therefore. Crss = 380pF. from equation. the required current is : dV Vi  5 Igd2  Cgd2  Cgd2 dt tr2 (4) It is helpful to calculate these currents in a typical case. The low side MOSFET is PHB95N03LT whose Ciss = 2200pF. input voltage VIN = 12V. respectively and referred to the data sheets as “Crss” the reverse transfer capacitance. At least one low ESR capacitor should be used to provide good local de-coupling. For example. are shown as below : Igs1  Cgs1 Igs2  Cgs1 dVg1 dt dVg2 dt   Cgs1 x 5 (1) tr1 (2) tr2 Before the low side MOSFET is turned on.283   0.

The derating curve in Figure 3 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. All rights reserved.6 1.8 0. carrying the large gate drive current pulses. θJA. should be as heavy as the gate drive trace. and difference between junction and ambient temperature. TA is the ambient temperature. rate of surrounding airflow. PWMx PHASEx EN COUT QLGx PHB95N03LT C1 PWM Signal 5V GND LGATEx Figure 4. it will generate a large amount of EMI.8 2. Furthermore. θJA.6 Four-Layer PCB 3. and LGATEx should also be short to decrease the noise of the driver output signals. The power circuit section is the most critical one. The bypass capacitor C1 should be connected to GND directly.5°C/W) = 3. is 30. The maximum power dissipation at TA = 25°C can be calculated by the following formula : PD(MAX) = (125°C − 25°C) / (30. it should be very careful.0 1. θJA. do not exceed absolute maximum junction temperature. VCORE PHB83N03LT + where TJ(MAX) is the maximum junction temperature. the bootstrap capacitors (CB) should always be placed as close to the pins of the IC as possible.0 0 25 50 75 100 125 Ambient Temperature (°C) Figure 3. DS9627A-02 August 2014 is a registered trademark of Richtek Technology Corporation.28W for WDFN-12L 3x3 package The maximum power dissipation depends on the operating ambient temperature for fixed T J(MAX) and thermal resistance. Derating Curve of Maximum Power Dissipation Copyright © 2014 Richtek Technology Corporation. and θJA is the junction to ambient thermal resistance. The maximum power dissipation depends on the thermal resistance of the IC package. Lx should be very close. PHASEx signals from the junction of the power MOSFET.RT9627A Thermal Considerations Layout Considerations For continuous operation. If not configured properly. the maximum junction temperature is 125°C.4 2. is layout dependent. PCB layout. the thermal resistance. QLGx. Maximum Power Dissipation (W)1 3. For WDFN-12L 3x3 package. The junction to ambient thermal resistance.2 0. Next.richtek. Synchronous Buck Converter Circuit When layout the PCB. The junction of QUGx. The maximum power dissipation can be calculated by the following formula : Figure 4 shows the schematic circuit of a synchronous Buck converter to implement the RT9627A. the trace from UGATEx. VBAT L1 + CIN1 CIN2 5V VIN R1 BOOTx CB QUGx PD(MAX) = (TJ(MAX) − TA) / θJA VCC RT9627A UGATEx Lx For recommended operating condition specifications.4 0. www.5°C/W on a standard JEDEC 51-7 four-layer thermal test 11 .2 2.

750 0.RT9627A Outline Dimension 2 1 2 1 DETAIL A Pin #1 ID and Tie Bar Mark Options Note : The configuration of the Pin #1 identifier is optional.450 0.104 Option2 1. R.014 0. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.400 1. 8.050 0.091 0.250 0. Chupei City Hsinchu. Information furnished by Richtek is believed to be accurate and reliable. However.006 0.950 12 DS9627A-02 August 2014 .010 b 0.081 2. Richtek reserves the right to change the circuitry and/or specifications without notice at any time.070 0. Tel: (8863)5526789 Richtek products are sold by description only. Tai Yuen 1st Street. Max. Symbol D2 Dimensions In Millimeters Min.650 0.120 Option1 1. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product.000 0.069 Option2 1.C.028 0.800 0. no responsibility is assumed by Richtek or its subsidiaries for its use.018 0.450 0.050 0.046 0.000 0.300 2.031 A1 0.950 3.150 0.010 D 2.160 1. www. Min.O.116 0.050 E E2 Dimensions In Inches e L 0.175 0. Max.richtek.018 W-Type 12L DFN 3x3 Package Richtek Technology Corporation 14F. nor for any infringements of patents or other rights of third parties which may result from its use.002 A3 0.055 0. No.007 0.250 0.120 Option1 2.700 0.078 0. A 0. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Taiwan.260 0.116 0. but must be located within the zone indicated.970 2.050 0.350 0.