Semiconductor Device Thermal Characterization and System Design

Roger Stout, PE Research Scientist Corporate R&D: Technology Development
RPS • 2010 April

<roger.stout@onsemi.com>

Corporate Research & Development Packaging Technology

Course outline
• Part I: Characterization (75 minutes)
– Why Everything you Thought You Knew (about device thermal characteristics) is Wrong – Characterization Techniques – Miscellaneous Measurement Techniques

• Part II: Linear Superposition (120 minutes)
– – – – – Basic Theory The Reciprocity Theorem A Detailed Example and its Implications Building a System Model Time Varying Heat Sources

• Part III: Thermal Runaway (45 minutes)
– Theory – Datasheet example – High-Temperature Reverse Bias “qual” example
1 Semiconductor Device Thermal Characterization and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology

Part I Characterization

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Can this device handle 2 W?

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Why is ON’s SOT-23 thermal number so much worse than the other guy’s?
• ON
– – – – – – SOT-23 package 60x60 die Solder D/A Copper leadframe Min-pad board Still air

• some other guy
– – – – – – SOT-23 package 20x20 die Epoxy D/A Alloy 42 leadframe 1” x 2oz spreader Big fan

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Fundamental ideas
• Heat flows from higher temperature to lower temperature • The bigger the temperature difference, the more heat that flows • Three modes of heat transfer – Conduction (solids, fluids with no motion) – Convection (fluids in motion) – Radiation (it just happens)

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Thermal-electrical analogy
temperature power Δtemp/power <=> voltage <=> current <=> resistance

energy/degree

<=> capacitance

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“Junction” temperature?
Historically, for discrete devices, the “junction” was literally the essential “pn” junction of the device. This is still true for basic rectifiers, bipolar transistors, and many other devices. More generally, however, by “junction” these days we mean the hottest place in the device, which will be somewhere on the silicon (2nd Law of Thermodynamics).

This gets to be somewhat tricky to identify as we move to complex devices where different parts of the silicon do different jobs at different times.
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What’s wrong with theta-JA?

2

JA

TJ Ta Pd
JA

TJ
Jtab

Ttab Pd

TJ
8

Pd

Ta

TJ
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Jtab

Pd

Ttab

Semiconductor Device Thermal Characterization and System Analysis (RPS) April 2010

Theta-JA vs. copper area

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Typical thermal test board types

Min-pad board

1-inch-pad board

Minimum metal area to attach device (plus traces to get signals and power in and out)

Device at center of 1”x1” metal area (typically 1-oz Cu); divided into sections based on lead count

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Theta ( ) vs.. Psi ( )
• JEDEC <http://www.jedec.org/> terminology – Z JX , R JA older terms ref JESD23-3, 23-4 – JA ref JESD 51, 51-1 – JMA ref JESD 51-6 – JT, TA ref JESD 51-2 – JB, BA ref JESD 51-6, 51-8 – R JB ref JESD 51-8 – Great overview, all terms: JESD 51-12

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“Theta” (Greek letter
We know actual heat flowing along path of interest

Tx
xy

Ty

qpath

Ty
Tx

true “thermal resistance”
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“Psi” (Greek letter
We don’t know actual heat flowing along path of interest

Tx
xy

Ty

qtotal

??
Tx
… all we know is total heat input
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Ty

a reference number only
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Facts and fallacies
• Basic idea: – “thermal resistance” is an intrinsic property of a package • Flaws in idea: – there is no isothermal “surface”, so you can’t define a “case” temperature
• Plastic body (especially) has big gradients

– different leads are at different temperatures – multiple, parallel thermal paths out of package

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An example of a device with two different “Max Power” ratings
• Suppose a datasheet says: – Tjmax = 150°C • But it also says: – JA = 100°C/W – JL = 25°C/W – Pd = 1.25W (Tamb=25°C) – Pd = 3.0W (TL=75°C)

25 100 *1.25 25 125 150

75 25 * 3 75 75 150

Where’s the “inconsistency”?
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Where’s the inconsistency?
TJ =150°C
25°C/W ( JL) 100°C/W ( JA)
What’s TL? Not 75°C !!

(try about 119°C)

TA =25°C

…¾ of the way from ambient to Tj

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Back in the good old days ...
metal can -fair approximation of “isothermal” surface axial leaded device -only two leads, heat path fairly well defined

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Which lead? Where on case?

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“Archetypal” package
10%

convection case

wire/clip

silicon
die attach

flag/leadframe
10%

20%

60%

circuit board
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Semiconductor Device Thermal Characterization and System Analysis (RPS) April 2010

Then we change things …
add an external heatsink …
optional heatsink

flip the die over …
optional heatsink

40%

60%

mold compound/ case wire/clip silicon
die attach

optional “case”

die attach pads/ balls optional underfill

silicon

flag/leadframe

20%

40%
application board

20%

application board

20%

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A bare “flip chip”
10%
silicon pads/ balls underfill application board

90%

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Same ref, different values
J tab

1.2 C/W
J tab

Pd Tc

50 W 25 C

0.8 C/W

Pd Tc

1.5W 25 C

1 GPM of H 2 O

still air

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Even when it’s constant, it’s not!
Tj
R1 (path down to board) constant at 20
package environment

R3 (path through case top) constant at 80

TL

TC
R4 (case to air path resistance) constant at 500, or 20x R2

1000 900 800 700 600 500 400 300 200 100 0 1

thetaJA - var brd only thetaJA - var airflow

JA

TJ Tamb Q total

1 1 R1 R 2
board

1 R3 R 4
1000

R2 (board resistance) vary from 1 to 1000

10 rstnc. [C/W] 100

theta-JA

Tamb
25 psi-JL - var brd only psi-JL - var airflow 60 50 40 15 20

psi-JT
psi-JC - var brd only psi-JC - var airflow

psi-JL
JL

T J TL Q total

R1 10 R1 R 2 1 5 R3 R 4
0 1 10
board rstnc. [C/W]

30 20 10 0 100 1000 1

JT

TJ TC Q total

10

R3 R3 R 4 1 board R1 R 2 rstnc. [C/W] 100

1000

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Tj
JA

Ta

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Fallacies recap:
• “Package resistance” isn’t fixed: – multiple heat paths exiting package – boundary conditions dictate heat flow
• • • • • Heat sinks Neighboring devices/power dissipation Single vs.. double-sided boards Local convection vs.. board-edge cooling Multiple layers/power/ground planes

• Therefore, different application environments will see different “package resistance”
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Characterization Techniques
Typical TSP behavior
calibrate forward voltage at controlled, small (say 1mA) sense current

Characterization Techniques
125°C sense current

T

Vf

25°C

0.5 V

Vf

0.7 V

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How to measure Tj
true const. current supply
(1 mA typical)

approximate const. current supply

10K DUT

OR

10.7V DUT If V f-0.7V, then I-1mA

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How to heat
sample current is off while heating current on sample current is always on

10K heating power supply

10K heating power supply

10.7V
DUT

10.7V

OR

DUT

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The importance of 4-wire measurements
+(1.00 V) Power Output = 1 W supply -(0 V) 0.18 V 0.64 W 0.70 W 0.05 V
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1A

0.82 V 0.90 W 0.85 V

0.15 V

0.95 V

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Which raises an interesting question:
+(1.00 V) Power Output = 3 W supply -(0 V) 0.45 V 1.3 W 0.02 V 0.55 V

3A

1.3 W 0.3 W 0.98 V

Is this a fair characterization of a low-Rds-on device?
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Bipolar transistor
• TSP is Vce at designated “constant” current • Heating is through Vce • Choose a base current that permits adequate heating
bias resistor TSP supply

10K

switch

TSP=Vce
bias supply heating supply

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Schottky diode
• TSP is forward voltage at “low” current • Voltages are typically very small (especially as temperature goes up) • Highly non-linear, though maybe better as TSP current increases; because voltage is low, higher TSP current may be acceptable • Heating current will be large

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MOSFET / TMOS
• Typically, use reverse bias “back body diode” for both TSP and for heating • May need to tie gate to source (or drain) for reliable TSP characteristic
TSP supply

10K

switch

TSP=Vsd

heating supply +

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MOSFET / TMOS method 2
• If you have fast switches and stable supplies • Forward bias everything and use two different gate voltages

TSP supply

10K
close switch to heat

close switch to heat

close switch to measure

+ V-gate for heating -

+ V-gate for measure -

TSP=Vds

+ heating supply -

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RF MOS
• They exist to amplify high frequencies (i.e. noise)! • Feedback resistors may keep them in DC
TSP supply

10K
close switch to heat

TSP supply + + heating supply -

close switch to heat

close switch to measure

+ V-gate for heating -

TSP = body diode

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IGBT
• Drain-source channel used for both TSP and heating • Find a gate voltage which “turns on” the drain-source channel enough for heating purposes • Use same gate voltage, but typically low TSP current for temperature measurement
TSP supply

10K

switch

TSP=Vds
gate voltage heating supply

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Thyristor
• Anode--to-cathode voltage path TSP supply used both for TSP and for heating 10K • typical TSP current probably lower switch than “holding” current, so gate must be turned on for TSP anode gate readings; try tying it to the anode (even so, we used 20mA to test SCR2146) TSP=Vac • Hopefully, with anode tied to gate, cathode enough power can be dissipated to heat device without exceeding gate voltage limit
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heating supply

Logic and analog
• Find any TSP you can – ESD diodes on inputs or outputs – Body diodes somewhere • Heat wherever you can – High voltage limits on Vcc, Vee, whatever – Body diodes or output drivers – Live loads on outputs
• (be very careful how you measure power!)

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Heating curve method vs.. cooling curve method

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Quick review: Basic Tj measurement
first we heat then we measure

10K heating power supply

10K heating power supply

10.7V DUT

10.7V DUT

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Question
• What happens when you switch from “heat” to “measure”?

Answer: stuff changes
• More specifically, the junction starts to cool down

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Basic “heating curve” transient method
Vf
calibrate forward voltage @ 1mA sense current convert cooling volts to temperature
.5V

measurements
voltage current

1 ma power-off cooling power-off cooling power-off cooling power-off cooling
steady state reached

highcurrent heating

highcurrent heating

highcurrent heating

highcurrent heating

T
25°C

Temperature

125°C

measured temperatures Time

Vf

.7V

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Heating curve method #2
voltage

1 ma

highcurrent heating

highcurrent heating

highcurrent heating

highcurrent heating

Temperature

power-off cooling

power-off cooling

power-off cooling

power-off cooling

Time

measured temperatures
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Time

current

measurements
voltage
current

Basic “cooling curve” transient method
Vf
calibrate forward voltage @ 1mA sense current Temperature
.5V

1 ma

highcurrent heating

power-off cooling convert cooling volts to temperature

125°C

T
25°C

steady state reached

Temperature

Vf

.7V

Time (from start of cooling)

Time transient cooling period (data taken)

heating period

subtract cooling curve from peak temperature to obtain “heating” curve equivalent

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Whoa! … that last step there …
• Heating vs.. cooling – Physics is symmetric, as long as the material and system properties are independent of temperature

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Heating vs.. cooling symmetry

Start of constant power input (“step heating”)

Start of (constant) power off
junction flag

lead

(all the same curves, flipped vertically)

back of board edge of board

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• For a theoretically valid cooling curve, you must begin at true thermal equilibrium (not uniform temperature, but steady state) • So whatever your JA, max power is limited to:
power
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T j max

Tambient
JA

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By the way … Steady-state vs.. transient ?
• Since you must have the device at steady state in order to make a full transient cooling-curve measurement, steady-state JA is a freebie. (given that you account for the slight cooling which took place before your first good measurement occurred)

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Effect of power on heating curve
24x steadystate power 6x steadystate power 3x steadystate power 2x steady-state power

Tj-max
junction temperature

steady-state max power

< steady-state max power

Tamb
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time
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Some initial uncertainty
a few initial points may be uncertain

high-current heating Temperature steady state reached

but once we’re past the “uncertain” range, all the rest of the points are “good”
power-off cooling
transient cooling period (data taken)

heating period Time

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Heating vs.. cooling tradeoffs
HEATING starting temperature ambient limited by tester closer to ambient all points similar error
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COOLING ? limited to steady-state closer to Tj-max error limited to first few points

heating power
temperature of fastest data error control
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Still air vs.. moving air
• Varying the air speed is mainly varying the heat loss from the test board surface area, not from the package itself • You just keep re-measuring your board’s characteristics

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100

total system thermal resistance
90

80
70 60 50 40 30 20

little package

package resistance

theta-JA [C/W]

mediumsized package

board resistance
10 0 0.1

big package

1

10

air speed [m/s]

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Different boards
• Min-pad board
• 1” heat spreader board • You’re mainly characterizing how copper area affects every package and board, not how a particular package depends on copper area

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1" pad vs min-pad
350

Roger Stout 5/25/2000

300

Source: Un-derated thermal data from old PPD database

SOD-323

250
TSOP-6

SOT-23

1" pad thetaJA (C/W)

SOT-23

200
SOD-123 SOD-123 TSOP-6(AL42) SOT-23

150
Micro 8

TSOP-6

SO-8

SOD-123 SMA & Pow ermite

100
SMB Dpak D2pak & TO220 Top Can Top Can SMC SOT-223 SO-8

50

overall linear fit is: 1" value = [0.51*(min-pad value) - 7]

0 0 100 200 300 400 500 600 700 min pad thetaJA (C/W)

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Standard coldplate testing
• “infinite” heatsink (that really isn’t) for measuring thetaJC on high-power devices • If both power and coldplate temperature are independently controlled, “two parameter” compact models may be created

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Standard coldplate testing
• Detailed design and placement of “case” TC can have significant effect on measured value

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2-parameter data reduction
Q
heat up, Q1

Q1 Q2

T1

Q
R1

1 T j T1 R1

(

)

1 T j T2 R2

(

)

This has the form of a two-variable linear equation: heat in, Q Tj R2

y

m1 x1 m2 x2 b

where:

m1
T2 heat down, Q2
Semiconductor Device Thermal Characterization and System Analysis (RPS) April 2010

m2

1 R1 1 R2

x1 x2

(T

j

T1 )
j

(T

T2 )

b

0

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A “single coldplate” test
ambient Ta Rja
80.0 0 120. 00 100. 00

Tj

Ta

Tjc ( ¡C)

Tc

coldplate

Tj Rjc Tc coldplate

60.0 0 40.0 0 20.0 0 Incr easing Power, Chuck H eld Cold No P ower, Chuck T emper ature Incr eased 20.0 0 40.0 0 60.0 0 80.0 0 100. 00

0.00 -20. 00 0.00 -20. 00

Tja (¡C)

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ambient Ta Rba Tb Rjb Tj Rjc Tc coldplate
Tjc ( ¡C)

A “single coldplate” test, package down
120. 00 100. 00 80.0 0 60.0 0 40.0 0 20.0 0 0.00 -10. 00 0.00 -20. 00 Incr easing Power, Chuck H eld Cold No P ower, Chuck T emper ature Incr eased 10.0 0 20.0 0 30.0 0 Tjb (¡C) 40.0 0 50.0 0 60.0 0

Tj

Ta

Tb

Tc coldplate

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Miscellaneous Measurement Topics

• Thermocouple Theory 101 • Infrared Theory 202

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Thermocouple Theory 101

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Thermocouple Theory
region “B” - 20cm of wire length between the junction and the door of the temperature chamber region “C” – 10cm of TC wire length passing from inside of chamber door to outside of chamber door

TC junction B A
perfectly uniform temperature chamber at 100°C

C D

TC scanner

perfectly uniform ambient temperature of 25°C

region “A” - a 1cc box around the junction

region “D” – 100cm of TC wire length from outside of chamber to TC measuring instrument

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Thermocouple Theory
• Question #1: – where is the temperature actually being “sensed”? or to put it another way, which region of the four defined above (A, B, C, D), is the one that matters, as far as generating the EMF being measured by the TC scanner? Why?
The emf is generated where there is a temperature gradient
B C D

TC junction A
perfectly uniform temperature chamber at 100°C

perfectly uniform ambient at 25°C

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Thermocouple Theory
• Question #2: – if the purpose of the TC scanner is to measure an EMF, theoretically how much current has to flow in the wire to make the correct measurement?

None. Ideally, a galvanometer circuit balances the EMF at the scanner until no current flows.

Corollary: wire size, and therefore resistance, may affect how long it takes the galvanometer circuit to stabilize.
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Thermocouple Theory
• Question #3: – what do the two wires in the TC actually do, and why do they have to be made of different materials?
100°C ΔV=0.0025V

100°C

Different materials have different Seebeck coefficients, i.e., V/°C. So if you have two different materials, the same temperature gradient appearing in along both wires will result in two different EMF’s.
ΔV=0.0037V

25°C

25°C

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Thermocouple Theory
• Question #4: – what does the “junction” in a TC actually do?
25°C

ΔV=0.0025V

100°C

Provides the common electrical point that relates the EMF’s in the two wires to each other, hence the net difference appears at the “open” end of the circuit.

Net ΔV=0.0012V

ΔV=0.0037V

The junction DOES NOT “measure” the temperature; the wires do!
25°C

Corollary: if the junction itself is isothermal, it can be made of any material whatsoever!
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Thermocouple Theory
• Question #5: – if you really wanted to “calibrate” this thermocouple, where would you need to apply the test conditions?

TC junction B A C

Everywhere along its length!
D

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Infrared Theory 202

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Infrared Theory
A opaque surface radiates thermal energy in proportion to its absolute temperature (to the fourth power), and some other things

 q
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AT

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Infrared Theory
It’s also absorbing infrared energy from everything else around it (since everything else has a temperature and is therefore emitting)

It turns out that the “absorptivity” equals the “emissivity.”
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Infrared Theory
There is thus a net energy transfer which, in the simplest situations, may be described by:

 q

obj

Aobj (Tobj

4

Tencl

4

)

(typically applies to a small, isothermal object in a big, isothermal enclosure)
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Infrared Theory
But it quickly gets more complicated when there are multiple objects (or temperatures) hanging around. • Each object has a “view factor” of every other object • Each object has its own emissivity (usually NOT unity)

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Infrared Theory
The “emissivity,” , is also related to the “reflectivity,” , as follows:

1
So the worse something emits, the better it reflects, and vice-versa.

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Infrared Theory

In other words, unless you’re looking at a perfect emitter (aka a “blackbody”), you don’t simply see less radiation than you would for a blackbody, you see some of the radiation of what’s behind you!

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Infrared Theory
In even the simplest real-life situation, you usually have four “objects,” and their associated temperatures, to consider: • The test specimen (130°C) • The surrounding room (25°C) • You (33°C) • The detector (-195°C)

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Infrared Theory

(the room) The “target”
(the detector itself)

(you)

(the room)
Semiconductor Device Thermal Characterization and System Analysis (RPS) April 2010

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Infrared Theory
So if you’re looking at a shiny, low emissivity specimen, you’ll see a combination of these four temperatures (that is, the radiation representing these four temperatures) all bouncing into the detector! Depending on the angles involved, therefore, it is quite possible to see vastly higher temperatures than are really there, or vastly lower temperatures are really there.
78 Semiconductor Device Thermal Characterization and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology

Hot water loop

Footprints

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Direct view

In mirror

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Reflection

Emissivity

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View at 10 am

View at 10 pm

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Infrared Theory
Moral:

For accurate temperature measurements, you must account for the emissivity of the target, and you must control the background!

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Infrared Theory
Here’s one way to approach it:
isothermal enclosure, high emissivity, opaque to infrared

IR camera

DUT

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Infrared Theory
Governing equation
Two reference scans

I

I back a T 4
1

I1
I2

I back a T14
I back a T2 4

Solve for Temperature

Solve for the unknowns

T

I

I back a

4

a

I2 T2
4

I1 T1
4

I back

T2 4 I1 T14 I 2 T2 4 T14

In terms of the reference scan quantities:

T

T2 (I
4

I1 ) T1 (I I 2 I1
4

I2 )

1

4

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Part II Linear Superposition

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Linear superposition – what is it?
• The total response of a point within the system, to excitations at all points of the system, is the sum of the individual responses to each excitation taken independently.
Tsource 2 

Tcomposite

Tsource1

Tsource n

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Linear superposition – when does it apply?
• The system must be “linear” – in brief, all individual responses must be proportional to all individual excitations.

Tnet A
TA
89 Semiconductor Device Thermal Characterization and System Analysis (RPS) April 2010

TA

B

TA

C

TA

D

2 qB

3 qC
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1.2 qD

Linear superposition doesn’t apply if the system isn’t linear.

T

a(T , q1 ) q1 b(T , q2 ) q2 

T

a q1

n1

b q2

n2

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Linear superposition – how do you use it?
Tamb

Tref5
Tj6 Tj5

Tj3
Tref3

Tj2

Tref1 Tj4 TB
91 Semiconductor Device Thermal Characterization and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology

Tj1

Linear superposition – when would you use it?

When you have multiple heat sources (that is, all the time!)

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junction temperature vector

theta matrix assembled from simplified subsystems

power input vector

T j1 Tj2  T jn
93

J 1A 21

12 J 2A

  

1n 2n


n1 n2


JnA

q1 q2  qn

Ta

self-heating terms
Semiconductor Device Thermal Characterization and System Analysis (RPS) April 2010

board interactions
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junction temperature vector

theta matrix assembled from simplified subsystems

power input vector

T j1 Tj2  T jn

JB1 21

BA1 JB 2

12 BA2

  

1n 2n


n1 n2


JBn BAn

q1 q2  qn

Ta

device resistance
94 Semiconductor Device Thermal Characterization and System Analysis (RPS) April 2010

board resistance
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visualizing theta and psi
heat in here measurements here are s

J1A J1B
(idle heat source “x”)

measurements here are s (idle heat source “y”)

xA

BA

yA

thermal ground
95 Semiconductor Device Thermal Characterization and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology

theta matrix doesn’t have to be square
junction temperature vector one column for each heat source
JA1 12 x1 L1 1 B1 12 JA 2 x2 L1 2 B2 13 23 x3 L1 3 B3

power input vector

T j1 Tj2 TxA TL1 A TBA

q1 q2 q3
(why is this and not ?)

one row for each heat source

one row for each temperature location of interest
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Electrical reciprocity

+ 5V -

+ -

+ ?V -

+

0.3 V V
-

I 0.3A 2 V

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Thermal reciprocity
heat input here

response here

same response here

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Another thermal reciprocity example

(r)
response here

heat input here same response here

(s)

(s)

(r)

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When does reciprocity NOT Apply?
• Upwind and downwind in forced-convection dominated applications

B

C
airflow A D Heat in at “A” will raise temperature of “C” more than heat in at “C” will raise temperature of “A” “B” and “D” may still be roughly reciprocal

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(square part of) matrix is symmetric
columns are the heat sources J1 J2 J3 J4 rows are the response locations J5 J6 75 65 55 60 22 10 73 65 71 60 55 25 11 65 55 60 65 61 21 15 55 60 55 61 73 18 11 59 22 25 21 18 125 14 22 10 11 15 11 14 180 10

R1
R3 R5 B
Semiconductor Device Thermal Characterization and System Analysis (RPS) April 2010

55
20 65

60
24 63

63
14 62

61
19 63

21
95 21

15
15 12

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Superposition example
Tamb=25 Tref5=47.0 Tj6=36.0 Tj5=49.2

Tj3=85.5 Tref3=85.5

Tj2=96.5

Device 1 heated, 1.1 W

Tref1=105.3 Tj4=91.0 Tj1=107.5 TB=96.5

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Reduce the data
Tj1 Tamb
j1A
j1A

75 65 55

q1
Tj2 Tamb q1

107.5 25 1.1
96.5 25 1.1

75

j2A j3A

j2 A

65

j4A j5A

60
22 10 73 55 20 65


TB
BA

j6A r1A

Tamb q1

96.5 25 1 .1

65

r3A r5A BA

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Device 2 heated, 1.2 W
j1A j2A

65 71

Tamb=25 Tref5=53.8 Tj6=38.2 Tj5=55.0

j3A
j4A j5A j6A r1A

60
55 25 11

65
60 24 63

Tj3=97.0 Tref3=97.0

Tj2=110.2
r3A r5A

Tref1=103.0 Tj4=91.0 Tj1=103.0 TB=100.6
104 Semiconductor Device Thermal Characterization and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology

BA

Device 3 heated, 1.3 W
j1A

55 60

Tamb=25
j2A

Tref5=43.2 Tj6=44.5

j3A

65
61 21 15

Tj5=52.3

j4A j5A j6A

Tj3=109.5 Tref3=106.9

Tj2=103.0
r1A r3A

55
63 14 62

Tref1=96.5

Tj4=104.3

Tj1=96.5
TB=105.6

r5A BA

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Device 4 heated, 1.1 W
j1A

60 55

Tamb=25
j2A

Tref5=45.9 Tj6=37.1

j3A

61
73 18 11

Tj5=44.8

j4A j5A j6A

Tj3=92.1 Tref3=92.1

Tj2=85.5
r1A r3A

59
61 19 63

Tref1=89.9

Tj4=105.3

Tj1=91.0
TB=94.3

r5A BA

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Device 5 heated, 0.7 W
j1A

22 25

Tamb=25
j2A

Tref5=91.5 Tj6=34.8

j3A

21
18 125 14

Tj5=112.5

j4A j5A j6A

Tj3=39.7 Tref3=39.7

Tj2=42.5
r1A r3A

22
21 95 21

Tref1=40.4

Tj4=37.6

Tj1=40.4
TB=39.7

r5A BA

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Device 6 heated, 0.5 W
j1A

10 11

Tamb=25
j2A

Tref5=32.5 Tj6=115.0

j3A

15
11 14 180

Tj5=32.0

j4A j5A j6A

Tj3=32.5 Tref3=32.5

Tj2=30.5
r1A r3A

10
15 15 12

Tref1=30.0

Tj4=30.5

Tj1=30.0
TB=31.0

r5A BA

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Collect the /
J1 J2 J3 75 65 55 60 22 10 65 71 60 55 25 11 55 60 65 61 21 15

values
60 55 61 73 18 11 22 25 21 18 125 14 10 11 15 11 14 180

columns are the heat sources

J4
rows are the response locations J5 J6 R1 R3 R5 B
Semiconductor Device Thermal Characterization and System Analysis (RPS) April 2010

73
55 20 65

65
60 24 63

55
63 14 62

59
61 19 63

22
21 95 21

10
15 15 12

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Now apply actual power

Tamb=25
Tref5=106.3

Actual power in application
Tj5=124.7

Tj6=139.1

Qj1

.4

Q j2
Tj3=134.9 Tj2=140.1

.4
.4 .4 .5 .2

Q j3 Q j4 Q j5 Q j6

Tref3=134.1
Tref1=138.8 Tj4=135.8 Tj1=140.0 TB=139.1
110 Semiconductor Device Thermal Characterization and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology

Compute some effective /

values

Take Tj1, for instance. Remember when it was heated all alone, we calculated its self-heating theta-JA like this:

Tj1 Tamb
j1A

q1

107.5 25 1.1

75

Now let’s see:

Tj1 Tamb
j1A

q1

140 25 0.4

288

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And that’s not just a single aberration!
Junction to Reference
Self heating
j1A j2A j3A j4A j5A j6A j1-R1

3.0 2.0 36.8

vs. 1.5x vs. 1.0x vs. 1.2x

2.0 2.0 30.0

288
288 274 277 199 309

vs. 3.8x vs. 4.1x vs. 4.2x vs. 3.8x

75
71 65 73

j3-R3 j5-R5

Junction to Board
j1-B

2.2

vs. 0.2x

10.0

vs. 125 1.6x vs. 180 1.7x

j2-B
j3-B j4-B

2.5
-10.5 -8.3

vs. 0.3x
vs. -3.5x vs. -0.8x

8.0
3.0 10.0

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Is the moral clear?
• You simply cannot use published theta-JA values for devices in your real system, even if those values are perfectly accurate and correct as reported on the datasheet and you know the exact specifications of the test conditions. • Not unless your actual application is identical to the manufacturer’s test board – and uses just that one device all by itself.

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So is it really this bad?
Only sort-of. Let’s revisit the math for one device …

Tj1 Tj2  Tjn

J1A 12

12 J2 A

  
12 q2
n

1n 2n


1n
Tj1
Tj1


JnA

1n qn

2n
J1A q1

q1 q2  qn
Ta
Ta

Ta

1nqn

J1A q1 2

“effective” ambient

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A graphical view
Isolated device
Tj1
J1A q1

power, q

1

Ta
Ta

J1A

junction temperature , TJ1

Device in a system
n

shift in effective ambient

Tj1

J1A q1 2 J1A q1

1n qn

Ta
Ta’

1
J1A

still the same slope

Ta

Ta

junction temperature , TJ1

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What about that “system” theta we saw earlier that was so different?
power q1 the “system” theta-JA 1
J1A J1A

device #1 power/temperature perturbations will fall on this line

NOT this one

1
n

Ta
116

1n qn 2

Ta’

the isolated-device theta-JA TJ1

junction temperature

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How does effective ambient relate to board temperature?
“system” slope for isolated device
if any of these are non-zero, Ta will be higher than Ta
n

Tj1

j1a

Q1
i 2
B1a

(

i1

Qi ) Ta

(

j1B

)Q
B1a

1

effective Ta ambient

j1B

Q1

Q1
TB1a

Ta
Ta

Tj1B
temperature rise, board to J1
117 Semiconductor Device Thermal Characterization and System Analysis (RPS) April 2010

when Q1 is not zero, both zero, both of of these be these willwill be non-zero zero

temperature rise, ambient to board
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Predicting the temperature of high power components
• The device and system are equally important to get right

Predicting the temperature of low power components
• The system is probably more important than the device
Semiconductor Device Thermal Characterization and System Analysis (RPS) April 2010

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Using the previous board example …
theta array
J1 J2 J3

75 65 55 60 22

65 71 60 55 25

55 60 65 61 21

60 55 61 73 18

22 25 21 18 125

10 11 15 11 14 Qj1

power vector
0.5

J4
J5 J6 R1 R3 R5 B

Q j2 0.5
Q j3 0.5 Q j4 0.5 Q j5 0.2 Q j6 0.02

10
73 55 20

11
65 60 24

15
55 63 14

11
59 61 19

14
22 21 95

180
10 15 15

65

63

62

63

21

12
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Semiconductor Device Thermal Characterization and System Analysis (RPS) April 2010

Observe the relative contributions
For junction 1 (a high power component) we have: the device itself … the other devices … = (75 x 0.5) + (65 x 0.5) + (55 x 0.5) + (60 x 0.5) + (22 x 0.2) + (10 x 0.02) + 25

=

37.5

+ 32.5 + 27.5 + 30 + 4.4 + 0.2

+

25

= 37.5 +
120 Semiconductor Device Thermal Characterization and System Analysis (RPS) April 2010

94.6

+

25

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Graphically, a high-power device looks like this:
power q1=0.5 W note the “embedded” theta-JA looks like 264 C/W decreasing power

increasing power

1
264 C/W

1
75 C/W

=94.6 C
n

25 C

1n qn 2

=37.5 C (θJ1Aq1)

157 C TJ1

junction temperature

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Relative contributions to TJ6
the other devices … = (10 x 0.5) + (11 x 0.5) + (15 x 0.5) + (11 x 0.5) + (14 x 0.2) + (180 x 0.02) + 25 the device itself …
= 5.0 + 5.5 + 7.5 + 5.5 + 2.8 + 3.6 = 26.3 + 3.6 + 25 + 25

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Graphically, low-power device #6 looks like this:

power and just in case you were wondering, the “embedded” theta-JA looks like 1495 C/W !
1 =3.6 C

q6=0.02 W
=26.3 C

180 C/W

25 C

54 C TJ6

junction temperature

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Controlling the matrix

How to harness this math in Excel®

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3x3 theta matrix, 3x1 power vector Excel® math
Matrix MULTiply obtained by using multi-cell placement Ctrl-Shift-Enter rather {=array formula notation} than ordinary Enter of array formula

theta matrix

power vector

array reference to theta matrix

array reference to power vector

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7x3 theta matrix, 3x1 power vector Excel® math
don’t forget to use theta matrix is no longer square – Ctrl-Shift-Enter # of columns still must equal # of rows of power vector to invoke array formula notation array formula now occupies 7 cells

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7x3 theta matrix, 3x2 power vector Excel® math
power “vector” is now a 3x2 array – each column is a different power scenario, yet both are still processed using a single array (MMULT) formula the single MMULT array formula now occupies 7 rows and 2 columns (one column for each independent power scenario result)

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Temperature direct contributions and totals
120

120

80

temperature rise [C] sum of sources
J1 J2 J3 J4 J5 J6 R1 R3 R5 B

temperature rise [C], each source

100

100

80

60

60

40

40

20

20

0 result location

0 J1 J2 J3 J4 J5 J6 R1 R3 R5 J3 at 0.4 W J6 at 0.2 W B result location J3 at 0.4 W J6 at 0.2 W J1 at 0.4 W J4 at 0.4 W J2 at 0.4 W J5 at 0.5 W

J1 at 0.4 W J4 at 0.4 W

J2 at 0.4 W J5 at 0.5 W

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Normalized responses at each location due to each source
200

normalized response [C/W], each source

180 160 140 120 100 80 60 40 20 0 J1 J2 J3 J4 J5 J6 R1 response location R3 R5 B J1 at 1 W J2 at 1 W J3 at 1 W J4 at 1 W J5 at 1 W J6 at 1 W

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Filling in the theta-matrix

• Handy formulas for quick estimates • Utilizing symmetry

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Conduction resistance
basic heat transfer relationship for 1-D conduction
q dT k A dx k A T L

if we define
R T q

then
R L k A
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Convection resistance
basic heat transfer relationship for surface cooling
q h A T

if we define
R T q

then
R 1 hA
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Semiconductor Device Thermal Characterization and System Analysis (RPS) April 2010

Radiation resistance
basic heat transfer relationship for surface radiation
q F A (T 4 Ta4 ) F A (T 2 Ta2 )(T Ta )(T Ta ) F A (T 2 Ta2 )(T Ta ) T

if we define
R T q

then
R 1 FA (T 2 Ta2 )(T Ta )

temperatures must be expressed in degrees “absolute”!

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Thermal capacitance and time constant
Capacitance is ability to store energy specific heat is energy storage/mass Based on simple RC concept, relate rate of storage to rate of flux, result is

C
so if

cp V
and if

= RC

R
then

L and C k A
c pL2 k L2

ρc p (L A )

R
then

1 and C h A
c pL h

ρc p (L A )

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Some useful formulas
• conduction resistance…………..……… R
• convection resistance…………...……… R
L k A 1 h A c pV c pL2 k c pL T h Q A 2 cp k t

• thermal capacitance……………...…….. C
• characteristic time…………………..…. – (dominated by 1-D conduction) • characteristic time……………………... – (dominated by 1-D convection) • short-time 1-D transient response……...

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Terms used in preceding formulas
• • • • • • • • • • • L - thermal path length A - thermal path cross-sectional area k - thermal conductivity k - density cp cp - heat capacity - thermal diffusivity cpk - thermal effusivity h - convection heat-transfer “film coefficient”) T - junction temperature rise Q - heating power t - time since heat was first applied

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When do these effects enter?
hundreds of seconds tens of seconds a second or so

junction temperature

mainly environmental convection and radiation effects

mainly local application board conduction effects

typical heating curve for device on FR-4 board in still-air
time

mainly package

materials/conduction effects
137 Semiconductor Device Thermal Characterization and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology

if

R

then

and

2R

4R
138 Semiconductor Device Thermal Characterization and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology

Cylindrical and spherical conduction (through radial thickness) resistance formulas
ro ln ri k L
[solid angle]

Half-cylinder

R

R

1 ri 2 1 ri 4

1 ro k 1 ro k

Hemisphere

[included angle]

Full cylinder

R

r ln o ri 2 k L
• • •

R

Full sphere

where

L – cylinder length ri – inner radius ro – outer radius

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Package-shrink “gotcha”
Remember how much of theta-JA depends on what isn’t the package?

Well, what if your cooling depends significantly on convection from the board surface (whether free or forced air)?

q

h A

T

A

q h T

So never mind the package resistance, the board can only transfer a certain amount of heat to the air:
*Special thanks to Dave Billings for the idea behind this slide
140 Semiconductor Device Thermal Characterization and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology

Package-shrink “gotcha”
1000 A 2 mm

1.0q W
W 1E-5 mm2 °C

h

100°C T
So if 4 SOT23’s each have 0.25 W, then T=0.25*200=50°C PROBLEM: No problem! 4 SOT23’s on a 1000 mm2 board, effective JA=400°C/W

1 SOT23 on a 250 mm2 spreader, JA=200°C/W

Fortunately, 0.25 W each x 400°C/W→100°C
*Special thanks to Dave Billings for the idea behind this slide
141 Semiconductor Device Thermal Characterization and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology

Whew!

Package-shrink “gotcha”
NOW your favorite supplier comes out with the next generation version (much smaller) of the same component.
SOT23 4 SOT723’s on a 1000 mm2 SOT23’s board, JA=400°C/W, T=100°C, power = 1 W total, power = 1 W total, 0.25 W each each

Decrease size (but not power and reduce power dissipation dissipation) (RDSON or other electrical performance)

How many SOT723’s can you put in that same 1000 mm2? ANSWER: 4 8
8 SOT723’s on a 1000 mm2 board, JA=800°C/W, T=100°C, power = 1 W total, 0.125 W each

SOT723
*Special thanks to Dave Billings for the idea behind this slide
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PERIODIC and NON-PERIODIC POWER INPUT

• Duty-cycle curves – Normalized and non-normalized • Linear superposition applied to time domain

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Square-wave duty cycles (aka ratios)
• What the heck are they?
– show peak junction temperature as a function of duty cycle and “pulse width”

• Where do they come from?
– “heating curve” is equivalent to the limiting case of a 0% duty-cycle, where once the “pulse width” is over, there’s never another cycle – “linear superposition” allows you to generate the whole family from the heating curve

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Representative “duty cycle” response chart
2.5 R(t), Thermal Resistance [°C/W]

2

1.5

d=0.5

1

0.2 0.1
0.05 Single pulse

0.5

0 0.00001

0.0001

0.001

0.01 t, time (s)

0.1

1

10

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It begins with one of these:
100

transient thermal response for axial lead rectifier Junction-to-Lead, 1/4" lead length

10

R(t)JL [°C/W]

1

0.1 0.0001

0.001

0.01

0.1

1

time [s]

10

100

1000

A “single-pulse” response is the same as a 0% duty cycle - if you think in terms of a 0% duty cycle meaning you have only one pulse (however long it lasts), but once you turn if off, you never turn it back on again. So any finite “on” time is zero percent of infinitely long “off”.
146 Semiconductor Device Thermal Characterization and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology

“published” formulas
Non-dimensionalized versions
r(t , d ) d
r(t , d ) d

dimensionalized versions
R(t , d ) d R

(1
(1

d ) * r(t )
d ) * r(t p) r(t ) r( p)

(1

d ) R(t )

r (t , d ) d

(1

d)*r t

t d

r (t ) r

t d

R(t , d ) d R

(1

d) R t

t d

R(t ) R

t d

lim R(t , d ) d R
t 0

lim R(t , d )
t

R

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A “normalized” curve:
1
JL=27.4°C/W

r(t)JL [normalized]

0.1

normalized transient thermal response for axial lead rectifier Junction-to-Lead, 1/4" lead length

0.01 0.0001

0.001

0.01

0.1

1

time [s]

10

100

1000

Is this really such a bright idea?

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Consider this family of “non-normalized” curves:
100

Transient thermal response for axial lead rectifier Junction-to-Lead, varying lead length

10

R(t)JL [°C/W]

R(t)-1" R(t)-3/8" 1 R(t)-1/32"

0.1 0.0001

0.001

0.01

0.1

time [s]

1

10

100

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The danger!
100

Transient thermal response for axial lead rectifier Junction-to-Lead, varying lead length

10

r(t)JL [normalized]

See what happens to the shorttime response when you “normalize”!

R(t)JL [°C/W]

R(t)-1" R(t)-3/8" 1 R(t)-1/32"

0.1 0.0001 1

0.001

0.01

0.1

time [s]

1

10

100

JL-1/32"=20.0°C/W JL-3/8"=34.9°C/W

0.1

JL-1"=54.9°C/W

0.01

r(t)-1/32" r(t)-3/8" r(t)-1"

normalized transient thermal response for axial lead rectifier, Junction-to-Lead varying lead length

0.001 0.0001

0.001

0.01

0.1

time [s]

1

10

100

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Compare the families of curves:
100

R(t)JL [°C/W]

Different steady states

square-wave duty cycles for 1/32" lead length

10

single pulse 1% duty cycle 2% duty cycle 5% duty cycle

1

10% duty cycle 20% duty cycle 50% duty cycle

Same shorttime 0% (single-pulse)

0.1 0.0001

0.001

0.01

0.1

time [s]

1

10

100

100

square-wave duty cycles for 1" lead length

R(t)JL [°C/W]

Different everything between !!

10

single pulse 1% duty cycle 2% duty cycle 5% duty cycle

1

10% duty cycle 20% duty cycle 50% duty cycle

0.1 0.0001

0.001

0.01

0.1

time [s]

1

10

100

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What to do if you’re given a normalized curve
• Find out what reference value it was normalized from
– Undo it

• If you can’t find out
– Throw the curve away

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Linear Superposition Applied to Time Domain

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Basic heating curve - a “single pulse”
R(t)

t

Q

t

power input corresponding to single pulse heating curve
154 Semiconductor Device Thermal Characterization and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology

Single pulse (actually turned off)
Finite pulse, decomposed into two infinite steps
Q

equals
a t

Q

plus
t

Q a t

Temperature response of a finite pulse (constructed from superposition of two single pulse responses)
R(t) R(t) R(t) a t

plus
t

equals
a t

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Two differing pulses
Two finite pulses decomposed into infinite steps
Q1 a Q2 b c Q1 t a -Q1 Q2 b c -Q2 t

is made up of

Temperature response constructed for two finite pulses (constructed from superposition of four single pulse responses)
R(t)
R(t)

results in this

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An arbitrary pulse train
• Temperature at end of nth pulse
n

Tn
i 1

Pi R(t2 n

[

1

t 2i

2

)

R(t2n

1

t 2i

1

)]

Notes: times and pulses must be in strictly increasing chronological order
P1 Pn P2

When there is no “off” period between two consecutive pulses, set t 2i 2 t 2i 3 (i.e. do not “combine” them into a single value)
t2n-1

Power
t0 t1 t2

t3 time

t2n-2

For temperature at the beginning of the nth pulse, set t 2n 1 t 2n 2

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An example
Item P1 P2 P3 t1 t3 t3-1 t3-2 t5 t5-1 t5-2 t5-3 t5-4
t0 t6 t4

Junction Temperarure

Value 80 40 70 0.0001 0.0013 0.0012 0.0010 0.0035 0.0034 0.0032 0.0022 0.0002
Item

unit W W W s s s s s s s s s
unit

P(PK) Peak Power (Watts)

100 80 60 40 20 0 t0 t1 t2 1 t3 2 t, Time (ms) 3 t4 t5 4 P1 P2 P3

T1
T2

P R(t1 ) 1
P R(t3 ) R(t3 t1 ) 1 P2 R(t3 t 2 )

[

]

T3 T1 T2

Value

T3
3 t4 t5 4

P R(t5 ) R(t5 t1 ) 1

[

] ]

0.0000 s 0.0003 s 0.0012 s

t0 t1 t2

1 t3 2 t, Time (ms)

P2 R(t5 t 2 ) R(t5 t3 ) P3 R(t5 t 4 )

[

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How to read the curve
• For small time differences, and on a low resolution log-log plot, what can you do?
100

Transient thermal response for axial lead rectifier Junction-to-Lead, varying lead length

10

1

0.1 0.0001

0.001

Item P1 P2 P3 t1 t3 t3-1 t3-2 t5 t5-1 0.01 t5-2 t5-3 t5-4

Value 80 40 70 0.0001 0.0013 0.0012 0.0010 0.0035 0.0034 0.0032 0.0022 0.0002

unit W W W s s s s s s 0.1 s s s

R(t)JL [°C/W]

R(t)-1" R(t)-3/8" R(t)-1/32"

time [s]

1

10

100

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Assume power law (straight line on log-log plot)
R(t ) a t
n

t2

t1

t1 t
a R(t1 ) t1
n

R(t 2 ) t2
n

R(t

) R(t )
R(t

t t

n

n

R(t ) 1

log n

R(t 2 ) log t2

t

R(t1 ) t1

)

R(t )

R(t )n

t

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How to read the curve #2
• For small time differences, and on a low resolution log-log plot, what can you do?
100

anchors R(.0001) 0.22 R(.02) 3.3

Transient thermal response for axial lead rectifier Junction-to-Lead, varying lead length

10

1

0.1 0.0001

0.001

0.01

0.1

time [s]

1

interpolate R(t1) 0.22 R(t3) 0.82 R(t3-1) 0.79 R(t3-2) 0.72 R(t5) 1.36 R(t5-1) 1.34 10 R(t5-2) 1.30 R(t5-3) 1.08 R(t5-4) 0.32

R(t)JL [°C/W]

R(t)-1" R(t)-3/8" R(t)-1/32"

100

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Results
P(PK) Peak Power (Watts)
100 80 60 40 20 0 t0 t1 t2 1 t3 2 t, Time (ms) 3 t4 t5 4 P1 P2 P3

T1 T2

P R(t1 ) 80 0.22 17 .6 C 1 P [ R(t3 ) R(t3 t1 )] P2 R(t3 t 2 ) 1 80 (0.82 0.79 ) 40 0.72 2.4 28 .8 31 .2 C

Junction Temperarure

T3 T1 T2

T3

P [ R(t5 ) R(t5 t1 )] 1 P2[ R(t5 t 2 ) R(t5 t3 )] P3 R(t5 t 4 ) 80 (1.36 1.34 ) 40 (1.30 1.08) 70 0.32 1.6 8.8 22 .4 32 .8 C

t0 t1 t2

1 t3 2 t, Time (ms)

3 t4

t5

4

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Another transient analysis example
power

18
25.2W

23

Here’s our power input scenario:
power 20 pulses 25.2W

repeat 20 times, then stop for 6800 microseconds
time

20 pulses

time 802 last of 20 pulses ends 7600

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equivalence of non-zero average response with (constant average) + (zero-average disturbance)
Actual duty cycle and response
“peak” Tavg “valley” Tavg due to Qavg

Superposition of average and disturbance

Power shifted to average zero

Q
0
Qavg= d · Q

(1-d) · Q

0
-d·Q

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Another example, cont’
How do we analyze it? Over three time scales:
power

18
25.2W

instantaneous excursions based on “local” duty cycle

23
power

“average” Tj based on local avg power

average excursions based on “global” duty cycle

repeat 20 times

time

25.2W

burst

time
power 25.2W

7600

15200

“average” Tj based on global avg power
20 pulses time 802 last of 20 pulses ends 7600

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Endless Possibilities

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A “ramp”
A finite ramp decomposed into several infinite steps
P
t a

P

is made up of

a

t

Temperature response constructed for finite ramp (constructed from superposition of many single pulse responses)
Q t a Q

results in this
a

t

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An arbitrary pulse
An arbitrary pulse decomposed into several infinite steps
Q t a Q

is made up of

Temperature response constructed for this arbitrary pulse
Q Q

t

results in this
t

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Multiple Time-Varying Heat Sources

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Basically the same theta-matrix idea, only now everything is a function of time as well
junction temperature vector
T j1 (t ) T j 2 (t ) TxA (t ) TL1 A (t ) TBA (t )

one column for each heat source
(t ) 12 (t ) x1 (t ) L1 1 (t ) B1 (t ) (t ) JA 2 (t ) x 2 (t ) L1 2 (t ) B 2 (t )
12

power input vector

JA1

(t ) 23 (t ) x 3 (t ) L1 3 (t ) B 3 (t )
13

q1 (t ) q2 (t ) q3 (t )

one row for each heat source

one row for each temperature location of interest
170 Semiconductor Device Thermal Characterization and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology

Each heat source needs to be independently heated.

Each temperature needs to be measured whether heating itself or being heated by another.

Time (sec) thermal system boundary

Measurement cycle(s)
Time (sec)

*Special thanks to Dave Billings for this slide
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Temperature (°C)

Power input (W)

but first, some words about …

Thermal RC networks
• Grounded (Cauer) vs.. non-grounded (Foster) • Orders of magnitude, rungs • Pulses and periodic waveforms • Short-time behavior, limits, and limitations

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Thermal capacitance (grounded vs.. non-grounded)
• In electrical circuit, voltage on a capacitor is difference between its two terminals, and you have physical access to both • A “lumped parameter” thermal model is predicated on energy storage being determined entirely by one temperature • Therefore, in a thermal circuit, you only have access to one “terminal” of each capacitor, namely the one where you identify the temperature. The other terminal is “ground”.
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Models: grounded vs.. non-grounded
“Cauer” ladders “Foster” ladders

• Physical significance: if thermal capacitors are grounded, they bear some relationship to a physical system; not so for non-grounded C’s • Mathematical convenience: certain non-grounded networks are mathematically “trivial” • Interchangeability: single-input thermal systems can be represented as either grounded or non-grounded; • multiple-input thermal systems are easy to model as grounded-C networks; it can be done, though with some intricate bookkeeping, using non-grounded-C networks
174 Semiconductor Device Thermal Characterization and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology

Actual thermal RC networks
Non-grounded C
“Foster” ladder
1.7004 ° C/W 2.6627 3.9740 10.0255 11.7747 35.3008 33.1212 Tj

vs..

grounded C comparison
“Cauer” ladder
Tj

7.02E-04 W-sec/°C 2.3207 ° C/W 4.41E-03 5.89E-02 1.55E-01 6.03E-01 1.46E+00 4.16E+00
2.7397 8.3551 14.6949 21.0538 39.637 9.7581 Ta

5.96E-04 W-s ec/°C 4.20E-03 3.67E-02 1.01E-01 4.13E-01 9.20E-01 1.14E+01

Ta
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2-rung Foster model

R1

C1

R1

1 sC1

1 sC1 1 R1

R1 R1C1 s 1

R2 R2 C2 s 1

R2

C2

R2

1 sC2

R2 R2 C2 s 1

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2-rung Cauer model
C1 R1
1 sC2

R1

1 sC1

R1
R2 R2 C2 s 1

1 sC1

R2

C2

R2

R1

R2 R2 C2 s 1

1 sC1

1 sC1 1 R1 R2 R2 C2 s 1

R1 R2 C2 s R1 R2 R1C1 R2 C2 s R1C1 R2 C1 R2 C2 s 1
2

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2-rung models compared
• • Time constants are roots of denominators "tau" is not RC product when capacitors are grounded !

non-grounded capacitors:
(Foster)
R1 R1C1 s 1 1 1 C1 s 1
1
2

grounded-capacitors:
R1 R2 C2 s R1 R2 R1C1 R2 C2 s R1C1 R2 C1 R2 C2 s 1
where time constants are 2 R1 C1
1

(Cauer)
s s R1 R2 R1 R2 C 2 1
1

can be written

1 C1

s

1
2

R2 R2 C2 s 1 1 1 C2 s 1
2

can be written

1

c r

c

1

c r

2

c

c 4 r

r 100 10 3 1 1

c 0.01 0.1 1 /3 0.1 1

1

2

R1C1

R2C2

2 R2 C2
2

where time constants are
1

r 1 c

r
r

r 1 c
R2 R1 c

2

r
C1 C2

4

r c

R1C1

2

R2 C2

and defining

0.99 0.91 0.73 0.90 0.38

1.01 1.10 1.36 1.11 2.62

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Interesting (and important) implications
“Foster” ladder
Rungs can be in any order and Tj has identical behavior! So where do you “split” it?
Tj

“Cauer” ladder
Order matters, so a “split” can make good physical sense. Tj
2.3207 ° C/W 5.96E-04 W-s ec/°C 4.20E-03 3.67E-02 1.01E-01 4.13E-01 9.20E-01 1.14E+01 Ta

1.7004 ° C/W 2.6627 3.9740 10.0255 11.7747 35.3008 33.1212

7.02E-04 W-sec/°C 4.41E-03 5.89E-02 1.55E-01 6.03E-01 1.46E+00 4.16E+00

package

2.7397 8.3551

??

14.6949 21.0538 39.637 9.7581

environment

Ta

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Orders of magnitude and rungs
• It is a rare transient curve that cannot be followed very accurately with time constants no closer than about 1 order of magnitude apart. This means that you need only about one rung per decade of transient response.

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For what it’s worth ...
Every Cauer (grounded-capacitor) ladder has a mathematical solution. By definition, its mathematical solution represents a corresponding Foster (non-grounded-capacitor) ladder. Every Foster (non-grounded-capacitor) ladder having distinct (i.e. non-repeated) time constants, has a corresponding Cauer (grounded-capacitor) equivalent. (However, there is no a priori guarantee that all R’s and C’s will be positive!)
Ref: L. Weinberg, Network Analysis and Synthesis, McGraw Hill Book Company, Inc., 1962

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RC network math
Cauer ladder continued fraction:
Z sC1 R1 sC 2 1 1 1 1 R2 ... 1 ...

with some algebra, both may be written:
Z Nn s Dn 1 s

Foster ladder, sum of simple fractions:
Z R1 R1C1s 1 R2 ... R2 C 2 s 1 Ri ... Ri Ci s 1

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Arbitrary repetitive pulse

Q

t p 2p

p – period of waveform

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Generalized periodic square wave
So consider a general rectangular pulse positioned arbitrarily within a

repetitive cycle of period p. We can derive expressions for the
infinite sum of responses in three regions :
Q t – arbitrary time of interest
m t a

R(t )
i 1

Ri 1 e Fi (t )
j 1

i

t a jp

Ri 1 e
m

i

t

R(t )
i 1

Ri 1 e

i

p b – pulse turns off a – pulse turns on

2p

t′ – measured from edge of power step
m t b

R(t )
i 1

Ri 1 e
t b jp

i

0 t
184

a

a t

b

b t

p

Fi (t )
j 1

Ri 1 e

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Infinite summation
Utilizing the identities
j 0

zj

1 1 z

and
j 1

z

j

1 z 1

and doing some algebra, we can show these results:

0 t
b t p

a
a t p

a t
i

b
b t p a t
i

b t
e
p
i i

p
b t a t

Fi (t )

Ri

e

i

e
p
i

Fi (t )

Ri 1

e

Fi (t )

Ri

e

i

e
p
i

i

1 e

1 e

1 e
m

In each domain, we then sum over all rungs of the Foster model:

F (t )
i 1

Fi (t )

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RCEnd result for arbitrary periodic power Model for Multiple Square Waves in One Cycle

An important point of this example is that for complex power inputs, absolute peak temperatures do not always correspond to the ends of the highest power pulse!
Semiconductor Device Thermal Characterization and System Analysis (RPS) April 2010

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Short-time limits
• What do RC models do at shortest time? – roll off linearly with time
t t

R(t )

R1 1 e

1

R2 1 e t
1

2

 t
2

R1 1 R1 t
1

1

t2  2 21

R2 1 R1 t
1

1

t2  2 2 2 

t2  2 21

t2  2 21

R(t )

R1
1

R2
2

t

R1
2 1

R2
2 2

t2   2

So for small t: R(t ) (const) t

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RC models and Surface Heating
• It turns out that if R’s and C’s grow at a uniform ratio, a sqrt(t) behavior ( b t ) is approached in the limit • If ratio is 1:3 (increasing with “distance” from junction node), rung-to-rung time constant ratio will be about

one order of magnitude, and the network will follow theoretical sqrt(t) within a few percent

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Rungs vs.. sqrt(t) behavior
1.0E+0

Exact sqrt(t) model
1.0E-1

1.0E-2

1 rung 1.0E-3 2 rungs @ 3.0:1 3 rungs @ 3.0:1 4 rungs @ 3.0:1 1.0E-4 1.0E-8 5 rungs @ 3.0:1 1.0E-7 1.0E-6 1.0E-5 1.0E-4 1.0E-3 1.0E-2 1.0E-1 1.0E+0 1.0E+1

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Where does that leave us with respect to the applicability of RC networks?
• We need to pay attention to silicon thickness vs.. device “technology”
– if surface heating is a good model, be sure your RC network has time constants short enough to land “within” the silicon – within the silicon timescale
L2

, if surface heating is a good

model, you have to “extend” the RC network into that region – on the other hand, if surface heating is not a good model (implying that volumetric heating is better), the fastest rung of your RC network can be set to the actual R&C corresponding to the volume being heated
190 Semiconductor Device Thermal Characterization and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology

Multiple heat-source RC networks
• You need data (experiment or simulation) • Fit an RC network (or networks) to the data
– Foster networks, we’ll see an Excel-based approach – Cauer networks, beyond the scope of this tutorial

• Using SPICE: directly input your RC networks
– Foster networks can be complicated – Cauer networks are straightforward

• Using Excel:
– Foster networks, we’ll see an Excel-based approach – Cauer networks are not practical

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Typical 2-input heating/response curves
250
q1 self avg q2 self avg interact

200

q1
R(t) [C/W]
150

q1 RC-fit q2 RC-fit q1<->q2 fit

100

q2

50

0 1E-4

1E-3

1E-2

1E-1

1E+0

1E+1

1E+2

1E+3

heating time [s]
Semiconductor Device Thermal Characterization and System Analysis (RPS) April 2010

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Fitting Foster ladders in Excel

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Using RMSE as fitting parameter
A 1 B C D E F G H I J K L

RMSE test pow er [W] Time

1.9 1.00

1.3 1.00

0.5 1.00 TABLE 1: Foster model taus 1.0E-4 1.0E-3 1.0E-2 1.0E-1 1.0E+0 1.0E+1 1.0E+2 q1 R's 11.2 7.6 12.5 76.6 70.0 2.3 41.0 q2 R's 0.8 2.9 2.3 45.6 67.5 2.2 37.7 interact R's -0.1 0.3 -0.7 -2.3 38.4 4.0 34.1

2
3

q1 self q2 self q1 RC- q2 RC- q1<avg avg interact fit fit >q2 fit 8.48 9.68 10.59 11.82 14.14 14.64 15.37 15.87 16.37 16.98 18.45 18.58 20.29 1.16 1.32 1.50 1.67 1.84 2.02 2.21 2.42 2.65 2.89 3.14 3.17 3.76 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 9.18 10.51 11.67 12.63 13.45 14.14 14.80 15.46 16.16 16.86 17.60 18.39 19.21 1.01 1.20 1.40 1.59 1.79 1.98 2.19 2.41 2.67 2.92 3.20 3.50 3.80 -0.03 -0.03 -0.03 -0.03 -0.02 -0.01 0.00 0.01 0.02 0.03 0.04 0.04 0.05

4 5 6 7 8 9

1.26E-4 1.64E-4 2.09E-4 2.60E-4 3.18E-4 3.82E-4 4.58E-4 5.48E-4 6.57E-4 7.78E-4 9.19E-4 1.09E-3 1.28E-3

10
11 12 13

{=SQRT(SUMSQ(E4:E100TABLE 5: results at arbitrary times B4:B100)/COUNT(E4:E100))} 120.5 100.7
0.00 25.0 {=$G$2*SUM(interact_Rs 25.0 *(1-EXP(-A4/taus)))} 30.0 0.01 59.6 0.05 90.0 39.1

14
15 16

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Excel’s “Solver”
Use Excel’s “solver” to minimize the error between the input data and the RC model.
1000 0.6 0.4 100 0.2 0

-0.2 10 -0.4 -0.6 1 Simlation data R-C model Fit Error -0.8 -1 -1.2 100 1000

0.1 1E06

1E05

1E- 0.001 0.01 04

Simulation data
0.1

1

10

Time (sec)

After optimization

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Fit error (C/W)

R(t) (C/W)

Using SPICE to exercise the models

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Using Foster RC models in SPICE
Tself1 (volts) Tself2 (volts)

Q1 (amps)
+ + Tj1 Tpos1 Tj2 -

Tpos2 time

Tneg2

Tneg1

Q2 (amps)

time

different networks of self heating elements
Semiconductor Device Thermal Characterization and System Analysis (RPS) April 2010

identical networks of positive interaction elements
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identical networks of negative interaction elements

197

1/4th of a 4-input Foster RC SPICE model
Piecewise linear current source for power input from each source generating heat.
Summing tool to add voltages from the separate interaction networks with the self heating network Thermal equivalent Foster RC networks (note that all these R’s are positive) The output port (OUT1) will be where you want to monitor the temperature response Each heat source will require a similar block in order to simulate the temperature response of the self heating effect as well as the interactions. Thermal ground – by adding a voltage potential to the ground point ambient temperature can be added.

*Special thanks to Dave Billings for this slide
198 Semiconductor Device Thermal Characterization and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology

A 2-input Cauer network model
Tj1 C11 R11 R12 C12 C22 R22 C23 R23 C24 time R21 Tj2 Apply q1 to Tj1 node

C21

q1 (watts)

C13

R33 R13 C14 R14 C5 R44

R24
R5 C6 R6 q2 (watts) Apply q2 to Tj2 node

C7 R7 time

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Using Excel to exercise Foster models

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Setting up a 2-input Excel model
I
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

J

K

L

M

N
ambient

O
25

P

Q

R

S

T

U

V

W

X

Y

Z

TABLE 1: Foster model taus 1.0E-4 1.0E-3 1.0E-2 1.0E-1 1.0E+0 1.0E+1 1.0E+2 q1 R's 11.2 7.6 12.5 76.6 70.0 2.3 41.0 q2 R's 0.8 2.9 2.3 45.6 67.5 2.2 37.7 interact R's -0.1 0.3 -0.7 -2.3 38.4 4.0 34.1

TABLE 2: pow er input vs time t0 change_at q1_pow er q2_pow er delta q1 delta q2 time 0.5 0.00 1.0 0.5 1.0 0.5 t1 0.10 1.0 0.0 0.0 -0.5 t2 0.25 0.0 1.3 -1.0 1.3 t3 0.40 0.8 0.9 0.8 -0.4 t4 1.00 0.8 0.0 0.0 -0.9 t5 1.10 0.0 0.0 -0.8 0.0 t6 1.50 0.0 1.0 0.0 1.0 t7 2.00 0.0 0.0 0.0 -1.0 t8 2.60 0.0 0.4 0.0 0.4 t9 3.00 0.6 0.4 0.6 0.0 t10 0.6 0.7 0.0 0.3 t11 0.0 0.7 -0.6 0.0

5.00 10.00

TABLE 3: unit step relative to chosen time 0.50 141.5 51.7 0.40 0.25 0.10 68.4 -15.1 0.00 0.0 0.0 0.00 0.0 0.0 0.00 0.0 0.0 0.00 0.0 0.0 0.00 0.0 0.0 0.00 0.0 0.0 0.00 0.0 0.0 1.4 0.00 0.0 0.0

TABLE 5: results at arbitrary times 120.5 0.00 0.01 0.05 0.10 0.25 0.26 0.26 0.27 0.29 25.0 59.6 90.0 112.2 143.6 116.5 110.0 101.0 89.2 100.7 25.0 30.0 39.1 47.4 37.1 46.3 50.3 56.9 67.4

TABLE 4: sum of terms T1_terms T2_terms -5.1 -109.3 -36.6 75.7

Tj1 =SUM(T2_terms)+ambient 180 Tj2 160 140 120 100 q1_pow er q2_pow er

{=IF(time>change_at,time-change_at,0)} {=SUM((S7*q1_Rs+S8*interact_Rs)* (1-EXP(-time/taus)))} 1.2
1

{=SUM((R7*interact_Rs+R8*q2_Rs)*(1-EXP(-time/taus)))}
{=TABLE(,time)}
0.8
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=SUM(T1_terms)+ambient
perature [C]

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Semiconductor Device Thermal Characterization and System Analysis (RPS) April 2010

80

Results from a 2-input Excel Foster model
180.0 160.0 140.0 1.00 120.0 Tj1 Tj2 q1_pow er q2_pow er 1.20 1.40

temperature [C]

100.0 80.0 60.0

0.80

0.60

0.40 40.0 20.0 0.0 0 1 2 3 tim e [s] 4 5 6 0.20

0.00

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power [W]

Organizing the sheet for transient solution
A cell for keeping track of the overall time progression of ALL blocks.

=IF(Master_Time>Row_Time,Master_time-Row_time,0)

Self heating column (each cell is a separate array formula) {=dP-D#*SUM(R1:R10*(1-EXP(-dtime/Tau1:Tau10)))}

Interaction heated columns (each cell is a separate array formula) {=dP-D#*SUM(R5:R10*(1-EXP(-dtime/Tau5:Tau10)))}

A section for power input to the heat sources
*Special thanks to Dave Billings for this slide
203 Semiconductor Device Thermal Characterization and System Analysis (RPS) April 2010

A section for Time changes

A section for power changes

A section for Temperature response calculation

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Table for plotting temperature output
=SUM(D1:D1_by_D4) +T_ambient

Note!

Time in this column can be independent of the time values in the power input section
Next, Select this whole region Apply a Data > Table option

*Special thanks to Dave Billings for this slide
204 Semiconductor Device Thermal Characterization and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology

Results from a 4-input Excel Foster model
Temperature (C)
1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 0.05 0.1 0.15 Time (Sec) 0.2 0.05 0.1 0.15 Time (Sec) 0.2 0.05 0.05 0.1 0.15 Time (Sec) 0.2 D1
3 2.5 2 1.5 1 0.5 0 0 0.05 0.1 Time (Sec) 0.15 T_D1 T_D2 T_D3 T_D4

Power (W)

0.25 D2

0.2

0.25

0.3

Last power input
0.1 0.15 Time (Sec) 0.2

0.25 D3

Temperature (C)

3 2.5 2 1.5 1 0.5 0 0 0.05 0.1 Time (Sec) 0.15 0.2 0.25 0.3

Power (W)

0.25

Temperature (C)

3 2.5 2 1.5 1 0.5 0 0 0.05 0.1 Time (Sec) 0.15 0.2 0.25 0.3

Power (W)

0.25

Temperature (C)

D4

3 2.5 2 1.5 1 0.5 0 0 0.05 0.1

Power (W)

Time (Sec) 0.15

0.2

0.25

0.3

*Special thanks to Dave Billings for this slide
205 Semiconductor Device Thermal Characterization and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology

Recap
• With the right tools, a thermal RC network can be generated from temperature data which is captured from measurements or finite element simulation. • Linear superposition provides a method for generating transient thermal models with several heat sources. • Foster networks can be used to simulate the thermal response of a system using a spreadsheet, whereas Cauer networks (which are closer to a physical lumped system) may require special tools (e.g. SPICE).

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Part III Thermal Runaway

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Thermal runaway
• Non-linear power vs.. junction temperature device characteristic • System thermal resistance isn’t low enough to shed small perturbations

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A linear thermal cooling system
TJ Q
Jx

Tx

junction temperature as function of power, theta, and ground … solving for power

Q

TJ

Tx
Jx

dQ dT

1
Jx

sensitivity (slope) of power with respect to temperature

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Effect of device line slope on system stability
system line power tendency to cool tendency to heat

Q

device line

Tx

TJ

junction temperature

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Operating points of thermal system when device line has negative second derivative
power the stable (that is, real) operating point an unachievable operating point system line tendency to cool device line

Q2

Q1

tendency to cool TJ1 Tx

power goes up with increasing temperature but rate of increase system falls with increase temperature tendency (negative second cannot be to heat system cannot derivative) maintained be successfully powered up

TJ2

junction temperature

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Operating points of thermal system when device line has positive second derivative
power an unachievable operating point even turning any the device on tendency perturbation destroyswill the stableit cause to cool (that is, real) runaway operating point tendency to heat system line

device line power goes up with increasing temperature, but rate of increase rises with increase (positive second derivative)

Q tendency to heat

Tx TJ

junction temperature

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Let’s see how it works
stable operating point device operating curve unstable operating point
2.0

1.6 Device Power Dissipation [W]

1.2

10°C/W system 25°C/W system 40°C/W system
213

0.8

NO operating point!

0.4

0.0 20 40 60 Junction Temperature [C] 80 100

Semiconductor Device Thermal Characterization and System Analysis (RPS) April 2010

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A paradox
0.5 W Case A 100°C junction identical 50°C/W 75°C 50°C/W 75°C 0.5 W Case B 100°C junction

lead
100°C/W

lead
0.2°C/W

25°C

thermal ground

74.9°C

thermal ground

thermal runaway, based on Jx=150°C/W, calculated to be at 125°C
Semiconductor Device Thermal Characterization and System Analysis (RPS) April 2010

thermal runaway, based on Jx=50.2°C/W, calculated to be at 150°C

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Paradox lost
raise the power by 0.1 W and see what happens
0.5 W0.1 +
0.5 W0.1 +

Case A
100 °C15 junction +

Case B
junction 100 °C5.02 + 50°C/W 75 °C0.02lead + 0.2°C/W

50°C/W 75 °C10 lead + 100°C/W

(fixed) 25°C

(fixed) 74.9°C

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Illustrating the paradox

Case B device line common nominal operating point 0.5 W

Case A

25°C

74.9°C 100°C

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Generic power law device and generic linear cooling system
power unstable operating point
Jx1

device line

system line A system line B 1
Jx1
Jx2

system line C

1

stable operating point

1

runaway point for original theta
runaway point for original thermal ground

Q

Tx
217

TJ Ty

TR2

TR1

junction temperature

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Don’t get confused by the terms!
a mathematical “power law” y ax an “exponential” power law (base is e)

device power

Q

V I

y
Semiconductor Device Thermal Characterization and System Analysis (RPS) April 2010

ex

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Definition of power law device
rule of thumb for leakage; 2x increase for every 10°C
T 2 10
( ln 2 ) T 10 T 10 ln 2

for constant voltage, power does the same
T T

I

Io

Q

VRIo e

Qo e

I Io e
I

Io e

T

1st and 2nd derivatives

Io e
T1 T2 I ln 1 I2

defining:

dQ dT

Qo

T

e

d Q dT
2

2

Qo
2

T

e

both always positive
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Semiconductor Device Thermal Characterization and System Analysis (RPS) April 2010

The mathematical essence
System line
Non-dimensionalizing

Leads to:
(system)

Q

T Tx
Jx

q

kz
Tx JxQo

z

T Tx

temperature

where:

Power law device line
T

k
q 1 e Qo
Tx

e

Q

power

(power law device)

Q

Qo e

q ez
Eliminating q:

kz

ez

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Perfect runaway transformed

ez

at point of tangency, slope equals height

k=ez

k=ez
k=ez k=ez z0

1

zTz

z
0

T Tx

1 z 0

zT

1

z0

zT

1

zT

zT
221 Semiconductor Device Thermal Characterization and System Analysis (RPS) April 2010

z0

1
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Transforming the nominal system
ez “operating” points nominal system line A k>e
(2 intersections)

k<e
(no intersections)

k=e 1
Semiconductor Device Thermal Characterization and System Analysis (RPS) April 2010

at point of tangency, slope equals height

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Everything transformed
non-dimensional power unstable, non-operating point

device line

q=ez

system line A

q=k1z q=k1(z-zx1)

system line B
1

stable operating point

k1

system line C

q=k2z

k2

e

runaway point for original theta

k2 1 zx1 zR2 1 zR1

k1

runaway point for original thermal ground

non-dimensional temperature

z x1 ln(k1) 1 z R 2
223 Semiconductor Device Thermal Characterization and System Analysis (RPS) April 2010

1 zR1 ln(k1)
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“Perfect runaway” results in original terms
runaway temperature based on original slope

runaway temperature based on original ambient

TR1

ln

Jx1Q o

TR2

Tx

max ambient that goes with it

system resistance that goes with it
Tx 1 Jx2

Tx1

ln

Jx1Q o

Qo

e

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The “operating” points
ez “operating” points unstable
kzu e zu

kz

stable 1
zs

kzs

e zs

zu

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Newton’s method for the intersections
kz
zi
1

ez
z

zi

F(zi ) F (z i )

ln kz

zi

1

F(z) z ln kz

1 F ( z) 1 z

k ln z i e 1 1 zi

For k/e ranging between 1.01 and 1000, convergence is to a dozen significant digits in fewer than 10 iterations.

zo

1 k

1 this initial guess k converges to lower, e e stable point

this initial guess converges to upper, z o unstable point
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ln k

1 ln

k e

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Semiconductor Device Thermal Characterization and System Analysis (RPS) April 2010

And the intersection points come from …
find the non-dimensional intersections first, then

Tstable

Tx

z stable

Tunstable

Tx

z unstable

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Real datasheet example
raw device data†
Vr [V]
Tmax [°C] Tref [°C] Itmax [A]

the device power curve parameters
@12V @40V

12
125 75 8.50E-3

40
125 75 2.80E-2

[°C]

17.9
9.4E-5

17.8
1.02E-3

Q o [W]

Itref [A]

5.20E-4

1.70E-3

T

I I0 e
Tmax Tref

Tmax Tref I ln max Iref

rule of thumb 10 gave us:

ln (2)

14.4

I0

It max e

Itref e

Q0

VRIo

† MBRS140T3

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Runaway analysis in nominal system
computed results

raw device data†
Vr [V] Tmax [°C] Tref [°C] Itmax [A] Itref [A] 12 125 75 8.50E-3 5.20E-4
Tx JxQo 1

@12V [°C] 17.9
9.4E-5 10.6 117.2 135.1 1055 92.9
Jx1

@40V 17.8
1.02E-3 0.97 74.4 92.2 96.6 92.8

@40V

40 125 75 2.80E-2 1.70E-3

Q o [W]

k (compare to unity) e Tx max [°C] given theta TR1[°C]
given ambient
Jx 2 max [°C/W]

1.609 83.5 101.3

k e

e

Tx

75

TR 2[°C]

100

† MBRS140T3

These translate into: a stable operating point at 80.6°C (and 0.09 W), an unstable point at 116.3°C (0.69 W)

Jx1

60

z z

0.312 2.315

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HTRB example
• Bidirectional Thyristor in reliability stress test (High Temperature Reverse Bias) • Goal is life tests at elevated temperature (say 125°C) • Problem is, they don’t last very long, and if junction temperature is anything like the chamber temperature, they appear to fail way too early good!
*Special acknowledgements to Dave Billings and Geoff Garcia for their contributions to this project
230 Semiconductor Device Thermal Characterization and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology

MT1 + 640 V G MT2

40 kΩ

HTRB test circuit

HTRB DUTHTRB data - sockets without heatsinks test time tab temperature vs..
200

Heatsink (tab) temperature [degC]

180 160 140 120 100 80 60 40 20 0 0 2000 4000 6000 test time [s] 8000 10000 12000 DUT T1 DUT T2 DUT T3 DUT T4 DUT T5 DUT T6 DUT T7 DUT T8 DUT T9 DUT T10

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HTRB DUT power vs.. test time
3 2.5 DUT W1 DUT W2 DUT W3 DUT W4 DUT W5 DUT W6 DUT W7 DUT W8 DUT W9 DUT W10

HTRB data - sockets without heatsinks

DUT Power [W]

2

1.5

1

0.5

0 0 2000 4000 6000 test time [s]
Semiconductor Device Thermal Characterization and System Analysis (RPS) April 2010

8000

10000

12000

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HTRB example

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Quick calculations from datasheet
Pd I (640 40000 I )
TJ
or

MT1

Ta
THS

Pd
Pd

JA

+ 640 V -

G MT2

TJ

J HS

• At room temp, if IDRM is 5 uA, then Pd is about zero (≈3mW), and TJ should thus equal chamber set point. • At 85°C, IDRM is about 0.1-0.2mA, thus Pd is on the order of 0.1W, so depending on theta-JA, TJ could be several degrees hotter than chamber set point (note, however, that TJ will still be well within 1°C of heatsink temperature, THS) • HOWEVER, at 125°C, if IDRM is 2mA, then Pd will be in excess of 1W. Depending on theta-JA, TJ could be 30-60°C above chamber set point (though still within a couple of degrees of heatsink temperature, if known).
234 Semiconductor Device Thermal Characterization and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology

40 kΩ

HTRB test circuit

Calculations based on actual measurements
Pd
I Vsense 1000

I (640 41000 I )
TJ
or

MT1

Ta
THS

Pd
Pd

JA

+ 640 V +

G MT2

TJ

J HS

• At room temp, IDRM (via Vsense) is 0.2uA, thus Pd is about zero (≈0.1mW), and TJ should thus equal chamber set point.
• At 85°C, IDRM is about 0.1-0.2mA, thus Pd is on the order of 0.1W, so depending on theta-JA, TJ could be several degrees hotter than chamber set point (note, however, that TJ will still be well within 1°C of heatsink temperature, THS) • At 125°C, IDRM is 2-3mA; Pd could be as high as 1.5W

40 kΩ

Vsense -

1 kΩ

• Max current observed was nearly 8mA (for Pd of 2.5W), and estimated TJ of 170°C just prior to device failure.
235 Semiconductor Device Thermal Characterization and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology

Modified HTRB test circuit

Actual “blocking current” data (time implicit)
1E-2 blocking current when theta-JA=35°C/W (DUT's in unmodified HTRB board)

1E-3 DUT I1 DUT I2 DUT I3 DUT I4 DUT I5 DUT I6 DUT I7 DUT I8 DUT I9 current

1E-4

1E-5

1E-6

1E-7 20 40 60 80 100 120 140 160
estimated junction temperature [°C]

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Actual “blocking Pd” data (time implicit)
1E+1 blocking Pd when theta-JA=35°C/W (DUT's in unmodified HTRB board)

1E+0

1E-1

1E-2

1E-3

DUT W1 DUT W2 DUT W3 DUT W4 DUT W5 DUT W6 DUT W7 DUT W8 DUT W9 power

1E-4 20 40 60 80 100 120 140 160
estimated junction temperature [°C]

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Power vs.. temperature (linear scales)
2.5 DUT W1 2 1.5 1 0.5 0 20 30 40 50 60 70 80 90 100 estimated junction temperature [°C] DUT W2 DUT W3 DUT W4 DUT W5 DUT W6 DUT W7 DUT W8 DUT W9
37°C/W system 10°C/ W system 4°C/W system

Pd [W]

110

120

130

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Proof-of-concept modified HTRB fixture

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Pd vs.. temperature on better heatsinks
1E-2 blocking current when theta-JA=10°C/W (using external 12°C/W heatsink)

1E-3 DUT I1 DUT I2 DUT I3 DUT I4 DUT I5 DUT I6 DUT I7 DUT I8 DUT I9

1E-4

1E-5

1E-6

1E-7 20 40 60 80 100 120 140 160
estimated junction temperature [°C]

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What if multiple devices on heatsink?
• Each device heats its neighbors to varying degrees, depending on distance • This adds background heat, that is, it raises the “effective ambient” of each device

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Graphically, background heat does this
2.0

Device Power Dissipation [W]

device operating curve

1.6

1.2

real runaway margin what you thought was your margin

0.8

25°C/W system

0.4

ij

Qi
60 Junction Temperature [C] 80

system with “background heating” of other devices
100

0.0 20

i j

40

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Math and Electrical References
1. M. Abramowitz, I. Stegun (eds), Handbook of Mathematical Functions, Dover Publications, Inc., 9th Printing, Dec. 1972 S.D. Senturia, B.D. Wedlock, Electronic Circuits and Applications, John Wiley & Sons, 1975 M.F. Gardner & J.L. Barnes, Transients in Linear Systems (Studied by the Laplace Transformation), Vol. I, John Wiley and Sons, 1942 R.S. Muller, T.I. Kamins, Device Electronics for Integrated Circuits, 2nd Ed., John Wiley & Sons, 1986 Ben Nobel, Applied Linear Algebra, Prentice Hall, 1969 H.H. Skilling, Electric Networks, John Wiley and Sons, 1974 L. Weinberg, Network Analysis and Synthesis, McGraw Hill Book Company, Inc., 1962 H. Wayland, Complex Variables Applied in Science and Engineering, Van Nostrand Reinhold Company

Thermal-Related Applications Notes available at http://www.onsemi.com/pub/Collateral/ANxxxx-D.PDF
569: “Transient Thermal Resistance - General Data and its Use,” May 2003 1083: “Basic Thermal Management of Power Semiconductors,” October 2003 1570: “Basic Semiconductor Thermal Management,” January 2004 8044: “Single-Channel 1206A ChipFET™ Power MOSFET Recommended Pad Pattern and Thermal Performance,” December 2005 8072: “Thermal Analysis and Reliability of WIRE BONDED ECL,” April 2006 8080: “TSOP vs.. SC70 Leadless Package Thermal Performance,” January 2004 8199: “Thermal Stability of MOSFETs,” August 2005 8214: “General Thermal Transient RC Networks ,” April 2006 8215: “Semiconductor Package Thermal Characterization,” April 2006 8216: “Minimizing Scatter in Experimental Data Sets,” April 2006 8217: “What's Wrong with %Error in Junction Temperature,” April 2006 8218: “How to Extend a Thermal - RC - Network Model,” April 2006 8219: “How to Generate Square Wave, Constant Duty Cycle, Thermal Transient Response Curves,” April 2006 8220: “How To Use Thermal Data Found in Data Sheets,” April 2006 8221: “Thermal RC Ladder Networks,” April 2006 8222: “Predicting the Effect of Circuit Boards on Semiconductor Package Thermal Performance,” April 2006 8223: “Predicting Thermal Runaway,” April 2006 8402: “Thermal Considerations for the NCS5650”, June 2009 8432: “Thermal Consideration for a 4x4 mm QFN”, December 2009

2. 3.

4.

5. 6. 7. 8.

Thermal Textbooks & References
9. H.S. Carslaw & J.C. Jaeger, Conduction of Heat In Solids, Oxford Press, 1959 10. E.R.G. Eckert & R.M. Drake Jr., Heat and Mass Transfer, McGraw Hill, 1959 11. J.P. Holman, Heat Transfer, 3rd Ed., McGraw Hill, 1972 12. J. VanSant, Conduction Heat Transfer Solutions, Lawrence Livermore National Laboratory, Livermore, CA, 1980

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Thermal Test Standards
1. EIA/JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air), Electronic Industries Alliance, December 1995

2. EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method Environmental Conditions - Forced Convection (Moving Air), Electronic Industries Alliance, March 1999
3. EIA/JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions - Junction-to-Board, Electronic Industries Alliance, October 1999 4. EIA/JEDEC Standard JESD51-12, Guidelines for Reporting and Using Electronic Package Thermal Information - Electronic Industries Alliance, May 2005 5. JEDEC Standards No. 24-3, 24-4, 51-1, Electronic Industries Alliance, 1990 6. MIL-STD-883E, Method 1012.1, U.S. Department of Defense, 31 December 1996

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Related Papers by Stout, et al
1. “Two-Dimensional Axisymmetric ANSYS® Simulation for TwoParameter Thermal Models of Semiconductor Packages,” 7th International ANSYS Conference & Exhibition, May 1996, R.P. Stout & R.L. Coronado 2. “End User's Method for Estimating Junction Temperatures Due to Interactions of Other Dominant Heat Sources in Close Proximity to the Device in Question,” ITHERM, May 1996, D.T. Billings & R.P. Stout 3. “Evaluation of Isothermal and Isoflux Natural Convection Coefficient Correlations for Utilization in Electronic Package Level Thermal Analysis,” 13th Annual IEEE Semiconductor Thermal Measurement and Management Symposium, January 1997, B.A. Zahn and R.P. Stout 4. "Electrical Package Thermal Response Prediction to Power Surge", ITHERM, May 2000, Y.L. Xu, R.P. Stout, D.T. Billings 5. “Accuracy and Time Resolution in Thermal Transient Finite Element Analysis,” ANSYS 2002 Conference & Exhibition, April 2002, R.P. Stout & D.T. Billings 6. “Minimizing Scatter in Experimental Data Sets,” ITHERM 2002 (Eighth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems), June 2002, R.P. Stout 7. “Combining Experiment and FEA into One, in Device Characterization,” ITHERM 2002 (Eighth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems), June 2002, R.P. Stout, D.T. Billings 8. “A Two-Port Analytical Board Model,” ITHERM 2002 (Eighth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems), June 2002, R.P. Stout 9. “On the Treatment of Circuit Boards as Thermal Two-Ports,” InterPack2003, July 2003, R.P. Stout 10.“A Conjugate Numerical-RC Network Prediction of the Transient Thermal Response of a Power Amplifier Module in Handheld Telecommunication,” InterPACK 2005, July 2005, T.Y. Lee, V.A. Chiriac, R.P. Stout 11.“Part 1:Linear Superposition Speeds Thermal Modeling,” Power Electronics Technology, January 2007, R.P. Stout 12.“Part 2:Linear Superposition Speeds Thermal Modeling,” Power Electronics Technology, February 2007, R.P. Stout 13.“Power Electronics System Thermal Design: Linear Superposition,” IEEE Expert Now on-line tutorial <http://ieeexplore.ieee.org/articleSale/modulesabstract.jsp?mdnu mber=EW1054>, February 2007, Roger Stout 14.“Power Electronics System Thermal Design: Thermal Runaway,” IEEE Expert Now on-line tutorial <http://ieeexplore.ieee.org/articleSale/modulesabstract.jsp?mdnu mber=EW1055>, February 2007, Roger Stout 15.“Using Linear Superposition to Understand the True Meaning of Theta-JA,” 12th Annual Automotive Electronics Council Reliability Workshop, May 2007, R.P. Stout 16.“Using Linear Superposition to Solve Multiple Heat Source Transient Thermal Problems,” InterPACK 2007, July 2007, D.T. Billings, R.P. Stout 17.“Linear Superposition and the True Meaning of Theta-JA,” 1-hr Seminar at 2007 Power Electronics Technology Exhibition and Conference, October 2007, R.P. Stout 18.“Thermal Performance of a Monolithic Thin-Shell Concrete Dome,” ASME Heat Transfer Conference, July 2007, R.P. Stout 19.“Beyond the Datasheet: Demystifying Thermal Runaway,” Power Electronics Technology, November 2007, R.P. Stout 20.“The Datasheet is Not Your Mother” (Executive Viewpoint article for) Power Electronics Technology, February 2008, R.P. Stout 21.“Psi or Theta: Which One Should You Choose?” Power Electronics Technology, March 2008, R.P. Stout 22.“Don’t Be Misled By Power Device Specs” Power Electronics Technology, May 2008, R.P. Stout 23.“Reliability of NLDMOS Transistors Subjected to Repetitive Power Pulses,” IEEE International Reliability Physics Symposium, April 2008, Poster Session paper, Chris Kendrick, Roger Stout, and Michael Cook

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