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97.477 Lecture

January 13, 2003

**Why this lecture is important.
**

We will use MOSFETs to design our circuits.

MOSFET capacitances tend to limit the

frequency response of circuits.

n

**In order to predict the circuit frequency response, we
**

need to estimate the circuit capacitance.

**We may use the MOSFET capacitance to our
**

advantage, by intentionally implementing

capacitors using MOSFETs.

Assume the drain implant region length is 6µm and the width equals the device width. .EXAMPLE PROBLEM: Differential Pair 3dB-Down Frequency Find the 3dB.down frequency (include the MOSFET capacitances). Ignore the sidewall capacitances. In order to solve this problem. The capacitance is a combination of the load capacitance and the MOSFET capacitances. we must find the total capacitance present at the output of the amplifier.

Extrinsic Versus Intrinsic MOSFET parasitic capacitances are subdivided into two general categories: n n extrinsic capacitances intrinsic capacitances. B S p+ n+ G D n+ p-sub intrinsic region . Extrinsic capacitances are associated with regions of the transistor outside the dashed line. Intrinsic capacitances are all those capacitances located within the boxed region.

e Extrinsic Capacitance Types Overlap capacitances that are mostly dependent on geometry.e Intrinsic Model G CGB. One capacitor is used between each pair of transistor terminals. D CGD. S .e B W CBW.e CSB.e CDB.e CGS. each of which is associated with a region of the transistor’s geometry.e CSD.EXTRINSIC CAPACITANCES Extrinsic capacitances are modeled by using lumped capacitances. plus an additional capacitor between the well and the bulk if the transistor is fabricated in a well. Junction capacitances that are dependent on geometry and on bias.

This overlap area gives rise to the gate overlap capacitances.Gate Overlap Capacitances There is some overlap between the gate and the source and the gate and the drain. .

where Cox is the thin -oxide field -capacitance per unit area under the gate region. the gate-drain and gate source overlap capacitances can be approximated by the expression C GSO = CGDO = W LD Cox. . IEEE Transactions on Electron Devices. the overlap capacitances can be highly bias dependent and therefore non-linear. W. “A Compact-Charge LDD-MOSFET Model”. The overlap capacitances CGSO and CGDO are proportional to the width. 44. refer to Klein. of the device and the amount that the gate overlaps the source and the drain. typically denoted as “LD” in SPICE parameter files. 1997. 1483-1490. Sep. The overlap capacitances of the source and the drain are often modeled as linear parallel-plate capacitors.. vol. Gate-Source/Drain Overlap Capacitances For MOSFETs constructed with a lightly-doped-drain (LDD-MOSFET). For non-LDD MOSFETs. P. pp. since the high dopant concentration in the source and drain regions and the gate material implies that the resulting capacitance is largely bias independent. For a treatment of overlap capacitances in LDD MOSFETs.Gate-Source/Drain Overlap Capacitances The overlap between the gate and the source and the gate and the drain gives rise to the gate overlap capacitances denoted by CGSO and CGDO for the gate-to-source overlap capacitance and the gate-todrain overlap capacitance respectively.

5382 + NSUB=1.4 THETA=1.3400E-04 MJ=0.0920E-10 CGSO=4.5100E-10 + MJSW=0.6684 DELTA=1.1930E-02 + KAPPA=9.4551 + NSUB=8.2440E-08 KP=4.8120E-01 RSH=1.8690E-02 + KAPPA=1.200000U TPG=1 + VTO=0.3660E+00 CGDO=2.MODEL CMOSP PMOS LEVEL=3 PHI=0.6100E-01 CGDO=4.9 THETA=5.7748E-04 + UO=493.1660E+00 GAMMA=0.7900E+05 ETA=1.0000E-11 + MJSW=0.9352 DELTA=1.0700E+00 LD=4.1260E-10 + CGBO=3.700000 TOX=9.0920E-10 + CGBO=3.7490E-02 RSH=1. Gate-Source/Drain Overlap Capacitances From Model Files .6890E-10 CJ=9.1500E+11 VMAX=2.2960E+05 ETA=2.71000 PB=0.9080E+11 VMAX=2.21200 PB=0.4927E-05 + UO=124.9900000 . The values are “per-width” values.0710E+16 NFS=5.7765E-10 CJ=5. Estimates of the fringing field capacitances based on measurements are normally used.Gate-Source/Drain Overlap Capacitances It turns out that fringing field lines add significantly to the total capacitance.76700 CJSW=2.48300 CJSW=2.1290E+17 NFS=7.MODEL CMOSN NMOS LEVEL=3 PHI=0. There are values for NMOS MOSFETs and PMOS MOSFETs.1260E-10 CGSO=2.930000 .2030E-08 KP=1.9000E-04 MJ=0.2380E-02 LD=5.200000U TPG=-1 + VTO=-0.700000 TOX=9.6000E-09 XJ=0.6000E-09 XJ=0.6680E+01 GAMMA=0. The gate-to -drain overlap capacitances are generally given as measured parameters in the MOSFET model files.

The parasitic extrinsic gate-bulk capacitance has little effect on the gate input impedance and is therefore often ignored. it is negligible in comparison to the intrinsic gate-bulk capacitance. The source-drain capacitance is denoted as CSD. .bulk capacitance. is located in the overlap region between the gate and the substrate (or well) material outside the channel region. The parasitic gate. Source-Drain Capacitance Accurate models of short channel devices may include the capacitance that exists between the source and drain region of the MOSFET. In particular.e.e .Gate-to-Bulk Overlap Capacitance There is a gate-to-bulk overlap capacitance caused by imperfect processing of the MOSFET. The parasitic extrinsic gate-bulk capacitance is extremely small in comparison to the other parasitic capacitances. CjGB.

e is very small in comparison to the other extrinsic capacitances.Source-Drain Capacitance Although the source-drain capacitance originates in the region normally associated with intrinsic capacitance. and is therefore normally ignored. it is still referred to as an extrinsic capacitance. . CSD. The value of this capacitance is difficult to calculate because its value is highly dependent upon the source and drain geometries. For longer channel devices.

The depletion region acts similarly to the dielectric of a capacitor.e. CjBD. and is called the depletion region. The depletion region increases in width as the reverse voltage across it increases. the capacitance should decrease.e. The resulting region contains almost no carriers. Increasing the reverse bias voltage across the PN junction therefore decreases the diode capacitance. .Refresher: Diode Capacitance When a reverse voltage is applied to a PN junction . the holes in the p-region are attracted to the anode terminal and electrons in the n-region are attracted to the cathode terminal. If we imagine that the diode capacitance can be likened to a parallel plate capacitor. and at the drain region there is a drain-to-bulk junction capacitance. the depletion region width) increases. then as the plate spacing (i. CjBS. Source/Drain-Bulk Junction Capacitances At the source region there is a source-tobulk junction capacitance.e.

Well-Bulk Junction Capacitance If the MOSFET is in a well. CjBW. n n The capacitance associated with the side wall portion is found by multiplying the length of the side-wall perimeter (excluding the side contacting the channel) by the effective sidewall capacitance per unit length. The well-bulk junction capacitance is calculated similarly to the source and drain junction capacitances. must be added. The capacitance for the bottom-wall portion is found by multiplying the area of the bottomwall by the bottom-wall capacitance per unit area.bulk junction capacitance into side-wall and bottom-wall components. by dividing the total well. If more than one transistor is placed in a well.Source/Drain-Bulk Junction Capacitances The junction capacitances can be calculated by splitting the drain and source regions into a “side-wall” portion and a “bottom-wall” portion. . a well-to-bulk junction capacitance. the well.e.bulk junction capacitance should only be included once in the total model.

The zero-bias side-wall capacitance and the per unit area zero-bias bottom-wall capacitance give the worst case (largest) capacitance. then you should generally use a worst case capacitance. Both the effective side-wall capacitance and the effective bottom-wall capacitance are bias dependent. .Junction Capacitance Equations A Note on Estimation If you are estimating a worst case delay.

There are values for NMOS MOSFETs and PMOS MOSFETs.7748E-04 + UO=493.76700 CJSW=2.6000E-09 XJ=0.700000 TOX=9.7490E-02 RSH=1.1500E+11 VMAX=2.9352 DELTA=1.0700E+00 LD=4.2030E-08 KP=1.7748E-04 + UO=493.0920E-10 CGSO=4.0000E11 MJSW=0. .200000U TPG=1 + VTO=0.6680E+01 GAMMA=0.48300 CJSW=2.0710E+16 NFS=5.4 THETA=1.1290E+17 NFS=7.5382 + NSUB=1.6000E-09 XJ=0.1930E-02 + KAPPA=9.1260E10 + CGBO=3.1660E+00 GAMMA=0.2960E+05 ETA=2.4551 + NSUB=8.71000 PB=0.5100E-10 MJSW=0.8690E-02 + KAPPA=1.9900000 Cj = CJSW × perimeter vd 1 − φ0 MJSW + CJ × area vd 1 − φ0 MJ .6890E-10 CJ=9.200000U TPG=-1 + VTO=-0.0920E10 + CGBO=3.700000 TOX=9.1260E-10 CGSO=2.6684 DELTA=1.0000E-11 MJSW=0.MODEL CMOSN NMOS LEVEL=3 PHI=0.7765E-10 CJ=5.8690E-02 + KAPPA=1.3400E-04 MJ=0.9900000 .1500E+11 VMAX=2.2030E-08 KP=1.2380E-02 LD=5.9000E-04 MJ=0.200000U TPG=1 + VTO=0.5382 + NSUB=1.76700 CJSW=2.6100E-01 CGDO=4.6000E-09 XJ=0.6100E-01 CGDO=4.4 THETA=1.6680E+01 GAMMA=0.8120E-01 RSH=1.21200 PB=0.9000E-04 MJ=0.1290E+17 NFS=7.930000 MODEL EXAMPLE .9080E+11 VMAX=2.MODEL CMOSP PMOS LEVEL=3 PHI=0.9 THETA=5.0920E-10 + CGBO=3.3660E+00 CGDO=2.0700E+00 LD=4.700000 TOX=9.7765E-10 CJ=5.7900E+05 ETA=1.MODEL CMOSN NMOS LEVEL=3 PHI=0.8120E-01 RSH=1.71000 PB=0.7900E+05 ETA=1.2440E-08 KP=4.4927E-05 + UO=124.6684 DELTA=1.Junction Capacitances From Model Files The junction capacitances can be calculated from parameters given in the MOSFET model files.0920E-10 CGSO=4.

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