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net/publication/270540478

**Simulation of Vedic Multiplier Using VHDL Code
**

Minor Project Report (Phase 1)

Technical Report · December 2014

DOI: 10.13140/2.1.2754.3367

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1 author:

Bhupendra Pratap Singh

Shri Mata Vaishno Devi University

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**Available from: Bhupendra Pratap Singh
**

Retrieved on: 14 April 2016

Simulation of Vedic Multiplier Using VHDL Code Minor Project Report (Phase 1) Submitted by Bhupendra Pratap Singh (2012EEC27) Avinash Pandey (2012EEC26) Saurabh Singh (2012EEC15) Saurabh Pandey (2012EEC11) School of Electronics and Communication Engineering Shri Mata Vaishno Devi University Katra December 2014 .

GUIDE Dr. The report has reached the standard of fulfilling of requirement of the regulation related to degree. We wish best for his endeavor. Saurabh Singh 2011eec15 and Saurabh Pandey 2012eec11 to the School of Electronics and Communication Engineering is completed under the supervision and guidance of the undersigned. Neeraj Tripathi DIRECTOR Mr.SHRI MATA VAISHNO DEVI UNIVERSITY School of Electronics and Communication Engineering CERTIFICATE This to be certify that the minor project entitled “ Simulation Of Vedic Multiplier Using VHDL Code ” being submitted by Bhupendra Pratap Singh 2012eec27. Sumeet Gupta . Rakesh Kumar Jha Dr. Avinash Pandey 2012eec26.

. In fact. area parameters of multipliers.In this project. Multiplication is one of the basic arithmetic operations and it requires substantially more hardware resources and processing time than addition and subtraction. the comparative study of different multipliers is done for low power requirement and high speed.Abstract -In a typical processor. In computers. a typical central processing unit devotes a considerable amount of processing time in implementing arithmetic operations.72% of all the instruction in typical processing units is multipliers. also gives information of “Urdhva Tiryakbhyam” algorithm of Ancient Indian Vedic Mathematics which is utilized for multiplication to improve the speed. 8. particularly multiplication operations .

We consider ourselves very lucky and honoured to have our teachers to guide us. Bhupendra Pratap Singh (2012eec27) Avinash Pandey (2012eec26) Saurabh Singh (2012eec15) Saurabh Pandey (2012eec11) . I am also very grateful to Dr. Rakesh Kumar Jha for his constant motivation and guidance. I would like to thank Dr. We would also like to express our gratitude to Department of Electronics and Communication Engineering. and for helping us to attain highest possible standard of our project on “Simulation of Vedic Multipler Using VHDL code”. SMVDU. Neeraj Tripathi for providing valuable information and guidance for making this project successful.Acknowledgement A mini project is a golden opportunity for learning and self-development.

..12 4......1 Logic implementation…………………………………………………………......1 Vedic Multiplication……………………………………………………………8 2.9 3 ARCHITECTURE 3.4 Algorithm for 4×4 bit multiplication Using Urdhva Triyakbhyam……………...8 2.10 3...no.13 5 CONCLUSION…………………………………………………….11 4 SIMULATION RESULT 4....Contents S....2 Speed…………………………………………………………………………......2 Urdhva Triyakbhyam Sutra……………………………………………………. Chapter Page 1 INTRODUCTION 1.........3 Result………………………………………………………………………….1 I/O Vedic multiplication Algorithm……………………………………………12 4.1 A brief General Introduction ………………………………………………….2 RTL Schematic……………………………………………………………….7 2 ALGORITHAMS OF VEDIC MATHMATICS 2..6 1...14 6 REFERENCES ………………………………………….8 2....3 Multiplication of Two Decimal Numbers……………………………………..15 .2 Vedic Mathematics ……………………………………………………………..

This work presents different multiplier architectures. Reducing the time delay and power consumption are very essential requirements for many applications. Since Multiplication dominates the execution time of most DSP algorithms. In the past multiplication was implemented generally with a sequence of addition. Particular multiplier architecture is chosen based on the application.CHAPTER 1 INTRODUCTION 1. Digital multipliers are the most commonly used components in any digital circuit design. circuit complexity. each offering different advantages and having trade-off in terms of speed. Minimizing power consumption for digital systems involves optimization at all levels of the design. and area and power consumption. Fast Fourier Transform (FFT). Depending upon the arrangement of the components. The speed of multiplication operation is of great importance in DSP as well as in general processor. So there is a need of high speed Multiplier. Multiplier based on Vedic Mathematics is one of the fast and low power multiplier. the multiplier lies in the critical delay path and ultimately determines the performance of algorithm. reliable and efficient components that are utilized to implement any operation. In many DSP algorithms. Multiplication based operations such as multiply and Accumulate (MAC) and Inner Product are among some of the frequently used Computations Intensive Arithmetic functions (CIAF) currently implemented in many digital signal processing (DSP) Applications such as Convolution. One of the key arithmetic operations in such applications is multiplication and the development of fast multiplier circuit has been a subject of interest over decades. the circuit style and topology. . the architecture for implementing the circuits and at the highest level the algorithms that are being implemented. This optimization includes the technology used to implement the digital circuits. there are different types of multipliers available. They are fast.1 A Brief General Introduction Multiplication is an important fundamental function in Arithmetic Operations.. Currently multiplication time is still the dominant factor in determining the instruction cycle Time of a DSP chip. There have been many algorithms proposals in literature to perform multiplication. subtraction and shift operations. Filtering and in Microprocessors in its Arithmetic and logic Unit (ALU).

Especially.1960) comprised all this work together and gave its mathematical explanation while discussing it for various applications. the other is zero. coordinate).1. 10. quadratic equations.2 VEDIC MATHMETICS Vedic mathematics is part of four Vedas (books of wisdom). Puranapuranabyham – By the completion or noncompletion. (Anurupye) Shunyamanyat – If one is in ratio. methods of basic arithmetic are extremely simple and powerful. trigonometry. 8. These Sutras along with their brief meanings are enlisted below alphabetically. 9. Vedic mathematics is not only a mathematical wonder but also it is logical. 2. 4. geometry (plane. Gunitasamuchyah – The product of the sum is equal to the sum of the product. Vedic maths deals with several basic as well as complex mathematical operations. algebra. His Holiness Jagadguru Shankaracharya Bharati Krishna Teerthaji Maharaja (1884.Veda (book on civil engineering and architecture). Swamiji constructed 16 sutras (formulae) and 16 Upa sutras (sub formulae) after extensive research in Atharva Veda. Chalana-Kalanabyham – Differences and Similarities. 3. 5. 15. Sankalana. which is an upa-veda (supplement) of Atharva Veda. Nikhilam Navatashcaramam Dashatah – All from 9 and last from 10. geometry etc. Ekanyunena Purvena – By one less than the previous one. Yaavadunam – Whatever the extent of its Deficiency. Paraavartya Yojayet – Transpose and adjust. The word “Vedic” is derived from the word “Veda” which means the store-house of all knowledge.vyavakalanabhyam – By addition and by subtraction. . Shesanyankena Charamena – The remainders by the last digit. Obviously these formulae are not to be found in present text of Atharva Veda because these formulae were constructed by Swamiji himself. factorization and even calculus. Sopaantyadvayamantyam – The ultimate and twice the penultimate. That’s why it has such a degree of eminence which cannot be disapproved. Shunyam Saamyasamuccaye – When the sum is the same that sum is zero. It is part of Sthapatya. 13. Vyashtisamanstih – Part and Whole. Ekadhikina Purvena – By one more than the previous One. It gives explanation of several mathematical terms including arithmetic. Vedic mathematics is mainly based on 16 Sutras (or aphorisms) dealing with various branches of mathematics like arithmetic. Vedic maths has already crossed the boundaries of India and has become an interesting topic of research abroad. Gunakasamuchyah – The factors of the sum is equal to the sum of the factors. 7. 11. 12. 14. Urdhva-tiryagbhyam – Vertically and crosswise. 6. Due these phenomenal characteristics. 1.

2.2 Urdhva Triyakbhyam Sutra The multiplier is based on an algorithm Urdhva Tiryakbhyam (Vertical & Crosswise) of ancient Indian Vedic Mathematics. Urdhva Tiryakbhyam Sutra is a general multiplication formula applicable to all cases of multiplication. the same ideas to the binary number system to make the proposed algorithm compatible with the digital hardware. Vedic multiplication based on some algorithms.1 Vedic Multiplication The proposed Vedic multiplier is based on the Vedic multiplication formulae (Sutras). 2. In this work.CHAPTER 2 ALGORITHAMS OF VEDIC MATHMATICS 2. space and power efficient. some are discussed below. It literally means “Vertically and crosswise”. Therefore it is time. It is based on a novel concept through which the generation of all partial products can be done with the concurrent addition of these partial products. These Sutras have been traditionally used for the multiplication of two numbers in the decimal number system. Power dissipation which results in higher device operating temperatures. It is demonstrated that this architecture is quite efficient in terms of silicon area/speed.3 Multiplication of Two Decimal Numbers Multiplication of two decimal numbers (Figure1) .

As the result of this multiplication would be more than 4 bits. For the simplicity. Line diagram for the multiplication is shown in Fig.4 Algorithm for 4×4 bit multiplication Using Urdhva Triyakbhyam To illustrate the multiplication algorithm. The digits on the both sides of the line are multiplied and added with the carry from the previous step. The process is followed according to the steps shown in Figure 2... This generates one of the bits of the result and a carry.4 where the dots represent bit „0‟ or „1‟. let us consider the multiplication of two binary numbers A3A2A1A0 and B3B2B1B0. each bit is represented by a circle.To illustrate this multiplication scheme. Line diagram for multiplication of two 4-bit numbers is shown in Fig. for example. R3R2R1R0. This carry is added in the next step and hence the process goes on. 2 which is nothing but the mapping in binary system.bit numbers . the multiplication of two decimal numbers (325 * 738). 2.2. Figure 2: Line diagram for multiplication of two 4. we express it as. an alternate illustration is given with the help of line diagrams in figure. Least significant bit R0 is obtained by multiplying the least significant bits of the multiplicand and the multiplier. To make the methodology more clear.

Firstly. CHAPTER 3 3. R0 = A0B0 R1 = A0B1+B1A1+C0 R2 = A2B0+B2A0+A1B1+C1 R3 = B0A3+B3A0+A2B1+B2A1+C2 R4 = A3B1+A1B3+A2B2+C3 R5 = A3B2+B3A2+C4 R6 = A3B3+C5 R7 = C6 .1 Logic implementation The following basic equations are being used in the construction of algorithm. the LSB of the multiplicand is multiplied with the next higher bit of the multiplier and added with the product of LSB of multiplier and next higher bit of the multiplicand (crosswise). least significant bits are multiplied which gives the least significant bit of the product (vertical). The sum gives second bit of the product and the carry is added in the output of next stage sum obtained by the crosswise and vertical multiplication and addition of three bits of the two numbers from least significant position. Then.

GATE LEVEL DESCRIPTION OF 4 BIT MULTIPLIER (FIGURE 3 GATE LEVEL DESCRIPTION OF 4 BIT MULTIPLER) .

2 RTL Schematic (FIGURE 3 RTL SCHEMATIC BLOCK REPRESENTATION) (FIGURE 5. RTL SCHEMATIC WITH INTERNAL ARCHITECTURE) .3.

1 I/O Vedic multiplication Algorithm (figure 6 input/output algorithm) 4.420ns. Vedic multiplier is also very fast in compare of booth multiplier and array multipliers which speed is approx. 22ns.CHAPTER 4 4.2 SPEED The speed of the designed Vedic multiplier is 16. . Which is faster than the simple multipliers.

4. B3B2B1B0=1001 OUTPUT: R7R6R5R4R3R2R1R0=01110101 (FIGURE 7 OUTPUT OF VEDIC MULTIPLER) .3 RESULT INPUT: A3A2A1A0=1101.

Multipliers are also very useful for DSP applications like FFT. Which increase the speed of devices.CHAPTER 5 CONCLUSION It can be concluded that Vedic multiplier is superior in all aspects like Speed. Delay. Urdhva Triyakbhyam is general mathematical formulae and equally works the best. Convolution. . and Complexity. Ancient Vedic Mathematics gives efficient algorithms or formulae for multiplication. Applicable to all cases of multiplication. filtering etc.

49. Member. 701-705. 10. [2]. Jiun-Ping Wang. [5].1253-1258. Proceedings published by International Journal of Computer Applications® (IJCA). ―High-Speed Booth Encoded Parallel Multiplier Design. 2001. IEEE. No. 7.Gianluca Corne a and Jordi Cortadella ―Asynchronous Multipliers with Variable-Delay Counters. Wen-Chang Yeh and Chein-Wei Jen. IEEE Conference.Yuan Guo. [7]. JULY 2000. Vol.xilinx. ―A Simple High-Speed Multiplier Design. [4]. and Jean-Luc Gaudiot.‖ IEEE Transactions On Circuits And Systems—II: Express Briefs. pp. Implementation of Vedic Multiplier for Digital Signal Processing. IEEE Transactions on Computers. pp. pp. and Cang. [3]. Shiann-Rong Kuang. pp. IEEE Conference. No. 55. ―Modified Booth Multipliers With a Regular Partial Product Array. 5. No. 56. 2001. IEEE Transactions on Computers. pp.CHAPTER 6 REFERENCES [1]. International Conference on VLSI. ―Design of a High Performance 32x32-Bit Multiplier With a Novel Sign Select Booth Encoder. Kiwon Choi and Minkyu Song. 701-704. October 2006.404-408 [8] www. May 2009.com . Jung-Yup Kang. 692-701. Communication & Instrumentation (ICVCI) 2011. Vol. Vol.

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