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CPEG 448: Introduction to VLSI Design

Fall 2014
2013 Catalog Data:
CPEG 448 - Design and implementation of very large scale integrated circuits. CMOS and BiCMOS
technologies, basic topological structure of ICs. Clocking characteristics, resistance, capacitance and
power estimation, system level design and implementation issues. Custom layout and verification
using CAD tools. Synthesis of designs from VHDL descriptions. Term project will include the design
and testing of a custom integrated circuit.
3 lecture hours, 3 semester hours.
Prerequisites: CPEG 315 and EE 348

“CMOS VLSI Design: A Circuits and Systems Perspective,” by Neil H E Weste, David
Harris; Addison-Wesley, 4th Edition, 2010

Course Learning Outcomes:
Having successfully completed this course, the student should be able to:
 Students will be able to design a complete digital VLSI chip ranging from its
digital design to its simulations, and CMOS layout.
 Students will be able to design CMOS digital circuits and optimize their layout for
less delay.
 Students will be able to design and simulate complex digital designs in VHDL and
 Students will be able to estimate the resistance, capacitances in VLSI circuits so
that they can optimize delays, and power consumption.
 Students will be able to design, layout, simulate and verify actual VLSI circuits
using modern tools such as Mentor Graphics.
 Students will demonstrate Engineering design skills.
 Students will exercise written communication skills in terms of technical writing.
 Students will be able to function competently in a related entry-level career.
Topics (by week):
o Review of Digital VLSI Circuit Design technologies

(1 Week)

and BiCMOS technologies.


Digital Gate structures in different technologies,
Comparison of different digital circuit technologies based on
Noise margins, fanouts, power consumption, rise/fall delays.
Identifying characteristics of an ideal digital circuit technology.
MOS transistor theory
MOS transistor fundamentals
PMOS and NMOS technologies

(1 Week)

determining pitch. floorplan design. CMOS Testing (if time permits) Class/Laboratory Schedule: Lectures: 2 sessions per week with duration of 1hr 15min each Lab Sessions: Laboratory work is an integral part of this course. VHDL/Verilog simulations and chip layout. simulation and layout of complex digital VLSI Circuits. o Circuit Characterization and Performance Estimation (3 Weeks) o Resistance estimation MOS transistor capacitance and routing capacitance Distributed RC effects. Laboratory projects are implemented using Mentor Graphics VLSI design software where students do the actual layout and simulation of the digital VLSI designs. their circuit design. noise margins. Clocked CMOS. routing power lines and busses using metal1.o Designing gates and PLAs in NMOS technology. sizing conductors Charge sharing. 10. wire length design guide Inductance calculations. Written reports (using a word processor) are . fanouts NAND. PseudoNMOS. Prevention against latchup in CMOS. Design. P-Well and Twin-tub processes Layout design rules in CMOS Layout of simple gates. latches and Master-Slave flip flops in CMOS CMOS Fabrication technology (1 Week) o N-Well. scaling of MOS transistor dimensions Complementary CMOS. CVSL. Several laboratory assignments emphasize the practical aspects of the course. yield calculations. metal2. CMOS technology (1 Week) o Pseudo NMOS technology CMOS inverter I/O characteristics. BiCMOS and Dynamic CMOS Layout of CMOS circuits using Mentor Graphics (2 Weeks) o CMOS Layout of digital gates and systems Layout verification using DRC and LVS SPICE and VHDL simulations using Mentor Graphics (2 Week) o Discussion of example chip design projects (1 Week) Examples of digital VLSI projects. delay estimation (rise and Fall delays) Gate delays and body effect minimization CMOS buffer design to optimize delay Power consumption estimation. System Design in CMOS technology (2 Weeks) Layout of adders and flip-flops Layout of a digital system. NOR and logic expressions in CMOS Multiplexers. decoders.

required for all labs. There is a required final project where a complete design of medium complexity digital VLSI circuit ranging from simulation to complete chip layout is required. Lab Schedule: Week 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Topic VHDL Part 1 and Assignment 1 VHDL Part 2 and Assignment 2 Assignment 3 Assignment 4 Verilog Part 1 and Assignment 5 Verilog Part 2 and Assignment 6 Mentor Graphics Part 1 and Assignment 7 Mentor Graphics Part 2 and Assignment 8 Assignment 9 Assignment 10 Project Project Project Project Project Contribution to ABET Criterion 5 Requirements: Engineering Topics 3 credits Relationship to Program Outcomes: The course objectives help in contributing towards the following program outcomes at a beginner’s level: Program Outcome 4 Techniques/Skills: Larger projects such as chip design and FPGA implementations with simulation and verification tools Program Outcome 10 Diversity/LLL: B/D continuum is used to collect incidental/anecdotal data from representative sample of courses Prepared by : Dr. 2014 Credit Hour: As a UB policy it is expected that each student that attends one hour of classroom instruction will require a minimum of two hours of out of class student work each week for approximately fifteen weeks for one semester. . Ausif Mahmood Date: June 20.