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The Physical Insights Into an Abnormal Erratic Behavior in the

Resistance Random Access Memory
Y. J. Huang1, Steve S. Chung1,*, H. Y. Lee2, Y. S. Chen2, F. T. Chen2, P. Y. Gu2, and M. -J. Tsai2
1

Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan
* Tel: (886)-3-573-1830, Email: schung@cc.nctu.edu.tw
2
Electronics and Optoelectronics Research Laboratory, Industrial Technology Research Institute, Taiwan

Keywords- RRAM, Soft-breakdown, Random Telegraph Noise,
Resistive Switching Mechanism, Multi-level Operation

I.

INTRODUCTION

The switching mechanism of HfOx based RRAM has been
considered as the formation and rupture of the soft-breakdown
(SBD) paths under applying bias, which are formed along the
grain boundaries (GBs) [1]. Under certain operating conditions,
traps are generated in the dielectric and strongly influence the
SBD path. On the other hand, the Random Telegram Noise
(RTN) method is one of the great techniques to study the
behavior of the oxide traps. Recently, by measuring the gate
current (IG) RTN fluctuation, it has been able to explain the
SBD behavior of high-κ dielectric MOSFET [2]. Few reports
have then been developed to understand the behavior of
switching in RRAMs by RTN [3]. Further understanding of the
traps becomes important for the reliable operation of RRAM. It
was found that different voltage ramping rates during operation
cause different distributions of the SBD paths. In this paper, we
will utilize the RTN approach, to analyze the carrier
trapping/de-trapping in the RRAM devices. By observing the
bias dependence of capture and emission time, the defect
location could be identified, and the carrier trapped/de-trapped
mechanisms will be investigated. The impact on the RRAM
readout error will then be demonstrated.
II. DEVICE PREPARATION
The structure of RRAM was the TiN/TiOx/HfOx/TiN
stack. The HfO2 thin film was deposited by atomic layer
deposition (ALD), while all the other thin films were
deposited by sputtering methods, as shown in Fig. 1. The
device area is 0.48x0.48 μm2, and the thickness of HfO2 layer
is 10 nm. The TiOx layer was originally titanium metal layer.

978-1-4799-0113-5/13/$31.00 ©2013 IEEE

After the deposition, the titanium and oxide formed an
imperfect titanium oxide layer [4].
TiN

TiN (sputtering)

Ti

TiOx

Ti (sputtering)
HfO2 (ALD)
TiN(sputtering)

HfO2

Form TiOx

Ti/SiO2/Si substrate

TiN

Fig. 1 The cross section and the major process flow of the
experimental RRAM device.

III. CHARACTERISTICS OF MULTI-LEVEL OPERATION
In this section, we will demonstrate the operation methods
of resistive random access memory to achieve multi-level
storage and the associated characteristics. One method is sweep
operation and the other one is pulse operation. Also, we will
discuss the reliability issues for these two different methods.

Current (A)

Abstract— The voltage ramping rate during the forming and setreset process is strongly related to the formation of softbreakdown (SBD) paths. In this paper, we examined the effect of
two different operation methods in RRAM, including sweep and
pulse modes. The RTN analysis has been utilized to examine their
influences on the SBD paths. For the first time, we found a
different behavior of the RTN currents generated by two
different modes of operation. Results show that more SBD paths
are created during the pulse mode which led to the instability of
switched resistance, and induced the erratic bit during the
readout of RRAM.

10

-3

10

-4

10

-5

10

-6

Vreset , Ireset,max

C.C.

Vstop

Vset

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

Top Voltage (V)
Fig. 2 Typical current-voltage characteristics of a bipolar RRAM.
C.C. represents the compliance current. Vstop is the maximum
negative sweep voltage. Vreset or Ireset,max are the voltage or current at
which reset takes place. Vset is the voltage at which set takes place.

A. The Sweep Operation
The RRAM structure that we used is suitable for bipolar
operation. In Fig. 2, when RRAM is switched to LRS, we
define Vset as the turn on voltage, and Iset as the corresponding
current. For the memory device, we limit the RRAM current
during the set and forming process by Agilent 4156C with the
compliance current (C.C.). When RRAM is switched to HRS,
we define Vreset as the turn off voltage and Ireset as the
corresponding current. Also, we define the maximum negative
voltage as Vstop. So, during the set operation by the sweep, the
waveform in Fig. 3(a) was used, and when the RRAM current
reaches the compliance current that we set, this current will be
fixed by Agilent 4156C. Hence, we can achieve multi-level
storage in the low resistance state by changing different

MY.3.1

5 V 0V 0V with C. we will focus on the random telegraph noise behavior which was operated by the case 1 and case 2 as aforementioned. the waveform in Fig. RRAM current becomes smaller as an electron captured in the trap site.C. Depth of the Traps The energy band diagram of the metal-insulator-metal (MIM) structure with the trap energy level ET and depth ZT is MY.2 2. Then. If the pulse amplitude is too large. Fig.4 1. and then.1 2. a smaller current will be expected. While if the trap is filled by electrons. (b) Fig. B. The current magnitude is about several nanoAmpere (nA) and noise amplitude is about 25% of the maximum current through the dielectric.2 . Then. 6(a) respectively.5 1. in contrast. we fix the pulse voltages where Vlow is 0 V and Vhigh is -2 V. and the trap energy apart from conduction band. a huge current through the dielectric can be measured. as shown in Fig.6 SBD path SBD path 0V -8 pulse width : 1x10 sec Filled Empty 100 1. As shown in Fig. the RRAM device will see reverse breakdown and this device will be failed during the switching. the multi-level storage is achieved by changing the pulse widths. 3 Two different operation modes of RRAM: (left) case 1-sweep mode. 1. B.4 2. So. For the high resistance state (HRS). HfO2 B.C.5 V to 2. C as e 1: S weep mode C as e 2: P uls e mode 4V IV.pulse mode. The pulse width is 1x10-8 sec. The positive pulse width is 1x10-8 sec.3 2. the pulse operation is another operating method for RRAM device. The negative pulse amplitude is -2 V. τc for high current states.9 2. A two-level RTN of the dielectric current between the top and bottom electrodes can be measured such that the trap properties can be well observed.5 V. The pulse amplitude should be selected appropriately. The same as sweep operation. So.E. SET without C. 3 (left) was used until a CC limit is reached. I versus time. 0V 0V A. T. (b) The pulse width dependence of the resistance at high resistance state. By investigating the current variation. General Equation of RTN 4V Forming 0V Forming Terminated as reaching Compliance Current (C. The multi-level storage can be achieved by changing different stop voltage Vstop.0 2.compliance currents. The two characteristic time in the above measured current can be defined: (1) capture time.E. 3 (right).5 2. we add a positive bias to RRAM top electrode to accomplish the set process. Fig. capture. during the set operation by the sweep.E. 5(b). 5(a). We can extract the trap position by analyzing the capture and emission time. we control the width of the negative pulse. In Fig.C. we change the pulse widths from 5x10-8 to 1x10-6 sec. such as the trap depth into dielectrics.) 0V Vhigh +1. and (2) emission time. Vstop RESET SET -2V RESET Pulse width Fig. where the current fluctuation (ΔI) is caused by the traps located in the dielectric. The multi-level operation is achieved by changing the pulse amplitudes. we will get different resistance levels. A typical result of the measured RTN signal is shown in Fig. The amplitude. 4 (a) The pulse voltage dependence of the resistance at low resistance state.7 1. by changing the pulse amplitudes from 1.E.8 1. as defined in Fig.3. the RRAM resistances at the low resistance state can be controlled by different pulse voltages to achieve multi-level storage. 5 (a) The schematic of the current instability caused by the electron trapping/detrapping (a) Trap empty with large current through the MIM dielectric.2 RTN MEASUREMENTS OF TRAPS In this section. The Pulse Operation Besides the sweep operation. τe for low current states. B. when the trap is empty. (right) case 2.6 1.0 0. (b) Trap filled state with smaller current. 10 Fig. 80 60 tRESET -2V VSET (V) 40 -7 10 -6 tRESET ( sec ) HfO2 (a) 20 1. The resistance decreases as the pulse voltage increases. 4(b). as illustrated in this figure. 5(a). Different from the set operation. and emission time are the critical parameters of the random telegraph noise (RTN) behavior and depend on the trap properties. 4(a). In this case. RRAM device after a negative voltage sweep now changes the resistance state.8 resistance ( kΩ ) resistance (kΩ) VSET T. we will discuss the random telegraph noise of RRAM. The reason is that electron trapped will screen the proximity of the trap and hence suppress the current. to achieve multi-level storage of high resistance state (HRS). we can understand what happened in the soft breakdown paths in the RRAM device. where the currents. at different VG caused by the trap are demonstrated.

25V RESET_1. Namely. q ∂V ⎣⎢ ⎝ τ e ⎠ ⎦⎥ 2 10 1 10 0 10 -1 10 -2 10 -3 τ c (sec) (2b) (3) 0. ECd is the conduction band edge of the HfO2. while the electrons escape in Case 2 is due to the thermionic emission since the electrons can not escape via the tunneling for the much deeper traps. two different operation methods.35 nm -1 Fig. The results predict excellent 10 years lifetime.35nm).86 nm ZT(Case 2) = 3. the trap location can be determined by Eq.1 Current ( nA ) 7 0. the LRS multi-level resistance is achieved by five compliance currents (200 μA ~ 650 μA) over a long period of time at 100oC. The Observation of Erratic Bit forMulti-Level Operation Next.7V SET_1. Vtop. and Vox is the oxide voltage drop which is the same as the applied bias. 7 (a) and (b).(1) The expression for the capture time and emission time in terms of the position of the trap can be derived as the following: ⎛τ ⎞ k BT ln ⎜ c ⎟ = Φ 0 − ⎡⎣( ECd − ET ) + E x ⎤⎦ and ⎝τe ⎠ z Ex =| q T Vox | . 10 8 10 τ e (sec) (a) Here. By differentiating Eq. Fig.E.3 . Depending on the operation mode. the ZT is derived as zT = 10 resistance (Ω) τc = exp ⎡⎣( ET − EF ) / k BT ⎤⎦ . but not for HRS where erratic bits were observed as a result of the window closure. For the data retention measurement.5V SET_1. the τc-τe plots show different behaviors. in which Case 1 is the sweep mode and Case 2 is the pulse mode. 7(b). the aforementioned sweep and pulse modes were performed.e. 8 (a) Data retention characteristics of multi-level states by the sweep mode (case 1).5) with respect to the applied bias. τe ( sec ) shown in Fig.the pulse mode. MY. RTN Behavior for Different Operation Modes B. (b) Energy band diagram of the MIM structure considering the trap energy level ET and the depth ZT.3V SET_2. The fractional occupancy of the oxide trap is governed by 1 10 2 10 3 10 4 10 5 10 Time ( sec ) 6 10 7 10 8 10 (b) Fig. 6 (a) The parameters of the measured RTN with a fluctuation of two level currents. τe τc.2 TOX τc = exp[(ET − EF ) / kBT ] τe k T ∂ ⎡ ⎛ τc ⎞⎤ ZT = B ln⎜ ⎟ ⋅Tox q ∂V ⎢⎣ ⎝ τe ∂ ⎠⎥⎦ 6 (b) To examine the correlation between forming-set-reset and SBD generation[5]. from which the location of traps can be identified. (b) Data retention characteristics of multi-level states by the pulse mode (case 2). Tox (2a) k BT ∂ ⎡ ⎛τ c ⎞ ⎤ ln ⎜ ⎟ ⋅ Tox .1V 4 RESET_1. ZT(Case 1) = 1. (c) The extracted trap depths for two different traps in case 1 (ZT= 1. we tried the multilevel operation by the sweep method (case 1). The results project excellent 10 years lifetime for LRS state.the sweep mode and (b) Case 2. Their mechanisms are different.5V 1 0 C. ZT is the position of the trap in the oxide from the top electrode.1 2 HfO2 (b) 10 EF ΔI 0 1 ECd -ET IHIGH ϕ0 10 Top Voltage.1V SET_2. Tox is oxide thickness. 8(a). Φ0 is the difference between the work function of TiN and electron affinity of HfO2. C.3.3 -0. The LRS data writing for five resistance levels has been demonstrated by varying the compliance currents of the sweep process. The prediction of 10-year lifetime on this plot shows excellent data retention characteristics.5V). and the HRS multi-level storage was obtained by using various stop voltages (-1. 10 Fig. (4. From the above understanding. in which the escape of electrons out of the trap is based on the tunneling. V top ( V ) resistance ( kΩ ) τc 1 T. as can be seen from the τc-τe plot in Figs. In Fig.5V 10 RESET_1.0V to -1.2 0. while they are much deeper into the HfO2 for the pulse operation. Further. i. (c) RESET_1.E. 6(b).86nm) and case 2 (ZT= 3.0V 10 years SET_200uA SET_250uA SET_350uA SET_500uA SET_650uA 3 0 10 1 10 2 10 3 10 4 10 5 Time (sec) 10 6 10 7 10 8 (a) RESET_1E-6s 100 L1 L3 L2 RESET_5E-7s RESET_1E-7s RESET_5E-8s 10 L4 10 years 1. q is the elementary charge.. IHIGH and ILOW. 7 Variation of τc and τe when the voltage on the top electrode increases: (a) Case 1.5 SET_1. we will discuss the correlation between the generated traps using different operating schemes and their impacts on the multi-level operation. the traps were generated more close to the top electrode for sweep operation.3 ZT 6 5 ILOW τe 5 Time ( sec ) (a) -0. first the τc-τe plots can be obtained from the measured top voltages. (3) [2].9V SET_2. 10 -0.

MY. but some levels are overlapped.In comparison.6 (b) Fig. and M. C. Iglesias.18 0. The first author would like to thank the Emerging Memory team of EOL. S. pp. 2010. The created SBD paths of fast voltage ramping rate operation are more disperse than that of the slower one. Jammy. vol. McKenna. N. Dig. -Li. (a) sweep operation.30 | Top Voltage | ( V ) [1] (b) Fig.20 0. Veksler. as illustrated in Fig. H. Bosman. C. Pey. and R. and H. Terai. December 15-17. 11(b). 10 The current variation amplitude versus different Vtop: ΔI and ΔI/I vs. M.Saito. Wu. J. P. Y. 3 V. as revealed in Fig. M.2 25 0 latter will cause the instability of switched resistance. For the low resistance state (LRS). the grain boundaries in the dielectric layer constitute a preferential leakage current path.” in IEDM Tech. Fig.” in IEDM Tech. 2008. T.fewer SBD paths are created. Kotsuji. 11(a). For the sweep operation (i. -L. 8(b). But after 200 seconds baking (100 oC). -H. 6 4 REFERENCES 2 0 0.e. Wu. “Low Power and High Speed Bipolar Switching with A Thin Reactive Ti Buffer Layer in Robust HfO2 Based RRAM. As shown in Fig.” in IEDM Tech. Padovani. Bersuker. M. Dig. no. For the pulse mode (i. Lee. Here. 456 – 459. the high and low resistance states are separated more than one order difference. Raghavan. 32. Hada.. more SBD paths of pulse operation are generated than the sweep operation ones. P. 716 – 718. the trap will screen most of the SBD paths.10 (a) and (b)..09 0. Larcher. Park. the window closure.. for the high resistance state (HRS).. -J.22 0. C. 6. The above observations are attributed to the difference in the operation mode as well as the generated traps.. Shluger. The [2] [3] [4] [5] G.. P. 2011. Wang. By sensing the current. it can be clearly seen that the overlap between L2 and L3 was observed around 102 seconds. D. To show their discrepancies. Y. Chen.06 0. “Metal Oxide RRAM Switching Mechanism Based on Conductive Filament Microscopic Properties. K. the faster ramping rate). Lian. When the influence becomes larger. Kauerauf “Very Low Reset Current for an RRAM Device Achieved in the Oxygen-vacancy-controlled Regime. Lien. X. (a) Sweep operation.10 | Top Voltage | ( V ) (a) ΔI / IHIGH ( % ) ΔI ( nA ) Fig. -C. Lin. Yum. which leads to the erratic bit during the readout. M. and T. 9(b). F.4 . So. -H. the SBD path will be generated intensively at the weakest point first. pp. the multi-level operation by the pulse mode was demonstrated in Fig. the RTN currents are used to describe the differences.e. L. C. Different carrier trapping/detrapping mechanisms have been observed from different operation methods. ITRI. S. S.07 0. which are then transformed into the soft-breakdown (SBD) path during the forming or set-reset process. We do not see any problem to control the high and low resistance states in the beginning. there are six levels which are operated by different pulse amplitudes at a fixed pulse width during the set operation. The ΔI/I is larger than 37 % and it might cause the resistance unstable.W.K. the other SBD paths increase near that point. Tsai. Dig. Vandelli. a huge RTN signal with ΔI/I over 37 % was observed. Gilmer.. Chen. Taiwan for the device fabrication. 775 – 778. D. i. Liu. Nafría.” IEEE Electron Device Lett. Vtop after different operation modes. pp. (b) By measuring the RTN current.more disperse SBD paths are created such that the RTN signal shows a much larger influence to the current flow. which is the origin of the erratic bit as seen in (a). -Y. Chung et al. Sakotsubo. W. D. Also.16 0. Kirsch. S. especially for multilevel operation.3. A. 787-790. the slower ramping rate). Tzeng.05 0. -H. -S. H. Taylor. 30 Current (μA) Resistance ( kΩ ) 20 ΔI/I = 37% reset_1E-7s reset_2E-7s reset_5E-7s reset_8E-7s 10 0 10 1 10 2 10 Time ( sec ) 3 10 4 2 10 3 Time ( sec ) 4 (b) (a) ΔI ( nA ) SUMMARY AND CONCLUSIONS In summary. A. the high resistance state becomes unstable. Chen. -J. 9(a). X.8 1.e. 40 2 ACKNOWLEDGMENT 20 1 0 30 20 10 0. (b) pulse operation. 11 Illustration of the SBD paths distribution after different operation modes. C.26 0. “The Observation in Trapping and Detrapping Effects in High-k Gate Dielectric MOSFETs by a New Gate Current Random Telegraph Noise(IG RTN) Approach. we found it was caused by the random telegraph noise (RTN).the high resistance states overlapped with each other. M. pp. larger RTN signal tends to induce the erratic bit in Fig.24 0. V. So.. -S.0 15 ΔI / IHIGH ( % ) (a) 2. pp. 9. Figs. After that. 2. 3) during the reset operation. Porti.28 0.” in IEDM Tech. Chang. 297 – 300. Y. Dig. 2008. L. 9 (a) Erratic bit. 2009. (b) Pulse operation. -Y. “Effect of Bottom Electrode of ReRAM with Ta2O5/TiO2 Stack on RTN and Retention. we used four levels which are achieved by different pulse widths (Fig. 1.. there are many weaker spots of GBs which will create more disperse SBD paths during a severe voltage jump. Results show that the pulse mode operation exhibits a more disperse SBD path which leads to the erratic bit during the readout of RRAM for multi-level operation.08 0.