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Internal Use Only

North/Latin America
Europe/Africa
Asia/Oceania

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LCD TV
SERVICE MANUAL
CHASSIS : LJ91T

MODEL : 47SL80YD

47SL80YD-SA

CAUTION
BEFORE SERVICING THE CHASSIS,
READ THE SAFETY PRECAUTIONS IN THIS MANUAL.

P/NO : MFL61862413 (0911-REV00)

Printed in Korea

CONTENTS

CONTENTS .............................................................................................. 2
PRODUCT SAFETY ..................................................................................3
SPECIFICATION ........................................................................................6
ADJUSTMENT INSTRUCTION ...............................................................12
EXPLODED VIEW .................................................................................. 17
SVC. SHEET ...............................................................................................

Copyright
LG Electronics. Inc. All right reserved.
Only for training and service purposes

-2-

LGE Internal Use Only

SAFETY PRECAUTIONS
IMPORTANT SAFETY NOTICE
Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by
in the
Schematic Diagram and Exploded View.
It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent
Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.

Leakage Current Hot Check (See below Figure)


Plug the AC cord directly into the AC outlet.

General Guidance
An isolation Transformer should always be used during the
servicing of a receiver whose chassis is not isolated from the AC
power line. Use a transformer of adequate power rating as this
protects the technician from accidents resulting in personal injury
from electrical shocks.
It will also protect the receiver and it's components from being
damaged by accidental shorts of the circuitry that may be
inadvertently introduced during the service operation.
If any fuse (or Fusible Resistor) in this TV receiver is blown,
replace it with the specified.
When replacing a high wattage resistor (Oxide Metal Film Resistor,
over 1W), keep the resistor 10mm away from PCB.

Do not use a line Isolation Transformer during this check.


Connect 1.5K/10watt resistor in parallel with a 0.15uF capacitor
between a known good earth ground (Water Pipe, Conduit, etc.)
and the exposed metallic parts.
Measure the AC voltage across the resistor using AC voltmeter
with 1000 ohms/volt or more sensitivity.
Reverse plug the AC cord into the AC outlet and repeat AC voltage
measurements for each exposed metallic part. Any voltage
measured must not exceed 0.75 volt RMS which is corresponds to
0.5mA.
In case any measurement is out of the limits specified, there is
possibility of shock hazard and the set must be checked and
repaired before it is returned to the customer.

Leakage Current Hot Check circuit


Keep wires away from high voltage or high temperature parts.

AC Volt-meter

Before returning the receiver to the customer,


always perform an AC leakage current check on the exposed
metallic parts of the cabinet, such as antennas, terminals, etc., to
be sure the set is safe to operate without damage of electrical
shock.
To Instruments
exposed
METALLIC PARTS

Leakage Current Cold Check(Antenna Cold Check)


With the instrument AC plug removed from AC source, connect an
electrical jumper across the two AC plug prongs. Place the AC
switch in the on position, connect one lead of ohm-meter to the AC
plug prongs tied together and touch other ohm-meter lead in turn to
each exposed metallic parts such as antenna terminals, phone
jacks, etc.
If the exposed metallic part has a return path to the chassis, the
measured resistance should be between 1M and 5.2M.
When the exposed metal has no return path to the chassis the
reading must be infinite.
An other abnormality exists that must be corrected before the
receiver is returned to the customer.

Copyright
LG Electronics. Inc. All right reserved.
Only for training and service purposes

-3-

Good Earth Ground


such as WATER PIPE,
CONDUIT etc.
0.15uF

1.5 Kohm/10W

When 25A is impressed between Earth and 2nd Ground


for 1 second, Resistance must be less than 0.1
*Base on Adjustment standard

LGE Internal Use Only

SERVICING PRECAUTIONS
CAUTION: Before servicing receivers covered by this service
manual and its supplements and addenda, read and follow the
SAFETY PRECAUTIONS on page 3 of this publication.
NOTE: If unforeseen circumstances create conflict between the
following servicing precautions and any of the safety precautions on
page 3 of this publication, always follow the safety precautions.
Remember: Safety First.
General Servicing Precautions
1. Always unplug the receiver AC power cord from the AC power
source before;
a. Removing or reinstalling any component, circuit board
module or any other receiver assembly.
b. Disconnecting or reconnecting any receiver electrical plug or
other electrical connection.
c. Connecting a test substitute in parallel with an electrolytic
capacitor in the receiver.
CAUTION: A wrong part substitution or incorrect polarity
installation of electrolytic capacitors may result in an
explosion hazard.
2. Test high voltage only by measuring it with an appropriate high
voltage meter or other voltage measuring device (DVM,
FETVOM, etc) equipped with a suitable high voltage probe.
Do not test high voltage by "drawing an arc".
3. Do not spray chemicals on or near this receiver or any of its
assemblies.
4. Unless specified otherwise in this service manual, clean
electrical contacts only by applying the following mixture to the
contacts with a pipe cleaner, cotton-tipped stick or comparable
non-abrasive applicator; 10% (by volume) Acetone and 90% (by
volume) isopropyl alcohol (90%-99% strength)
CAUTION: This is a flammable mixture.
Unless specified otherwise in this service manual, lubrication of
contacts in not required.
5. Do not defeat any plug/socket B+ voltage interlocks with which
receivers covered by this service manual might be equipped.
6. Do not apply AC power to this instrument and/or any of its
electrical assemblies unless all solid-state device heat sinks are
correctly installed.
7. Always connect the test receiver ground lead to the receiver
chassis ground before connecting the test receiver positive
lead.
Always remove the test receiver ground lead last.
8. Use with this receiver only the test fixtures specified in this
service manual.
CAUTION: Do not connect the test fixture ground strap to any
heat sink in this receiver.
Electrostatically Sensitive (ES) Devices
Some semiconductor (solid-state) devices can be damaged easily
by static electricity. Such components commonly are called
Electrostatically Sensitive (ES) Devices. Examples of typical ES
devices are integrated circuits and some field-effect transistors and
semiconductor "chip" components. The following techniques
should be used to help reduce the incidence of component
damage caused by static by static electricity.
1. Immediately before handling any semiconductor component or
semiconductor-equipped assembly, drain off any electrostatic
charge on your body by touching a known earth ground.
Alternatively, obtain and wear a commercially available
discharging wrist strap device, which should be removed to
prevent potential shock reasons prior to applying power to the
Copyright
LG Electronics. Inc. All right reserved.
Only for training and service purposes

unit under test.


2. After removing an electrical assembly equipped with ES
devices, place the assembly on a conductive surface such as
aluminum foil, to prevent electrostatic charge buildup or
exposure of the assembly.
3. Use only a grounded-tip soldering iron to solder or unsolder ES
devices.
4. Use only an anti-static type solder removal device. Some solder
removal devices not classified as "anti-static" can generate
electrical charges sufficient to damage ES devices.
5. Do not use freon-propelled chemicals. These can generate
electrical charges sufficient to damage ES devices.
6. Do not remove a replacement ES device from its protective
package until immediately before you are ready to install it.
(Most replacement ES devices are packaged with leads
electrically shorted together by conductive foam, aluminum foil
or comparable conductive material).
7. Immediately before removing the protective material from the
leads of a replacement ES device, touch the protective material
to the chassis or circuit assembly into which the device will be
installed.
CAUTION: Be sure no power is applied to the chassis or circuit,
and observe all other safety precautions.
8. Minimize bodily motions when handling unpackaged
replacement ES devices. (Otherwise harmless motion such as
the brushing together of your clothes fabric or the lifting of your
foot from a carpeted floor can generate static electricity
sufficient to damage an ES device.)
General Soldering Guidelines
1. Use a grounded-tip, low-wattage soldering iron and appropriate
tip size and shape that will maintain tip temperature within the
range or 500F to 600F.
2. Use an appropriate gauge of RMA resin-core solder composed
of 60 parts tin/40 parts lead.
3. Keep the soldering iron tip clean and well tinned.
4. Thoroughly clean the surfaces to be soldered. Use a mall wirebristle (0.5 inch, or 1.25cm) brush with a metal handle.
Do not use freon-propelled spray-on cleaners.
5. Use the following unsoldering technique
a. Allow the soldering iron tip to reach normal temperature.
(500F to 600F)
b. Heat the component lead until the solder melts.
c. Quickly draw the melted solder with an anti-static, suctiontype solder removal device or with solder braid.
CAUTION: Work quickly to avoid overheating the circuit
board printed foil.
6. Use the following soldering technique.
a. Allow the soldering iron tip to reach a normal temperature
(500F to 600F)
b. First, hold the soldering iron tip and solder the strand against
the component lead until the solder melts.
c. Quickly move the soldering iron tip to the junction of the
component lead and the printed circuit foil, and hold it there
only until the solder flows onto and around both the
component lead and the foil.
CAUTION: Work quickly to avoid overheating the circuit
board printed foil.
d. Closely inspect the solder area and remove any excess or
splashed solder with a small wire-bristle brush.

-4-

LGE Internal Use Only

IC Remove/Replacement
Some chassis circuit boards have slotted holes (oblong) through
which the IC leads are inserted and then bent flat against the
circuit foil. When holes are the slotted type, the following technique
should be used to remove and replace the IC. When working with
boards using the familiar round hole, use the standard technique
as outlined in paragraphs 5 and 6 above.
Removal
1. Desolder and straighten each IC lead in one operation by gently
prying up on the lead with the soldering iron tip as the solder
melts.
2. Draw away the melted solder with an anti-static suction-type
solder removal device (or with solder braid) before removing the
IC.
Replacement
1. Carefully insert the replacement IC in the circuit board.
2. Carefully bend each IC lead against the circuit foil pad and
solder it.
3. Clean the soldered areas with a small wire-bristle brush.
(It is not necessary to reapply acrylic coating to the areas).
"Small-Signal" Discrete Transistor
Removal/Replacement
1. Remove the defective transistor by clipping its leads as close as
possible to the component body.
2. Bend into a "U" shape the end of each of three leads remaining
on the circuit board.
3. Bend into a "U" shape the replacement transistor leads.
4. Connect the replacement transistor leads to the corresponding
leads extending from the circuit board and crimp the "U" with
long nose pliers to insure metal to metal contact then solder
each connection.
Power Output, Transistor Device
Removal/Replacement
1. Heat and remove all solder from around the transistor leads.
2. Remove the heat sink mounting screw (if so equipped).
3. Carefully remove the transistor from the heat sink of the circuit
board.
4. Insert new transistor in the circuit board.
5. Solder each transistor lead, and clip off excess lead.
6. Replace heat sink.

Circuit Board Foil Repair


Excessive heat applied to the copper foil of any printed circuit
board will weaken the adhesive that bonds the foil to the circuit
board causing the foil to separate from or "lift-off" the board. The
following guidelines and procedures should be followed whenever
this condition is encountered.
At IC Connections
To repair a defective copper pattern at IC connections use the
following procedure to install a jumper wire on the copper pattern
side of the circuit board. (Use this technique only on IC
connections).
1. Carefully remove the damaged copper pattern with a sharp
knife. (Remove only as much copper as absolutely necessary).
2. carefully scratch away the solder resist and acrylic coating (if
used) from the end of the remaining copper pattern.
3. Bend a small "U" in one end of a small gauge jumper wire and
carefully crimp it around the IC pin. Solder the IC connection.
4. Route the jumper wire along the path of the out-away copper
pattern and let it overlap the previously scraped end of the good
copper pattern. Solder the overlapped area and clip off any
excess jumper wire.
At Other Connections
Use the following technique to repair the defective copper pattern
at connections other than IC Pins. This technique involves the
installation of a jumper wire on the component side of the circuit
board.
1. Remove the defective copper pattern with a sharp knife.
Remove at least 1/4 inch of copper, to ensure that a hazardous
condition will not exist if the jumper wire opens.
2. Trace along the copper pattern from both sides of the pattern
break and locate the nearest component that is directly
connected to the affected copper pattern.
3. Connect insulated 20-gauge jumper wire from the lead of the
nearest component on one side of the pattern break to the lead
of the nearest component on the other side.
Carefully crimp and solder the connections.
CAUTION: Be sure the insulated jumper wire is dressed so the
it does not touch components or sharp edges.

Diode Removal/Replacement
1. Remove defective diode by clipping its leads as close as
possible to diode body.
2. Bend the two remaining leads perpendicular y to the circuit
board.
3. Observing diode polarity, wrap each lead of the new diode
around the corresponding lead on the circuit board.
4. Securely crimp each connection and solder it.
5. Inspect (on the circuit board copper side) the solder joints of
the two "original" leads. If they are not shiny, reheat them and if
necessary, apply additional solder.
Fuse and Conventional Resistor
Removal/Replacement
1. Clip each fuse or resistor lead at top of the circuit board hollow
stake.
2. Securely crimp the leads of replacement component around
notch at stake top.
3. Solder the connections.
CAUTION: Maintain original spacing between the replaced
component and adjacent components and the circuit board to
prevent excessive component temperatures.
Copyright
LG Electronics. Inc. All right reserved.
Only for training and service purposes

-5-

LGE Internal Use Only

SPECIFICATION
NOTE : Specifications and others are subject to change without notice for improvement.

1. Application range

3. Test method

This specification is applied to the LCD TV used LJ91T


chassis.

2. Requirement for Test

1) Performance: LGE TV test method followed


2) Demanded other specification
- Safety: CE, IEC specification
- EMC: CE, IEC specification

Each part is tested as below without special appointment.


1) Temperature : 255C (779F), CST : 405C
2) Relative Humidity : 6510%
3) Power Voltage : Standard input voltage(100~240V@50/60Hz)
* Standard Voltage of each products is marked by models.
4) Specification and performance of each parts are followed
each drawing and specification by part number in
accordance with BOM.
5) The receiver must be operated for about 5 minutes prior to
the adjustment.

4. Electrical specification
4.1 General Specification
No
1.
2.

Item
Receiving System
Available Channel

3.
4.
5.

Input Voltage
Market
Screen Size

6.
7.
8.

Aspect Ratio
Tuning System
Module

9.

Operating Environment

10.

Storage Environment

Specification
1) SBTVD / NTSC / PAL-M / PAL-N
1) VHF : 02~13
2) UHF : 14~69
3) DTV : 02-69
4) CATV : 01~135
1) AC 100 ~ 240V 50/60Hz
Central and South AMERICA
32 inch Wide(1920x1080)
42 inch Wide(1920x1080)
47 inch Wide(1920x1080)
55 inch Wide(1920x1080)

Remark

Mark : 110V, 60Hz


32SL80YD-SA
42SL80YD-SA
47SL80YD-SA
55SL80YD-SA

16:9
FS
LC320WUD-SBA1(Vitaz 4)
LC420WUD-SBT1(Vitaz 4)
LC470WUD-SAT1(Vitaz 4)
1) Temp : 0 ~ 40 deg
2) Humidity : ~ 80 %
1) Temp : -20 ~ 60 deg
2) Humidity : ~ 85 %

Copyright
LG Electronics. Inc. All right reserved.
Only for training and service purposes

-6-

32LH70YD-SH
42LH70YD-SE
47LH70YD-SE

LGE Internal Use Only

5. Chromiance & Luminance spec.


No
1.

Item
Max Luminance
(Center 1-point / Full White
Pattern)

Module

Set

2.
3.
4.
5.
6.
7.
8.
9.
10.

Luminance uniformity
Color
RED
coordinate
GREEN
BLUE
WHITE
RED
GREEN
BLUE
WHITE
RED
GREEN
BLUE
WHITE
RED
GREEN
BLUE
WHITE

X
Y
X
Y
X
Y
X
Y
X
Y
X
Y
X
Y
X
Y
X
Y
X
Y
X
Y
X
Y
X
Y
X
Y
X
Y
X
Y

Min
Typ
480(TBD) 540(TBD)
480
600
480
600
470(TBD) 590(TBD)
400
500
400
450
400
500
400
500
77
0.638
Typ.
-0.03
0.334
0.291
0.607
0.145
0.062
0.279
0.292
Typ.
0.638
-0.03
0.334
0.290
0.606
0.144
0.064
0.279
0.292
Typ.
0.636
-0.03
0.334
0.290
0.608
0.145
0.064
0.279
0.292
Typ.
0.637
-0.03
0.333
0.287
0.605
0.145
0.064
0.279
0.292

Copyright
LG Electronics. Inc. All right reserved.
Only for training and service purposes

-7-

Max

Unit
cd/m2
cd/m2
cd/m2
cd/m2
cd/m2
cd/m2
cd/m2
cd/m2
%

Typ.
+0.03

Remark
32SL80YD-SA
42SL80YD-SA
47SL80YD-SA
55SL80YD-SA
32SL80YD-SA
42SL80YD-SA
47SL80YD-SA
55SL80YD-SA
Full white
32SL80YD-SA

Typ.
+0.03

42SL80YD-SA

Typ.
+0.03

47SL80YD-SA

Typ.
+0.03

55SL80YD-SA

LGE Internal Use Only

11.
12.

13.

Color coordinate uniformity


Contrast ratio

Color
Temperature

Cool
Standard
Warm

14.
15.
16.
17.

N/A
32SL80YD-SA

800:1
40000:1
(DCR)

1200:1
50000:1
(DCR)

1000:1
40000:1
(DCR)

1200:1
50000:1
(DCR)

42SL80YD-SA

800:1
40000:1
(DCR)

1200:1
50000:1
(DCR)

47SL80YD-SA

900:1
40000:1
(DCR)
Typ.
-0.015
Typ.
-0.015
Typ.
-0.015

1300:1
50000:1
(DCR)
0.269
0.273
0.285
0.293
0.313
0.329

55SL80YD-SA

Color Distortion, DG
Color Distortion, DP
Color S/N, AM/FM
Color Killer Sensitivity

Typ.
+0.015
Typ.
+0.015
Typ.
+0.015
10.0
10.0

43.0
-80

<Test Condition>
85% Full white pattern
** The W/B Tolerance is
0.015 for Adjustment
Dynamic contrast : off
Dynamic color : off
OPC : off
%
deg
dB
dBm

6. Component Input (Y, CB/PB, CR/PR)


No
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.

Resolution
720*480
720*480
720*480
720*480
1280*720
1280*720
1920*1080
1920*1080
1920*1080
1920*1080
1920*1080
1920*1080
1920*1080
1920*1080
1920*1080
1920*1080

H-freq(kHz)
15.73
15.73
31.47
31.47
45.00
44.96
33.75
33.72
67.500
67.432
27.000
26.97
33.75
33.71
56.25
28.125

V-freq.(kHz)
60
59.94
60
59.94
60.00
59.94
60.00
59.94
60
59.939
24.000
23.94
30.000
29.97
50.000
25.000

Copyright
LG Electronics. Inc. All right reserved.
Only for training and service purposes

-8-

Pixel clock
13.5135
13.5
27.027
27.0
74.25
74.176
74.25
74.176
148.50
148.352
74.25
74.176
74.25
74.176
148.5
74.25

Proposed
SDTV ,DVD 480I
SDTV ,DVD 480I
SDTV 480P
SDTV 480P
HDTV 720P
HDTV 720P
HDTV 1080I
HDTV 1080I
HDTV 1080P
HDTV 1080P
HDTV 1080P
HDTV 1080P
HDTV 1080P
HDTV 1080P
HDTV 1080P
HDTV 1080P

LGE Internal Use Only

7. RGB Input (PC)


No

Resolution
PC
1.
640*350
2.
720*400
3.
640*480
4.
800*600
5.
800*600
6.
1024*768
7.
1280*768
8.
1360*768
9.
1280*1024
10. 1600*1200
11 1920*1080

H-freq(kHz)
31.468
31.469
31.469
35.156
37.879
48.363
47.776
47.712
63.981
75.00
67.5

V-freq.(Hz)
70.09
70.08
59.94
56.25
60.31
60.00
59.870
60.015
60.020
60.00
60

Pixel clock(MHz)
25.17
28.32
25.17
36.00
40.00
65.00
79.5
85.50
108.00
162
148.5

Proposed
EGA
DOS
VESA(VGA)
VESA(SVGA)
VESA(SVGA)
VESA(XGA)
CVT(WXGA)
VESA (WXGA)
VESA
VESA (UXGA)
HDTV 1080P

DDC
X
O
O
O
O
O
O
O
O
O
O

** RGB PC Monitor Range Limits


- Min Vertical Freq - 56 Hz
- Max Vertical Freq - 62 Hz
- Min Horiz. Freq - 30 kHz
- Max Horiz. Freq - 80 kHz
- Pixel Clock - 170 MHz

8. HDMI Input (PC/DTV)


No
1
2
3
4
5
6
7
8
9
10
11
1
2
3
4
5
6
7
8
9
10
11
12
17.
18.

Resolution
PC
640*350
720*400
640*480
800*600
800*600
1024*768
1280*768
1360*768
1280*1024
1600*1200
1920*1080
DTV
720*480
720*480
1280*720
1280*720
1920*1080
1920*1080
1920*1080
1920*1080
1920*1080
1920*1080
1920*1080
1920*1080
1920*1080
1920*1080

H-freq(kHz)

V-freq.(Hz)

Pixel clock(MHz)

Proposed

31.468
31.469
31.469
35.156
37.879
48.363
47.776
47.712
63.981
75.00
66.587

70.09
70.08
59.94
56.25
60.31
60.00
59.870
60.015
60.020
60.00
59.934

25.17
28.32
25.17
36.00
40.00
65.00
79.5
85.50
108.00
162
138.5

EGA
DOS
VESA(VGA)
VESA(SVGA)
VESA(SVGA)
VESA(XGA)
CVT(WXGA)
VESA (WXGA)
VESA (SXGA)
VESA (UXGA)
HDTV 1080P

31.47
31.47
45.00
44.96
33.75
33.72
67.500
67.432
27.000
26.97
33.75
33.71
56.25
28.125

60
59.94
60.00
59.94
60.00
59.94
60
59.939
24.000
23.94
30.000
29.97
50.000
25.000

27.027
27.00
74.25
74.176
74.25
74.176
148.50
148.352
74.25
74.176
74.25
74.176
148.5
74.25

SDTV 480P
SDTV 480P
HDTV 720P
HDTV 720P
HDTV 1080I
HDTV 1080I
HDTV 1080P
HDTV 1080P
HDTV 1080P
HDTV 1080P
HDTV 1080P
HDTV 1080P
HDTV 1080P
HDTV 1080P

DDC
X
O
O
O
O
O
O
O
O
O
O

** HDMI Monitor Range Limits


- Min Vertical Freq - 56 Hz
- Max Vertical Freq - 62 Hz
- Min Horiz. Freq - 30 kHz
- Max Horiz. Freq - 80 kHz
- Pixel Clock - 170 MHz
Copyright
LG Electronics. Inc. All right reserved.
Only for training and service purposes

-9-

LGE Internal Use Only

9. Consignment Setting (OUTGOING CONDITION)


No
1.
2.
3.
4.
5.
6
7.

8.

9.

10.

11.

Item
Input Mode
Volume Level
Mute
Aspect Ratio
System Color
Booster
Picture
Picture Mode
Backlight
Contrast
Brightness
Sharpness
Color
Tint
Color Temperature
Picture Reset
Audio
Sound Mode
Auto Volume
Clear Voice
SRS TruSurround XT
Balance
TV Speaker
Time
Clock
Off Timer / On Timer
Sleep Timer / Auto Sleep
Option
Language (Menu/Audio)
SimpLink
Key Lock
Caption
Set ID
Channel Memory

Copyright
LG Electronics. Inc. All right reserved.
Only for training and service purposes

Condition
TV02CH
10
Off
16:9
PAL-M
On
Vivid
100
100
50
70
70
0
Cool
Standard
Off
Off
Off
0
On
Auto
Off
Portugues
On
Off
Off
1
RF : 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13,
14, 30, 51, 63
CATV : 15, 16, 17

- 10 -

LGE Internal Use Only

10. Mechanical Specification


32SL80YD-SA
No.
1.

Item
Product
Dim ension

W/O Packing
With Packing

2.

Product
Weight

Width (W)

Con tent
Length (D)

764.8

224.8

764.8

49.8

550.2
490.4

910

137

488

W/O Packing
With Packing

Height (H)

Unit
mm

Remark

mm

With Stand

mm
mm

W/O Stand
With Stand

mm

W/O Stand

12.9

Kg

With Stand

11.2

Kg

W/O Stand

15

Kg

With Stand

Kg

W/O Stand

Unit
mm

Remark

mm

With Stand

mm
mm

W/O Stand
With Stand

42SL80YD-SA
No.
1.

Item
Product
Dim ension

Width (W)
W/O Packing
With Packing

2.

Product
Weight

Con tent
Length (D)

Height (H)

1001.2

261

1001.2

45

689.7
623.2

228

770

910

W/O Packing
With Packing

mm

W/O Stand

21

Kg

With Stand

18.7

Kg

W/O Stand

22.5

Kg

With Stand

Kg

W/O Stand

Unit
mm

Remark

mm

With Stand

mm
mm

W/O Stand
With Stand

mm

W/O Stand

47SL80YD-SA
No.
1.

Item
Product
Dim ension

W/O Packing
With Packing

2.

Product
Weight

Width (W)

Con tent
Length (D)

1109.6

320.2

1109.6

45.5

751.7
685.3

1195.0

253.0

860.0

W/O Packing
With Packing

Height (H)

TBD

Kg

With Stand

23.6

Kg

W/O Stand

TBD

Kg

With Stand

Kg

W/O Stand

Unit
mm

Remark

mm

With Stand

mm
mm

W/O Stand
With Stand

mm

W/O Stand

55SL80YD-SA
No.
1.

Item
Product
Dim ension

W/O Packing
With Packing

2.

Product
Weight

Width (W)

Con tent
Length (D)

1279

320.2

1279

45.5

854.3
780.5

1395

464

965

W/O Packing
With Packing

Copyright
LG Electronics. Inc. All right reserved.
Only for training and service purposes

Height (H)

35.2

Kg

With Stand

32.0

Kg

W/O Stand

39

Kg

With Stand

Kg

W/O Stand

- 11 -

LGE Internal Use Only

ADJUSTMENT INSTRUCTION
1. Application Range

4. PCB Assembly Adjustment

This specification sheet is applied all of the LJ91T LCD TV


models, which produced in manufacture department or similar
LG TV factory.

4.1. CPLD DOWNLOAD : JTAG MODE

2. Notice
1) Because this is not a hot chassis, it is not necessary to use
an isolation transformer. However, the use of isolation
transformer will help protect test instrument.
2) Adjustment must be done in the correct order. But it is
flexible when its factory local problem occurs. .
3) The adjustment must be performed in the circumstance of
25 5C of temperature and 6510% of relative humidity if
there is no specific designation.
4) The input voltage of the receiver must keep 100~220V,
50/60Hz.
5) Before adjustment, execute Heat-Run for 5 minutes.

4.2. << PRINT PORT >> PIN MAP

After Receive 100% Full white pattern (06CH) then process


Heat-run
(or 8. Test pattern condition of Ez-Adjust status)
How to make set white pattern
1) Press Power ON button of Service Remocon
2) Press ADJ button of Service remocon. Select 8. Test
pattern and, after select White using navigation button,
and then you can see 100% Full White pattern.

Pin

JTAG Mode Signal Name

TCK

TMS

TDI

11

TDO

13

15

VCC

18 TO 25

GND

* In this status you can maintain Heat-Run useless any


pattern generator
* Notice: if you maintain one picture over 20 minutes
(Especially sharp distinction black with white pattern
13Ch, or Cross hatch pattern 09Ch) then it can appear
image stick near black level.

3. Adjustment Items
3.1 PCB Assembly adjustment
CPLD DOWNLOAD
Adjust 480i Comp1
Adjust 1080p Comp1/RGB
- If it is necessary, it can adjustment at Manufacture Line
- You can see set adjustment status at 1. ADJUST
CHECK of the In-start menu

3.2 Set Assembly Adjustment


EDID (The Extended Display Identification Data ) / DDC
(Display Data Channel) download
Color Temperature (White Balance) Adjustment
Make sure RS-232C control
Selection Factory output option

Copyright
LG Electronics. Inc. All right reserved.
Only for training and service purposes

- 12 -

LGE Internal Use Only

4.3. << 10P WAFER >> PIN MAP

Copyright
LG Electronics. Inc. All right reserved.
Only for training and service purposes

- 13 -

LGE Internal Use Only

4.4. Using RS-232C


Adjust 3 items at 3.1 PCB assembly adjustments 4.1.3
sequence one after the order.
O Adjustment protocol
Order

Command

1. Inter the

ad 00 00

d 00 OK00x

Set response

kb 00 40

b 00 OK40x (Adjust 480i Comp1/1080p Comp1)

kb 00 60

b 00 OK60x (Adjust 1080p RGB)

Adjustment mode
2. Change the
Source

3.Start Adjustment ad 00 10
4.Return the

OKx ( Success condition )

Response
5.Read
Adjustment data

6.Confirm

NGx ( Failed condition )


(main)

(main : component1 480i, RGB 1080p)

ad 00 20

000000000000000000000000007c007b006dx

(main)

(main : component1 1080p)

ad 00 30

000000070000000000000000007c00830077x

ad 00 99

NG 03 00x (Failed condition)

Adjustment

NG 03 01x (Failed condition)


NG 03 02x (Failed condition)
OK 03 03x (Success condition)

7. End of Adjustment ad 00 90

d 00 OK90x

See ADC Adjustment RS232C Protocol_Ver1.0


O Adjustment protocol
- Pattern Generator : (MSPG-925FA)
- Adjust 480i Comp1 (MSPG-925FA : model :209 , pattern
: 65)
- Adjust 1080p Comp1/RGB(MSPG-925FA:model : 225 ,
pattern : 65)
- Adjust RGB (MSPG-925FA:model :225 , Pattern :65)
RGB-PC Mode
* If you want more information then see the below Adjustment
method (Factory Adjustment)
O Adjustment sequence
- ad 00 00 : Enter the ADC Adjustment mode.
- xb 00 40: Change the mode to Component1 (No actions)
- ad 00 10: Adjust 480i Comp
- ad 00 10: Adjust 1080p Comp
- xb 00 60: Change to RGB-PC mode(No action)
- ad 00 10: Adjust 1080p RGB
- ad 00 90: End of the adjustment

Copyright
LG Electronics. Inc. All right reserved.
Only for training and service purposes

- 14 -

LGE Internal Use Only

5. Factory Adjustment
5.1 Manual Adjust Component 480i/1080p
RGB 1080p
O Summary : Adjustment component 480i/1080i and RGB
1080p is Gain and Black levelsetting at Analog
to Digital converter, and compensate the RGB
deviation
O Using instrument
- Adjustment remocon, 801GF(802B, 802F, 802R) or
MSPG925FA pattern generator (It can output 480i/1080i
horizontal 100% color bar pattern signal, and its output
level must setting 0.7V0.1V p-p correctly)

5.2 EDID
(The
Extended
Display
Identification Data) / DDC (Display Data
Channel) Download.
<Pic.4 Adjustment pattern : 480i / 1080p 60Hz Pattern >

O Summary
It is established in VESA, for communication between
PC and Monitor without order from user for building user
condition. It helps to make easily use realize Plug and
Play function.
For EDID data write, we use DDC2B protocol.

* You must make it sure its resolution and pattern cause every
instrument can have different setting
O Adjustment method 480i Comp1, Adjust 1080p
Comp1/RGB (Factory adjustment)
ADC 480i Component1 adjustment
- Check connection of Component1
- MSPG-925FA Model: 209, Pattern 65
Set Component 480i mode and 100% Horizontal Color
Bar Pattern(HozTV31Bar), then set TV set to
Component1 mode and its screen to NORMAL
ADC 1080p Component1 / RGB adjustment
- Check connection both of Component1 and RGB
- MSPG-925FA Model: 225, Pattern 65
Set Component 1080p mode and 100% Horizontal Color
Bar Pattern(HozTV31Bar), then set TV set to
Component1 mode and its screen to NORMAL
After get each the signal, wait more a second and enter
the IN-START with press IN-START key of Service
remocon. After then select 7. External ADC with
navigator button and press Enter.
After Then Press key of Service remocon Right
Arrow(VOL+)
You can see ADC Component1 Success
Component1 1080p, RGB 1080p Adjust is same
method.
Component 1080p Adjustment in Component1 input
mode
RGB 1080p adjustment in RGB input mode
If you success RGB 1080p Adjust. You can see ADC
RGB-DTV Success

Copyright
LG Electronics. Inc. All right reserved.
Only for training and service purposes

O Auto Download
After enter Service Mode by pushing ADJ key,
Enter EDID D/L mode.
Enter START by pushing OK key.
Caution: - Never connect HDMI & D-sub Cable when the user
downloading .
- Use the proper cables below for EDID Writing.

- 15 -

LGE Internal Use Only

- HDM2 EDID table (0x3D, 0x1C)

Edid data and Model option download (RS232)


NO
Enter
download MODE

Item
Download
ModeIn

CMD 1

CMD 2

Data 0

Edid data and


Model option
download

Download

*Note1

*Note2

Adjust Mode Out

Adjustment
Confirmation

When transfer the Mode In ,


Carry the command.
Automaticall y download
(The use of a internal Data)
To check Download
on Assembly line.

O Manual Download
Write HDMI EDID data
- Using instruments
=> Jig. (PC Serial to D-Sub connection) for PC, DDC
adjustment.
=> S/W for DDC recording (EDID data write and
read)
=> D-sub jack
=> Additional HDMI cable connection Jig.

- HDMI-3 EDID table (0x3D, 0x0C)

- Preparing and setting.


=> Set instruments and Jig. Like pic.5), then turn on
PC and Jig.
=> Operate DDC write S/W (EDID write & read)
=> It will operate in the DOS mode.

PC

VSC
B/D

Pic.3) For write EDID data, setting Jig and another instruments.
EDID data for LJ91D Chassis (Model name = LG TV)
- HDMI-1 EDID table (0x3D, 0x2C)

- Analog (RGB) EDID table (0x9B, 0x25)

See Workig Guide of you want more information about EDID


communication.

Copyright
LG Electronics. Inc. All right reserved.
Only for training and service purposes

- 16 -

LGE Internal Use Only

5.3 Adjustment Color Temperature


(White balance)
O Using Instruments
Color Analyzer: CA-210 (CH 9)
- Using LCD color temperature, Color Analyzer (CA-210)
must use CH 9, which Matrix compensated (White, Red,
Green, Blue compensation) with CS-2100. See the
Coordination bellowed one.
Auto-adjustment Equipment (It needs when Autoadjustment It is availed communicate with RS-232C :
Baud rate: 115200)
Video Signal Generator MSPG-925F 720p, 216Gray
(Model: 217, Pattern 78)

O White Balance Adjustment


If you cant adjust with inner pattern, then you can adjust
it using HDMI pattern. You can select option at "Ez-Adjust
Menu 7. White Balance" there items "NONE, INNER,
HDMI". It is normally setting at inner basically. If you cant
adjust using inner pattern you can select HDMI item, and
you can adjust.
In manual Adjust case, if you press ADJ button of service
remocon, and enter "Ez-Adjust Menu 7. White
Balance", then automatically inner pattern operates. (In
case of "Inner" originally "Inner" will be selected.
Connect all cables and equipments like Pic.5)
Set Baud Rate of RS-232C to 115200. It may set
115200 orignally.
Connect RS-232C cable to set
Connect HDMI cable to set

O Connection Diagram (Auto Adjustment)


Using Inner Pattern

F u l l W h i t e P at t er n

C A -100+
COL OR
A NA L Y ZER
T Y PE ; C A -100+

R S-232C

Using HDMI input

RS-232C Command (Commonly apply)


00
00

00
10

wb
wb

00
00

1f
20

wb
wb

00
00

2f
ff

White Balance adjustment start.


Start of adjust gain (Inner white
pattern)
End of gain adjust
Start of offset adjust(Inner white
pattern)
End of offset adjust
End of White Balance adjust(Inner
pattern disappeared)

"wb 00 00": Start Auto-adjustment of white balance.


"wb 00 10": Start Gain Adjustment (Inner pattern)
"jb 00 c0" :

"wb 00 1f": End of Adjustment


* If it needs, offset adjustment (wb 00 20-start, wb 00
2f-end)
"wb 00 ff": End of white balance adjustment (inner
pattern disappear)

<Pic.5 Connection Diagram for Adjustment White balance> .

Copyright
LG Electronics. Inc. All right reserved.
Only for training and service purposes

wb
wb

- 17 -

LGE Internal Use Only

O White Balance Adjustment (Manual adjustment)


Test Equipment: CA-210
- Using LCD color temperature, Color Analyzer (CA210) must use CH 9, which Matrix compensated
(White, Red, Green, Blue compensation) with CS2100. See the Coordination bellowed one.
Manual adjustment sequence is like bellowed one.
- Turn to "Ez-Adjust" mode with press ADJ button of
service remocon.
- Select "10.Test Pattern" with CH+/- button and press
enter. Then set will go on Heat-run mode. Over 30
minutes set let on Heat-run mode.
- Let CA-210 to zero calibration and must has gap more
10cm from center of LCD module when adjustment.
- Press "ADJ" button of service remocon and select
"7.White-Balance" in "Ez-Adjust" then press ""
button of navigation key.
(When press "" button then set will go to full white
mode)
- Adjust at three mode (Cool, Medium, Warm)
- If "cool" mode
Let B-Gain to 192 and R, G, B-Cut to 64 and then
control R, G gain adjustment High Light adjustment.
- If "Medium" and "Warm" mode
Let R-Gain to 192 and R, G, B-Cut to 64 and then
control G, B gain adjustment High Light adjustment.
- All of the three mode
Let R-Gain to 192 and R, G, B-Cut to 64 and then
control G, B gain adjustment High Light adjustment.
- With volume button (+/-) you can adjust.
- After all adjustment finished, with Enter ( key) turn
to Ez-Adjust mode. Then with ADJ button, exit from
adjustment mode
Attachment: White Balance adjustment coordination and color
temperature.
O Using CS-1000 Equipment.
- COOL : T=11000K, uv=0.000, x=0.276 y=0.283

5.5 Test of RS-232C control


Press IN-Start button of service remocon then set the 4.Baud
rate to 15200, Then check RS-232C control and

5.6 Selection of Country option.


Selection of country option is allowed only North American model
(Not allowed Korean model). It is selection of Country about
Rating and Time Zone.
Models: All models which use LA75A Chassis (See the first
page.)
Press In-Start button of Service Remocon, then enter the
Option Menu with PIP CH- Button
Select one of these three (USA, CANADA, MEXICO)
defends on its market using Vol. +/-button.
* Caution : Dont push The Instop Key ater completing the
function inspection.

5.7 Check the Ginga(Data Broadcasting)


1) Turn on TV
2) Press the OK Button on the ADJ R/C

- MEDIUM : T=9300K, uv=0.000, x=0.285 y=0.293


- WARM : T=6500K, uv=0.000, x=0.313 y=0.329

5.4 EYE-Q Function check.


1) Turn on TV
2) Press EYE Key of Adj R/C
3) Cover the Eye Q II sensor on the front of the using your
hand and wait for 6 seconds
4) Confirm that R/G/B va;ie os ;pwer tjam 10 of the Raw
Data (Sensor data, Back light). If after 6 seconds, R/G/B
value is not lower than 10, re[;ace EYE Q II sensor.
5) Remove your hand from the EYE Q II sensor and wait for
6 sencond
6) Confirm that OK pop up.
If change is not seen, replace EYE Q II sensor

Copyright
LG Electronics. Inc. All right reserved.
Only for training and service purposes

3) Check the Ginga icon

- 18 -

LGE Internal Use Only

EXPLODED VIEW
IMPORTANT SAFETY NOTICE

910
550

A2

122

510

300

310

500

120

LV1

580

LV2

200T

A10

200N

200

803

802

804

801

805

806

810

811

900

530

540

520

812

400

Many electrical and mechanical parts in this chassis have special safety-related characteristics. These
parts are identified by
in the Schematic Diagram and EXPLODED VIEW.
It is essential that these special safety parts should be replaced with the same components as
recommended in this manual to prevent X-RADIATION, Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.

Copyright
LG Electronics. Inc. All right reserved.
Only for training and service purposes

-17 -

LGE Internal Use Only

29

AA

AB

AC

10K
R1101
ZD1101
5.1V

FIX-TER

SIDE AV

AH

AI

AJ

AK

AL

AM

AN

AO

D3.3V

1K

C1130
0.1uF
16V

C1142

IC1103
M24C02-RMN6T

+5V

R1104
470K

VCC

D3B

D3A

Q3

D2B

D2A

14

13

12

11

R1119
1K

5.1V
ZD1139

R1128
470K

1uF
25V

C1136
100pF

ZD1147
5.1V

SIDE_R_IN
3:T20

3:T15 DSUB_G
C1144
47pF
50V

L1108-*1
BG1608B121F

RGB_BEAD

L1109
0

R1169
10K
1K
R1170

L1109-*1
BG1608B121F RGB_BEAD

DSUB_DET
3:T16

T_SPRING

R1109
470K

5.1V
ZD1131

ZD1132
5.1V

10

0
R1117

C1128
100pF
50V

COMP2_R_IN
3:T23

6B
8

C1133

SHIELD_PLATE

R1139

1uF
25V

3:T13

5.1V
ZD1114

ZD1113
5.1V

R1105
10K

SPDIF OPTIC JACK

5.1V
ZD1118
5.1V
ZD1120

ZD1119
5.1V

JST1223-001

GND

C1125
100pF

AV1_L_IN
3:T18
SPDIF_OUT
G4;3:T12

VINPUT

VCC

1K

ZD1145
OPT
5.6B

C1129
0.1uF
50V

R1107
470K

THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.

AV1_R_IN
3:T18

R1164 0
DDC_GND

DDC_CLOCK

SYNC_GND

GND_1

V_SYNC

NC

BLUE

H_SYNC

BLUE_GND

GREEN

DDC_DATA

GREEN_GND

SHILED
16

15
10

14

13
3

12

3:T12

14

13

RIN1

C2-

12

ROUT1

V-

11

DIN1

3:T12

VCC

DOUT1

C1141
0.47uF
25V
C2+

C1139
0.47uF
25V

16

R1167
220

R1168
220

2
R1148
100
OPT

R1149
100
OPT

50V
C1147
220pF

50V
C1148
220pF

3
8

50V
47pF
C1150

50V
47pF
C1149

4
9
5

DOUT2

10

RIN2

10

DIN2

+5V_ST
US_Commercial
R1165
3.3K

ROUT2
OPT
R1158
3.3K

US_Commercial
R1160
100K

R1154
0
FIX_POLE
R1140
100

R1113
0
C1126
100pF

SPG09-DB-009

+5V_ST

R1126

R1112
0

R1106
470K

C1111
25V 1uF

+5V

D3.3V

ZD1117
5.1V

JK1105

3:T18

JK1107

R1146
0

C1110
25V 1uF
JK1103

C1124
47pF
50V

R1171
75

Fiber Optic

5.1V
ZD1116

ZD1115
5.1V

GND

C1-

R1110
15
AV1_CVBS_IN

C1146
0.1uF
50V

RS232C_RxD

15

AV1_CVBS_DET
3:T18

C1106
0.1uF
16V

R1145
4.7K

RS232C_TxD
C1138
0.1uF
50V
V+

R1111
1K

6
8

R1144
4.7K

R1147
0
C1+

AV1

L1107
BLM18PG121SN1D

C1140
0.47uF
25V

D3.3V

+5V_ST

PC_L_IN
0

IC1101
MAX3232CDR

3:T13

RS-232C
C1134

B_TERMINAL2
T_TERMINAL2

R1138
PC_R_IN

1uF
25V

5.1V
ZD1154

C1115

1uF
25V

11
R_SPRING

7B

11

6
1

B_TERMINAL1

5.1V
ZD1141

T_TERMINAL1

7A

R1132
470K

R1108
470K

5.1V
ZD1129

ZD1130
5.1V

1uF
25V

COMP2_L_IN
3:T23

D1106
ADMC5M03200L
5.6V

E_SPRING

6A

5.1V
ZD1143

C1127
100pF
50V

0
R1116

JK1104
PEJ027-01

R1133
470K

COMP2_Pr_IN
3:T22

50V
27pF
C1121

ZD1153
5.1V

5.1V
ZD1125
5.1V
ZD1127

R1122
15

50V
27pF
C1109

C1114

12

JK1106
SPG09-DB-010

PC AUDIO
L1105
CM2012FR27KT

ZD1142
5.1V

13

COMP2_Pb_IN
3:T22

50V
27pF
C1120

ZD1144
5.1V

R1152
0
[RD]MONO

ZD1128
5.1V

14

13

ZD1126
5.1V

4
JK1102

R1121
15

50V
27pF
C1108

R1162 0

OPT
L1110-*1

5.1V
ZD1152
ZD1155
5.1V

L1104
CM2012FR27KT

C1152
100pF
50V

BG1608B121F RGB-BEAD
RED_GND

C1145
47pF
50V

RED

COMP2_Y_IN
3:T23

50V
27pF
C1119

L1110
0

GND_2

3:T16 DSUB_R

5.1V
ZD1150

R1120
15

50V
27pF
C1107

15

D1105
ADMC5M03200L
5.6V

L1108
0

R1173
0
OPT

+5V

ZD1151
5.1V

5.1V
ZD1123

ZD1124
5.1V

16

R1163
22

C1143
47pF
50V

COMP2_DET
3:T23

L1106
CM2012FR27KT

10

DDC_SDA
3:T17

BCM RECOMMAND

11

ZD1140
5.1V

10K
R1102
5.1V
ZD1121

ZD1122
5.1V

FIX-TER

DDC_SCL
3:T17
SDA

BCM Reference

D3.3V

18

D1102
ADUC30S03010L
30V

3:T15 DSUB_B

C1102
100pF
50V

EDID_WP
3:T16

SCL

D1101
ADUC30S03010L
30V

R1136

COMPONENT2

R1143
22
RGB_HSYNC
3:T14

C1132

19

50V

R1166
0

WC

D0A

Q0

D0B

C1135
100pF

R1127
470K

COMP1_R_IN
3:T21

C1123
100pF
50V

74F08D
IC1102

1uF
25V

D1A

SIDE_L_IN
3:T20

ZD1149
5.1V

5.1V
ZD1112

ZD1111
5.1V

20

0
R1115

VCC

D1104
ADMC5M03200L
5.6V

C1113

1uF
25V

5.1V
ZD1146

21

R1135

D1B

7
R1150
0

C1153
4700pF

0.1uF
50V

R1159
10K
OPT

R1157
22

5.1V
ZD1148

C1122
100pF
50V

5.1V
ZD1137

COMP1_L_IN
3:T22

ZD1138
5.1V

R1103
470K

5.1V
ZD1110

ZD1109
5.1V

R1131
0
C1131

0
R1114

10

1uF
25V

VSS

3:T20

50V
27pF
C1118

C1112

22

Q2

R1172
75

E2

ZD1136
5.1V

C1137
47pF
50V

Q1

50V
27pF
C1105

SIDE_CVBS_IN
3:T19

23

R1125
15
COMP1_Pr_IN

5.1V
ZD1108

ZD1107
5.1V

L1103
CM2012FR27KT

E1

RGB_VSYNC
3:T14

R1130
15

3
[RD]MONO

R1142
22

COMP1_Pb_IN
3:T21

50V
27pF
C1117

50V
27pF
C1104

E0

R1129
0

GND

5.1V
ZD1106

ZD1105
5.1V
R1151
0

R1124
15

5.1V
ZD1135

L1102
CM2012FR27KT

17

C1151
R1156
4.7K

P1101
12507WS-08L

SIDE_CVBS_DET
3:T19

R1153
4.7K

50V
27pF
C1116

R1137

0.1uF

13

3:T21
COMP1_Y_IN

5.1V
ZD1133

50V
27pF
C1103

JK1101

R1123
15

R1134
2.7K

ZD1134
5.1V

5.1V
ZD1104

ZD1103
5.1V

24

C
A2

25

+5V_ST

D1103
ENKMC2838-T112
A1

10

26

R,G,B PC&DDC

C1101
100pF
50V

L1101
CM2012FR27KT

AG

R1118
1K

11

27

AF

COMP1_DET
3:T21
5.1V
ZD1102

28

AE

D3.3V

COMPONENT1

AD

R1141
100

R1155
10K
IR
3:T11

C
Q1101
2SC3052

Q1102
2SC3052
US_Commercial
E
R1161
100K
US_Commercial
B

OPT
OPT

BCM (BRAZIL VENUS)

2009. 03. 23

LEE GI YOUNG
IN - OUT

15

AP

AA

AB

AC

AD

AE

AF

AG

AH

AI

AJ

AK

AL

AM

AN

AO

* HDMI CEC

29

+3.3V_ST

18
17
16
15

26

14
13
12

25

11
10
9

24

8
7
6
5

23

4
3
2

22

AH19
HPD4

HPD

Q601
SSM6N15FU

DRAIN1

+5V_POWER
R642

DDC/CEC_GND

R14;AG19
DDC_SDA_4
R13;AG19
DDC_SCL_4

SDA
SCL

R639

NC

R643

CEC_REMOTE
H8;H17;R26;AL11

GATE2

H8;H17;W27;AL11
CEC_REMOTE
AG19
CK-_HDMI4

CEC
CLK-

CLK+

SOURCE2

12:F6

SOURCE1

HDMI_CEC
GATE1

DRAIN2

C612
0.1uF

R664

GND

AG19
CK+_HDMI4
AF19
D0-_HDMI4

CLK_SHIELD

C629
0.1uF

C623
0.1uF

R658
AVRL161A1R1NT
VR607

27

68K
R666
9.1K

R641
0
19

L602
BLM18PG121SN1D

L601
BLM18PG121SN1D

R667

20

MMBD301LT1G
D601

Q16;AH18
5V_HDMI_4

JACK_GND

28

+3.3V_HDMI

D3.3V

+1.8V_HDMI

+1.8V_AMP

OPT

GND

DATA0AF19
D0+_HDMI4
AF19
D1-_HDMI4

DATA0_SHIELD
DATA0+
DATA1-

AF19
D1+_HDMI4
AE19
D2-_HDMI4

DATA1_SHIELD
DATA1+

+3.3V_HDMI

DATA2AE19
D2+_HDMI4

DATA2_SHIELD

R665
0

DATA2+

19

AL11
HPD2

18
R616

R617

16

DDC_SCL_2

47K

DDC_SCL_4

13

HPD1

12

2
1

HPD4

DDC_SDA_4

CK+_HDMI4

CK-_HDMI4

DDC_SCL_4

D0+_HDMI4
D0-_HDMI4

D1+_HDMI4
D1-_HDMI4

D2-_HDMI4

D2+_HDMI4

C615

C614
0.1uF

C613
0.1uF

RXD_5V

RXD_HPD
76

77

RXD_DDC_CLK

RXD_DC-

RXD_DDC_DAT
78

79

80

VDDH[3V3]_7

RXD_D0-

RXD_D0+

RXD_DC+
81

82

83

84

RXD_D1-

RXD_D1+

VDDH[3V3]_8

VSS_10
85

86

87

88

RXD_D2+

RXD_D289

90

VSS_11

OUT_D2+

VDDC[1V8]_3
91

92

93

OUT_D294

RXC_C-

61

RXC_DDC_CLK

RXA_D0-

16

60

RXC_DDCC_DAT

RXA_D0+

17

59

RXC_5V

25

51

XTAL_IN

THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.

DDC_SCL_2
DDC_SDA_2
HPD2

R677

CEC_REMOTE

50

Net Labels changed for HDMI2


R678

0
OPT

OPT

CEC_REMOTE
Y12
CK-_HDMI1

UI_HW_PORT1

CK+_HDMI2
CK-_HDMI2

R675

+1.8V_HDMI

C606
0.1uF

C617
0.1uF

C608
0.1uF

C618
5.6nF

+3.3V_HDMI
R672
4.7K OPT

R669

R673
4.7K

OPT
4.7K
R674
OPT

Y10
D2+_HDMI1

GND

D0+_HDMI2
D0-_HDMI2

SCL/SEL0

SDA/SEL1

PD

0 MODE

VDDC[3V3]

R668

VDDC[1V8]_2

VSS_6

RXB_D2+

CDEC_DDC

RXB_D2-

RXB_D1+

DDC_SDA_1
M17;X12
DDC_SCL_1

RXB_D1-

M18;X13

49

NC

VSS_5

R663

48

XTAL_OUT

47

52
46

24
45

INT/HP_CTRL

VDDH[1V8]_1

44

CDEC_STBY

53

43

VDDS[3V3]

54

23

42

55

22

RXA_D2+

41

21

RXA_D2-

40

VDDH[3V3]_2

39

VSS_7

38

56

37

20

36

RXA_D1+

35

CEC

34

RXC_HPD

57

33

58

19

32

18

26

VSS_3
RXA_D1-

5:G5;16:G14

2
1

YKF45-7058V
JK500

VDDO[1V8]

62

15

Y11
D1+_HDMI1
Y10
D2-_HDMI1

4
3

95

14

VDDH[3V3]_1

+5.0V

Y11
D0+_HDMI1
Y11
D1-_HDMI1

C611
0.1uF

RXA_C+

CK+_HDMI1

R671

10

OUT_D1+

63

RXC_C+

CK-_HDMI1

13

Y12
CK+_HDMI1
Y12
D0-_HDMI1

96

VDDH[3V3]_5

RXA_C-

VARISTORS(VR500/501/502/503/504/505/506/507) on lines-HPD1/2/3/4 are all options


in case HDMI Switch doesnt support ESD protection

SCL1_3.3V
5:G5;16:G14

97

RXC_D0-

DDC_SCL_1

C604
0.1uF

11

RXC_D0+

D1+_HDMI2
D1-_HDMI2

13

66
64

Y13
HPD1

H17;R26;W27;AL11
0

TDA9996HL

D2+_HDMI2
D2-_HDMI2

R607

VSS_8

R670

14

RXC_D1-

67

SDA1_3.3V

RXC_D1+

68

RXB_D0+

69

IC601

VDDH[3V3]_4

15

RXB_C+

R606

16

RXB_D0-

RXA_HPD

VDDH[3V3]_3

R605

VSS_2
VDDC[1V8]_1

65

C605
0.1uF

17

VDDH[3V3]_6

12

18

RXC_D2-

70

VSS_4

R627
0

71

11

D2-_HDMI1
D2+_HDMI1

19

OUT_DDC_DAT

10

D1+_HDMI1

10

OUT_DDC_CLK

C621
0.1uF

12K

RXA_5V

D1-_HDMI1

20

RXC_D2+

RXA_DDC_CLK

D0+_HDMI1

L19;Z14
5V_HDMI_1

72

RXA_DDC_DAT

D0-_HDMI1

20

DDC_SDA_1

GND

11

VSS_9

VDDO[3V3]

RXB_C-

EDID Pull-up

VDDH[1V8]_2
R676
R12K

73

75

31

UI_HW_PORT2

YKF45-7058V
JK501

74

RXB_DDC_CLK

AL14
D2+_HDMI2

C607
0.1uF

DDC_SDA_4

30

OUT_C-

29

R657

R655
47K

VSS_1
OUT_C+

RXB_5V

AL13
D1+_HDMI2
AL14
D2-_HDMI2

C628
0.1uF

5V_HDMI_2

C619
0.1uF

5V_HDMI_1

5
4

RXB_DDC_DAT

OUT_D1-

5V_HDMI_4

AL13
D0+_HDMI2
AL13
D1-_HDMI2

C622
0.1uF

C620
0.1uF

VSS_12

+1.8V_HDMI

OUT_D0+

AL12
CK+_HDMI2
AL13
D0-_HDMI2

10
9

12

C610
0.1uF

C616
0.1uF

CEC_REMOTE
AL12
CK-_HDMI2

98

11

14

DDC_SDA_2

DDC_SCL_1

99

12

15

DDC_SDA_1

H8;R26;W27;AL11

13

16

0.1uF

5V_HDMI_4

100

R618

0.1uF
C626

R661
1.8K

28

17

47K

27

14

DDC_SDA_2
R17;AL12
DDC_SCL_2

R653
47K

47K

C624
0.1uF
C625

0.1uF
C627

TEST

15

R18;AL12

R656

RXB_HPD

17

R635

OUT_D0-

18

R662
1.8K
R634
47K

HDMI0_RX2-_BCM 11:W16
HDMI0_RX2+_BCM 11:W16

R628
0

HDMI0_RX0-_BCM 11:W17
HDMI0_RX0+_BCM 11:W17

20

HDMI_SCL

P19;AJ15
5V_HDMI_2

20

19

HDMI_SDA

+5.0V
5V_HDMI_2

5V_HDMI_1

HDMI0_RXC+_BCM 11:W17

20

HDMI0_RXC-_BCM 11:W17

SIDE_HDMI_PORT4

GND

HDMI0_RX1-_BCM 11:W16
HDMI0_RX1+_BCM 11:W16

0.1uF

JK503

C609
0.1uF

KJA-ET-0-0032

21

HDMI S/W For MSTAR Platform

BCM (BRAZIL VENUS)

2009.03.23

LEE GI YOUNG
HDMI

15

AP

IC503
D3.3V

AZ1117H-1.8TRE1(EH13A)

+1.8V_AMP

7
INPUT

ADJ/GND

2
C548
10uF
10V

OUTPUT

C549
0.1uF
16V

GND

C551
0.1uF
16V

C552
10uF
10V

6
+24V

+24V_AMP

L511
MLB-201209-0120P-N2

SPK_L+

+24V_AMP
R511
3.3

T_330uF_Capacitor

C511
R504
0

C508
0.1uF

PVDD1B_2

PVDD1B_1

OUT1B_2

OUT1B_1

PGND1B_2

PGND1B_1

BST1B

VDR1B

48

47

46

45

44

43

PVDD1A_1

49

PVDD1A_2

OUT1A_1

OUT1A_2

51
50

52

NC

41

VDR2A

40

BST2A

AD

39

PGND2A_2

DVSS_1

38

PGND2A_1

VSS_IO

37

OUT2A_2

CLK_I

36

OUT2A_1

35

PVDD2A_2

34

PVDD2A_1

IC501
NTP-3100L

C507
1000pF
50V

VDD_IO

DGND_PLL

R503

AGND_PLL

10

33

PVDD2B_2

LFM

11

32

PVDD2B_1

AVDD_PLL

12

31

OUT2B_2

30

OUT2B_1

29

PGND2B_2

C510
10uF
10V

4.7K

C538
0.47uF
50V

C532
1000pF
50V

1S

3.3

SPEAKER_L

R528

1F
C541
0.1uF
50V

22uH

R519

H3

R527

R524
4.7K

3.3
C545
0.01uF
50V

50V

D503
1N4148W
100V
OPT

D504
1N4148W
100V
OPT

R520

L505
DA-8580
EAP38319001
2S
2F

5.6

SPK_L-

H3

SPK_R+

H3

C533
1000pF
50V
C534
1000pF
50V

1S

C546
C539
0.47uF
50V

C542

R525

0.1uF
50V

4.7K

0.01uF
50V
R529

SPEAKER_R

3.3

1F

R530

22uH
R521
5.6

C543

R526

0.1uF
50V

4.7K

3.3
C547
0.01uF
50V

SPK_R-

H3

+24V_AMP

28

C518
1uF
10V

C513
0.1uF
16V

C525
22000pF

R522
3.3

PGND2B_1

27
BST2B

26
VDR2B

25
FAULT

24
MONITOR_2

23
MONITOR_1

22
MONITOR_0

21
SCL

20
SDA

+1.8V_AMP

19

C505
0.1uF
16V

BCK

14
18

TEST0

EAN60664001

WCK

13

17

DVDD_PLL

15

C503
10uF
6.3V

PGND1A_1

42

3.3K

C502
0.1uF
16V

C523
16V1uF

RESET

16

100pF
50V

R523

Change 22uH(L504,L505) TO 15uH/6.3mm After DV1

VDR1A

DVDD

C504

C521
1uF
16V

BST1A

SDATA

C501
10uF
10V

10V

L502
R501
0

L501

1uF

DVSS_2

MLB-201209-0120P-N2

+1.8V_AMP

MLB-201209-0120P-N2

9:G6
+1.8V_AMP AUDIO_M_CLK

53

C506
1000pF
50V

PGND1A_2

9:G7;9:I3;12:I4 AMP_RST

0.01uF
50V

C531
1000pF
50V

C540
0.1uF
50V

C544
0.01uF
50V

L503

54

100

D502
1N4148W
100V
OPT

C526

L504
DA-8580
EAP38319001
2S
2F

5.6

C519
22000pF
50V

55

R502

C553
330uF
35V

R518

5.6

C514
22000pF
50V

D3.3V

56

MLB-201209-0120P-N2

C522
0.1uF
50V

C520
0.1uF
50V

C515
0.01uF
50V

D501
1N4148W
100V
OPT

C527

C528

0.01uF
50V

0.1uF
50V

C530
0.1uF
50V

C529
330uF

C535
0.01uF
50V

WAFER-ANGLE

H5

SPK_L+

H5

SPK_L-

H4

SPK_R+

H4

SPK_R-

C524

4
L508
120-ohm

T_330uF_Capacitor

22000pF
50V

L507
120-ohm

3
L510
120-ohm

R513
AMP_MUTE
11:F7

BCM_I2S_DATA_OUT

11:F6

BCM_I2S_WORD_CLK

11:F7

BCM_I2S_BIT_CLK

9:I4;2:AH5
9:I4;2:AH5

SDA1_3.3V
SCL1_3.3V

R505

100

R506

100

R507

100

R508

100

R509

100

C517
33pF
50V

2
L509
120-ohm

12:F3

100

1
P501

OPT

2A => 5A
C512
33pF
50V

C509
33pF
50V

MCLK SDATA WCK BCK TP is necessory


Monitor0_1_2 TP is necessory

1
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.

BCM (BRAZIL VENUS)

KIM JONG HYUN


AUDIO

2009.03.23

15

* FROM LIPS & POWER B/D -->Apply changed Pin Map


+12V

+3.3V_ST

+5V_ST
L806

GND

15

16

GND

24V

17

18

24V

19

20

Inverter_On

21

22

Error_Out

23

24

PWM_Dim

JP810
C808
16V
0.1uF
OPT
C895
0.1uF
50V

R818
3.3K

C
B

E
Q806
2SC3052

OPT
R826
10K

R824
10K

R822
0
OPC_OUT1
7:I5

VCC

C1806
1uF
25V

OPT
C1819
0.1uF
50V

R875
0
7

D1_1
D2_2
D2_1

10uF
25V

C872
1uF

470pF
C880

Q813
2SC3875S(ALY)
OPT

C879
470pF

415 mA @85% efficiency

D1.8V
INV_ON/OFF
12:I5

OPT

+5.0V

+1.8V_MEMC

750 mA

D3.3V

R827
10K
OPT

IC802

INPUT

ERROR_OUT
12:F6

C806 R802
0
0.1uF
16V
OPT

0
OPT

3
1

0.1uF

MLB-201209-0120P-N2
L813

1%
R825
66.5

1%
R857
56

+12V

PGND
0.1uF

L812
MLB-201209-0120P-N2

R1

R2

Vout = (1+R2/R1)*1.25
C840

1.8V_BCM3556

+12V

C838
1uF
25V

VIN

AGND

R819
56
1%

* +12V to +5.0V

L815
3.6uH

C822
330uF
C818
4V

ADJ/GND

12:A3;A6;C4;F7;G7;I2;14:B2

400 mA + 600 mA

IC805
AOZ1073AIL

OUTPUT

C811

C876
100uF
16V

OPT

0.1uF

1000pF

C836

50V

FB

C841
10uF

LX_2

C1817
10uF

LX_1

C859
0.1uF

C855
10uF
6.3V

EN

COMP

12:A3;A6;B5;F7;G7;I2;14:B2

R871
20K

1/10W

C887

must be placed with pin#8,#10 as close as possible.

* D1.8V

R870
10K

R807

R834
150K

A1[RD]

1K

AZ1085S-ADJTR/E1

C829
1uF
25V
OPT

R876
A2[GN]1K

SAM2333

R863

L826
BG2012B080TF

R832
3.3K

R861
3.3

25V

R830
0

OPT
R869
0

+3.3V_ST

TruMotion_240Hz

PWM_DIM
9:G7;9:I3;7:I5

C856
6800pF

C802
68uF
35V

+5.0V

R815
100

S2

R844
11K

C805
1uF
25V

C804
1uF
50V

C807
68uF
35V

R854
10K

25

G1

NC

G2

C812
0.1uF
50V

OPT
R816
6.8K

A_DIM
9:G6;9:I3

L804
BG2012B080TF

DRV

10

LDFB

GND_1

N.C
N.C

4.7K
R801

L805
CB4532UK121E

A.Dim

LDOG

+24V

C1816
10uF
6.3V

D1_2

12V

C886

GND

14

22uF
16V

LD1

12

13

S1

R864
620

R862
5.6K

DL

11

0.1uF

11

12V

FB
C842

C819
22uF
16V

C899
100uF
16V

C827
100uF

10K

GND

Q812
SI4804BDY

C885

5.2V

2.2uH

GND_2

33uF

5.2V

10

12

R843

0.01uF C884

5.2V

COMP
220uF ==> 100uF*2 + 22uF for Depth

L807

100uF
16V C883

5.2V

CB4532UK121E

10uF C881
6.3V

GND

L830
MLB-201209-0120P-N2

L828

PN

10uF C882
6.3V

GND

13

+5V_ST
C1814

14

A3.3V
Well change SI4804 to KECs Product

10uF
6.3V

GND

D803
1N4148W
100V
DH

C878

GND

OCS

L829
MLB-201209-0120P-N2

+12V

0.1uF

C826
47uF
25V

OPT

BST

POWER_ON

GND

C828
0.1uF
50V

C896
22uF
16V

C824
0.1uF
50V
OPT

10K
OPT

+3.3V_MEMC

C873
1uF
25V

C1809

L808
MLB-201209-0120P-N2

RL_ON
12:I5;14:E5

C862
470pF

+12V

R828

N.C

IC809
SC2621ASTRT

Q807
2SC3875S(ALY)

D3.3V

MLB-201209-0120P-N2

1/10W

R829
0

RT1P141C-T112

P801
FM20020-24

R820
33K

R817
33K

L822

R859
330K

R873
3.3K

R823
1K

OPT

C820
15pF
50V

OPT

Q805

0.1uF

MLB-201209-0120P-N2

MLB-201209-0120P-N2
L811

C835
1uF
25V

R855
12.4K
1%

16V

C877

6.3V

NC_3 R856
22K

6.3V

C1810

1K

R846

VO

D805

C1805
1uF
25V

G2

CB3216PA501E
L801

* +5v_ST to +3.3V_ST

6
5

D2_1

22uF
16V

D1_2

G1

D1_1

S2

D2_2

G2

D2_1

0.1uF

* +12v -> PANEL_POWER

C1807

10uF 6.3V

0.01uF

C865

C861

4V

6.3V
C854

10uF

1.2K

C852

330uF

D2_2

Q804
SI4925BDY

S1

+5V_ST

+3.3V_ST

7:I5;7:I7
12V_TCON

OPT
IC801

INPUT

C803
0.1uF
16V

R810
22K

OUTPUT

1
C801
10uF
16V

ADJ/GND

C817
4.7uF
25V

R812
47K

AZ1117D-3.3TRE1

1uF
25V

1uF
25V

C1811

C898

D1_1

3.3

C1804

S2

R836

G1

NC

VCC

A1.2V

C833
22uF
25V

47K
R813
OPT
R806
10K

12:I5
PANEL_CTL

R805
10K B

2SC3052

C
Q803
2SC3052

B
C

22K

R811

ADJ

SAM2333

Q802

R814
15K
1%

DRV

D1_2

470pF

C815
2200pF

C825
220pF

GND_1

10

C847

LDFB

C1800 1uF
25V

LDOG

C844

S1

R872

R842

DL

0.1uF

11

C839

2K

2.2uH

GND_2
Q809
SI4804BDY

FB

C870
0.1uF
16V

L821
MLB-201209-0120P-N2

L817

470pF

PN

200

12

DH

D1.2V

R847

SC4215ISTRT
IC803

C868
10uF
10V

13

+5V_ST

1.5K

COMP

D801
1N4148W
100V

R848

14

NC_2

* +5.0V to 1.2V

R878

OCS

GND

GND

+12V

IC804
SC2621ASTRT
BST

EN

VIN

0.1uF

10uF
6.3V

+5.0V

1/8W

ADJ

10uF

C858
33uF
10V

R852
10K

10uF

R833
390K

EN

2
R835
NC_1
1
C1815

NC_1
L827
MLB-201209-0120P-N2

VO
3

must be placed with pin#8,#10 as close as possible.

R831
6.8K

NC_3
5

4
VIN

C875

NC_2

A1[RD]

C848
470pF

C832
1uF
25V

10uF
25V

C837
1uF
25V

33uF 10V
C888
A2[GN]

OPT
C1818
0.1uF
50V

+1.26V_MEMC

IC807
SC4215ISTRT

A2.5V

6.3V

D2_1

D2.5V

6.3V

VCC

C851

3.3

10uF

D2_2

600 mA

+1.8V_MEMC

10uF

R821
1.8K

C830
2200pF

C821
0.068uF

* +1.26V Core for FRC

VOUT : 2.533V

C1813

G2

GND_1

D1_1

D3.3V

0.01uF

C1812

S2

NC

470pF

R837

10uF
16V

39K

C1801
10uF 10uF
16V
16V

10V

G1

C1808

18K

10

C863

1.1K

LDFB

DRV

R874

LDOG

C853 C860

D1_2

C845

S1

33uF

DL

0.1uF
50V

11

C1802

FB

R849
10K

R840

Q810
SI4804BDY

C1803

R853
300

2.2uH

GND_2

R841

12

C814 0.1uF
16V

R845
15K

50V

* +1.8V_MEMC for FRC DDR

L819

PN

16V

13

C810

COMP

C846
330pF

DH

22uF

14

12:A3;2:Y20;2:Z10;B3;C6;H5;7:A3;14:I7;14:J1

MLB-201209-0120P-N2
L824

OCS

D802
1N4148W
100V

100uF
16V

BST

+5.0V

R877

IC806
SC2621ASTRT

1
FLASH, A1.2, +1.8_DDR_BCM3556, VTT

THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.

BCM (BRAZIL VENUS)

2009.03.23

AN SO YOUNG
POWER

15

D1.8V

C354
0.1uF

C353
0.1uF

C352
0.1uF

C335
470pF

C334
2700pF

C333
0.047uF

C332
0.01uF

C331
0.1uF

C330
10uF

C329
470pF

C328
2700pF

C327
0.047uF

C326
0.01uF

C325
0.1uF

C324
10uF

C323
100uF

C351
0.1uF

C350
0.1uF

C349
0.1uF

C317
470pF

C316
2700pF

C315
0.047uF

C314
0.01uF

C313
0.1uF

C312
10uF

C311
470pF

C310
2700pF

C309
0.047uF

C308
0.01uF

C307
0.1uF

C306
10uF

C305
100uF

D1.8V

A1.2V

IC100
BCM3556

DDR_EXT_CLK
DDR0_CLK
DDR0_CLKB
DDR1_CLK
DDR1_CLKB
DDR01_A00
DDR01_A01
DDR01_A02
DDR01_A03
DDR0_A04
DDR0_A05
DDR0_A06
DDR01_A07
DDR01_A08
DDR01_A09
DDR01_A10
DDR01_A11
DDR01_A12
DDR01_A13
DDR1_A04

DDR1_A05
DDR1_A06
DDR01_BA0
DDR01_BA1
DDR01_BA2
DDR01_CASB
DDR0_DQ00
DDR0_DQ01
DDR0_DQ02
DDR0_DQ03
DDR0_DQ04
DDR0_DQ05
DDR0_DQ06
DDR0_DQ07
DDR0_DQ08
DDR0_DQ09
DDR0_DQ10
DDR0_DQ11
DDR0_DQ12
DDR0_DQ13

DDR0_DQ14
DDR0_DQ15
DDR1_DQ00
DDR1_DQ01
DDR1_DQ02
DDR1_DQ03
DDR1_DQ04
DDR1_DQ05
DDR1_DQ06
DDR1_DQ07
DDR1_DQ08
DDR1_DQ09
DDR1_DQ10
DDR1_DQ11
DDR1_DQ12
DDR1_DQ13
DDR1_DQ14
DDR1_DQ15
DDR0_DM0
DDR0_DM1

DDR1_DM0
DDR1_DM1
DDR0_DQS0
DDR0_DQS0B
DDR0_DQS1
DDR0_DQS1B
DDR1_DQS0
DDR1_DQS0B
DDR1_DQS1
DDR1_DQS1B
DDR01_RASB
DDR_VREF0
DDR_VREF1
DDR01_WEB
DDR_VDDP1P8_1

DDR1_VREF0

Qimonda

B24
B23
B17
C22

Qimonda

IC300

F20
R312
0
OPT
R313

R301
22

DDR0_DQ[0-15]

E5;H5;I2

DDR01_ODT

VREF

J2

DDR01_A[0]

A0

M8

DDR01_A[1]

A1

M3
M7

B6;H6;H2;B5 DDR01_A[0-3,7-13]

E5;H5;I1

B12

DDR0_CLK

E5

C12

DDR0_CLKb

E5

DDR1_CLK

H5

DDR01_A[2]

A2

DDR1_CLKb

H5

DDR01_A[3]
DDR0_A[4]

A3

N2

A4

N8

DDR0_A[5]

A5

N3

DDR0_A[6]

A6

N7

A13
A12

DDR0_A[4-6]

B6;H2

DDR01_A[0]

E14

DDR01_A[1]

A15

DDR01_A[2]

D15

DDR01_A[3]

E13

DDR0_A[4]

E12

DDR0_A[5]

F13

DDR0_A[6]

C14

DDR01_A[7]

F14

DDR01_A[8]

DDR01_A[0-3]

E6;H6;H2

A7

DDR01_A[7]
DDR0_A[4-6]

D6;H2

P2

DDR01_A[8]

A8

P8

DDR01_A[9]

A9

P3

DDR01_A[10]

A10/AP

M2

DDR01_A[11]

A11

P7

DDR01_A[12]

A12

R2

B14

DDR01_A[9]

D14

DDR01_A[10]

C13

DDR01_A[11]

B5;H5;I1

DDR01_BA0

BA0

L2

D13

DDR01_A[12]

B5;H5;I1

DDR01_BA1

BA1

L3

B13

DDR01_A[13]

B5;H5;I1

DDR01_BA2

BA2

L1

F15

DDR1_A[4]

C15

DDR1_A[5]

D16

DDR1_A[6]

CK

J8

DDR01_A[7-13]

DDR1_A[4-6]

E6;H6;H2

H6;H1

R300
100

F16

B6

DDR0_CLKb

CK

K8

B6;H5;I2

DDR01_CKE

CKE

K2

DDR01_BA0

B16

DDR01_BA1

E15

DDR01_BA2

G8

DQ0

DDR0_DQ[0]

G2

DQ1

DDR0_DQ[1]

H7

DQ2

DDR0_DQ[2]

H3

DQ3

DDR0_DQ[3]

H1

DQ4

DDR0_DQ[4]

H9

DQ5

DDR0_DQ[5]

F1

DQ6

F9

DQ7

DDR0_DQ[7]

C8

DQ8

DDR0_DQ[8]

C2

DQ9

D7

DQ10

DDR0_DQ[10]

D3

DQ11

DDR0_DQ[11]

D1

DQ12

DDR0_DQ[12]

D9

DQ13

DDR0_DQ[13]

B1

DQ14

DDR0_DQ[14]

B9

B4

DQ15

B6;E6;H2;B5

DDR1_A[4-6]

B5;H1

DDR0_DQ[6]

DDR0_DQ[9]

DDR0_DQ[15]

B5;E5;I1

K9

A9

VDDQ10

L8

C1

VDDQ9

E9

VDDQ5

DDR0_DQ[5]

G1

VDDQ4

G3

VDDQ3

B3

G7

VDDQ2

B3

G9

VDDQ1

E10

DDR0_DQ[9]

E9

DDR0_DQ[10]

F11

DDR0_DQ[11]

F12

DDR0_DQ[12]

E8

DDR0_DQ[13]

D10

DDR0_DQ[14]

F8

DDR0_DQ[15]

C18

DDR1_DQ[1]

A18

DDR1_DQ[2]

B21

DDR1_DQ[3]

C21

DDR1_DQ[4]

B18

DDR1_DQ[5]

B20

DDR1_DQ[0-15]

N8
N3
N7
P2
P8

A9

P3

A10/AP

M2

A11

P7

A12

R2

BA0

L2

BA1

L3

NC_4/BA2

L1

DDR1_DQ[11]

A22

DDR1_DQ[12]

DQ3

H3

DQ3

H1

DQ4

H1

DQ4

H9

DQ5

H9

DQ5

F1

DQ6

F1

DQ6

F9

DQ7

F9

DQ7

C8

DQ8

C8

DQ8

C2

DQ9

C2

DQ9

D7

DQ10

D7

DQ10

D3

DQ11

D3

DQ11

D1

DQ12

D1

DQ12

D9

DQ13

D9

DQ13

B1

DQ14

B1

DQ14

B9

DQ15

B9

DQ15

A1

VDD_5

E1

VDD_4

A0

M8

A1

M3

A2

M7

A3

N8
N3

A6
A7
A8

A1

VDD_5

E1

VDD_4

N2

A4
A5

N7
P2
P8

A9

P3

A10

M2

A11

P7

A12

R2

BA0

L2

BA1

L3

BA2

L1

J9

VDD_3

J9

VDD_3

CK

J8

M9

VDD_2

CK

J8

M9

VDD_2

K8

R1

VDD_1

CK

K8

R1

VDD_1

CKE

K2

CKE

K2

ODT

K9

A9

VDDQ_10

CS

L8

C1

VDDQ_9

RAS

K7

C3

VDDQ_8

CAS
WE

CAS

L7

C7

VDDQ_7

WE

K3

C9

VDDQ_6

E9

VDDQ_5

G1

VDDQ_4

G3

VDDQ_3

G7

VDDQ_2

G9

VDDQ_1

UDQS

F7
B7

ODT

K9

A9

VDDQ_10

CS

L8

C1

VDDQ_9

RAS

K7

C3

VDDQ_8

L7

C7

VDDQ_7

K3

C9

VDDQ_6

E9

VDDQ_5

G1

VDDQ_4

G3

VDDQ_3

G7

VDDQ_2

G9

VDDQ_1

LDQS
UDQS

F7
B7

LDM

F3

LDM

F3

UDM

B3

UDM

B3

DDR1_DQ[10]

E20

H3

CK

LDQS

DDR1_DQ[9]

F18

J6

N2

A4
A5

A8

DDR1_DQ[8]

D21

M7

A7

DDR1_DQ[7]

E18

A2

A6

DDR1_DQ[6]

D18

M3

A3

DDR1_DQ[0]

C20

M8

A1

A3

VSS_5

E8

E3

VSS_4

LDQS

A8

J3

VSS_3

UDQS

N1

VSS_2

P9

VSS_1

NC_5

R3

LDQS
UDQS

NC_5/A14

R3

F17

DDR1_DQ[13]

NC_6/A15

R7

B22

DDR1_DQ[14]

NC_1

A2

E17

DDR1_DQ[15]

NC_2

E2

NC_3/A13

R8

B2

VSSQ_10

B8

VSSQ_9

A7

VSSQ_8

D2

VSSQ_7

A3

VSS_5

E8

E3

VSS_4

A8

J3

VSS_3

N1

VSS_2

P9

VSS_1

NC_6

R7

NC_1

A2

NC_2

E2

NC_3

R8

A3

VSS5

B3

DDR0_DQS0b

LDQS

E8

E3

VSS4

B3

DDR0_DQS1b

UDQS

A8

J3

VSS3

N1

VSS2

P9

VSS1

R3

NC5

R7

NC1

A2

NC2

E2

NC3

VSSDL

R8

J7

B2

VSSQ10

B8

VSSQ9

A7

VSSQ8

D2

VSSQ7

D8

VSSQ6

E7

VSSQ5

F2

VSSQ4

F8
VDDL

J1

VREF

J2

A0

M8

A1

M3

A2

M7

A3

VSSQ3

VSSQ9

A7

VSSQ8

D2

VSSQ7

D8

VSSQ6

E7

N2

A4

N8

A5

N3

A6

N7

A7

P2

VSSQ5

H2

VSSQ2

A8

P8

A9

VSSQ1

P3

H8

A10/AP

M2

A11

P7

A12

R2

VSSQ_10

B8

VSSQ_9

BA0

L2

A7

VSSQ_8

BA1

L3

D2

VSSQ_7

NC_4/BA2

L1

H1

DQ4

M3

H9

DQ5

A2

M7

F1

DQ6

A3

N2

F9

DQ7

A4

N8

C8

DQ8

A5

N3

C2

DQ9

A6

N7

D7

DQ10

A7

P2

D3

DQ11

A8

P8

D1

DQ12

D9

DQ13

A10

M2

B1

DQ14

A11

P7

B9

DQ15

A12

R2

BA0

L2

A1

VDD_5

BA1

L3

E1

VDD_4

BA2

L1

J9

VDD_3

J8

M9

VDD_2

R1

VDD_1

H4

H8

VSSQ_1

H8

VSSQ_1

VSSQ_6

VREF

A9

J2

M8

P3

G8

DQ0

G2

DQ1

H7

DQ2

H3

DQ3

H1

DQ4

H9

DQ5

F1

DQ6

F9

DQ7

C8

DQ8

C2

DQ9

D7

DQ10

D3

DQ11

D1

DQ12

D9

DQ13

B1

DQ14

B9

DQ15

A1

VDD_5

E1

VDD_4

J9

VDD_3

CK

J8

M9

VDD_2

CK

K8

R1

VDD_1

CKE

K2

ODT

K9

A9

VDDQ_10

ODT

A9

VDDQ_10

C1

VDDQ_9

K9

L8

CS

L8

C1

VDDQ_9

DDR1_DM1

H4

CS

E4

K7

C3

VDDQ_8

DDR0_DQS0

RAS

C3

L7

C7

VDDQ_7

K7

VDDQ_8

CAS

CAS

C7

E4

K3

C9

VDDQ_6

L7

VDDQ_7

WE

DDR0_DQS0b

WE

C9

VDDQ_6

VDDQ_5

K3

E9

E9

VDDQ_5

G1

VDDQ_4
LDQS

VDDQ_4

VDDQ_3

G1

G3

UDQS

VDDQ_3

G7

VDDQ_2

G3
G7

VDDQ_2

G9

VDDQ_1

G9

VDDQ_1

A3

VSS_5

RAS

H4

DDR1_DQS0b

H4

DDR1_DQS1

D19

DDR1_DQS1b

UDQS

F7
B7

E4

DDR1_DQS0

E19

LDQS

E4

DDR0_DQS1b

* DDR_VTT

H4
H4
DDR0_VREF0

DDR01_RASb
E5;H5;I1

DDR_VTT

DDR1_VREF0

D3.3V

A23

LDM

UDM

F3

B3

UDM

B3

1uF 470pF 470pF

1uF

C864
0.1uF
16V

C874
10uF
10V

GND

VSS_5

LDQS

E8

E3

VSS_4

LDQS

E3

VSS_4

J3

VSS_3

E8

A8

UDQS

J3

VSS_3

VSS_2

A8

N1

VSS_2

R3

P9

VSS_1

N1

NC_5/A14

NC_5

P9

VSS_1

NC_6/A15

R3

R7

NC_6

R7

NC_1

A2

B2

VSSQ_10

NC_2

E2

B8

VSSQ_9

A7

VSSQ_8

VDDL

C869
100uF
16V

A3
UDQS

R8

J7

C7

1uF

B7

F3

VSSDL

IC808
BD35331F-E2

F7

LDM

NC_3/A13

DDR01_WEb

1uF 470pF 470pF

VSSQ10

B8

A1

K2

C355
0.1uF

B2

A0

K8

D22

VSS1

DQ3

CK

DDR_VDDP1P8_2

VSS2

P9

H3

CK

D1.8V

VSS3

N1

DQ2

CKE

C17

VSS4

J3

DQ1

VSSQ_5

A7

E3

A8

DQ0

VSSQ_2

C16

E8

UDQS

H7

VSSQ_3

C19

LDQS

G2

VSSQ_4

B19

VSS5

DDR1_DQS0b
DDR1_DQS1b

G8

E7

F9

A3
B3

ELPIDA

H2

DDR0_DQS1

B7

B3

IC301-*1
EDE1116ACBG-1J-E

F8

F10

VDDQ1

HYNIX
IC301-*2
H5PS1G63EFR-20L

F2

B9

VDDQ2

G9

UDQS

B3

VSSQ_5

B10

VDDQ3

G7

DDR1_DQS1

F7

UDM

VSSQ_2

F19

VDDQ4

G3

DDR1_DQS0

DDR1_DM1

VSSQ_3

J1

VDDQ5

G1

LDQS

B3

VSSQ_4

VDDL

VDDQ6

E9

B3

E7

J1

C9

UDM

H2
VDDL

K3

DDR0_DM1

F8

DDR1_DM0

WE

B3

B2

D8

DDR01_WEb

F3

F2

J7

VDDQ7

B2;E5;I1

LDM

E4

VSSDL

C7

DDR1_DM0

E4

VSSQ_6

L7

B3

DDR0_DM1

D8

VDDQ8

CAS

F3

DDR0_DM0

J7

C3

DDR01_CASb

LDM

C10

VSSDL

K7

B5;E5;I1

DDR0_DM0

A10
A20

DDR01_RASb

RAS

B2;E5;I1

B3

NC4

VDD4

CS

DDR0_DQ[4]

A0

DDR1_CLK

ODT

C8

B7

E1

J1

B2

VSSQ_10

B8
A7

VSSQ_9

NC_1

A2

VSSQ_8

NC_2

E2

D2

VSSQ_7

NC_3

R8

D8

VSSQ_6

E7

VSSQ_5

F2

VSSQ_4

F8

VSSQ_3

H2

VSSQ_2

H8

VSSQ_1

D2
D8

VSSDL

J7

E7
F2

VDDL

J1

NC4

R3

NC5

R7

NC1

A2

NC2

E2

NC3

VSSDL

R8

J7

F2

VDDL

DDR1_DQ[5]

DDR1_DQ[9]

DDR1_DQ[12]

D1.8V

DDR01_ODT

E11

DDR0_DQS1

VDD5

B6;E5;I1

VDDQ6

B3

A1

VDD1

C9

DQ2

DDR1_DQ[15]

VDD2

K3

DQ1

DQ15

K2

WE

DQ0

B9

CKE

DDR01_WEb

H7

DDR1_DQ[14]

DDR01_CKE

B2;H5;I1

G2

DDR1_DQ[13]

DQ14

B6;E5;I2

DDR0_DQ[3]

G8

DQ13

B1

VDD3

D11

J2

DQ12

D9

R1

VDDQ7

VREF

L2

D1

K8

C7

DQ2

BA0

DDR1_DQ[11]

CK

L7

DQ1

DDR01_BA0

DDR1_DQ[10]

DQ11

DDR1_CLKb

CAS

DQ0

R2

DQ10

D3

B6

DDR01_CASb

H7

P7

A12

DQ9

D7

VDD1

B5;H5;I1

G2

M2

A11

DDR01_A[12]

C2

R1

DDR0_DQ[2]

G8

A10/AP

DDR01_A[11]

DDR1_DQ[8]

M9

B8

J2

DDR01_A[10]

DQ8

J9

VDDQ8

VREF

P3

C8

J8

VDDQ9

DDR0_DQ[8]

P8

A9

DDR1_DQ[7]

CK

VDDQ10

DDR0_DQ[7]

P2

A8

DDR01_A[9]

R303
100

C3

D8

A7

DDR01_A[8]

DQ7

B6

C1

C9

DDR01_A[7]

DDR1_DQ[6]

F9

VDD2

A9

UDQS

N7

DQ6

VDD3

K7

B3

N3

A6

F1

VDD4

L8

G6

A5

DDR1_A[6]

DQ5

M9

K9

DDR0_DQ[0-15]

DDR1_A[5]

DDR1_DQ[4]

H9

J9

CS

DDR0_DQ[6]

N8

DQ4

E1

RAS

C11

A4

DDR1_DQ[3]

H1

L1

ODT

F7

M7
N2

DDR1_DQ[2]

DQ3

L3

DDR01_RASb

LDQS

A2
A3

DDR1_DQ[1]

DQ2

H3

BA2

DDR01_ODT

DDR0_DQS0

DDR01_A[2]
DDR01_A[3]
DDR1_A[4]

DQ1

H7

BA1

B2;H5;I1

IC300-*1
EDE1116ACBG-1J-E

M3

G2

DDR01_BA1

B6;H5;I1

ELPIDA

M8

A1

DDR1_DQ[0]

DDR01_BA2

DDR0_DQ[1]

HYNIX

A0

DDR01_A[1]

DQ0

B5;E5;I1

DDR0_DQ[0]

IC300-*2
H5PS1G63EFR-20L

DDR01_A[0]

G8

B5;E5;I1

B11

DDR01_CASb

J2

VDD5

A1

A8

A17

VREF

DDR01_A[0-3,7-13]

D1.8V

DDR0_CLK

B6

DDR1_DQ[0-15]

HYB18TC1G160C2F-1.9

C322

470pF 0.1uF

C23

B15

C321

B4

470pF 0.1uF

240

E16

IC301

HYB18TC1G160C2F-1.9

C301

C300
DDR01_CKE

C361

DDR0_VREF0

C360

DDR_COMP
DDR01_ODT

C346

C342

DDR01_CKE

C345

0.1uF

B7

C343

DDR_PLL_LDO

0.1uF

A24

C358

DDR_BVSS1
DDR_PLL_TEST

A6

C344

DDR_BVSS0

C359

DDR_BVDD1

C347

DDR_BVDD0

J1

VSSQ4

F8

VSSQ3

H2

VSSQ2

H8

VSSQ1

VSSQ_7
VSSQ_6
VSSQ_5

DDR_VTT

VSSQ_4

F8

VSSQ_3

H2

VSSQ_2

H8

VSSQ_1

D1.8V

DDR01_A[0-3,7-13]

VTT

DDR1_A[4]

R304

DDR01_A[0]

75

DDR01_A[1]

DDR0_A[4-6]

C336
0.01uF

DDR01_A[2]
EN

VTT_IN

R305

DDR1_VREF0
DDR0_VREF0
R850

R851

75

C337
0.01uF

DDR01_A[3]

R306

C338
0.01uF

DDR01_A[7]

75

DDR0_A[4]
VTTS

VREF

DDR0_A[5]

VCC

DDR0_A[6]
VDDQ

1M
R858

16V

C834
0.1uF
16V

C897
0.1uF
16V

C339
0.01uF

DDR01_A[9]

C871
1uF
6.3V

DDR01_A[10]

R307

DDR01_A[11]

75

DDR01_A[12]

BCM recommends to remove this R


B6;E5;H5

DDR01_CKE

OPT
DDR1_A[5]

75

B5;E5;H5
B5;E5;H5

THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.

DDR1_A[4-6]

R310
R308

DDR01_BA1

C362
0.1uF

DDR01_BA2

B2;E5;H5

DDR01_RASb

R309

B5;E5;H5

DDR01_BA0

75

B5;E5;H5

DDR01_CASb

B2;E5;H5

DDR01_WEb

B6;E5;H5

DDR01_ODT

75

R311

BCM (BRAZIL VENUS)

HONG YEON HYUK


DDR Memory

C341
0.01uF

75

DDR1_A[6]

C340
0.01uF

DDR01_A[13]

0.1uF

C831
0.1uF
16V

C866

DDR01_A[8]
C867
100uF
16V

2009.03.23

15

M_XTALO

R917

AVDD_PLL

URSA_B3P
URSA_B3M

GPIO[22]

M4

C16

LVB3M

GPIO[23]

M5

D15

LVB4P

URSA_B4P

GPIO[14]

G3

D16

LVB4M

URSA_B4M

E4

F9

GPIO[16]

F4

G10

GND_4

GPIO[17]

G4

E15

LVC0P

E16

LVC0M
LVC1P

URSA_C1P

GPIO[20]

K4

F14

LVC1M

URSA_C1M
URSA_C2P
URSA_C2M

GPIO[21]

L4

F16

LVC2P

VDDP_2

J6

F15

LVC2M

GND_7

H9

G15

LVCCKP

URSA_CCKP

G16

LVCCKM

URSA_CCKM

G14

LVC3P

URSA_C3P

H14

LVC3M

URSA_C3M
URSA_C4P

J16

J1

J14

LVD1P

URSA_D1P

K14

LVD1M

MDATA[27]

J2

URSA_DQ[28]

MDATA[28]

J3

URSA_DQ[25]

MDATA[25]

K1

URSA_DQ[30]

MDATA[30]

K2

URSA_DCKM

L16
M16

LVDCKM

L1

F8

J8

M15

LVD3P

DQS[2]

L2

M14

LVD3M

L3

N16

LVD4P

AVDD_DDR_4

L6

N15

LVD4M

VDDP_3

L8
H10

H6

VDDC_5
GPIO[24]

N6

M2

E12

GPIO[7]

L7

D14

GPIO[6]

MDATA[31]

M3

F12

GPIO[5]

MDATA[24]

N1

E13

GPIO[4]

GND_11

J9

F13

GPIO[3]

MDATA[26]

N2

G13

GPIO[2]

MDATA[29]

N3

H13

GPIO[1]

L10

J13

GPIO[0]

K12

PWM0

[N13]

L12

PWM1
CSZ

[N12]

K13
M12

SDO

M13

SDI

L13

SCK

G7

N14

GPIO[30]

L9

N13

30
31
32
33
34

URSA_A2M
URSA_A2P
URSA_A1M
URSA_A1P
URSA_A0M
URSA_A0P

35
36
37
38
39
40

OPT
R936

OPC_OUT1
PWM_DIM

42

43
44

0
R937
OPC_EN

45
46

+3.3V_MEMC
12V_TCON

47

3.3K
OPT

R954

49
50
51
52

R941

OPC_EN

R940

LVDS_SEL

0 OPC_EN
0

URSA_D4M

+3.3V_MEMC

0.1uF

R938

P904
TF05-41S

URSA_D4M
URSA_D4P
URSA_D3M
URSA_D3P
M_SPI_DO
M_SPI_DI
M_SPI_CK

3
4
5
6
7

M_SPI_CZ

GPIO[29]
GPIO[28]

URSA_DCKM
URSA_DCKP

8
9
10

URSA_D2M
URSA_D2P
URSA_D1M
URSA_D1P
URSA_D0M
URSA_D0P

11
12
13
14
15
16

G6

17
18

VDDC_4

M11
RESET

N11

N9

N10

GND_17

GPIO[26]

GPIO[27]

P16

R16
MCLK[1]

MCLKZ[1]

T16
MDATA[5]

R15

T15

P15
MDATA[2]

MDATA[0]

MDATA[7]

P14
MDATA[13]

R14
MDATA[10]

T14
MDATA[8]

R13

P13
MDATA[15]

T13
DQS[1]

URSA_D2M

URSA_C4M
URSA_C4P
URSA_C3M
URSA_C3P

GPIO8

PWM1

PWM0

HIGH

LOW

HIGH

URSA_CCKM
URSA_CCKP
URSA_C2M
URSA_C2P
URSA_C1M
URSA_C1P
URSA_C0M
URSA_C0P

19
20
21
22
23

I2C

24

C951

0.1uF

0.1uF

C950
0.1uF

EEPROM

HIGH

HIGH

LOW

25

SPI

HIGH

HIGH

HIGH

27
28
29
30
31
32
33

+3.3V_MEMC

C939

C938

C936

+3.3V_MEMC

C934

DQSB[1]

H11
VDDP_1

J7

R12

P12

GND_9

DQS[0]

DQSB[0]

T12

J11

P11

DQM[0]

DQM[1]

AVDD_DDR_1

R11
MDATA[14]

P10

T11
MDATA[9]

MDATA[12]

K11

R10
MDATA[11]

AVDD_DDR_3

T10

P9

R9

K7
GND_13

MDATA[6]

MDATA[1]

MDATA[3]

T9

F7
VDDC_3

MDATA[4]

C945

* SPI FLASH

29

26

0.1uF

K10

P8

N8
MCLKE

GND_16

C941

MADR[3]

T8

P7

R8
MADR[7]

MADR[9]

MADR[12]

L11

T7

R7
MADR[5]

AVDD_DDR_7

MADR[10]

P6

R6

MADR[1]

BADR[0]

T6

R5

P5
WEZ

BADR[1]

C922

MADR[11]

RASZ

0.1uF

T5

N4
T3

C921

N12

N5
P4

ODT

URSA_ODT

[N4]

J10

MVREF

[N5]

GND_12

GND_1

[L9]

MADR[8]

C925 0.1uF

28

URSA_D4P

M1

P2

27

URSA_D3M
C953

DQS[3]

MCLKZ[0]

26

URSA_D3P

DQSB[3]

R2

25

URSA_D2P
0.1uF

AVDD_DDR_5

MCLK[0]

24

AVDD_33_1

DQSB[2]

T2

C932

URSA_DCKP

K3

MDATA[21]

10K
R913

LVD2M

K6

URSA_DQ[21]

0.1uF

LVD2P

GND_10

T1

URSA_MCLKZ

GND_3

DQM[2]

MDATA[18]

URSA_MCLK

G9
L15

DQM[3]

URSA_DQ[18]

23

URSA_D1M

L14

LVDCKP

R1

22

C957

AVDD_DDR_2

MDATA[16]

21

3.3K

H3

MDATA[22]

URSA_DQ[16]

20

OPT
R953

48

URSA_DQ[27]

LGE7329A

19

URSA_ACKM
URSA_ACKP

URSA_C0M

E14

IC901

17

41

0.1uF

J4

F6

16

URSA_C0P

GPIO[19]

P1

14

R955

H4

MDATA[23]

13

URSA_A4M
URSA_A4P
URSA_A3M
URSA_A3P

C956

AVDD_33_2

GPIO[15]

URSA_DQ[23]

CB3216PA501E

L909

REXT
D12

LVB1M
C14

LVB3P

URSA_DQ[22]

0.1uF

1000pF 50V

C961

0.1uF

C949

0.1uF
LVB0M

LVB0P

LVB1P
C13

A13

B13

GPIO_6

GPIO_4
D7

D9

LVA4M
B12

LVA3M

LVA3P

LVA4P
A12

C12

C11

LVACKP

LVACKM
A11

B11

LVA2M
B10

LVA2P
A10

LVA1M
C10

LVA0M

LVA0P

LVA1P
C9

A9

B9

F10

B16

GND_8

0.1uF 50V
C960

10uF
C954

L908
10uF
C952

BLM18PG121SN1D

URSA_B1M

URSA_B1P

URSA_B0M

URSA_B0P

URSA_A4M

URSA_A3M

URSA_A4P

URSA_A3P

URSA_A2M

URSA_ACKP

URSA_ACKM

URSA_A1M

URSA_A1P

URSA_A2P

1uF
GPIO_8

GPIO_9

GPIO_12

GND_2
G8

D11

D13

E11

SCLM

SDAM

GPIO_1

GPIO[25]
N7

D6

D5

A14

XIN

XOUT

GPIO_14

GPIO_2
B14

D3

D4

K16

G2

AVDD_DDR_6

URSA_A0M

URSA_A0P

L907

BLM18PG121SN1D

C943

0.1uF
C944

C948

C942

0.1uF
GPIO_13

GND_5
H7

G11

AVDD_LVDS_2

RO0P

RO0N
B8

A8

C8

RO1N

RO2N

RO1P
C7

A7

B7

RO2P

ROCKP

ROCKN
B6

A6

C6

RO3N

RO4N

RO3P
C5

A5

K15

0.1uF

C940
GND_6
H8

F11

AVDD_LVDS_1

RE0P

RE0N
B4

A4

C4

RE1N

RE2N

RE1P
C3

A3

RECKN

RE2P
B3

B2

A2

C2

RE3N

RECKP

0.1uF

RE3P

RE4N

GPIO[13]

0.1uF

C906

C1

A16

MADR[6]

L902

BLM18PG121SN1D

F3

LVBCKM

AVDD_MEMPLL
10uF

URSA_BCKM

GPIO[12]

URSA_D0M

URSA_DQ[29]

C908

URSA_BCKP

URSA_D0P

+3.3V_MEMC
2.2K
R907
OPT

LVBCKP

URSA_C4M

C920

OPT

A15

LVD0M

URSA_DQ[26]

2.2K
R908

F2

LVD0P

URSA_DQ[24]

ISP_TXD_TR

URSA_B2M

LVC4M

URSA_DQ[31]

B6

LVB2M

J15

C928

B15

H15

URSA_DQS3

B6

E2

[D1]

H16

URSA_DQSB3

C15

URSA_B2P

H2

0.1uF

12

BIT_SEL

H1

0.1uF

ISP_RXD_TR

E10

GPIO_11

MDATA[17]

* ISP Port for MEMC

GPIO_7

MDATA[19]

URSA_DQSB2

D10

URSA_DQ[17]

URSA_DQS2

GPIO_5

URSA_DQ[19]

C919

TJC2508-4A

D8

LVB2P

0.1uF

18

0.1uF

LVC4P

C918

11

URSA_B2M
URSA_B2P
URSA_B1M
URSA_B1P
URSA_B0M
URSA_B0P

C955

MDATA[20]

URSA_DQM2

+5.0V

[E1]

GND_15 K9

C927

URSA_DQ[20]

15

GPIO_3

VDDC_2

URSA_BCKM
URSA_BCKP

820

D2

GPIO[11]

URSA_B4M
URSA_B4P
URSA_B3M
URSA_B3P

R931

K8

GPIO[10]

10

GND_14

E5

GPIO_10

0.1uF 0.1uF

URSA_DQM3

P902

100

E3

R4

BLM18PG121SN1D

10uF
C909

10uF
C907

0.1uF

0.1uF
C3020

C901

C904

22uF/16 CST PROBLEM

10uF

L904

+1.8V_MEMC

URSA_DQ[0-31]

PI Result

100

R948

C930

100
R928

P903
TF05-51S

499
OPC_EN

C913
0.1uF
16V

1K

100
R922

G1

MADR[4]

10uF

C912
0.1uF
16V

R916
OPT

R927

OPT
R949

L903

1K

100

R921

GPIO[9]

GPIO[18]

10uF
C911

R915

C910

BLM18PG121SN1D

+3.3V_MEMC

100
R926

100

3.3K

+3.3V_MEMC

R925

100
R920

1K

1/16W
5%

R919

12V_TCON
+3.3V_MEMC

D1
F1

VDDC_1

+3.3V_MEMC

1K
OPT

9:G6;I5

100

1K
R942

C929

R3029
0

100

1K
R943

OPT
LVDS_SEL

0.1uF
C937

GPIO[8]

T4

SCL3_3.3V

SCLS

E1

OPT
R939

R912

SDAS

A1

100
100

B1

R911

SDA3_3.3V

P3

9:I4

R3

9:I4

R910

MADR[2]

ISP_TXD_TR

MADR[0]

ISP_RXD_TR

A3

CASZ

A3

0.1uF

R909

RE4P

PI Result

10uF
C935

C926

L906

0.1uF

0.1uF

C923

C931

10uF
C916

C3019 10uF

C915

10uF

C914 0.1uF

6.3V

6.3V

22uF/16 CST PROBLEM

10uF
10V
C933

L905

BLM18PG121SN1D

BLM18PG121SN1D

+3.3V_MEMC

100
R924

RO4P

+1.26V_MEMC

R923

100
R918

B5

M_XTALI

LVDS_TX_0_DATA0_N

LVDS_TX_0_DATA0_P

LVDS_TX_0_DATA1_N

LVDS_TX_0_DATA2_P

LVDS_TX_0_DATA1_P

LVDS_TX_0_CLK_N

LVDS_TX_0_DATA2_N

LVDS_TX_0_CLK_P

LVDS_TX_0_DATA3_N

LVDS_TX_0_DATA4_N

LVDS_TX_0_DATA4_P

LVDS_TX_0_DATA3_P

LVDS_TX_1_DATA0_N

LVDS_TX_1_DATA1_N

22pF

LVDS_TX_1_DATA1_P

22pF

LVDS_TX_1_DATA0_P

C947

LVDS_TX_1_DATA2_N

12MHz

C946

LVDS_TX_1_DATA2_P

M_XTALI

M_XTALO

LVDS_TX_1_CLK_N

1M
X901

LVDS_TX_1_CLK_P

R929

* XTAL

LVDS_TX_1_DATA4_N

D
LVDS_TX_1_DATA3_N

C
LVDS_TX_1_DATA4_P

LVDS_TX_1_DATA3_P

34
35
36
37

M_SPI_CK

H3

M_SPI_DI

H3

4.7K
R933

R930

URSA_A[3]

URSA_A[7]

URSA_A[12]

URSA_A[9]

URSA_A[5]

URSA_A[10]

URSA_A[1]

URSA_A[11]

URSA_A[8]

URSA_A[6]

URSA_A[4]

URSA_A[2]

URSA_A[0]

40
41

URSA_DQ[5]

56

URSA_DQ[2]

56

R952

URSA_DQ[0]

R951

DIO

URSA_DQ[7]

CLK

URSA_DQ[13]

URSA_DQ[10]

HOLD

URSA_DQ[8]

URSA_DQ[15]

URSA_DQ[14]

URSA_DQ[9]

WP

URSA_DQ[12]

DO

GND

39

42

URSA_DQ[11]

10K

URSA_DQ[6]

56

R947

VCC

URSA_DQ[1]

R946

CS

38

FRC_RESET
URSA_DQ[3]

M_SPI_DO

56

0.1uF

URSA_DQ[4]

M_SPI_CZ

R945

C917

W25X20AVSNIG

C924
1uF

10K
R914

IC902

0.1uF

C958

0.1uF

0.1uF 0.1uF 0.1uF 0.1uF

THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.

URSA_MCLK1

URSA_MCLKZ1

URSA_DQSB1

URSA_DQS1

URSA_DQS0

URSA_DQSB0

URSA_DQM0

URSA_DQM1

URSA_A[0-12]

URSA_MCLKE

URSA_BA0

URSA_BA1

URSA_WEZ

URSA_CASZ

URSA_RASZ

URSA_DQ[0-31]

BCM (BRAZIL VENUS)

PARK.S.W

LVDS / Mstar FRC

2009.03.23

15

AA

AB

AC

AD

AE

AF

AG

AH

AI

AJ

AK

AL

AM

AN

AO

29
DDR2 1.8V By CAP - Place these Caps near Memory
+1.8V_FRC_DDR +1.8V_FRC_DDR

+1.8V_MEMC

28

+1.8V_FRC_DDR

C1021

0.1uF

0.1uF
C1020

0.1uF

0.1uF
C1018

0.1uF
C1019

C1016

0.1uF
C1017

0.1uF

0.1uF
C1014

0.1uF
C1015

0.1uF
C1013

10uF
C1011

0.1uF
C1012

0.1uF
C1009

0.1uF
C1010

0.1uF
C1007

0.1uF
C1008

10uF
C1006

10V

C1005

C1004

10uF

C1003

0.1uF

0.1uF

0.1uF

C1041

0.1uF

C1040

0.1uF

C1039

C1038

0.1uF

0.1uF

C1037

0.1uF

C1036

0.1uF
C1024

10uF
C1035

0.1uF

C1034

0.1uF

C1033

0.1uF

C1032

C1031

0.1uF

0.1uF

C1030

0.1uF

C1029

0.1uF

C1028

10uF

C1027

10V

C1026

C1025

10uF

0.1uF

C1042

0.1uF

0.1uF

C1045

27

0.1uF
C1044

C1043

BLM18PG121SN1D
L1002

PI Result

26
25
24

DDR_DQ[30]

URSA_DQ[26]

19

URSA_DQ[16]

18

G8

DQ1

G2

DDR_DQ[18]

DQ2

H7

DDR_DQ[19]

DQ3

H3

DDR_DQ[20]

DQ4

H1

DDR_DQ[21]

DQ5

H9

DDR_DQ[22]

DQ6

F1

DDR_DQ[23]

DQ7

F9

DDR_DQ[24]

DQ8

C8

DDR_DQ[25]

DQ9

C2

DDR_DQ[16]

DDR_DQ[26]

DQ10

D7

DDR_DQ[18]

DDR_DQ[27]

DQ11

D3

DDR_DQ[21]

DDR_DQ[28]

DQ12

D1

DDR_DQ[29]

DQ13

D9

DDR_DQ[30]

DQ14

B1

DDR_DQ[31]

DQ15

DDR_DQ[31]

DDR_DQ[29]
AR1001

URSA_DQ[23]

URSA_DQ[21]

DQ0

DDR_DQ[17]

DDR_DQ[26]

URSA_DQ[29]

URSA_DQ[18]

DDR_DQ[16]

DDR_DQ[19]
DDR_DQ[20]

DDR_DQ[24]
56

56

1K

0.1uF
C1023

1000pF

1K 1%

R1003

0.1uF

DDR_DQ[7]

DDR_DQ[23]

17

B9

+1.8V_FRC_DDR
VDD5

16

11

A1

DDRB_A[1]

M7

A2

DDRB_A[2]

N2

A3

DDRB_A[3]

N8

A4

N3

A5

DDRB_A[5]

N7

A6

DDRB_A[6]

P2

A7

P8

A8

DDRB_A[8]

P3

A9

DDRB_A[9]

M3

DDRB_A[4]

DDRB_A[7]

A10/AP
A11

DDRB_A[11]

R2

A12

DDRB_A[12]

L2

BA0

L3

BA1

J8

CK

M9

K8

CK

K2

CKE

K9

ODT

VDDQ10

A9

L8

CS

VDDQ9

C1

K7

RAS

C3

L7

CAS

VDDQ7

C7

K3

WE

VDDQ6

C9

VDDQ5

E9

VDDQ4

G1

VDDQ3

G3

VDDQ2

G7

VDDQ1

G9

F7

LDQS

B7

UDQS

DDRB_A[10]

AR1005

DDRB_A[1]

22

DDRB_A[12]

AR1006

DDRB_A[7]

22

URSA_A[9]

URSA_A[12]

DDRA_A[9]

URSA_A[12] AR1013

DDRA_A[12]

22

DDRA_A[7]

URSA_A[7]

URSA_A[7]

DDRB_A[5]

URSA_A[5]

URSA_A[5]

DDRA_A[5]

DDRB_A[0]

URSA_A[0]

URSA_A[2]

DDRA_A[2]

URSA_A[2]

URSA_A[0]

URSA_A[4]

URSA_A[6]

AR1007

DDRB_A[2]

22

DDRB_A[4]
DDRB_A[6]

AR1014

URSA_RASZ

B_URSA_CASZ
DDRB_A[11]

URSA_CASZ
URSA_A[11]
URSA_A[8]

URSA_CASZ
URSA_A[8]

DDRB_A[8]

R1005

DDRA_A[4]

R1008

A_URSA_RASZ

22

22

URSA_A[11]

DDRA_A[11]

7:B3

7:G1

URSA_MCLK1

URSA_MCLKZ

7:B3

7:G1

URSA_MCLKZ1

22

URSA_ODT

7:B3;X15

56
56

F3

LDM

R1009

56

B3

UDM

R1010

56

R1014

B_URSA_RASZ

R17

X17

A_URSA_RASZ

B_URSA_CASZ

R17

X17

A_URSA_CASZ

M7

A3

N2

DDRA_A[4]

A4

N8

DDRA_A[5]

A5

N3

DDRA_A[6]

A6

N7

DDRA_A[7]

A7

P2

DDRA_A[8]

A8

P8

DDRA_A[9]

A9

P3

DDRA_A[10]

A10/AP

M2

DDRA_A[11]

A11

P7

DDRA_A[12]

A12

R2

A_URSA_BA1
22

22

R1015

22

A_URSA_WEZ

U10

T11

M3

A2

DDRA_A[3]

A_URSA_MCLKE

URSA_ODT

7:B3;Q15

M8

A1

DDRA_A[2]

A_URSA_BA0
R1013

U10

T11

A0

A_URSA_CASZ
DDRA_A[8]

URSA_MCLK

B_URSA_WEZ

R1007

AR1011

22
22

B_URSA_MCLKE

R1006

DDRA_A[6]

URSA_A[4]

URSA_A[6]
URSA_RASZ

B_URSA_BA0
B_URSA_BA1
R1004

DDRA_A[0]

22

AR1008
B_URSA_RASZ

DDRA_A[1]

DDRA_A[10]

URSA_A[3]
URSA_A[9]

DDRA_A[0]

DDRA_A[1]

22

URSA_A[10]

URSA_A[1]

J2

DDRA_A[3]

AR1012

URSA_A[1]

URSA_A[10]

DDRB_A[3]
DDRB_A[9]

DDRB_A[10]

M2
P7

J9
R1

VREF
URSA_A[3]

E1

URSA_DQS2

7:B4

7:F1

URSA_DQS0

URSA_DQS3

7:B4

7:F1

URSA_DQS1

URSA_DQM2

7:B4

7:F1

URSA_DQM0

URSA_DQM3

7:B4

7:F1

URSA_DQM1

URSA_DQSB2

7:B4

7:F1

URSA_DQSB0

URSA_DQSB3

7:B4

7:F1

URSA_DQSB1

R1016
R1017

56
56

BA0

L2

BA1

L3

G8

DQ0

DDR_DQ[0]

G2

DQ1

DDR_DQ[1]

H7

DQ2

DDR_DQ[2]

56

H3

DQ3

DDR_DQ[3]

H1

DQ4

DDR_DQ[4]

H9

DQ5

DDR_DQ[5]

F1

DQ6

DDR_DQ[6]

F9

DQ7

DDR_DQ[7]

C8

DQ8

DDR_DQ[8]

C2

DQ9

DDR_DQ[9]

D7

DQ10

DDR_DQ[10]

D3

DQ11

DDR_DQ[11]

D1

DQ12

DDR_DQ[12]

D9

DQ13

B1

DQ14

DDR_DQ[14]

B9

DQ15

DDR_DQ[15]

A1

VDD5

E1
CK

J8

J9

VDD3

CK

K8

M9

VDD2

CKE

K2

R1

VDD1

K9

CS

L8

A9

VDDQ10

RAS

K7

C1

VDDQ9

CAS

L7

C3

VDDQ8

WE

K3

C7

VDDQ7

C9

VDDQ6

E9

VDDQ5

G1

VDDQ4

G3

VDDQ3

G7

VDDQ2

G9

VDDQ1

LDQS
UDQS

F7
B7

R1018

56

LDM

F3

R1019

56

UDM

B3

R1020

56

LDQS

E8

A3

VSS5

R1021

56

UDQS

A8

A3

E8

LDQS

R1011

56

VSS4

E3

A8

UDQS

R1012

56

E3

VSS4

VSS3

J3

J3

VSS3

VSS2

N1

N1

VSS2

VSS1

P9

P9

VSS1

B2

VSSQ10

B8

VSSQ9

A7

VSSQ8

D2

VSSQ7

D8

VSSQ6

E7

VSSQ5

VSSQ10

B2

VSSQ9

B8
A7

VSSQ7

D2

VSSQ6

D8

VSSQ5

E7

AR1009

L1

NC4

NC4

L1

R3

NC5

B_URSA_BA0

URSA_BA0

7:D1;T11

NC5

R3

R7

NC6

B_URSA_BA1

URSA_BA1

7:D1;T10

NC6

R7

URSA_MCLKE

7:E1;T10

URSA_WEZ

7:D1;T10

NC1

A2

NC2

E2

A2

NC1

E2

NC2

R8

NC3

Q16

B_URSA_MCLKE

Q14

B_URSA_WEZ

+1.8V_FRC_DDR

7:D1;U12

URSA_BA0

A_URSA_BA0

7:D1;U12

URSA_BA1

A_URSA_BA1

7:E1;U11
J7

22
AR1010

VSSDL

7:D1;U11

URSA_MCLKE
URSA_WEZ

NC3

AA17
+1.8V_FRC_DDR

AA17

A_URSA_MCLKE

Z16

A_URSA_WEZ

X14

22

VSSDL

R8

J7

VSSQ4

F2

VSSQ3

F8

F8

VSSQ3

VSSQ2

H2

H2

VSSQ2

VSSQ1

H8

H8

VSSQ1

J1

F2

VDDL

VDDL

J1

DDR_DQ[12]

URSA_DQ[11]
56

DDR_DQ[9]

DDR_DQ[6]

URSA_DQ[12]
URSA_DQ[9]
URSA_DQ[14]

AR1015

URSA_DQ[6]
56

URSA_DQ[1]

DDR_DQ[3]

URSA_DQ[3]

DDR_DQ[4]

URSA_DQ[4]

DDR_DQ[13]

+1.8V_FRC_DDR

VDD4

ODT

URSA_DQ[5]
AR1016

DDR_DQ[14]

DDR_DQ[1]

URSA_DQ[7]
URSA_DQ[0]
URSA_DQ[2]

DDR_DQ[5]
DDR_DQ[11]

7:G1;C22

URSA_DQ[13]
AR1017

DDR_DQ[0]

VSS5

VSSQ8

10

DDRB_A[0]

VDD2

13
12

M8

A0

VDD3

VDDQ8

14

VREF

VDD4

VDD1

15

A1

J2

URSA_DQ[0-31]

URSA_DQ[8]
URSA_DQ[10]

DDR_DQ[13]

IC1002
H5PS5162FFR-S6C

DDR_DQ[0-15]

AR1002

URSA_DQ[31]
URSA_DQ[24]

DDR_DQ[17]

150

URSA_DQ[20]

URSA_DQ[15]
56

DDR_DQ[10]

DDR_DQ[22]

R1024
OPT

20

56

DDRA_A[0-12]

URSA_DQ[22]

AR1018
DDR_DQ[15]
DDR_DQ[8]

DDR_DQ[2]

DDRB_A[0-12]

AR1003

URSA_DQ[17]
URSA_DQ[19]

IC1001
H5PS5162FFR-S6C

DDR_DQ[25]

150

21

DDR_DQ[28]
56

URSA_DQ[30]

DDR_DQ[16-31]

URSA_DQ[25]

OPT
R1001

URSA_DQ[28]

C1001

DDR_DQ[27]

1000pF
C1002

AR1004

R1023

7:G1;AM22

URSA_DQ[27]

R1022

URSA_A[0-12]

URSA_DQ[0-31]

22

+1.8V_FRC_DDR

1K 1%

R1002

+1.8V_FRC_DDR

1K
C1022

23

VSSQ4

9
8
7
6
resonance Compensation

0.1uF

C1053

0.1uF

0.1uF
C1051

0.1uF
C1050

C1049

0.1uF

C1048

0.1uF

+1.8V_FRC_DDR

C1047

C1046

0.1uF

+1.8V_MEMC

0.1uF
C1052

3
2
1

THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.

BCM (BRAZIL VENUS)

HONG.Y.H

M-STAR FRC DDR

2009.03.23

15

AP

RESET

SYS_RESETb
10:E4

D3.3V

F26
H28
J26
H27

C400
10uF
G5

BCM_AVC_DEBUG_TX2

R116

G26
J27
J28
F27

G5

G24

BCM_AVC_DEBUG_RX2

R117
33

H26
G27
G28
K23
G25

NAND_IO[0-7]

EBI_ADDR0

GPIO_04

EBI_ADDR5

GPIO_05

EBI_ADDR6

GPIO_06

EBI_ADDR8

GPIO_07

EBI_ADDR9

GPIO_08

EBI_ADDR13

GPIO_09

EBI_ADDR12

GPIO_10

EBI_ADDR11

GPIO_11

EBI_ADDR10

GPIO_12

EBI_ADDR7

GPIO_13

EBI_TAB

GPIO_14

EBI_WE1B

GPIO_15

EBI_CLK_IN

GPIO_16

EBI_CLK_OUT

GPIO_17

EBI_RWB

GPIO_18

EBI_CS0B

GPIO_19
GPIO_20

D3.3V

D3.3V

C3

32/42/55 - 6T SMD Gasket

4.7K

4.7K
R192

NAND_IO[3]

U26

NAND_IO[4]

U27

NAND_IO[5]

V26

NAND_IO[6]

V27

NAND_IO[7]

V28

NAND_CEb

T24

C2

NAND_ALE

C3

NAND_REb

T23

C2

NAND_CLE

T25

NAND_WEb

R24

NAND_RBb

U25

GPIO_21
NAND_DATA0

GPIO_22

NAND_DATA1

GPIO_23

NAND_DATA2

GPIO_24

NAND_DATA3

GPIO_25

NAND_DATA4

GPIO_26

NAND_DATA5

GPIO_27

NAND_DATA6

GPIO_28

NAND_DATA7

GPIO_29

NAND_CS0B

GPIO_30

NAND_ALE

GPIO_31

NAND_REB

GPIO_32

NAND_CLE

GPIO_33

NAND_WEB

GPIO_34

NAND_RBB

GPIO_35
GPIO_36

GAS5_6T

GAS4_6T

MDS61887702

MDS61887702

GAS3_6T

GAS2_6T

MDS61887702

MDS61887702

GAS1_6T

T27

GPIO_37

W24
U23
V23
V24

SF_MISO

GPIO_38

SF_MOSI

GPIO_39

SF_SCK

GPIO_40

SF_CSB

GPIO_41
GPIO_42

SCL2_3.3V

SDA2_3.3V

I4;12:F3

I4;12:F3

GPIO_45
47 - 7T SMD Gasket
GAS1-*1

GPIO_46

GAS2-*1 GAS3-*1

GPIO_47

GAS4-*1 GAS5-*1

GPIO_48
GPIO_49

GAS5_7T

GPIO_50
GPIO_51
GPIO_52
GPIO_53
GPIO_54
GPIO_55
GPIO_56
GPIO_57
SGPIO_00
SGPIO_01
SGPIO_02
SGPIO_03

SGPIO_04
SGPIO_05
SGPIO_06

* NAND FLASH MEMORY 1Gbit (128M)

Boot Strap
D3.3V

R2040
R315

2.7K

E3;E6

OPT

E5

NAND_RBb

E6

NAND_REb

NC_5

E6

NAND_CEb

RB

Open Drain

E
NC_7

OPT

R321
2.7K

C3024
4700pF
C114
0.1uF

R2030
2.7K

R2033
2.7K

E3;E6
NAND_IO[6]

NAND_IO[5]
R2031
2.7K

K25

100

R2004

AA27
R2009

AA28

100

AA26

AMP_RST
VREG_CTRL
PWM_DIM

I3;4:A5;7:I5

GAIN_SWITCH

L1

14:A6

DSUB_DET

L3

OPT

L2

R189

Y25

BCM_RX

Y26

BCM_TX

M27
AA25

RF_SWITCH

R25
N28

14:A6

SIDE_CVBS_DET

N27

R105
22

AH18
P23

M23

AUDIO_M_CLK

R195
OPT

AD19

100

R2008

A_DIM

3:C4
I3;4:A6

AE19
M4
M5

R2018 OPT 100

L23

R3030

OPT

100

Y28
Y27
G2

SF_SCK

R198

OPT

G3

SF_MISO

R196

OPT

G5

SF_MOSI

R197

OPT

G6

SF_CSB

R109

OPT

G4
L24

R161

P25
L5

R103

100

BIT_SEL
LVDS_SEL
BCM_AVC_DEBUG_TX1

C7

BCM_AVC_DEBUG_RX1

C7

AV1_CVBS_DET
BLUETOOTH_RESET
FRC_RESET

K4

14:A5
I3;14:I3
7:H2

K1
L27

BCM_AVC_DEBUG_RX2

M26

BCM_AVC_DEBUG_TX2

N23

C6
C7

R28
R27
R26
P28
P27
K6
K5

22

R2024

P26

22
22

R160

M3

DDC_SCL

I3;14:A6

DDC_SDA

I3;14:A6

D3.3V

R102

M2
M1
L4
L6
W27

HDMI_HPD_IN
COMP1_DET

14:A6

COMP2_DET

14:A5

OPT

22

R186

W28

22

R174

W26

22

R175

W25

22

R178

J2

22

R179

J1

22

R181

K3

22

R182

K2

22

R185

SGPIO_07

OPT

SCL0_3.3V

14:A6

SDA0_3.3V

14:A6

SCL1_3.3V

3:D3;2:AH5

SDA1_3.3V

3:D3;2:AH5

SCL2_3.3V
SDA2_3.3V

B5;12:F3
B5;12:F3

SCL3_3.3V

7:B6

SDA3_3.3V

7:B6

NC_8
VDD_1
VSS_1
NC_9

E5
IF FUNDMENTAL IS USED => LOW
IF DIP IS USED => HIGH

E6

CL

NAND_CLE

AL

NAND_ALE
E5

NAND_WEb
D3.3V

NAND_IO[1] : NAND Block 0 Write (DNS)


0 : Enable Block 0 Write
1 : Disable Block 0 Write
NAND_IO[3:2] : NAND ECC (10)
00 : No ECC
01 : 1 ECC Bit
10 : 4 ECC Bit
11 : 8 ECC Bit

WP

4.7K

R136

NC_11
NC_12
NC_13
NC_14

C
FLASH_WP_1

Q101
KRC103S

NC_15

48

47

46

45

44

43

42

41

40

10

39

11

38

12

37

13

36

14

35

15

34

16

33

17

32

18

31

19

30

20

29

21

28

22

27

23

26

24

25

NC_29

* I2C_0 : TUNER

NC_28

* I2C_1 : Audio amp, HDMI S/W

NC_27

G6;4:A6

2.7K

R2015
2.7K

A_DIM

G7;4:A5;7:I5

PWM_DIM

BLUETOOTH_RESET

NAND_IO[0-7]

NC_26

R2010
2.7K

R131

* I2C_2 : NVRAM,Micom

I/O7

NAND_IO[7]

I/O6

NAND_IO[6]

G7;12:I4;3:C5

* I2C_3 : FRC

I/O5

NAND_IO[5]

I/O4

NAND_IO[4]

AMP_RST
VREG_CTRL
HDMI_HPD_IN

G7;14:A6

TUNER_RESETb

NC_25
NC_24 D3.3V
NC_23

C136

10uF
6.3V

VDD_2
VSS_2

C115
0.1uF

NC_22

NAND_IO[0-7]

2.7K

2.7K

NC_3
NC_4

R191

R2032
2.7K

OPT
2.7K

R317

OPT

NC_2

NC_10

100 OPT R2005

* I2C MAP
NC_1

D3.3V

D3.3V

NAND_IO[0] : Flash Select (1)


0 : Boot From Serial Flash
1 : Boot From NAND Flash

OPT

OPT

K26

D3.3V

NC_6

NAND_IO[4]
E3;E6

K24

IC101
NAND01GW3A2CN6E

NAND_IO[2]
E3;E6

R2029
2.7K

K28

I3;14:A6

OPT

D3.3V

2.7K

R316

2.7K

R314

E3;E6
NAND_IO[3]

E3;E6

22
22

D3.3V

D3.3V

NAND_IO[0]

22

R2001
R2002

R2014
2.7K

R412
22

MDS61887703

SDA

GPIO_44

GAS4_7T

R411
22

MDS61887703

T26

NAND_IO[2]

R23

C2
C3

GAS5

U24

NAND_IO[1]

GPIO_43
SCL

GAS3_7T

WP

MDS61887703

GND

C416
0.1uF

GAS4

MDS61887703

A2

VCC

GAS3

GAS2_7T

A1
R3016
4.7K

MDS61887703

MDS61887702

A0

GAS2

GAS1_7T

4.7K

4.7K

R422

R419

GAS1

IC403
AT24C512BW-SH-T

R193

SMD Gasket Option

NAND_IO[0]

R199

K27

R2016
2.7K

NVRAM

R194

4.7K

L25

4.7K
R170

TUNER_RESETb

N25

R2013
2.7K

L26

R2011
2.7K

4.7K

GPIO_03

4.7K
R171

BCM_AVC_DEBUG_RX1

J25

R408
330

EBI_ADDR1

4.7K
R176

G6

H23

GPIO_02

4.7K
R177

GPIO_01

EBI_ADDR2

4.7K
R180

G6

BCM_AVC_DEBUG_TX1

GPIO_00

EBI_ADDR4

4.7K
R183

H24

EBI_ADDR3

4.7K
R184

R410
10K

R409
910

H25

4.7K
R187

J24
1

IC400
KIA7029AF

N26

J23

OPT
OPT

RESET
10:I2;12:I5

GIL-G-06-S3T2

R2003
0

IC100
BCM3556

P100
D3.3V

D3.3V

R2025
0

Hot Plug input pin should be feeded over 5mA.


BCM Recommend

D3.3V

POWER_DET
12:B3;12:I4

NC_21
NC_20
I/O3

NAND_IO[3]

I/O2

NAND_IO[2]

I/O1

NAND_IO[1]

I/O0

NAND_IO[0]

NC_19
NC_18
NC_17
NC_16

NAND_IO[4] : CPU Endian (0)


0 : Little Endian
1 : Big Endian

NAND_IO[6:5] : Xtal Bias Control (1, DNS)


00 : 1.2mA
01 : 1.8mA
10 : 2.4mA (Recommand)
11 : 3.0mA

THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.

BCM (BRAZIL VENUS)

2009.03.23

JANG.J.H
BCM3556 & NAND FLASH

15

When usding FUNDMENTAl then series R = 0 ohm and CL = 8 pF

IC100
BCM3556

LVDS_TX_0_DATA3_P
LVDS_TX_0_DATA3_N

G23
D25
D24
C25
E27
E26
D28
D27
D26
E23
E24
F25
C27
C26
B28
B27
A27
F24
F23
E25
C28

POD2CHIP_MDI2

LVDS_TX_0_CLK_N

POD2CHIP_MDI3

LVDS_TX_1_DATA0_P

POD2CHIP_MDI4

LVDS_TX_1_DATA0_N

POD2CHIP_MDI5

LVDS_TX_1_DATA1_P

POD2CHIP_MDI6

LVDS_TX_1_DATA1_N

POD2CHIP_MDI7

LVDS_TX_1_DATA2_P

POD2CHIP_MISTRT

LVDS_TX_1_DATA2_N

POD2CHIP_MIVAL

LVDS_TX_1_DATA3_P

CHIP2POD_MCLKO

LVDS_TX_1_DATA3_N

CHIP2POD_MDO0

LVDS_TX_1_DATA4_P

CHIP2POD_MDO1

LVDS_TX_1_DATA4_N

CHIP2POD_MDO2

LVDS_TX_1_CLK_P

CHIP2POD_MDO3

LVDS_TX_1_CLK_N

CHIP2POD_MDO4

LVDS_PLL_VREG

CHIP2POD_MDO5

LVDS_TX_AVDDC1P2

CHIP2POD_MDO6

LVDS_TX_AVDD2P5_1

CHIP2POD_MDO7

LVDS_TX_AVDD2P5_2
LVDS_TX_AVSS_1

CHIP2POD_MOVAL

LVDS_TX_AVSS_2

CHIP2POD_MOSTRT

AC18

AG21
C223

VDAC_AVDD2P5

LVDS_TX_AVSS_5

VDAC_AVDD1P2

LVDS_TX_AVSS_6

VDAC_AVDD3P3_1

LVDS_TX_AVSS_7

VDAC_AVDD3P3_2

LVDS_TX_AVSS_8
LVDS_TX_AVSS_9
LVDS_TX_AVSS_10

AF19
VDAC_AVSS_1

AD20

VDAC_AVSS_3

AH20
AG19

VDAC_RBIAS

CLK54_AVDD1P2

VDAC_1

CLK54_AVDD2P5

VDAC_2

CLK54_AVSS
CLK54_XTAL_N
CLK54_XTAL_P
CLK54_MONITOR

BSC_S_SDA
VCXO_AGND_2
USB_AVSS_1

T6
R7
T7

V2
U1
U2
T5

R2
T2

RESETB
NMIB

USB_AVDD2P5REF

TMODE_0

USB_AVDD3P3

TMODE_1

USB_RREF

TMODE_2

USB_DM1

TMODE_3

USB_DP1

SPI_S_MISO

USB_DM2

POR_OTP_VDD2P5

USB_DP2

POR_VDD1P2

T1

EJTAG_TCK

USB_PWRFLT_1

EJTAG_TDI

USB_PWRFLT_2

EJTAG_TDO

USB_PWRON_1

EJTAG_TMS

USB_PWRON_2

EJTAG_TRSTB

EPHY_RDAC

N3
N2
P1

P4
N4

PLL_MAIN_AVDD1P2

EPHY_RDP

PLL_MAIN_AGND

EPHY_TDN

PLL_MAIN_MIPS_EREF_TESTOUT

EPHY_TDP

PLL_RAP_AVD_TESTOUT

EPHY_AVDD1P2

PLL_RAP_AVD_AVDD1P2

EPHY_AVDD2P5

PLL_RAP_AVD_AGND

EPHY_AGND_1

N5
P7

14:A5

AV1_R_IN

14:A5
14:A6

AV1_INCM
COMP1_L_IN

14:A6

COMP1_R_IN

14:A6
14:A5

COMP1_INCM
COMP2_L_IN

14:A5

COMP2_R_IN

14:A5
14:A4

COMP2_INCM
SIDE_L_IN

14:A4

SIDE_R_IN

14:A4

SIDE_INCM
PC_L_IN

14:A3
14:A3

PC_R_IN

14:A3

PC_INCM

R204

51

C206

15nF

AE6

R214

51

C210

15nF

AD7

BYP_CPU_CLK

EPHY_AGND_3

BYP_DS_CLK
BYP_SYS175_CLK

51

C211

15nF

AH4

51

C232

15nF

AG5

R229

51

C220

15nF

AG6

R230

51

C221

15nF

AF7

51

C224

15nF

AH5

51

C225

15nF

AG7

51

C226

15nF

AD8

R234

51

C227

15nF

AF8

AUDMX_RIGHT2
AUDMX_INCM2

E7
F7
G7
A1.2V

H7

A2.5V

AD28
AD26
AC26
AC27
AE25

54MHz_XTAL_N

I2

54MHz_XTAL_P

I2

Y23

A1.2V

AB24
AC24

L203
BLM18PG121SN1D

AF25
AF24

C233
0.1uF

C235
4.7uF

F6

SYS_RESETb
4.7K

N24
J5
J4
J6
J3
V25
AH3

9:B7

R221
A2.5V
L201
BLM18PG121SN1D
C231
10uF

A1.2V

C234
0.1uF

AB8
D3.3V
H3

OPT
R224
4.7K

H2
H1

OPT
R225
4.7K

G1
H6

CONNECT NEAR BCM CHIP

H5
A1.2V
L204
BLM18PG121SN1D

AC25
AB27
M6
N6

R226
4.7K

R227
4.7K

INCM

R240
A1.2V
L207
BLM18PG121SN1D

390
OPT

N7

C4001

0.1uF

TU_CVBS_INCM
3:T25

5.1
R4009

C4002

Y24
AE24

1K

R222

AD25

1K

R223

0.1uF

SIDE_CVBS_INCM
3:T19

0.15uF
C4010

SIDE_INCM
3:T18
0.47uF
C4014

5.1
AV1_INCM 3:T20
R4011

C4003

0.1uF

0.15uF
C4011

0.47uF
C4015

AV1_CVBS_INCM
3:T19
5.1
R4012

C4004

0.1uF

COMP1_VID_INCM 3:T23

AUDMX_RIGHT5

0.15uF
C4008

COMP1_INCM
3:T24
C4016
0.47uF

5.1
R4010

AUDMX_INCM5
AUDMX_LEFT6
AUDMX_RIGHT6
AUDMX_INCM6
AUDMX_AVSS_1

C4005

0.1uF

C4000

0.1uF

C4006

0.1uF

C4007

0.1uF

R4008

AUDMX_AVSS_4
AUDMX_AVSS_5

AB11

COMP2_INCM
3:T22
0.47uF
C4013

5.1

AUDMX_AVSS_3

AA11

0.15uF
C4009

COMP2_VID_INCM
3:T21

AUDMX_AVSS_2

AB10

R_VID_INCM
3:T15

0.15uF
C4012

PC_INCM
3:T14
0.47uF
C4017

AUDMX_AVSS_6

AC8

AUDMX_LDO_CAP

AE5

AUDMX_AVDD2P5

R4002
34

C3003 47nF

C3002 47nF

C3001 47nF

47nF

C3007 47nF

47nF

C3004 47nF

C298

C296

D7

AUDMX_LEFT5

AB9

47nF

E6

AUDMX_INCM4

AA10

C279

E5

AUDMX_RIGHT4

AF5

C277

A5

AUDMX_LEFT4

AG8

47nF

C4

AUDMX_INCM3

AH8

47nF

F3

AUDMX_RIGHT3

AH7

C274

C1

AUDMX_LEFT3

AE8

C222
0.1uF

12pF
C229

F2

AUDMX_LEFT2

AH6
R233

7:E7

AUDMX_INCM1

AE7
R231

7:E7

LVDS_TX_0_CLK_P

AUDMX_RIGHT1

AG4

R232

LVDS_TX_0_CLK_N

22
R211
A1.2V A2.5V

AUDMX_LEFT1

AF6
R215
R228

7:E7

AA24

EPHY_AGND_2

BYP_SYS216_CLK
AV1_L_IN

7:E7

LVDS_TX_0_DATA0_P

F4

EPHY_PLL_VDD1P2

N1

14:A5

7:E7

LVDS_TX_0_DATA0_N

AB26

EPHY_RDN

P2
A2.5V

7:E7

LVDS_TX_0_DATA1_P

EPHY_VREF

P5
P3

A1.2V

7:E7

LVDS_TX_0_DATA1_N

EJTAG_CE1

P6
1K R219

7:E7

LVDS_TX_0_DATA2_P

H4

USB_MONPLL

EJTAG_CE0
R218
240

7:E7

LVDS_TX_0_DATA2_N

R4006
34

USB_CTL1

LVDS_TX_0_DATA3_P

54MHz_XTAL_P

R4007
34

R235
2.7K

R1

USB_OCD1

7:E7

D3.3V
RESET_OUTB

USB_MONCDR

R5

Place test points, resistors


near audio connector.
Connect the other side of
the resistor to GND as close
as possible to the ground
connection of the associated
audio connector.

LVDS_TX_0_DATA3_N

54MHz_XTAL_N

R4004
34

USB_DP2

C209

C208

C207

C203

C202

R210
120

V1

USB_DP1
USB_DM2
D3.3V

F1

OPT

C228
10uF

7:E7

R4000
34

4.7uF

0.1uF

0.1uF

0.1uF

R209
3.9K

0.1uF

U4

C201
100pF

F5

7:E7

LVDS_TX_0_DATA4_P

P24

USB_AVDD2P5

T3
R4

The INCM trace ends at the


same point where the connector
ground connects to the board ground
(thru-hole connector pin).

VCXO_PLL_AUDIO_TESTOUT

USB_AVDD1P2PLL

T4

USB_DM1

VCXO_AVDD1P2

USB_AVSS_3

USB_AVDD1P2

U3

Route INCM between associated


left and right signals of same channel

VCXO_AGND_3

USB_AVSS_2

USB_AVSS_5

R3

D4

7:D7

LVDS_TX_0_DATA4_N

USB_AVSS_4

T8

L200
BLM18PG121SN1D

D3

7:D7

LVDS_TX_1_CLK_P

R4005
34

A2.5V

E4

7:D7

LVDS_TX_1_CLK_N

R4001
34

A1.2V

E3

7:D7

LVDS_TX_1_DATA0_P

R4003
34

A3.3V

E2

7:D7

LVDS_TX_1_DATA0_N

AA23
VCXO_AGND_1

R6

E1

7:D7

LVDS_TX_1_DATA1_P

BSC_S_SCL

M24

3
JP203

D2

7:D7

LVDS_TX_1_DATA1_N

PM_OVERRIDE

M25

JP202

D1

AD27

VDAC_VREG

C3

LVDS_TX_AVSS_11

AH21

R242
0
OPT

C2

LVDS_TX_1_DATA2_P

C230
12pF

22
R212

4.7uF

R200
1.5K

MNT OUT FOR BCM


R201
1.5K

JP201

C200
4.7uF

JP200
1

B2

VDAC_AVSS_2

AE20
560AH22

R241
0
OPT

C213
0.01uF

B1

7:D7

0.1uF
C240

P200
TJC2508-4A

R220

B5

7:D7

LVDS_TX_1_DATA2_N

C237

R220 : BCM recommened resistor 562 ohm


C215
0.1uF

C5

4.7uF

D3.3V

D6

C218
0.1uF

0.1uF

0.1uF

C219

C214

4.7uF

0.1uF

LVDS_TX_0_CLK_P

LVDS_TX_AVSS_4

AG20
C212

POD2CHIP_MDI1

LVDS_TX_AVSS_3

AF20

BROAD BAND STUDIO

LVDS_TX_0_DATA4_N

D5

C241

L202
BLM18PG121SN1D

R237

R236

A28

POD2CHIP_MDI0

A2

0.1uF

A3.3V A1.2V A2.5V

LVDS_TX_0_DATA4_P

A1

C238

POD2CHIP_MCLKI

A3

7:D7

LVDS_TX_1_DATA3_P

LVDS_TX_0_DATA2_N

7:D7

LVDS_TX_1_DATA3_N

RMX0_SYNC

7:D7

LVDS_TX_1_DATA4_P

X903
54MHz

LVDS_TX_0_DATA2_P

B3

LVDS_TX_1_DATA4_N

RMX0_DATA

B6

C3012

LVDS_TX_0_DATA1_N

C6

L8014

RMX0_CLK

A4

1008LS-272XJLC 33pF

LVDS_TX_0_DATA1_P

R3027
604

A26

LVDS_TX_0_DATA0_N

PKT0_SYNC

0.1uF

B25

LVDS_TX_0_DATA0_P

PKT0_DATA

C3008

A25

PKT0_CLK

C236
0.1uF

B26

TU_SYNC

C239
0.1uF
C242
4.7uF
C295
0.1uF
C3005
4.7uF

C24

TU_SDATA

When usding Dip-type X-tal then series R = 22 ohm and CL = 12 pF

B4

D23

TU_SCLK

54MHz X-TAL

G_VID_INCM
3:T15
B_VID_INCM
3:T15

A2.5V

7
C217
10uF

THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.

BCM (BRAZIL VENUS)

JANG.J.H

BCM3556 AUD_IN/LVDS

2009.03.23

10

15

7
IC100
BCM3556
AE18

AB19
AB25

C122
4.7uF

AUD_LEFT0_P

EDSAFE_DVDD1P2

AUD_AVDD2P5_0

EDSAFE_IF_N

AUD_AVSS_0_1

EDSAFE_IF_P

AUD_AVSS_0_2

PLL_DS_AGND

AUD_AVSS_0_3

PLL_DS_AVDD1P2

AUD_AVSS_0_4

PLL_DS_TESTOUT

AUD_AVSS_0_5
AUD_RIGHT0_N

A2.5V

AUD_RIGHT0_P

AB18
BLM18PG121SN1D

C112
0.1uF

C111
0.1uF

AC17

L104 C120
1000pF
BLM18PG121SN1D
L105
C117
1000pF

C123
0.01uF

AB17
AD14
AD16
AB15
AC15
AD13

C118
0.01uF

AE13
AC13
AB14
AC14

14:A4

DSUB_R

AC12

14:A4

R_VID_INCM
DSUB_G

AD12

14:A3

G_VID_INCM
DSUB_B

AA14

14:A3

B_VID_INCM

AD11

14:A4
14:A3

AC11

91
R120

10pF

C103

C102

10pF
R119 75

10pF
R118 75

C101

COMP1_Pb_IN

R115

14:A6

14:A6 COMP1_VID_INCM

0.1uF

AD10
AC10

C128

0.1uF

AE9
AF9

C129

91

COMP1_Pr_IN

C127

0.1uF

AH9
AG9

C130

R129

14:A5

OPT

COMP1_Y_IN

10pF
R127 91

14:A6

75

AB12

C104

AB13

0.1uF

AG15

C131

0.1uF

AE15

C132

0.1uF

AF15
AH15

14:A5

COMP2_Y_IN

14:A5

COMP2_Pr_IN

14:A5

COMP2_Pb_IN

C133

0.1uF

AG16

C134

0.1uF

AF16

C135

0.1uF

R140 91

10pF

R138 91

OPT
C105

R135 91

AG14
TP101
TP102
TP103
TP104
TP105

TP106
TP107
R142

91

TP108

OPT
R143
91

TP109
TP110

OPT
R141
75

TP111
TP112

OPT
14:A6

TU_CVBS_IN

14:A5
14:A5

AV1_CVBS_IN
SIDE_CVBS_IN

14:A6

TU_CVBS_INCM

14:A5

AV1_CVBS_INCM

14:A5

SIDE_CVBS_INCM

AH17
AH16

14:A5 COMP2_VID_INCM

AE14
AF14
AH14
AH10
AG10
AE10
AE11
AF11
AH11
AH13
AE12
AF12

C110

TP113
0.1uF

AD9

C124

0.1uF

AG11

C125

0.1uF

AG12
AF13
AC9
AF10

A2.5V

A2.5V

AH12
AG13
AF17

R137
10K

14:A6

TU_SIF

R128
0

R4020
10K

0.1uF
C106

R3055
240

AG17
AD15
AE16

A1.2V

R139
12K

L106
BLM18PG121SN1D

AE17

C121
0.1uF

AA15

C140
4.7uF

AB16
AC16

0.1uF

12K
R4021

120
R3056

AG3
C4020

AF4

SD_V5_AVDD1P2

AUD_LEFT1_N

SD_V5_AVDD2P5

AUD_LEFT1_P
AUD_RIGHT1_N

SD_V5_AVSS
SD_V1_AVDD1P2

AUD_RIGHT1_P

SD_V1_AVDD2P5

AUD_AVDD2P5_1

SD_V1_AVSS_1

AUD_AVSS_1_1

SD_V1_AVSS_2

AUD_AVSS_1_2

SD_V2_AVDD1P2

AUD_AVSS_1_3

SD_V2_AVDD2P5

AUD_LEFT2_N

SD_V2_AVSS_1

AUD_LEFT2_P

SD_V2_AVSS_2

AUD_RIGHT2_N

SD_V2_AVSS_3

AUD_RIGHT2_P

SD_V3_AVDD1P2

AUD_AVDD2P5_2

SD_V3_AVDD2P5

AUD_AVSS_2_1

SD_V3_AVSS_1

AUD_AVSS_2_2

SD_V3_AVSS_2

AUD_SPDIF

SD_V4_AVDD1P2

SPDIF_AVDD2P5

SD_V4_AVDD2P5

SPDIF_AVSS

SD_V4_AVSS

SPDIF_IN_N

SD_R

SPDIF_IN_P

SD_G
HDMI_RX_0_CEC_DAT
HDMI_RX_0_HTPLG_IN

SD_B

HDMI_RX_0_HTPLG_OUT

SD_INCM_B
SD_Y1

HDMI_RX_0_DDC_SCL

SD_PR1

HDMI_RX_0_DDC_SDA

SD_PB1

HDMI_RX_0_RESREF

SD_INCM_COMP1

HDMI_RX_0_CLK_N
HDMI_RX_0_CLK_P

SD_Y2
SD_PR2

HDMI_RX_0_DATA0_N

SD_PB2

HDMI_RX_0_DATA0_P

SD_INCM_COMP2

HDMI_RX_0_DATA1_N

SD_Y3

HDMI_RX_0_DATA1_P

SD_PR3

HDMI_RX_0_DATA2_N

SD_PB3

HDMI_RX_0_DATA2_P

SD_INCM_COMP3

HDMI_RX_0_VDD3P3

SD_L1

HDMI_RX_0_VDD1P2

SD_C1

HDMI_RX_0_VDD2P5

SD_INCM_LC1

HDMI_RX_0_AVSS_1

SD_L2

HDMI_RX_0_AVSS_2

SD_C2

HDMI_RX_0_AVSS_3

SD_INCM_LC2

HDMI_RX_0_AVSS_4
HDMI_RX_0_AVSS_5

SD_L3

HDMI_RX_0_AVSS_6

SD_C3
SD_INCM_LC3

HDMI_RX_0_PLL_AVSS

SD_CVBS1

HDMI_RX_0_PLL_DVDD1P2

SD_CVBS2

HDMI_RX_0_PLL_DVSS

AA20
AB21

HDMI_RX_1_CEC_DAT

SD_INCM_CVBS2 HDMI_RX_1_HTPLG_IN
SD_INCM_CVBS3 HDMI_RX_1_HTPLG_OUT

SD_INCM_CVBS4

HDMI_RX_1_DDC_SCL

SD_SIF1

HDMI_RX_1_DDC_SDA

SD_INCM_SIF1

HDMI_RX_1_RESREF

SD_FB

HDMI_RX_1_CLK_N

SD_FS

HDMI_RX_1_CLK_P

SD_FS2

HDMI_RX_1_DATA0_N
HDMI_RX_1_DATA0_P
PLL_VAFE_AVDD1P2
PLL_VAFE_AVSS HDMI_RX_1_DATA1_N
HDMI_RX_1_DATA1_P
PLL_VAFE_TESTOUT
RGB_HSYNC
HDMI_RX_1_DATA2_N
HDMI_RX_1_DATA2_P
HDMI_RX_1_VDD3P3
HDMI_RX_1_VDD1P2
HDMI_RX_1_AVSS_1

14:A3

RGB_HSYNC

HDMI_RX_1_AVSS_2

14:A3

RGB_VSYNC

HDMI_RX_1_AVSS_3
HDMI_RX_1_AVSS_4
HDMI_RX_1_AVSS_5
HDMI_RX_1_AVSS_6
HDMI_RX_1_AVSS_7
HDMI_RX_1_AVSS_8
HDMI_RX_1_AVSS_9
HDMI_RX_1_PLL_AVSS
HDMI_RX_1_PLL_DVDD1P2
HDMI_RX_1_PLL_DVSS

C147
0.01uF

C155
0.1uF

C162
10uF

C148
0.01uF

C156
0.1uF

C163
10uF

AC22
AC23
AD23
AH25

R168

AG25
AH23
AG23
AG24

0
OPT

R166

0
OPT

R167

AH24

0
OPT

AE22
AB20
AC21
AE23
AF21

R169

AE21

0
OPT

R172

AF22
AG22

0
OPT

AD21
AC20

C149
0.01uF

AD22

C164
10uF

C157
0.1uF

SPDIF_OUT14:A3

AC6
AE4

C150
0.1uF

AF3

+5.0V

AH1

R2036
1K

HDMI_HPD_IN_5MA
C

AA6
AA5

R188

HDMI_HPD_IN_5MA

10K

Y6
499

Q906
ISA1530AC1

G5

HDMI_HPD_IN

9:G4;9:I3

A2.5V

AB3
AC4

A2.5V

A2.5V

AH2

R157

R158

R152

AC1

HDMI_SCL

2:AA19

HDMI_SDA

2:AA19

HDMI0_RXC-_BCM

AC2
AD1
AD2
AE1
AE2
AF1
AF2
AD3

C3006
0.1uF
16V

2:AA18

HDMI0_RXC+_BCM

2:AB18

HDMI0_RX0-_BCM

2:AB18

HDMI0_RX0+_BCM

2:AB18

HDMI0_RX1-_BCM

2:AC18

HDMI0_RX1+_BCM

2:AC18

HDMI0_RX2-_BCM

2:AC18

HDMI0_RX2+_BCM

2:AD18

A3.3V

BLM18PG121SN1D
L109
A1.2V

A2.5V

AE3
AC3
AD4

C145
4.7uF

AB5

C160
0.1uF

C153
0.1uF

BLM18PG121SN1D
L107

AB6
AG2
AB4
AA7
Y8

C151
0.01uF

C158
1000pF

AC5

C165
10uF

W8

AA3

SD_INCM_CVBS1

RGB_VSYNC

OPT

AF23

SD_CVBS3
SD_CVBS4

3:D3
A2.5V

AH26

AG1

SD_INCM_G

3:D3

BCM_I2S_WORD_CLK

SD_INCM_R

HDMI_RX_1_VDD2P5

CONNECT NEAR BCM CHIP

OPT
R165

270

C119
0.1uF

AD24

AUD_LEFT0_N

EDSAFE_AVDD2P5

AG26

R3041

BLM18PG121SN1D
A1.2V

AE27

C144
0.1uF

EDSAFE_AVSS_5

AG18

3:D3

BCM_I2S_DATA_OUT

470

C116
4.7uF

I2S_LR_OUT

OPT
R164

OPT

AE28
C113
0.1uF
L103

A1.2V

I2S_LR_IN

EDSAFE_AVSS_4

BCM_I2S_BIT_CLK
0

OPT

AE26

EDSAFE_AVSS_3

AH19
AD18

0
OPT

R163

R3042

AG27

I2S_DATA_OUT

AD17

V4
U6
V5

10K

AF28

EDSAFE_AVSS_2

R162

AF18

10K

AF27

I2S_DATA_IN

10K

A1.2V
BLM18PG121SN1D
L102

I2S_CLK_OUT

EDSAFE_AVSS_1

R146

AF26

I2S_CLK_IN

DS_AGCT_CTL

R2039

AB22

A2.5V

DS_AGCI_CTL

R2038

AA21

R2037
OPT
10K

AH28

R2035
0

AG28

D3.3V

V3
W4

499

R153

W2
W3
Y1
Y2

A3.3V

AA2
AA1
AB1

BLM18PG121SN1D
L110

Y3

A1.2V

AB2

A2.5V

Y4
W5
W1
U5
W6

C146
4.7uF

C154
0.1uF

C161
0.1uF
BLM18PG121SN1D
L108

U7
V7
W7
U8
V8
Y5
V6
AA4
Y7

C159
1000pF

C152
0.01uF

C166
10uF

1
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.

BRAZIL VENUS

JANG.J.H.

BCM3556 VIDEO IN

2009.03.23

11

15

14:E5

4:C5

ERROR_OUT

LED_POWER_ON

14:E6

14:E5

LED_WARM_STBY

14:E7

UCOM_SDA_3.3V

UCOM_SCL_3.3V

R435

R439
0

R435 : READY FO 1.2V BCM ENABLE

OPT

OPT

OPT

100

4.7K

R444

R442

P5.3

P5.2

P5.0

P5.1

34

36

35

C412
0.1uF

P6.4

P6.3

P6.2

P6.1

P6.0/CLKO1

+5.0V

OPT

22

21

20

12
HSDA2/P7.4

OPT

R428

100
OPT

100

9:C1

9:G7;9:I3;3:C5

EDID_WP

14:A4

C
GND

Q402
RT1N141C-T112-1

+3.3V_ST
OPT
R459
4.7K

4.7K
R455
4.7K
OPT

GND
R462
100
KEY2

14:E6

KEY1

14:E6

GND

R445

R446
OPT

1K
R453

22

GND
SDA

OPT

100

R443

22

22

SCL

READY FO 1.2V BCM ENABLE

OPC_EN

AMP_MUTE

VSS

R436

GND

C414
0.1uF
16V

C413
0.1uF

GND

7:I5

R483
0

A2

C409
22pF
50V

3:E3

R486
0

R434

OPT

VCC

C408
22pF
50V

SCL2_3.3V

GND

A1

C406
0.1uF
WP 16V

+3.3V_ST

9:B5;9:I4

3
1

VCC

SDA2_3.3V

R487
100K
OPT

9:B5;9:I4

NCP803SN293
RESET

4.7K
R496

A0

R413

R449
R450

OPT
R452
47K

R441

OPT

IC1003

4.7K
R495

R490
0

E
R480
2.2K
OPT

2SC3052

OPT
R477
6.8K

1K
Q404

4.7K

P6.6

OPT

X401
24MHz
R415

OPT
B

1K

GND

4.7K

R492
0

37

P6.5

19

23

24LC16BT-I/SN

R432
47K

15K

VDD

11

C
Q405
2SC3052

38

ISCL/P7.5

18

22

R447

9:A7

R456
100

R491
5.1K

OPT

OPT
B

R475

R484
30K

R482
30K
OPT

POWER_DET

OPT
R479

R476

9:A7;I4

100

R425

17

P6.7

16

25
24

R429
OPT

4:C7;14:E5

RL_ON

100

POWER_DET

10

15K
OPT
R481
R478
10K

100

C415
0.1uF
16V

22

R431

AMP_RST

ISDA/P3.4/T0

+3.3V_ST

IC405

39

P7.2/HCLAMP

+5.0V
+12V

40

26

GND

R485
10K

41

27

+5V_ST +24V

+3.3V_ST

42

44
7

P3.2/INT0
P3.3/INT1

4:C5

OPT

P7.1/VBLANK

OPT

R418
4.7K

POWER DETECT

MTV416GMF

VSS

P4.1/AD1

IC406

R467

4:C5

INV_ON/OFF

100

RESET

HSDA1/P3.1/TXD

R404
220
UCOM_TX

28

22

OPT

14:I1

29

P7.0/HBLANK

R424

R423

UCOM_RX

P5.7/CLKO2

R468

FLASH_WP_1

R472
4.7K

4.7K

30

4:H1

PANEL_CTL

68K

22

R421

P4.0/AD0

R405
220

R420

P5.6

15

IR

31

X1

DDC_SDA

14

9:G7;14:A4
14:A3;14:E6

32

100

6.8K

P4.3/AD3

DDC_SCL

9:G7;14:A4

R466 OPT 100

R460

HSCL1/P3.0/RXD

R465

P5.5

13

R494
4.7K

R499
4.7K

4.7K

RST
22

R417

P5.4

X2

OPT

OPT

R402
GND

14:H2

P1.7/SOGI

33

R461

C411
100uF
16V

16V

OPT

4.7K
R427

HSYNC/P1.5

+3.3V_ST

R406

C410
0.1uF

GND

VSYNC/P1.6
R416

+3.3V_ST

R430
100

OPT
M5V_ON
R403

R440

+3.3V_ST

GND

GND

R474

GND

C403
0.1uF
16V

R401
1K

GND

P4.2/AD2

P1.0/ET2

GND

2
C402
0.1uF
16V

100

P1.4/DA3

C407
Q401
OPT
OPT
2SC3875S(ALY)

43

HSCL2/P7.3

R488
33K

+3.3V_ST

R414
10K

R407
47K

KIA7029AF
I

R471

R489
33K

P1.1/DA0

IC402

100

+3.3V_ST

+3.3V_ST

100

HDMI_CEC

R464

2K

D3.3V

R470

2K

P1.2/DA1

R454
R451

P1.3/DA2

2:AD26

+3.3V_ST

1
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.

BCM (BRAZIL VENUS)

LIM.K.R

MICOM

2009.03.23

12

15

D1.2V

C243
0.1uF

C249
4.7uF

C250
1000pF

C253
10uF

C252
0.1uF

C251
0.01uF

C254
10uF

C287
33uF

C286
33uF

IC100
BCM3556

6
D1.2V

D1.2V

IC100
BCM3556

AD5
AD6
J7
K7

H8
C244
1000pF

C246
0.01uF

C256
0.1uF

C262
0.01uF

C259
1000pF

C258
4.7uF

C265
0.1uF

C266
4.7uF

C288
1000pF

C290
0.01uF

J8
K8
L8
M8
N8
P8
R8
AA8

D3.3V

H9
H10
H11
H12

C245
4.7uF

C255
1000pF

C257
0.01uF

C261
0.1uF

C263
4.7uF

C264
1000pF

C267
0.01uF

C289
0.1uF

C291
10uF

H13
H14
H15
H16
H17
H18
H19

D3.3V

H21
J21
K21
L21
M21

C216
0.1uF

C268
1000pF

C269
0.01uF

C270
0.1uF

C271
4.7uF

C292
1000pF

C293
0.01uF

C294
0.1uF

N21
P21
R21
T21
A3.3V

U21
V21
W21

R205
20

D1.8V

Y21

VDDC_1

L7

VDDC_2

M7

VDDC_3

AB7

VDDC_4

AC7

VDDC_5

G8

VDDC_6

D9

VDDC_7

AA9

VDDC_8

G10

VDDC_9

A11

VDDC_10

L11

VDDC_11

M11

VDDC_12

N11

VDDC_13

P11

VDDC_14

R11

VDDC_15

T11

VDDC_16

U11

VDDC_17

V11

VDDC_18

D12

VDDC_19

G12

VDDC_20

L12

VDDC_21

M12

VDDC_22

N12

VDDC_23

P12

VDDC_24

R12

VDDC_25

T12

VDDC_26

U12

VDDC_27

V12

VDDC_28

L13

VDDC_29

M13

VDDC_30

N13

VDDC_31

P13

VDDC_32

R13

VDDC_33

T13
U13

V13

AH27
AGC_VDDO

D3.3V
C275
0.1uF

C272
0.1uF

C247
0.1uF

C278
4.7uF

C276
0.1uF

C280
4.7uF

C297
4.7uF

C2003
0.1uF

C2004
33uF

L14
M14

AA12
AA13
AA18
AA19
E28
L28
U28
AB28

D1.8V

VDDO_1

N14

VDDO_2

P14

VDDO_3

R14

VDDO_4

T14

VDDO_5

U14

VDDO_6

V14

VDDO_7

L15

VDDO_8

M15

D1.8V

N15
P15

A9
G9
C248
1000pF

C281
1000pF

C282
1000pF

C283
1000pF

C284
0.01uF

C285
0.01uF

C2005
0.01uF

C2006
0.01uF

G11
G13
A14
G15

G14

G17
A19
G19

DDRV_1

R15

DDRV_2

T15

DDRV_3

U15

DDRV_4

V15

DDRV_5

A16

DDRV_6

G16

DDRV_7

L16

DDRV_8

M16

DDRV_9

N16

P16
DVSS_1

DVSS_62

DVSS_2

DVSS_63

DVSS_3

DVSS_64

DVSS_4

DVSS_65

DVSS_5

DVSS_66

DVSS_6

DVSS_67

DVSS_7

DVSS_68

DVSS_8

DVSS_69

DVSS_9

DVSS_70

DVSS_10

DVSS_71

DVSS_11

DVSS_72

DVSS_12

DVSS_73

DVSS_13

DVSS_74

DVSS_14

DVSS_75

DVSS_15

DVSS_76

DVSS_16

DVSS_77

DVSS_17

DVSS_78

DVSS_18

DVSS_79

DVSS_19

DVSS_80

DVSS_20

DVSS_81

DVSS_21

DVSS_82

DVSS_22

DVSS_83

DVSS_23

DVSS_84

DVSS_24

DVSS_85

DVSS_25

DVSS_86

DVSS_26

DVSS_87

DVSS_27

DVSS_88

DVSS_28

DVSS_89

DVSS_29

DVSS_90

DVSS_30

DVSS_91

DVSS_31

DVSS_92

DVSS_32

DVSS_93

DVSS_33

DVSS_94

DVSS_34

DVSS_95

DVSS_35

DVSS_96

DVSS_36

DVSS_97

DVSS_37

DVSS_98

DVSS_38

DVSS_99

DVSS_39

DVSS_100

DVSS_40

DVSS_101

DVSS_41

DVSS_102

DVSS_42

DVSS_103

DVSS_43

DVSS_104

DVSS_44

DVSS_105

DVSS_45

DVSS_106

DVSS_46

DVSS_107

DVSS_47

DVSS_108

DVSS_48

DVSS_109

DVSS_49

DVSS_110

DVSS_50

DVSS_111

DVSS_51

DVSS_112

DVSS_52

DVSS_113

DVSS_53

DVSS_114

DVSS_54

DVSS_115

DVSS_55

DVSS_116

DVSS_56

DVSS_117

R16
T16
U16
V16
AA16
D17
L17
M17
N17
P17
R17
T17
U17
V17
AA17
AC19
G18
L18
M18
N18
P18
R18
T18
U18
V18
D20
G20
H20
A21
E21
F21
G21
E22
F22
G22
H22
J22
K22
L22
M22
N22
P22
R22
T22
U22
V22
W22
Y22
AA22
W23
AB23
F28
M28
T28
AC28

DVSS_57
DVSS_58
DVSS_59
DVSS_60
DVSS_61

D1.8V

C365
0.1uF
16V

C364
0.1uF
16V

C363
0.1uF
16V

C357
10uF
10V

C356
0.1uF
16V

C348
0.1uF
16V

C320
0.1uF
16V

C319
0.1uF
16V

C318
0.1uF
16V

C304
0.1uF
16V

1
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.

BRAZIL DVR DV

JANG.J.H

BCM3549 POWER

2009.03.23

13

15

CONTROL IR & LED

USB JACK & USB +5V Current Protection

D3.3V

SDA

GND

D701

CDS3C05HDMI1

SCL

CDS3C05HDMI1

VOUT
UCOM_SCL_3.3V

ILIMIT

D702

C716
0.1uF
16V

GND

12:F6
FAULT/

R716

USB_CTL1
10:D5

R717
KEY2

ZD701

C704
0.1uF

C706
0.1uF

ZD703

C708
0.1uF

IR

11

12

L702
CB3216PA501E
C709
0.1uF
16V

13
GND

LED_WARM_STBY
OPT

USB_DM2 10:D4

USB_DP2 10:D4

C714
100uF

+3.3V_ST

C701
0.1uF

R711
0

+3.3V_ST

3.3V_ST

POWER_ON

OPT

L708
BLM18PG121SN1D

C703
1000pF
50V

OPT

OPT

Not enough space

0
R708

0
R714

RL_ON
C

Q701
2SC3052

LED_POWER_ON
R713
0

R709
4.7K

C715
100uF
16V

D703
D704
CDS3C05GTA
CDS3C05GTA
5.6V
5.6V
OPT
OPT

ZD702

C702
100pF

R707
10K

10

GND

Make this trace minimum 12 mil

KJA-UB-4-0004
JK702

R712
0

Q702
2SC3052

C710
0.1uF
16V

IR
12:D4;A3

L701
BG2012B080TF

USB_POWER_OUT_2

+3.3V_ST

WARM_ST

OPT

47

+5V_ST

C
9

USB_OCD1 10:D4

12:H3

GND

L705
CB3216PA501E

5V_ST

L704
BG2012B080TF

L703
BG2012B080TF

USB DOWN STREAM

KEY2

12:H3

OPT

KEY1

R715
120K

KEY1

R710
10K

L710
USB_+5V

ENABLE

130
4

L709
USB_5VST

VIN

12:F6

UCOM_SDA_3.3V

OPT
C707
1000pF
50V

OPT
C705
1000pF
50V

R721
2.7K

R718
2.7K

IC701
MIC2009YM6-TR

USB_POWER_OUT_2

+5.0V
MLB-201209-0120P-N2

P701
12507WS-12L

MLB-201209-0120P-N2

+5V_ST

BCM Tolerance

4
CB3216PA501E

D3.3V

Blue Tooth

RS232_SWITCHING

L707
11
JP712
10

R702
0

+5V_ST

RS232_BYPASS

R701
0

Y1

BCM_RX
9:G6
Y0
UCOM_RX
12:D4

16

15

8
L706
MLB-201209-0120P-N2

VDD

Z0

INH

14

13

12

11

10

X1

0.1uF

C712
47uF
16V

RS232C_TxD

VSS

USB_DP1

10:D4

R720
0
BLUETOOTH_RESET

4
9:G6
3

+5.0V

X0
UCOM_TX

10:D4

JP715

A3

JP716
R719
0

12:D4

R706
4.7K

R_RS232_SWITCHING
VEE

USB_DM1

JP713
D706
CDS3C05GTA
5.6V
OPT

RS232_BYPASS
R703
0

BCM_TX

D705
CDS3C05GTA
5.6V
OPT

R723
27
C711

A3
RS232C_RxD

16V
Z1

R722
27

JP711

R705
0

C713
10uF
16V

IC702
MC14053BDR2G
0ISTL00024A

VREG_CTRL

R704
100K

12507WR-10L
P702

1
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.

BRAZIL VENUS

2009.03.23

DO.J.G
CONTROL IR/BT/USB

14

15

4
5

LGIT

6
TU102

TDYR-H071F

8
9
10
11
12
13
14
15
16
17
18
19
20
21

22
23

B0[+5V]
VTU
RF_AGC

R50010 LGIT

16V
22uF
C5000
LGIT

C5002
0.1uF
50V
LGIT

TU101
VA1G5BF8005

NC_1

SIF

VIDEO_OUT

NC_2

NC_3
AIF

6
R50000

B2[2.5V]

7
LGIT
8

B3[3.3V]

B4[1.2V]

10

RESET[SYRSTN]

11

SDA

12

SCL

13

RSEORF

14

SBYTE

15

SPBVAL

16

SRDT

17

SRCK

24
SHIELD

18
C5001
22pF
50V

C5003
22pF
50V

LGIT

LGIT

R5015
4.7K

RF_SWITCH

R5014

3:T24

GAIN_SWITCH

GAIN_SWITCH

3:T24

TU_+5.0V

R5013
C5007
2200pF
50V

R50020 LGIT

B1[+5V]

RF_SWITCH

0
C5005
2200pF
50V

RF-GAIN_SW

L5005

RF_SW
GAIN_SW

D2.5V

BB

C5012

C5014C5016

0.01uF

22uF 0.1uF
Place close to Pin

B1
D3.3V

L5002

AFT

SIF

R5004

L5004
C5010
22uF

VIDEO

C5011
0.1uF
C5015
22uF

B2

C5017
0.1uF
A1[RD]

D1.2V

B3

A2[GN]
L5006

B4
RESET

22

R5005

SDA

22

R5006

22

R5007

SCL

C5018

TUNER_RESETb 3:T26

22uF

SDA0_3.3V

3:T26

SCL0_3.3V

3:T26

C5020
0.1uF

22

SPBVAL

R5008

TU_SYNC

22

R5012
R5009

SRCK

22

R5010

A1[RD]
A2[GN]

3:T27

TU_+5.0V

SRDT

D3.3V

SAM2333
LD5001
R5023
1K

RSEORF
SBYTE

330

R5025

LD5000
SAM2333

TU_SDATA

3:T27

TU_SCLK

3:T27

L5007

19
SHIELD
SHARP

R5022
0

R5024
470

C5005-*1
0.1uF
50V
LGIT

CTR

R5020
12K

L5000

LGIT
1

OPT

D3.3V

TU_+5.0V

C5021
0.01uF

TU_SIF

OPT
2SA1530A-T112-1R
Q5000

C5004
91pF
50V OPT

OPT

R5018
56
R5019
56

16V
OPT

R5003
82

L5001
OPT

FI-C3216-103KJT

R5021
10K

10uF C5009

3:T25

C5019
0.01uF

TU_CVBS_IN

3:T25

GND

3
+5V

GND2

L5009
MLB-201209-0120P-N2

D3.3V

IC5001
KIA78R05F

C5031
0.1uF
16V

OPT
C5033
4.7uF
10V

C5035
100uF
16V

5
L5010
MLB-201209-0120P-N2

GND1

4
NC

VC

VIN

3
VOUT

R5026
100

TU_+5.0V
2

+12V
C5032
0.1uF
16V

IC5002

AS7809DTRE1
L5008
MLB-201209-0120P-N2
INPUT

C5034
4.7uF
10V
OPT

C5036
100uF
16V

OUTPUT

2
GND
C5022
0.1uF
16V

C5023
100uF
16V

C5024
0.1uF
50V

C5025
100uF
16V

C5026
0.33uF
16V

C5027
0.1uF
50V

C5028
47uF
16V

C5029
0.1uF
50V

C5030
0.01uF
50V

1
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.

BRAZIL VENUS

2009.03.23

DO.J.G
TUNER

15

15

Block Diagram
Overall Block Diagram
for Brazil DTV (LH70)

TU_SCLK, TU_SDATA, TU_SYNC

VA1G5BF8005

Qimonda/Hynix
TU_SIF
SDA0/SCL0_3.3V
LVDS
RF_Switch, Gain_Switch

FRC IC
(MST7323S)

CVBS, L/R, AV_DET

FRC Block

AV1
AV2

DDR2(256Mbit)

TU_CVBS_IN

(FHD, 120Hz)

SIDE_CVBS, SIDE_L/R, SIDE_DET


X-tal
12MHz

Y Pb Pr, L/R, DET

Component 1

Y Pb Pr, L/R, DET

Component 2

DDR_Data[0:15], DQS, DM
RGB/H/V

DDR2 (1Gbit)

D-sub RGB

Elpida/Hynix

Addr.[0:13], ctrl. data

Audio L/R

Audio L/R (for RGB)


JACK BACK
at REAR

LCD Module

BCM3556

HDMI 1

(Brazil)

3x1
HDMI Switch

HDMI 2
HDMI 3

DDR2 (1Gbit)
Elpida/Hynix

Data[16:31]

Data [0 7]
CS ,RE,WE
SPDIF

Digital Audio (Optic)

RS-232C (Ctrl./SVC)

RX/TX

RX/TX

MAX3232

Bluetooth Module
USB

NAND Flash
(512Mbit)

+5V

Reset Switch

Copyright 2009 LG Electronics. Inc. All right reserved.


Only for training and service purposes

DP1/DM1

USB_DM1

DP2/DM2

USB_DP1
USB_DM2

O.C. Protector

USB_DP2
+5V

Reset IC

X-tal

I2S

SCL, SDA_3.3V

SCL, SDA_3.3V

54MHz

CLK,TDI,TDO,MS,RST

Digital AMP
NTP3100L

NVRAM
MICOM
(MTV416GMF)
JTAG

X-tal
24MHz

LGE Internal Use Only

I2C
I2C &
& RS232
RS232 Communication
Communication

22 ohm

22 ohm
22 ohm

SCL0
SDA0

+3.3V_HDMI

2.7k ohm

4.7k ohm

D3.3V

4.7k ohm

4.7k ohm

VA1G5BF8005

P
7
0
1

22 ohm

47PF

Main B/D

D3.3V

2.7k ohm

Sub B/D

4.7k ohm

Block Diagram

SCL1

22 ohm

0 ohm

SDA1

22 ohm

0 ohm

HDMI
S/W

47PF

100 ohm

NTP3100L

100 ohm

33PF
33PF

MAX3232

4.7k ohm

22 ohm

22 ohm

SDA3

22 ohm

22 ohm

MICOM

100 ohm
100 ohm
D3.3V

4.7k ohm

RS232C_TxD

P
7
0
2

SCL3

SCL2
SDA2

Copyright 2009 LG Electronics. Inc. All right reserved.


Only for training and service purposes

22 ohm
22 ohm

4.7k ohm

RS232C_RxD

BCM3556

4.7k ohm

4.7k ohm

+5V_ST

4.7k ohm

D3.3V

100 ohm

MST7323

100 ohm

LGE Internal Use Only

Block Diagram

I2C channel [LH70]


CH0 (+3.3V)

CH0
TUNER
TUNER 11
0xC2
0xC2
Demod(0x30)
Demod(0x30)
QPSK(0x32)
QPSK(0x32)

CH1

CH1 (+ 3.3V)
AMP
AMP
NTP3100L
NTP3100L
0x54
0x54

HDMI
HDMI SW
SW
TDA9996
TDA9996

BCM3556
BCM3556

CH2 (+3.3V)

CH2
EEPROM
EEPROM
AT24C512
AT24C512
0xA6
0xA6

Micom
Micom
MTV416
MTV416
0x50
0x50

CH3 (+3.3V)

CH3
FRC
FRC
MST7323
MST7323

Copyright 2009 LG Electronics. Inc. All right reserved.


Only for training and service purposes

LGE Internal Use Only

Block Diagram

D1.2V, D2.5V, +3.3V, +5.0V_ST


SPDIF , EDID_WP .
SCL0_3.3V, SDA0_3.3V, DDC_SCL, DDC_SDA

Jack
Board

MAIN
Board

CVBS, SIF, AV, RGB ,COMPONENT, R/L,

TU_SCLK, TU_DATA, TU_SYNK..

< Signal Interface >

Copyright 2009 LG Electronics. Inc. All right reserved.


Only for training and service purposes

LGE Internal Use Only

1. Power-Up Boot Fail Trouble Shooting


Overall Block Diagram
for Brazil DTV (LH70)

TU_SCLK, TU_SDATA, TU_SYNC

VA1G5BF8005

Qimonda/Hynix
TU_SIF
SDA0/SCL0_3.3V
LVDS
RF_Switch, Gain_Switch

FRC IC
(MST7323S)

CVBS, L/R, AV_DET

FRC Block

AV1
AV2

DDR2(256Mbit)

TU_CVBS_IN

(FHD, 120Hz)

SIDE_CVBS, SIDE_L/R, SIDE_DET


X-tal
12MHz

Y Pb Pr, L/R, DET

Component 1

Y Pb Pr, L/R, DET

Component 2

DDR_Data[0:15], DQS, DM
RGB/H/V

DDR2 (1Gbit)

D-sub RGB

Elpida/Hynix

Addr.[0:13], ctrl. data

Audio L/R

Audio L/R (for RGB)


JACK BACK
at REAR

LCD Module

BCM3556

HDMI 1

(Brazil)

3x1
HDMI Switch

HDMI 2
HDMI 3

DDR2 (1Gbit)
Elpida/Hynix

Data[16:31]

Data [0 7]
CS ,RE,WE
SPDIF

Digital Audio (Optic)

RS-232C (Ctrl./SVC)

RX/TX

RX/TX

MAX3232

Bluetooth Module
USB

NAND Flash
(512Mbit)

+5V

Reset Switch

Copyright 2009 LG Electronics. Inc. All right reserved.


Only for training and service purposes

DP1/DM1

USB_DM1

DP2/DM2

USB_DP1
USB_DM2

O.C. Protector

USB_DP2
+5V

Reset IC

X-tal

I2S

SCL, SDA_3.3V

SCL, SDA_3.3V

54MHz

CLK,TDI,TDO,MS,RST

Digital AMP
NTP3100L

NVRAM
MICOM
(MTV416GMF)
JTAG

X-tal
24MHz

LGE Internal Use Only

1. Power-Up Boot Fail Trouble Shooting


Check P801 All Voltage Level
(24V, 12V, 5V_ST)

Y
Check Power connector

Replace Power board

Y
Check All Voltage Level
at L805/L807/L808

Replace one of L805/L807/L808


& Recheck

Replace one of
IC809/Q812/L828/L829/L830/L822
& Recheck

Replace one of IC803/L824/L827


& Recheck

Y
Check Voltage Level 3.3V at L830
Y
Check Voltage Level 2.5V at L827

Check Micom IC406


Redownload or replace

Y
Check Voltage Level 1.8V
at IC802 #2 pin or L815

Replace one of IC802/IC805/L815


& Recheck

Replace one of
IC804/Q809/L811/L817/L821
& Recheck

Y
Check Voltage Level 1.2V at L821
Y
Check X903 Clock 54MHz

Replace X903

Y
Check signal transition
at IC101 #9 pin

Maybe BCM3556 has troubles

Y
Replace IC101 Flash Memory

Copyright 2009 LG Electronics. Inc. All right reserved.


Only for training and service purposes

LGE Internal Use Only

2. No OSD Trouble Shooting


Overall Block Diagram
for Brazil DTV (LH70)

TU_SCLK, TU_SDATA, TU_SYNC

VA1G5BF8005

Qimonda/Hynix
TU_SIF
SDA0/SCL0_3.3V
LVDS
RF_Switch, Gain_Switch

FRC IC
(MST7323S)

CVBS, L/R, AV_DET

FRC Block

AV1
AV2

DDR2(256Mbit)

TU_CVBS_IN

(FHD, 120Hz)

SIDE_CVBS, SIDE_L/R, SIDE_DET


X-tal
12MHz

Y Pb Pr, L/R, DET

Component 1

Y Pb Pr, L/R, DET

Component 2

DDR_Data[0:15], DQS, DM
RGB/H/V

DDR2 (1Gbit)

D-sub RGB

Elpida/Hynix

Addr.[0:13], ctrl. data

Audio L/R

Audio L/R (for RGB)


JACK BACK
at REAR

LCD Module

BCM3556

HDMI 1

(Brazil)

3x1
HDMI Switch

HDMI 2
HDMI 3

DDR2 (1Gbit)
Elpida/Hynix

Data[16:31]

Data [0 7]
CS ,RE,WE
SPDIF

Digital Audio (Optic)

RS-232C (Ctrl./SVC)

RX/TX

RX/TX

MAX3232

Bluetooth Module
USB

NAND Flash
(512Mbit)

+5V

Reset Switch

Copyright 2009 LG Electronics. Inc. All right reserved.


Only for training and service purposes

DP1/DM1

USB_DM1

DP2/DM2

USB_DP1
USB_DM2

O.C. Protector

USB_DP2
+5V

Reset IC

X-tal

I2S

SCL, SDA_3.3V

SCL, SDA_3.3V

54MHz

CLK,TDI,TDO,MS,RST

Digital AMP
NTP3100L

NVRAM
MICOM
(MTV416GMF)
JTAG

X-tal
24MHz

LGE Internal Use Only

2. No OSD Trouble Shooting


Check 12V Voltage Level
at P801 #13 Pin

Y
Check Power connector

Replace Power board

Y
Check 12V Voltage Level
at L801

Replace one of L801/Q804


& Recheck

Replace one of
Q802/Q803/Q804/L801
& Recheck

Replace one of IC803/L824/L827


& Recheck

Replace one of IC802/IC805/L815


& Recheck

Replace IC807
& Recheck

Maybe BCM3556(IC100) or
7329A(IC901)
has troubles

Y
Check 12V Voltage Level at L909
Y
Check Voltage Level 2.5V at L827
Y
Check Voltage Level 1.8V
at IC802 #2 pin or L815
Y
Check Voltage Level 1.26V
at IC807 #6 pin
Y
Check P903
#16(TXAC-), #17(TXAC+),
#32(TXBC-), #33(TXBC+)
Y
Check LVDS Cable

Replace Cable

Y
Check Voltage LCD Module

Copyright 2009 LG Electronics. Inc. All right reserved.


Only for training and service purposes

LGE Internal Use Only

3. Digital TV Video Trouble Shooting


Overall Block Diagram
for Brazil DTV (LH70)

TU_SCLK, TU_SDATA, TU_SYNC

VA1G5BF8005

Qimonda/Hynix

TU_SIF
SDA0/SCL0_3.3V
LVDS
RF_Switch, Gain_Switch

FRC IC
(MST7323S)

CVBS, L/R, AV_DET

FRC Block

AV1
AV2

DDR2(256Mbit)

TU_CVBS_IN

(FHD, 120Hz)

SIDE_CVBS, SIDE_L/R, SIDE_DET


X-tal
12MHz

Y Pb Pr, L/R, DET

Component 1

Y Pb Pr, L/R, DET

Component 2

DDR_Data[0:15], DQS, DM
RGB/H/V

DDR2 (1Gbit)

D-sub RGB

Elpida/Hynix

Addr.[0:13], ctrl. data

Audio L/R

Audio L/R (for RGB)


JACK BACK
at REAR

LCD Module

BCM3556

HDMI 1

(Brazil)

3x1
HDMI Switch

HDMI 2
HDMI 3

DDR2 (1Gbit)
Elpida/Hynix

Data[16:31]

Data [0 7]
CS ,RE,WE
SPDIF

Digital Audio (Optic)

RS-232C (Ctrl./SVC)

RX/TX

RX/TX

MAX3232

Bluetooth Module
USB

NAND Flash
(512Mbit)

+5V

Reset Switch

Copyright 2009 LG Electronics. Inc. All right reserved.


Only for training and service purposes

DP1/DM1

USB_DM1

DP2/DM2

USB_DP1
USB_DM2

O.C. Protector

USB_DP2
+5V

Reset IC

X-tal

I2S

SCL, SDA_3.3V

SCL, SDA_3.3V

54MHz

CLK,TDI,TDO,MS,RST

Digital AMP
NTP3100L

NVRAM
MICOM
(MTV416GMF)
JTAG

X-tal
24MHz

LGE Internal Use Only

3. Digital TV Video Trouble Shooting

Check RF Cable
Y
Check Tuner(TU101) Power
(5.0V, 2.5V, 3.3V, 1.2V)

Replace one of IC101, IC102 at


Jack Board or IC803/ IQ812/ C804/
Q809/+5V_ST and +12V of P801 at
Main Board& Recheck

Y
Check TP Clock, Data, Sync
R107, R108, R109

Maybe Tuner(TU101) has problems

Y
Check cable between P203 at Jack
Board and P701 at Main Baord

Maybe Cable Pin has problems

Y
Maybe BCM3556(IC100)
has problems

Copyright 2009 LG Electronics. Inc. All right reserved.


Only for training and service purposes

LGE Internal Use Only

4. Analog TV Video Trouble Shooting


Overall Block Diagram
for Brazil DTV (LH70)

TU_SCLK, TU_SDATA, TU_SYNC

VA1G5BF8005

Qimonda/Hynix

TU_SIF
SDA0/SCL0_3.3V
LVDS
RF_Switch, Gain_Switch

FRC IC
(MST7323S)

CVBS, L/R, AV_DET

FRC Block

AV1
AV2

DDR2(256Mbit)

TU_CVBS_IN

(FHD, 120Hz)

SIDE_CVBS, SIDE_L/R, SIDE_DET


X-tal
12MHz

Y Pb Pr, L/R, DET

Component 1

Y Pb Pr, L/R, DET

Component 2

DDR_Data[0:15], DQS, DM
RGB/H/V

DDR2 (1Gbit)

D-sub RGB

Elpida/Hynix

Addr.[0:13], ctrl. data

Audio L/R

Audio L/R (for RGB)


JACK BACK
at REAR

LCD Module

BCM3556

HDMI 1

(Brazil)

3x1
HDMI Switch

HDMI 2
HDMI 3

DDR2 (1Gbit)
Elpida/Hynix

Data[16:31]

Data [0 7]
CS ,RE,WE
SPDIF

Digital Audio (Optic)

RS-232C (Ctrl./SVC)

RX/TX

RX/TX

MAX3232

Bluetooth Module
USB

NAND Flash
(512Mbit)

+5V

Reset Switch

Copyright 2009 LG Electronics. Inc. All right reserved.


Only for training and service purposes

DP1/DM1

USB_DM1

DP2/DM2

USB_DP1
USB_DM2

O.C. Protector

USB_DP2
+5V

Reset IC

X-tal

I2S

SCL, SDA_3.3V

SCL, SDA_3.3V

54MHz

CLK,TDI,TDO,MS,RST

Digital AMP
NTP3100L

NVRAM
MICOM
(MTV416GMF)
JTAG

X-tal
24MHz

LGE Internal Use Only

4. Analog TV Video Trouble Shooting

Check RF Cable
Y
Check Tuner(TU101) Power
(5.0V, 2.5V, 3.3V, 1.2V)

Replace one of IC101, IC102 at


Jack Board or IC803/ Q812/ IC804/
IC809/Q809/+5V_ST and +12V of
P801 at Main Board& Recheck

Y
Check CVBS Signal
TU101 #7 Pin and R118

Maybe Tuner(TU101) has problems

Y
Check cable between P203 at Jack
Board and P701 at Main Baord

Maybe Cable Pin has problems

Y
Check CVBS Signal
R703 and C110 at Main Baord

Replace one of R703 and C110


& Recheck

Y
Maybe BCM3556(IC100)
has problems

Copyright 2009 LG Electronics. Inc. All right reserved.


Only for training and service purposes

LGE Internal Use Only

5. Component Video Trouble Shooting


Overall Block Diagram
for Brazil DTV (LH70)
)
(

TU_SCLK, TU_SDATA, TU_SYNC

VA1G5BF8005

Qimonda/Hynix

TU_SIF
SDA0/SCL0_3.3V
LVDS
RF_Switch, Gain_Switch

FRC IC
(MST7323S)

CVBS, L/R, AV_DET

FRC Block

AV1
AV2

DDR2(256Mbit)

TU_CVBS_IN

(FHD, 120Hz)

SIDE_CVBS, SIDE_L/R, SIDE_DET


X-tal
12MHz

Y Pb Pr, L/R, DET

Component 1

Y Pb Pr, L/R, DET

Component 2

DDR_Data[0:15], DQS, DM
RGB/H/V

DDR2 (1Gbit)

D-sub RGB

Elpida/Hynix

Addr.[0:13], ctrl. data

Audio L/R

Audio L/R (for RGB)


JACK BACK
at REAR

LCD Module

BCM3556

HDMI 1

(Brazil)

3x1
HDMI Switch

HDMI 2
HDMI 3

DDR2 (1Gbit)
Elpida/Hynix

Data[16:31]

Data [0 7]
CS ,RE,WE
SPDIF

Digital Audio (Optic)

RS-232C (Ctrl./SVC)

RX/TX

RX/TX

MAX3232

Bluetooth Module
USB

NAND Flash
(512Mbit)

+5V

Reset Switch

Copyright 2009 LG Electronics. Inc. All right reserved.


Only for training and service purposes

DP1/DM1

USB_DM1

DP2/DM2

USB_DP1
USB_DM2

O.C. Protector

USB_DP2
+5V

Reset IC

X-tal

I2S

SCL, SDA_3.3V

SCL, SDA_3.3V

54MHz

CLK,TDI,TDO,MS,RST

Digital AMP
NTP3100L

NVRAM
MICOM
(MTV416GMF)
JTAG

X-tal
24MHz

LGE Internal Use Only

5. Component Video Trouble Shooting


Check Signal Format
Is it supported signal?
Y
Check Component Cable
Y
Check Component Jack JK209 at
Jack Board

Replace Jack at Jack board

Y
Check Component Signal
R292, R293, R294
R295, R296, R297
at Jack Board

Replace one of
R292, R293, R294, R295, R296, R297
L212, L213, L214, L215, L216, L217
& Recheck

Y
Check cable between P203 at Jack
Board and P701 at Main Baord

Maybe Cable Pin has problems

Y
Check Component Signal
C130, C131, C132
C133, C134. C135

Replace it

Y
Maybe BCM3556(IC100)
has problems

Copyright 2009 LG Electronics. Inc. All right reserved.


Only for training and service purposes

LGE Internal Use Only

6. RGB Video Trouble Shooting


Overall Block Diagram
for Brazil DTV (LH70)

TU_SCLK, TU_SDATA, TU_SYNC

VA1G5BF8005

Qimonda/Hynix

TU_SIF
SDA0/SCL0_3.3V
LVDS
RF_Switch, Gain_Switch

FRC IC
(MST7323S)

CVBS, L/R, AV_DET

FRC Block

AV1
AV2

DDR2(256Mbit)

TU_CVBS_IN

(FHD, 120Hz)

SIDE_CVBS, SIDE_L/R, SIDE_DET


X-tal
12MHz

Y Pb Pr, L/R, DET

Component 1

Y Pb Pr, L/R, DET

Component 2

DDR_Data[0:15], DQS, DM
RGB/H/V

DDR2 (1Gbit)

D-sub RGB

Elpida/Hynix

Addr.[0:13], ctrl. data

Audio L/R

Audio L/R (for RGB)


JACK BACK
at REAR

LCD Module

BCM3556

HDMI 1

(Brazil)

3x1
HDMI Switch

HDMI 2
HDMI 3

DDR2 (1Gbit)
Elpida/Hynix

Data[16:31]

Data [0 7]
CS ,RE,WE
SPDIF

Digital Audio (Optic)

RS-232C (Ctrl./SVC)

RX/TX

Reset Switch

Copyright 2009 LG Electronics. Inc. All right reserved.


Only for training and service purposes

RX/TX

MAX3232

Bluetooth Module
USB

NAND Flash
(512Mbit)

+5V

DP1/DM1

USB_DM1

DP2/DM2

USB_DP1
USB_DM2

O.C. Protector

USB_DP2
+5V

Reset IC

X-tal

I2S

SCL, SDA_3.3V

SCL, SDA_3.3V

54MHz

CLK,TDI,TDO,MS,RST

Digital AMP
NTP3100L

NVRAM
MICOM
(MTV416GMF)
JTAG

X-tal
24MHz

LGE Internal Use Only

6. RGB Video Trouble Shooting


Check Signal Format
Is it supported signal?
Y
Check RGB Cable
Y
Check RGB Jack JK208 at Jack
Board

Replace JK208 at Jack board

Y
Check RGB Signal
L207, L208, L209 at Jack Board

Replace one of L207, L208, L209


at Jack Board & Recheck

Y
Check cable between P203 at Jack
Board and P701 at Main Board

Maybe Cable Pin has problems

Y
Check RGB Signal
C127, C128, C129 at Main Board

Replace it

Y
Maybe BCM3556(IC100)
has problems

Copyright 2009 LG Electronics. Inc. All right reserved.


Only for training and service purposes

LGE Internal Use Only

7. AV Video Trouble Shooting


Overall Block Diagram
for Brazil DTV (LH70)

TU_SCLK, TU_SDATA, TU_SYNC

VA1G5BF8005

Qimonda/Hynix

TU_SIF
SDA0/SCL0_3.3V
LVDS
RF_Switch, Gain_Switch

FRC IC
(MST7323S)

CVBS, L/R, AV_DET

FRC Block

AV1
AV2

DDR2(256Mbit)

TU_CVBS_IN

(FHD, 120Hz)

SIDE_CVBS, SIDE_L/R, SIDE_DET


X-tal
12MHz

Y Pb Pr, L/R, DET

Component 1

Y Pb Pr, L/R, DET

Component 2

DDR_Data[0:15], DQS, DM
RGB/H/V

DDR2 (1Gbit)

D-sub RGB

Elpida/Hynix

Addr.[0:13], ctrl. data

Audio L/R

Audio L/R (for RGB)


JACK BACK
at REAR

LCD Module

BCM3556

HDMI 1

(Brazil)

3x1
HDMI Switch

HDMI 2
HDMI 3

DDR2 (1Gbit)
Elpida/Hynix

Data[16:31]

Data [0 7]
CS ,RE,WE
SPDIF

Digital Audio (Optic)

RS-232C (Ctrl./SVC)

RX/TX

Reset Switch

Copyright 2009 LG Electronics. Inc. All right reserved.


Only for training and service purposes

RX/TX

MAX3232

Bluetooth Module
USB

NAND Flash
(512Mbit)

+5V

DP1/DM1

USB_DM1

DP2/DM2

USB_DP1
USB_DM2

O.C. Protector

USB_DP2
+5V

Reset IC

X-tal

I2S

SCL, SDA_3.3V

SCL, SDA_3.3V

54MHz

CLK,TDI,TDO,MS,RST

Digital AMP
NTP3100L

NVRAM
MICOM
(MTV416GMF)
JTAG

X-tal
24MHz

LGE Internal Use Only

7. AV Video Trouble Shooting


Check Signal Format
Is it supported signal?
Y
Check AV Cable
Y
Check AV Jack JK209 at Jack
Board

Replace JK209 at Jack board

Y
Check AV Signal
R203, R204, R214, R215 at Jack
Board

Replace one of R203, R204, R214,


R215 at Jack Board
& Recheck

Y
Check cable between P203 at Jack
Board and P701 at Main Board

Maybe Cable Pin has problems

Y
Check AV Signal
C124, C125 at Main Board

Replace it

Y
Maybe BCM3556(IC100)
has problems

Copyright 2009 LG Electronics. Inc. All right reserved.


Only for training and service purposes

LGE Internal Use Only

8. HDMI Video Trouble Shooting


Overall Block Diagram
for Brazil DTV (LH70)

TU_SCLK, TU_SDATA, TU_SYNC

VA1G5BF8005

Qimonda/Hynix

TU_SIF
SDA0/SCL0_3.3V
LVDS
RF_Switch, Gain_Switch

FRC IC
(MST7323S)

CVBS, L/R, AV_DET

FRC Block

AV1
AV2

DDR2(256Mbit)

TU_CVBS_IN

(FHD, 120Hz)

SIDE_CVBS, SIDE_L/R, SIDE_DET


X-tal
12MHz

Y Pb Pr, L/R, DET

Component 1

Y Pb Pr, L/R, DET

Component 2

DDR_Data[0:15], DQS, DM
RGB/H/V

DDR2 (1Gbit)

D-sub RGB

Elpida/Hynix

Addr.[0:13], ctrl. data

Audio L/R

Audio L/R (for RGB)


JACK BACK
at REAR

LCD Module

BCM3556

HDMI 1

(Brazil)

3x1
HDMI Switch

HDMI 2
HDMI 3

DDR2 (1Gbit)
Elpida/Hynix

Data[16:31]

Data [0 7]
CS ,RE,WE
SPDIF

Digital Audio (Optic)

RS-232C (Ctrl./SVC)

RX/TX

Reset Switch

Copyright 2009 LG Electronics. Inc. All right reserved.


Only for training and service purposes

RX/TX

MAX3232

Bluetooth Module
USB

NAND Flash
(512Mbit)

+5V

DP1/DM1

USB_DM1

DP2/DM2

USB_DP1
USB_DM2

O.C. Protector

USB_DP2
+5V

Reset IC

X-tal

I2S

SCL, SDA_3.3V

SCL, SDA_3.3V

54MHz

CLK,TDI,TDO,MS,RST

Digital AMP
NTP3100L

NVRAM
MICOM
(MTV416GMF)
JTAG

X-tal
24MHz

LGE Internal Use Only

8. HDMI Video Trouble Shooting


Check Signal Format
Is it supported signal?
Y
Check HDMI Cable
Y
Check HDMI Jack
JK600, JK601, JK602

Replace Jack

Y
Check IC601 Voltage Level
+1.8V_HDMI, +5.0V_HDMI

Replace one of
L601/L602/R619/R615

Y
Check I2C Signal
R624/R625/R157/R158

Replace It & Recheck

Y
Maybe BCM3556(IC100)
has problems

Copyright 2009 LG Electronics. Inc. All right reserved.


Only for training and service purposes

LGE Internal Use Only

9. All Source Audio Trouble Shooting


Overall Block Diagram
for Brazil DTV (LH70)

TU_SCLK, TU_SDATA, TU_SYNC

VA1G5BF8005

Qimonda/Hynix

TU_SIF
SDA0/SCL0_3.3V
LVDS
RF_Switch, Gain_Switch

FRC IC
(MST7323S)

CVBS, L/R, AV_DET

FRC Block

AV1
AV2

DDR2(256Mbit)

TU_CVBS_IN

(FHD, 120Hz)

SIDE_CVBS, SIDE_L/R, SIDE_DET


X-tal
12MHz

Y Pb Pr, L/R, DET

Component 1

Y Pb Pr, L/R, DET

Component 2

DDR_Data[0:15], DQS, DM
RGB/H/V

DDR2 (1Gbit)

D-sub RGB

Elpida/Hynix

Addr.[0:13], ctrl. data

Audio L/R

Audio L/R (for RGB)


JACK BACK
at REAR

LCD Module

BCM3556

HDMI 1

(Brazil)

3x1
HDMI Switch

HDMI 2
HDMI 3

DDR2 (1Gbit)
Elpida/Hynix

Data[16:31]

Data [0 7]
CS ,RE,WE
SPDIF

Digital Audio (Optic)

RS-232C (Ctrl./SVC)

RX/TX

RX/TX

MAX3232

Bluetooth Module
USB

NAND Flash
(512Mbit)

+5V

Reset Switch

Copyright 2009 LG Electronics. Inc. All right reserved.


Only for training and service purposes

DP1/DM1

USB_DM1

DP2/DM2

USB_DP1
USB_DM2

O.C. Protector

USB_DP2
+5V

Reset IC

X-tal

I2S

SCL, SDA_3.3V

SCL, SDA_3.3V

54MHz

CLK,TDI,TDO,MS,RST

Digital AMP
NTP3100L

NVRAM
MICOM
(MTV416GMF)
JTAG

X-tal
24MHz

LGE Internal Use Only

9. All Source Audio Trouble Shooting

Make sure you cant hear any audio


Y
Check Speaker

Replace Speaker

Y
Check Connector P501

Replace Connector

Y
Check Signal
L504, L505

Replace one of
L508/L509/L510/L507/L504/L505
& Recheck

Replace one of
L511L503/L501 and IC503
& Recheck

Y
Check IC501 Power
24V, 3.3V, 1.8V
L511, L503, L501

Maybe NTP3100 has problems.


Replace It

Y
Check BCM3556 I2S Output
R505, R506, R507

N
Replace It & Recheck

Y
Maybe BCM3556(IC100)
has problems

Copyright 2009 LG Electronics. Inc. All right reserved.


Only for training and service purposes

LGE Internal Use Only

10. Digital TV Audio Trouble Shooting


Overall Block Diagram
for Brazil DTV (LH70)

TU_SCLK, TU_SDATA, TU_SYNC

VA1G5BF8005

Qimonda/Hynix

TU_SIF
SDA0/SCL0_3.3V
LVDS
RF_Switch, Gain_Switch

FRC IC
(MST7323S)

CVBS, L/R, AV_DET

FRC Block

AV1
AV2

DDR2(256Mbit)

TU_CVBS_IN

(FHD, 120Hz)

SIDE_CVBS, SIDE_L/R, SIDE_DET


X-tal
12MHz

Y Pb Pr, L/R, DET

Component 1

Y Pb Pr, L/R, DET

Component 2

DDR_Data[0:15], DQS, DM
RGB/H/V

DDR2 (1Gbit)

D-sub RGB

Elpida/Hynix

Addr.[0:13], ctrl. data

Audio L/R

Audio L/R (for RGB)


JACK BACK
at REAR

LCD Module

BCM3556

HDMI 1

(Brazil)

3x1
HDMI Switch

HDMI 2
HDMI 3

DDR2 (1Gbit)
Elpida/Hynix

Data[16:31]

Data [0 7]
CS ,RE,WE
SPDIF

Digital Audio (Optic)

RS-232C (Ctrl./SVC)

RX/TX

RX/TX

MAX3232

Bluetooth Module
USB

NAND Flash
(512Mbit)

+5V

Reset Switch

Copyright 2009 LG Electronics. Inc. All right reserved.


Only for training and service purposes

DP1/DM1

USB_DM1

DP2/DM2

USB_DP1
USB_DM2

O.C. Protector

USB_DP2
+5V

Reset IC

X-tal

I2S

SCL, SDA_3.3V

SCL, SDA_3.3V

54MHz

CLK,TDI,TDO,MS,RST

Digital AMP
NTP3100L

NVRAM
MICOM
(MTV416GMF)
JTAG

X-tal
24MHz

LGE Internal Use Only

10. Digital TV Audio Trouble Shooting

Check video output

Follow procedure digital TV video


trouble shooting

Maybe BCM3556 internal audio


DSP has problems. Replace It

Y
Follow procedure All source audio
trouble shooting

Copyright 2009 LG Electronics. Inc. All right reserved.


Only for training and service purposes

LGE Internal Use Only

11. Analog TV Audio Trouble Shooting


Overall Block Diagram
for Brazil DTV (LH70)

TU_SCLK, TU_SDATA, TU_SYNC

VA1G5BF8005

Qimonda/Hynix

TU_SIF
SDA0/SCL0_3.3V
LVDS
RF_Switch, Gain_Switch

FRC IC
(MST7323S)

CVBS, L/R, AV_DET

FRC Block

AV1
AV2

DDR2(256Mbit)

TU_CVBS_IN

(FHD, 120Hz)

SIDE_CVBS, SIDE_L/R, SIDE_DET


X-tal
12MHz

Y Pb Pr, L/R, DET

Component 1

Y Pb Pr, L/R, DET

Component 2

DDR_Data[0:15], DQS, DM
RGB/H/V

DDR2 (1Gbit)

D-sub RGB

Elpida/Hynix

Addr.[0:13], ctrl. data

Audio L/R

Audio L/R (for RGB)


JACK BACK
at REAR

LCD Module

BCM3556

HDMI 1

(Brazil)

3x1
HDMI Switch

HDMI 2
HDMI 3

DDR2 (1Gbit)
Elpida/Hynix

Data[16:31]

Data [0 7]
CS ,RE,WE
SPDIF

Digital Audio (Optic)

RS-232C (Ctrl./SVC)

RX/TX

RX/TX

MAX3232

Bluetooth Module
USB

NAND Flash
(512Mbit)

+5V

Reset Switch

Copyright 2009 LG Electronics. Inc. All right reserved.


Only for training and service purposes

DP1/DM1

USB_DM1

DP2/DM2

USB_DP1
USB_DM2

O.C. Protector

USB_DP2
+5V

Reset IC

X-tal

I2S

SCL, SDA_3.3V

SCL, SDA_3.3V

54MHz

CLK,TDI,TDO,MS,RST

Digital AMP
NTP3100L

NVRAM
MICOM
(MTV416GMF)
JTAG

X-tal
24MHz

LGE Internal Use Only

11. Analog TV Audio Trouble Shooting

Check video output

Y
Check Tuner(TU101) Power
(5.0V, 2.5V, 3.3V, 1.2V)

Follow procedure analog TV video


trouble shooting
Replace one of IC101, IC102 at
Jack Board or IC803/ Q812/ IC804/
IC809/Q809/+5V_ST and +12V of
P801 at Main Board& Recheck

Y
Check SIF Signal
TU101 #6 Pin and R118 at Jack
Board

Maybe Tuner(TU101) has problems

Y
Check SIF Signal
IC501 #4 Pin

Replace one of
L505/L514/C502/C511/Q500/Q502
IC501 & Recheck

Replace one of C123, R120, R121,


R124, L109, Q101, C128
& Recheck

Y
Check SIF Signal
C128 at Jack Board
Y
Check cable between P203 at Jack
Board and P701 at Main Baord

Maybe Cable Pin has problems

Y
Check SIF Signal
R704 and C106 at Main Board

Replace one of R704/R128/C106


& Recheck

Maybe BCM3556 audio block has


problems. Replace It

Y
Follow procedure All source audio
trouble shooting

Copyright 2009 LG Electronics. Inc. All right reserved.


Only for training and service purposes

LGE Internal Use Only

12. Component / RGB / AV Audio Trouble Shooting


Overall Block Diagram
for Brazil DTV (LH70)

TU_SCLK, TU_SDATA, TU_SYNC

VA1G5BF8005

Qimonda/Hynix

TU_SIF
SDA0/SCL0_3.3V
LVDS

(FHD, 120Hz)

FRC Block

CVBS, L/R, AV_DET


SIDE_CVBS, SIDE_L/R, SIDE_DET

X-tal
12MHz

Y Pb Pr, L/R, DET

Component 1

Y Pb Pr, L/R, DET

Component 2

DDR_Data[0:15], DQS, DM
RGB/H/V

DDR2 (1Gbit)

D-sub RGB

Elpida/Hynix

Addr.[0:13], ctrl. data

Audio L/R

Audio L/R (for RGB)


JACK BACK
at REAR

LCD Module

FRC IC
(MST7323S)

RF_Switch, Gain_Switch

AV1
AV2

DDR2(256Mbit)

TU_CVBS_IN

BCM3556

HDMI 1

(Brazil)

3x1
HDMI Switch

HDMI 2
HDMI 3

DDR2 (1Gbit)
Elpida/Hynix

Data[16:31]

Data [0 7]
CS ,RE,WE
SPDIF

Digital Audio (Optic)

RS-232C (Ctrl./SVC)

RX/TX

Reset Switch

Copyright 2009 LG Electronics. Inc. All right reserved.


Only for training and service purposes

RX/TX

MAX3232

Bluetooth Module
USB

NAND Flash
(512Mbit)

+5V

DP1/DM1

USB_DM1

DP2/DM2

USB_DP1
USB_DM2

O.C. Protector

USB_DP2
+5V

Reset IC

X-tal

I2S

SCL, SDA_3.3V

SCL, SDA_3.3V

54MHz

CLK,TDI,TDO,MS,RST

Digital AMP
NTP3100L

NVRAM
MICOM
(MTV416GMF)
JTAG

X-tal
24MHz

LGE Internal Use Only

12. Component / RGB / AV Audio Trouble Shooting

Check Video Output

Follow procedure external input


video trouble shooting

Y
Check Jack JK208/JK209

Replace Jack

Y
Check Signal
R235, R236 (Comp1)
R216, R217 (Comp2)
R249, R250 (RGB)
R219, R221 (AV1)
R218, R220 (AV2)
at Jack Board

Replace one of
R235/R236/C231/C232 (Comp1)
R216/R217/C207/C208 (Comp2)
R219/R221/C210/C212 (AV1)
R218/R220/C209/C211 (AV2)
R249/R250/C246/C247 (RGB)
& Recheck at Jack Board

Y
Check cable between P203 at Jack
Board and P701 at Main Baord

Y
Check Signal
C206, C210, C211, C232, C220,
C221, C224, C225, C226, C227
at Main Board

Maybe Cable Pin has problems

Replace one of
R215/R228/C211/C232 (Comp1)
R229/R230/C220/C221 (Comp2)
R204/R214/C206/C210 (AV1)
R231/R232/C224/C225 (AV2)
R233/R234/C226/C227 (RGB)
& Recheck at Main Board

Y
Follow procedure All source audio
trouble shooting

Maybe BCM3556 audio block has


problems. Replace It

Copyright 2009 LG Electronics. Inc. All right reserved.


Only for training and service purposes

LGE Internal Use Only

13. HDMI Audio Trouble Shooting


Overall Block Diagram
for Brazil DTV (LH70)

TU_SCLK, TU_SDATA, TU_SYNC

VA1G5BF8005

Qimonda/Hynix

TU_SIF
SDA0/SCL0_3.3V
LVDS
RF_Switch, Gain_Switch

FRC IC
(MST7323S)

CVBS, L/R, AV_DET

FRC Block

AV1
AV2

DDR2(256Mbit)

TU_CVBS_IN

(FHD, 120Hz)

SIDE_CVBS, SIDE_L/R, SIDE_DET


X-tal
12MHz

Y Pb Pr, L/R, DET

Component 1

Y Pb Pr, L/R, DET

Component 2

DDR_Data[0:15], DQS, DM
RGB/H/V

DDR2 (1Gbit)

D-sub RGB

Elpida/Hynix

Addr.[0:13], ctrl. data

Audio L/R

Audio L/R (for RGB)


JACK BACK
at REAR

LCD Module

BCM3556

HDMI 1

(Brazil)

3x1
HDMI Switch

HDMI 2
HDMI 3

DDR2 (1Gbit)
Elpida/Hynix

Data[16:31]

Data [0 7]
CS ,RE,WE
SPDIF

Digital Audio (Optic)

RS-232C (Ctrl./SVC)

RX/TX

RX/TX

MAX3232

Bluetooth Module
USB

NAND Flash
(512Mbit)

+5V

Reset Switch

Copyright 2009 LG Electronics. Inc. All right reserved.


Only for training and service purposes

DP1/DM1

USB_DM1

DP2/DM2

USB_DP1
USB_DM2

O.C. Protector

USB_DP2
+5V

Reset IC

X-tal

I2S

SCL, SDA_3.3V

SCL, SDA_3.3V

54MHz

CLK,TDI,TDO,MS,RST

Digital AMP
NTP3100L

NVRAM
MICOM
(MTV416GMF)
JTAG

X-tal
24MHz

LGE Internal Use Only

13. HDMI Audio Trouble Shooting


N
Check video output

Follow procedure HDMI video


trouble shooting

Y
Re-download EDID data

Replace IC601

Y
Follow procedure All source audio
trouble shooting

Maybe BCM3556 audio block has


problems. Replace it

Copyright 2009 LG Electronics. Inc. All right reserved.


Only for training and service purposes

LGE Internal Use Only

14. USB Trouble Shooting


Overall Block Diagram
for Brazil DTV (LH70)

TU_SCLK, TU_SDATA, TU_SYNC

VA1G5BF8005

Qimonda/Hynix

TU_SIF
SDA0/SCL0_3.3V
LVDS
RF_Switch, Gain_Switch

FRC IC
(MST7323S)

CVBS, L/R, AV_DET

FRC Block

AV1
AV2

DDR2(256Mbit)

TU_CVBS_IN

(FHD, 120Hz)

SIDE_CVBS, SIDE_L/R, SIDE_DET


X-tal
12MHz

Y Pb Pr, L/R, DET

Component 1

Y Pb Pr, L/R, DET

Component 2

DDR_Data[0:15], DQS, DM
RGB/H/V

DDR2 (1Gbit)

D-sub RGB

Elpida/Hynix

Addr.[0:13], ctrl. data

Audio L/R

Audio L/R (for RGB)


JACK BACK
at REAR

LCD Module

BCM3556

HDMI 1

(Brazil)

3x1
HDMI Switch

HDMI 2
HDMI 3

DDR2 (1Gbit)
Elpida/Hynix

Data[16:31]

Data [0 7]
CS ,RE,WE
SPDIF

Digital Audio (Optic)

RS-232C (Ctrl./SVC)

RX/TX

RX/TX

MAX3232

Bluetooth Module
USB

NAND Flash
(512Mbit)

+5V

Reset Switch

Copyright 2009 LG Electronics. Inc. All right reserved.


Only for training and service purposes

DP1/DM1

USB_DM1

DP2/DM2

USB_DP1
USB_DM2

O.C. Protector

USB_DP2
+5V

Reset IC

X-tal

I2S

SCL, SDA_3.3V

SCL, SDA_3.3V

54MHz

CLK,TDI,TDO,MS,RST

Digital AMP
NTP3100L

NVRAM
MICOM
(MTV416GMF)
JTAG

X-tal
24MHz

LGE Internal Use Only

14. USB Trouble Shooting

Check USB 2.0 Cable


Y
Check USB device
If devuce is 2.5 inch HDD,
Check power adaptor
Y
Check P704

Replace Jack

Y
Check 5V voltage level at L703

Replace one of
IC701/L703/IC806/Q810/L819
& Recheck

Y
Maybe BCM3556(IC100)
has problems. Replace It.

Exception
- USB power could be disabled by inrushing current
- In this case, remove the device and try to reboot the TV (AC power off/on)

Copyright 2009 LG Electronics. Inc. All right reserved.


Only for training and service purposes

LGE Internal Use Only

14. Bluetooth Trouble Shooting


Overall Block Diagram
for Brazil DTV (LH70)

TU_SCLK, TU_SDATA, TU_SYNC

VA1G5BF8005

Qimonda/Hynix

TU_SIF
SDA0/SCL0_3.3V
LVDS
RF_Switch, Gain_Switch

FRC IC
(MST7323S)

CVBS, L/R, AV_DET

FRC Block

AV1
AV2

DDR2(256Mbit)

TU_CVBS_IN

(FHD, 120Hz)

SIDE_CVBS, SIDE_L/R, SIDE_DET


X-tal
12MHz

Y Pb Pr, L/R, DET

Component 1

Y Pb Pr, L/R, DET

Component 2

DDR_Data[0:15], DQS, DM
RGB/H/V

DDR2 (1Gbit)

D-sub RGB

Elpida/Hynix

Addr.[0:13], ctrl. data

Audio L/R

Audio L/R (for RGB)


JACK BACK
at REAR

LCD Module

BCM3556

HDMI 1

(Brazil)

3x1
HDMI Switch

HDMI 2
HDMI 3

DDR2 (1Gbit)
Elpida/Hynix

Data[16:31]

Data [0 7]
CS ,RE,WE
SPDIF

Digital Audio (Optic)

RS-232C (Ctrl./SVC)

RX/TX

RX/TX

MAX3232

Bluetooth Module
USB

NAND Flash
(512Mbit)

+5V

Reset Switch

Copyright 2009 LG Electronics. Inc. All right reserved.


Only for training and service purposes

DP1/DM1

USB_DM1

DP2/DM2

USB_DP1
USB_DM2

O.C. Protector

USB_DP2
+5V

Reset IC

X-tal

I2S

SCL, SDA_3.3V

SCL, SDA_3.3V

54MHz

CLK,TDI,TDO,MS,RST

Digital AMP
NTP3100L

NVRAM
MICOM
(MTV416GMF)
JTAG

X-tal
24MHz

LGE Internal Use Only

14. USB Trouble Shooting

Check Bluetooth Module

Replace Bluetooth

Y
Check Cable between Bluetooth
and Main Board

Replace cable

Y
Check P705

Replace Jack

Y
Check Signal
R3022, R3023

Replace one of
R3022, R3023
& Recheck

Y
Maybe BCM3556(IC100)
has problems. Replace It.

Copyright 2009 LG Electronics. Inc. All right reserved.


Only for training and service purposes

LGE Internal Use Only

15. Digital TV Recording Fail Trouble Shooting


Overall Block Diagram
for Brazil DTV (LH70)

TU_SCLK, TU_SDATA, TU_SYNC

VA1G5BF8005

Qimonda/Hynix

TU_SIF
SDA0/SCL0_3.3V
LVDS
RF_Switch, Gain_Switch

FRC IC
(MST7323S)

CVBS, L/R, AV_DET

FRC Block

AV1
AV2

DDR2(256Mbit)

TU_CVBS_IN

(FHD, 120Hz)

SIDE_CVBS, SIDE_L/R, SIDE_DET


X-tal
12MHz

Y Pb Pr, L/R, DET

Component 1

Y Pb Pr, L/R, DET

Component 2

DDR_Data[0:15], DQS, DM
RGB/H/V

DDR2 (1Gbit)

D-sub RGB

Elpida/Hynix

Addr.[0:13], ctrl. data

Audio L/R

Audio L/R (for RGB)


JACK BACK
at REAR

LCD Module

BCM3556

HDMI 1

(Brazil)

3x1
HDMI Switch

HDMI 2
HDMI 3

DDR2 (1Gbit)
Elpida/Hynix

Data[16:31]

Data [0 7]
CS ,RE,WE
SPDIF

Digital Audio (Optic)

RS-232C (Ctrl./SVC)

RX/TX

RX/TX

MAX3232

Bluetooth Module
USB

NAND Flash
(512Mbit)

+5V

Reset Switch

Copyright 2009 LG Electronics. Inc. All right reserved.


Only for training and service purposes

DP1/DM1

USB_DM1

DP2/DM2

USB_DP1
USB_DM2

O.C. Protector

USB_DP2
+5V

Reset IC

X-tal

I2S

SCL, SDA_3.3V

SCL, SDA_3.3V

54MHz

CLK,TDI,TDO,MS,RST

Digital AMP
NTP3100L

NVRAM
MICOM
(MTV416GMF)
JTAG

X-tal
24MHz

LGE Internal Use Only

15. Digital TV Recording Fail Trouble Shooting


N
Check video/audio output

Follow procedure digital TV


video/audio trouble shooting

Y
Check USB

Follow procedure USB trouble


shooting

Copyright 2009 LG Electronics. Inc. All right reserved.


Only for training and service purposes

LGE Internal Use Only

18. Digital TV Video Trouble Shooting while recording (Watch & Record)
Overall Block Diagram
for Brazil DTV (LH70)

TU_SCLK, TU_SDATA, TU_SYNC

VA1G5BF8005

Qimonda/Hynix

TU_SIF
SDA0/SCL0_3.3V
LVDS
RF_Switch, Gain_Switch

FRC IC
(MST7323S)

CVBS, L/R, AV_DET

FRC Block

AV1
AV2

DDR2(256Mbit)

TU_CVBS_IN

(FHD, 120Hz)

SIDE_CVBS, SIDE_L/R, SIDE_DET


X-tal
12MHz

Y Pb Pr, L/R, DET

Component 1

Y Pb Pr, L/R, DET

Component 2

DDR_Data[0:15], DQS, DM
RGB/H/V

DDR2 (1Gbit)

D-sub RGB

Elpida/Hynix

Addr.[0:13], ctrl. data

Audio L/R

Audio L/R (for RGB)


JACK BACK
at REAR

LCD Module

BCM3556

HDMI 1

(Brazil)

3x1
HDMI Switch

HDMI 2
HDMI 3

DDR2 (1Gbit)
Elpida/Hynix

Data[16:31]

Data [0 7]
CS ,RE,WE
SPDIF

Digital Audio (Optic)

RS-232C (Ctrl./SVC)

RX/TX

RX/TX

MAX3232

Bluetooth Module
USB

NAND Flash
(512Mbit)

+5V

Reset Switch

Copyright 2009 LG Electronics. Inc. All right reserved.


Only for training and service purposes

DP1/DM1

USB_DM1

DP2/DM2

USB_DP1
USB_DM2

O.C. Protector

USB_DP2
+5V

Reset IC

X-tal

I2S

SCL, SDA_3.3V

SCL, SDA_3.3V

54MHz

CLK,TDI,TDO,MS,RST

Digital AMP
NTP3100L

NVRAM
MICOM
(MTV416GMF)
JTAG

X-tal
24MHz

LGE Internal Use Only

18. Digital TV Video Trouble Shooting while recording (Watch & Record)

Check RF Cable
Y
N
Check video/audio output

Follow procedure digital TV


video/audio trouble shooting

Y
Check USB

Follow procedure USB trouble


shooting

Follow procedure OSD trouble


shooting

Y
Check Watch

Y
Check HDD (User)

Copyright 2009 LG Electronics. Inc. All right reserved.


Only for training and service purposes

Replace Jack

LGE Internal Use Only

19. Digital TV Audio Trouble Shooting while recording (Watch & Record)
Overall Block Diagram
for Brazil DTV (LH70)

TU_SCLK, TU_SDATA, TU_SYNC

VA1G5BF8005

Qimonda/Hynix

TU_SIF
SDA0/SCL0_3.3V
LVDS
RF_Switch, Gain_Switch

FRC IC
(MST7323S)

CVBS, L/R, AV_DET

FRC Block

AV1
AV2

DDR2(256Mbit)

TU_CVBS_IN

(FHD, 120Hz)

SIDE_CVBS, SIDE_L/R, SIDE_DET


X-tal
12MHz

Y Pb Pr, L/R, DET

Component 1

Y Pb Pr, L/R, DET

Component 2

DDR_Data[0:15], DQS, DM
RGB/H/V

DDR2 (1Gbit)

D-sub RGB

Elpida/Hynix

Addr.[0:13], ctrl. data

Audio L/R

Audio L/R (for RGB)


JACK BACK
at REAR

LCD Module

BCM3556

HDMI 1

(Brazil)

3x1
HDMI Switch

HDMI 2
HDMI 3

DDR2 (1Gbit)
Elpida/Hynix

Data[16:31]

Data [0 7]
CS ,RE,WE
SPDIF

Digital Audio (Optic)

RS-232C (Ctrl./SVC)

RX/TX

Reset Switch

Copyright 2009 LG Electronics. Inc. All right reserved.


Only for training and service purposes

RX/TX

MAX3232

Bluetooth Module
USB

NAND Flash
(512Mbit)

+5V

DP1/DM1

USB_DM1

DP2/DM2

USB_DP1
USB_DM2

O.C. Protector

USB_DP2
+5V

Reset IC

X-tal

I2S

SCL, SDA_3.3V

SCL, SDA_3.3V

54MHz

CLK,TDI,TDO,MS,RST

Digital AMP
NTP3100L

NVRAM
MICOM
(MTV416GMF)
JTAG

X-tal
24MHz

LGE Internal Use Only

19. Digital TV Audio Trouble Shooting while recording (Watch & Record)

Check video output

Follow procedure digital TV video


trouble shooting while recording
(watch & record)

Maybe BCM3556 internal audio


DSP has problems. Replace It

Y
Follow procedure All source audio
trouble shooting

Copyright 2009 LG Electronics. Inc. All right reserved.


Only for training and service purposes

LGE Internal Use Only