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Common Analog IC Layout Tips-and-Tricks

#10: Do not lay the transistors out as they are placed in the schematics
Quite often you stare a little bit too much on the schematics when you do your layout. A
classical example is a cascade of differential amplifiers. In the schematics you typically
have your differential pair, active load, etc., in each sub-amplifier. You lay out according
to the schematics and you put your input terminals to the left and your output terminals to
the right. Then you start hooking the cascaded stages up and there it starts to get
messed up. You start to cross wires back-and-forth to fit the input to output terminals. It is
much better to rotate the amplifier 90 degrees and then put the input terminals to the left
and outputs to the right. Then you can more or less put the stages adjacent and
automatically hook up.
There are more things like this spend some more time on what you actually have in the
schematics and do not follow it too much in detail (from a placement point of view).

#9: Matching
Matching is very important we all know that. Any small variations in transistor sizes
might give you large variations in terms of voltage or current dependent on gain and
architecture. So, essentially, this bullet is stating the obvious do not forget to match
your circuit. The question though is how should you match? We have those well-known
interdigitized and common-centroid approaches, where one interleaves in one or two
dimensions in order to spread out the statistical variation to more than one transistor.
However, what about these things:
o avoid metal on top of the gate
o orient all transistors (that should be matched) such that the current flows in the
same physical direction
o proximity effects, i.e., the edges should also match
o shallow trench isolation, i.e., do not put the combined active area edges to far
from the gates (that is, do not place the transistors in too large islands)
o and much, much more.

#8: Add rubberband options and spares


Unless you do RAMs or other very regular structures that need to be laid out very dense
in order to reach high density, you should definitely think of rubberband options and
spares. There are three aspects of this:

o You need to do a metal mask change i.e., a bug is detected in your design once
chip is back in bench and you need to hook up an additional inverter or so
somewhere. To save money, you just want to change the (upper) metal layers on
your wafer. However, if the spare inverter is not there to begin with you need to
pay quite a few extra k$.
o Five hours before tape-out you realize you want some more driving capability in
one of your amplifiers, just a little bit of extra current. Unfortunately, since you
have done a dense design, adding that extra transistors forces you to do a
substantial redesign of your layout.
o There is a misunderstanding between PNR/RTL and analog macro and you need
to do some digital encoding for some control wires. Running an ECO on the
digital core takes too much time and you have to do a manual, digital place-androute inside the analog macro.
For all of these cases it would be very nice to have extra circuitry already at hand in your
layout. Remember that normally you are not really doing the most dense layouts in the
market. Especially for the first test runs this is not the case, area and cost optimization
follows later on. First, it is about time-to-market, and to be able to do quick changes to
your design is very important. Layout can be quite tedious, even if you have an
experienced layout engineer at hand, there will be communication required that takes
time.
So add extra transistors/resistors/capacitors, extra inverters/nand/nor/gates, why not
even an extra amplifier? You can even make them programmable (remember one of the
other lists) such that you can add/increase through software.

#7: Electromigration
Modern consumer-market temperature specifications actually stretches beyond 125
degrees. It could very well be 150 degrees. The tough requirements on metal wire widths
for these temperatures get even more tougher. In some cases, the design kit is not really
characterized at these frequencies, but instead data relies on linear extrapolation of other
data points.
Notice also that you might want to run some simulations and bench tests outside the spec
points in order to characterize the circuit better. Thereby, why not design your circuit to
meet also those external corners.
So, in short do not forget to make your wires extra-wide.

#6: Parasitic capacitances


Of course, some of these bullets would get explained/resolved by running proper physical
verification and post-extract simulations. However, quite often you do become a bit
sloppy, you do some minor checks first on your sub levels and for the upper levels the
extracted netlists do become quite big and time-consuming to simulate.
So, main two tips:

o avoid routing wires on top of high-gain nodes. This might give you a strong
capacitive coupling that could have significant impact on performance
o remember that the capacitive side-wall coupling between drain and source could
become quite large if you stack many vias on top of eachother in order to reach a
higher level metal.

#5: Metal fill and other density checks


More or less to guarantee high yield one wants a certain density in certain regions on the
chip. These regions are mostly windows that are moved around the chip and the
physical verification (pv) tool checks for density in that window. This could have the
nasty property that once you are happy with your density checks in your local sub block,
it might turn out that you have too high (or too low) density once you instantiate your
block in the top level design. Annoying, but mostly solveable by changing the pv deck to
have finer stepping between the windows being swept over your design. It could take
slightly more time to run, but definitely quicker than running on the top level.
The tip here is to not be afraid to add fill structures in your subcircuits (as long as you
know that you will not need that space for routing or so). This will further improve
matching. Assume, for example, that you have a time-interleaved ADC where all parallel
channels should be matched properly. Here, you want to add fill structures for each
channel rather than adding them on the top level ADC.

#4: Floorplanning do not miss the whole picture


This is of course also well-known, but yet the problem with floorplanning is that
mostly not all people are involved in the floorplanning process. This makes sense too of
course, but eventhough you are only doing one small block in the overall design,
maintain a good view of the overall system. How can your block be done such that the
overall design benefits from that? For example, by rotating some components in your
block you will help the top-level routing, avoid bends, etc. Remember that the top-level
responsible, in case (s)he is stressed, (s)he will mainly focus on your ports and hook them
up according to instructions. Too often, Ive seen, for example, bias current wires being
routed back-and-forth since the overall picture has not been considered. This causes extra
resistance and noise.

#3: Think digital


The canyon between analog and digital design seems to become even wider the layout
tools are fundamentally different, the design style is fundamentally different, the
simulators different, etc., etc. So no wonder it is so difficult to interface between them
My message here though is to think digital, at least from a floorplanning and perimeter
point-of-view:
o Route your wires on digital routing grid
o Use same widths for supply wires, and signals on the boundary that needs to
interact with digital core

o Make your design as regular as possible, let your (wild) target be to place-androute your analog design using a digital back-end tool (!)
o Jump back-and-forth between the two different worlds to mutually understand the
complexities at both ends. How can an analog macro be inserted (and properly
verified) in the digital PNR? How can a digital macro be inserted (and properly
verified) in the analog flow?

#2: Strengthen metal, etc.


You have a couple of different bullets (#5 and #7) that motivates this one and maybe one
that contradicts (#6). Anyway, the idea here is that if you have a layout in which you have
plenty of routing that needs to be strengthened, say reducing resistance or so. Spend some
hours to develop a script that enables you to draw the interconnections in say metal 1.
Then in cadence virtuoso, at least, you have a functionality that enables you to do layer
manipulations. You could for example create a metal 3 layer which is an xor between
metal 1 and metal 2. Using this approach, you can automatically generate support layers
to your existing metal layers. Further on, you can also program the tool to find where two
metals overlap and automatically insert vias in that region.

#1: Re-use and re-configurability


We slightly touched upon this bullet earlier (rubberband #8). The idea here though is for
the wider scope: how can your circuit be re-used in different environments/designs/chips.
Still, as outlined in bullet #4, we must not loose the whole picture, but yet we can
probably layout one circuit to be reused by adding some redundancy. Normally, the area
penalty is not that high and the design time you save could be quite significant. Chip area
can be expensive, but so is lost hours to the market.
So, same message as I have been mentioning before: think porting. How can you move
your design from one process to another in the shortest possible time? There are some
software tools out there to simplify life for you and why not spend some time
investigating them?