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DIPLOMAT ELECTRONICS

1293-A Mountain View/AlviSo Road
Sunnyvale, california 94086
(408) 134-1 900

MICROCOMPUTER DATA BOOK

.HITACHI

INDEX

GENERAL INFORMATION ________________________________________________________________________________________________________________________________
Type and Package Information ____________________________________________________________________________________________________________________________
Reliability and Quality Assurance ______________________________________________________________________________________________________________________
Design Procedure and Support Tools for 8-bit Single-chip Microcomputer ________________________________________
HMCS6800 Family Instruction Set ____________________________________________________________________________________________________________________
8-bit Microcomputers for Industrial Application __________________________________________________________________________________________

5
7
12
20
23
29

DATA SHEETS__________________________________________________________________________________________________________________________________________________________
• 8-bit Microcomputer HM CS6800 Single-chip Series ____________________________________________________________________________________
HD6801S0
Microcomputer Unit ________________________________________________________________________________________________________________
HD6801 S5
Microcomputer Unit ________________________________________________________________________________________________________________
HD680 1VO
Microcomputer Unit __________________________________________________________________________________ ,_____________________________
HD680 1V5
Microcomputer Unit __________________________________________________________________________________1_________________________ _____
HD6803
Micro Processing Unit ____________________________________________________________________________________________________________
HD6803-1
Micro Processing Unit ____________________________________________________________________________________________________________
HD6805S 1
Microcomputer Unit ________________________________________________________________________________________________________________
HD6805Ul
Microcomputer Unit ________________________________________________________________________________________________________________
HD6805Vl
Microcomputer Unit ________________________________________________________________________________________________________________
HD6805WO
Microcomputer Unit ________________________________________________________________________________________________________________
HD6805XO
Microcomputer Unit ________________________________________________________________________________________________________________
HD630 1VO (CMOS)
Microcomputer Unit ________________________________________________________________________________________________
HD63AO 1VO (CMOS) Microcomputer Unit ________________________________________________________________________________________________
HD63 BO 1VO (CMOS) Microcomputer Unit ________________________________________________________________________________________________
Micro Processing Unit ____________________________________________________________________________________________
HD6303 (CM OS)
HD63A03 (CMOS)
Micro Processing Unit ____________________________________________________________________________________________
HD63B03 (CMOS)
Micro Processing Unit ____________________________________________________________________________________________
Microcomputer Unit ________________________________________________________________________________________________
HD63 L05 (CMOS)
HD68POIS0
Microcomputer Unit ________________________________________________________________________________________________________________
HD68POIV05 Microcomputer Unit ________________________________________________________________________________________________________________
HD68PO 1V07 Microcomputer Unit ________________________________________________________________________________________________________________
HD68P05V05 Microcomputer Unit ________________________________________________________________________________________________________________
HD68P05V07 Microcomputer Unit ________________________________________________________________________________________________________________
• 8,-bit Microcomputer HMCS6800 Multi-chip Series __________________________________________________________________________________
HD6800
Micro Processing Unit ____________________________________________________________________________________________________________
HD68AOO
Micro Processing Unit ____________________________________________________________________________________________________________
HD68BOO
Micro Processing Unit ____________________________________________________________________________________________________________
HD6802
Microprocessor with Clock and RAM ______________________________________________________________________________
HD6802W
Microprocessor with Clock and RAM ______________________________________________________________________________
HD6809
Micro Processing Unit ____________________________________________________________________________________________________________
HD68A09
Micro Processing Unit ____________________________________________________________________________________________________________
HD68B09
Micro Processing Unit ____________________________________________________________________________________________________________
HD6809E
Micro Processing Unit ____________________________________________________________________________________________________________
HD68A09E
Micro Processing Unit ____________________________________________________________________________________________________________
HD68B09E
Micro Processing Unit ____________________________________________________________________________________________________________
HD6821
Peripheral Interface Adapter ________________________________________________________________________________________________
HD68A21
Peripheral Interface Adapter ________________________________________________________________________________________________
HD68B21
Peripheral Interface Adapter ________________________________________________________________________________________________
HD6840
Programmable Timer Module ______________________________________________________________________________________________
HD68A40
Programmable Timer Module ______________________________________________________________________________________________
HD68B40
Programmable Timer Module ______________________________________________________________________________________________
HD6843
Floppy Disk Controller __________________________________________________________________________________________________________
HD68A43
Floppy Disk Controller __________________________________________________________________________________________________________

31
31
33
33
67
67
101
101
128
148
169
190
218
220
220
220
247
247
247
249
276
276
276
313
313
335
337
337
337
368
380
392
392
392
423
423
423
455
455
455
472
472
472
486
486





HD6844
Direct Memory Access Controller ......................................................................................
HD68A44
Direct Memory Access Controller ......................................................................................
HD68B44
Direct Memory Access Controller ......................................................................................
HD6845S
CR T Controller ........................................................................................................................
HD68A45S
CR T Controller ........................................................................................................................
HD68B45S
CR T Controller ........................................................................................................................
HD6846
Combination ROM 110 Timer ............................................................................................
HD6850
Asynchronous Communication Interface Adapter ........................................................
HD68A50
Asynchronous Communication Interface Adapter ........................................................
HD6852
Synchronous Serial Data Adapter ......................................................................................
HD68A52
Synchronous Serial Data Adapter ......................................................................................
HD46508
Analog Data Acquisition Unit.. ............................................................................................
HD46508-1
Analog Data Acquisition Unit ..............................................................................................
HD46508A
Analog Data Acquisition Unit.. ............................................................................................
HD46508A -1
Analog Data Acquisition Unit.. ............................................................................................
HD146818 (CMOS)
Real Time Clock Plus RAM ................................................................................
Peripheral Interface Adapter ................................................................................
HD6321 (CMOS)
Peripheral Interface Adapter ................................................................................
HD63A21 (CMOS)
HD63B21 (CMOS)
Peripheral Interface Adapter ................................................................................
HD6340 (CMOS)
Programmable Timer Module ..............................................................................
Programmable Timer Module ..............................................................................
HD63A40 (CMOS)
Programmable Timer Module ..............................................................................
HD63B40 (CMOS)
HD6350 (CMOS)
Asynchronous Communication Interface Adapter ........................................
Asynchronous Communication Interface Adapter ........................................
HD63A50 (CMOS)
Asynchronous Communication Interface Adapter ........................................
HD63B50 (CMOS)
• 16-bit Microcomputer HMCS68000 Multi-chip Series ..............................................................................
HD68000-4
Micro Processing Unit ............................................................................................................
HD68000-6
Micro Processing Unit ............................................................................................................
HD68000-8
Micro Processing Unit ............................................................................................................
HD68000-10
Micro Processing Unit ............................................................................................................
HD68450
Direct Memory Access Controller ......................................................................................







513
513
513
546
546
546
585
606
606
616
616
630
630
630
630
649
665
665
665
666
666
666
667
667
667
669
671
671
671
671
752

INTRODUCTION OF THE· RELATED DEViCES...................................................................................... 753
MOS Memories ........................................................................................................................................................ 754
TTL HD74 I HD74S I HD74LS Series ................................................................................................................ 756
Advanced Low Power Schottky TTL HD74ALS Series ............................................................................ 761
CMOS Logic HD 14000B I UB Series ............................................................................................................... ' .. 762
Linear ICs .................................................................................................................................................................... 764
Interface Circuits ...................................................................................................................................................... 766
CROSS REFERENCE ............................................................................................................................................ 767

NOTICE
The example of an applied circuit or combination with other equipment shown
herein indicates characteristics and performance of a semiconductor-applied
products. The Company shall assume no responsibility for any problem involving a
patent caused when applying the descriptions in the example.

GENERAL
INFORMATION
• Type and Package Information
• Reliability and Quality Assurance
• Design Procedure and Support
Tools for 8-bit Single-chip
Microcomputer
• HMCS6800 Family Instruction Set
.8-bit Microcomputers for Industrial
Application

5

6

TYPE AND PACKAGE INFORMATION
IDivision of Package Material I

The Hitachi Microcomputer LSI are classified into 3 types;
plastic mold type, side-brazed ceramic type and flat package,
according to the type of material and outline used for the package. Therefore, after taking into consideration the operating
environment and other conditions, please select the optimum
package. In regard to the types which have two package
materials, please define clearly when ordering the package
material code (C or P) (See the following table). As List of 8/16bit Microcomputer LSI Package shows, old type numbers are
changed from HD468XX to HD68XX (standard number). But
as for original products of Hitachi, the type numbers are not
changed.

Types which have side-brazed ceramic and plastic mold package.
Side·brazed Ceramic
Single-chip LSI
Multi-chip LSI

Plastic Mold

HD68XX~

HD68XX

HD68XX.f
"£ No indication

• List of 8/16-bit Microcomputer LSI Package

Clip Division

Type No.

Package *
PinNo.

C

P

40















HD6801 SO

-

HD6801S5

-

HD6801VO
HD6803

-

HD6803-1

-

HD6805S1
HD6805Vl

-

HD6805WO

-

HD6805XO

-

HD6301VO

-

40

HD63B01VO

-

40

HD6303

-

HD63A03

-

40
40

HD6801V5

HD6805Ul

8-bit Single-chip

Function

Old type No.

HD63A01VO

HD63B03
HD6333

-

HD63A33
HD63B33
HD63L05

-

HD68P01SO

-

HD68P01V05
HD68P05V05

-

HD68P05V07

-

HD68P01V07

40
Microcomputer Unit

40
40

Micro Processing Unit

40

40
28
40
40

Microcomputer Unit

40
64
40

Micro Processing Unit

40
40
40
60
40**
40**

Microcomputer Unit

40**
40**
40**

* The package codes of C, P, and F are applied to the package materials as follows.
C: Side-brazed Ceramic DIP, P: Plastic DIP, F: Flat Package.
*. EPROM on the package.

7





40





F

(to be continued)

TYPE AND PACKAGE I N F O R M A T I O N - - - - - - - - - - - - - - - - - - -

Chip Division

Type No.
HD6800

HD468AOO

HD68BOO

HD468BOO

HD6802

HD46802

HD6802W

-

HD6809

-

C

P

40






























40
40

Microprocessor with Clock
and RAM

40
40
40
40

-

HD68A09E

-

40

HD68B09E

-

40

HD6821

HD46821

HD68A21

HD468A21

HD68B21

HD468B21

HD6840
HD68A40
HD68B40

-

HD6843

HD46503S

HD68A43

HD46503S-1

HD6844

HD46504

HD68A44

HD46504-1

HD68B44
HD6845S

HD46504-2
HD46505S

Micro Processing Unit

40
40

40
Peripheral Interface Adapter

40
40
28

Programmable Timer Module

28
28

Floppy Disk Controller
Direct Memory Access
Controller

40
40
40
40
40
40

HD68A45S

HD46505S-1

CRT Controller

40

HD68B45S
HD6846

HD46505S-2
HD46846

Combination ROM 1/0 Timer

40

Asynch ronous Communications
Interface Adapter

24

HD6850

HD46850

HD68A50

HD468A50

HD6852

HD46852

HD68A52

HD468A52

HD46508

-

HD46508-1

HD146818

-

HD68000-4

-

HD68000-6
HD68000-10

-

HD68450

-

HD46508A
HD46508A-1

16-bit Multi·chip

Micro Processing Unit

Package*
Pin No.

HD6809E

HD68B09

8-bit Multi-chip

HD46800D

HD68AOO

HD68A09

Function

Old type No.

HD68000-8

40

Synchronous Serial Data
Adapter

24
24
24
40

Analog Data Acquisition Unit

40
40
40

Real Time Clock Plus RAM

24
64

Micro Processing Unit

64
64
64

Direct Memory Access Controller

* The package codes of C, P, and F are applied to the package materials as follows.
C; Side-brazed Ceramic DIP, P; Plastic DIP, F: Flat Package.

8

64



































F

- - - - - - - - - - - - - - - - - - T V P E AND PACKAGE INFORMATION
• Package Information (Dimensions in mm)
• Side-brazed Ceramic DIP

DC-24

N
W

o.•oo.••

DC-40

DC-28

W···

DC-40P (EPROM on the package)

o
19

H

~

o.• oo ...

I.tr""--~:;---,

DC-64

2
3
4
5

6
7

9
10
II
12
10
14

15

16

17

II
19

20

21
22
23
24
25

26
27

2'

29

30
31
32 'l---,--~~

I

22.56

Applicable LSIs
DC-24

HD6850, HD68A50, HD6852, HD68A52

DC-28

HD6840, HD68A40, HD68B40

DC-40

HD6801SOC, HD6803C, HD6800, HD68AOO, HD68BOO, HD6802, HD6809, HD68A09, HD68B09, HD6809E,
HD68A09E, HD68B09E, HD6821, HD68A21, HD68B21, HD6843, HD68A43, HD6844, HD68A44, HD68B44,
HD6845S, HD68A45S, HD68B45, HD6846

DC-40P

HD68P01SO, HD68P01V05, HD68P01V07, HD68P05V05, HD68P05V07

DC-64

HD68000-4, HD68000-6, HD68000-8, HD6800o-10, HD68450

9

TYPE AND PACKAGE I N F O R M A T I O N - - - - - - - - - - - - - - - - - • Plastic DIP

DP-24

:
R

DP-28

1.1.4

'S 24
.

2.S4mln

a·-IS'

_o20-038

I

DP-40

2.54min
5.06max

I--"""'J---'

OP-64
~

~
~
~

9

:~

'2
'l

'4
'5

I ~:l

~:~
~~
> ~~
56

~

53
52

5.
50

:t

::

20

45

..
.9

2.

~L~~
r-24
25
26
27

21
29
30
3.

47
46

~

..

:~

4.
40

39
31

37

36

35
34

321!=",=====""""""",~33--'L

Applicable LSls
DP·24

0.20-0.36

0'-'5'

HD6850P, HD68A50P, HD6852P, HD68A52P, HD146818P

DP·28

HD6805S1P, HD6840P, HD68A40P, HD68B40P

DP-40

HD6801SOP, HD6801S5P, HD6801VOP, HD6801V5P, HD6803P, HD6803P-l, HD6805U1P, HD6805V1P,
HD6805WOP, HD6301VOP, HD63A01VOP, HD63B01VOP, HD6303P, HD63A03P, HD63B03P, HD6333P,
HD63A33P, HD63B33P, HD6800P, HD68AOOP, HD68BOOP, HD6802P, HD6802WP, HD6809P, HD68A09P,
HD68B09P, HD6809EP, HD68A09EP, HD68B09EP, HD6821P, HD68A21P, HD68B21P, HD6843P, HD68A43P,
HD6844P, HD68A44P, HD68B44P, HD6845SP, HD68A45SP, HD68B45SP, HD6846P, HD46508P, HD46508P-l,
HD46508PA, HD46508PA·l

DP·64

HD6805XOP

10

- - - - - - - - - - - - - - - - - - T V P E AND PACKAGE INFORMATION

Flat Package

'-i

t

Applicable LSI

FP-60A

• Marking
There are two kinds of marking. One has a new ordering
No. (Case I) and the other has both new and old ordering No.
(Case II). They are listed on the List of 8/16-bit Microcomputer LSI Package. Case I is applied to the LSI which has

HD63l05

only new ordering No. listed in the List of 8/16-bit Microcomputer LSI Package and Case II is applied to the LSI
which has both Ordering No.

Case I (Indicated an ordering No.)

I. 'mOB

I

Case 111 (Example of marking on Single-chip)
(a)
(b)

.~~~

(C)BDB809B (C)B DB8DL1]S DB
O~B~r5J
~ DO
(n

(d)

Case II (Indicated a New & Old ordering No.)

'. mOB
(e)

B D~BBOBSB
(d)

(c)

D~B~r5J

Meaning of each mark
(a)

B DB8~BSB
11

Hitachi mark

(b)

lot Code

(e)

New type No.

(d)

Japan mark

(e)

Old type No.

(f)

ROM Code

RELIABILITY AND QUALITY ASSURANCE
1. INTRODUCTION

proved, recently their applications have been expanded to automobiles measuring and control systems, and computer terminal
equipment operated under relatively severe conditions.
ActuaUy, field application data has revealed that their failure
rates in a commercial environment are equivalent to those
of the hermetic sealed type.
However, in a view of reliability guarantee, the hermetic
sealed type passes a leak test 100%. Due to poor screening
technology, the plastic type may exhibit moisture absorption or
permeation inherent to their plastic materials.
Therefore, Hitachi recommends users employ the hermetic
sealed type for certain systems which require hjgh durability
against severe conditions, long service life and high reliability.
On the other hand, production output and application of
plastic molded type continue to increase.
To meet such requirements, Hitachi has considerably improved moisture resistance, operation stability, and chip and
plastic manufacturing process.
Plastic and side-braze package type structure are shown in
Figure 1 and Table 1.

Microcomputer is required to provide higher reliability and
quality with increasing function, enlarging scale and widening
application. To meet this demand, Hitachi is improving the
quality by evaluating reliability, building up quality in process,
strengthening inspection and analyzing field data etc ..
This chapter describes reliability and quality assurance data
for Hitachi 8-bit and 16-bit microcomputer based test and
failure analysis results. More detail data and new information
will be reported in another reliability data sheet.
2. PACKAGE AND CHIP STRUCTURE

2.1 Package
Packages are generally classified into 2 types; one is the
hermetic sealed type using metal or glass and the other is the
plastic molded type. Hitachi 8-bit microcomputer are produced
in plastic package or side-braze package.
Selection of package type should be done considering the
application, environment, reliability, cost and other factors of
the system.
The reliability of plastic molded type has been greatly im-

(21 Plastic

(11 Side-braze

Bonding wire

Figure 1 Package Structure

Table 1 Package Material and Properties
Plastic

Side-braze

Item
Package

Alumina

epoxy

Lead

Tin plating Brazed Alloy 42

Solder dipping Alloy 42

Seal

Au·Sn Alloy

N.A

Die bond

Au-Si

Au-Si

Wire bond

Ultrasonic

Thermo compression

Wire

AI

Au

12

- - - - - - - - - - - - - - - - - R E L I A B I L I T Y AND QUALITY ASSURANCE
2.2 Chip Structure
HMCS6800 family are produced in NMOS E/D technology or
low power CMOS technology. Si-gate process is used in both

types because of high reliability and high density.
Chip structure and basic circuit are shown in Figure 2.

Si·Gate N-channel E/D

Drain

Source

FET1

Drain

Si·Gate CMOS

SiO,

Source

Drain

Source

FET2

FET2

P-channel
EMOS

N-channel
DMOS

N-channel
EMOS

N-channel
EMOS

Figure 2 Chip Structure and Basic Circuit

3. QUALITV QUALIFICATION AND EVALUATION

3.1 Reliability Test Methods
Reliability test methods shown in Table 2 are used to qualify

and evaluate the new products and new process.

Table 2 Reliability Test Methods
Test Items

Test Condition

MIL-STO-883B Method No.

Operating Life Test

125°C,1000hr

1005,2

High Temp, Storage
Low Temp, Storage
Steady State Humidity
Steady State Humidity Biased

Tstg max, 1000hr
Tstg min, 1000hr
65°C 95%RH, 1000hr
85°C 85%RH, 1000hr

1008,1

Temperature Cycling
Temperature Cycling
Thermal Shock
Soldering Heat
Mechanical Shock
Vibration Fatigue
Valiable Frequency
Constant Acceleration
Lead Integrity

-55:C - 150:C, 10 cycles
-20 C"" 125 C, 200 cycles
0° C ,.., 100° C, 100 cycles
260° C, 10 sec
1500G 0.5 sec, 3 times/X, V, Z
60Hz 20G, 32hrs/X, V, Z
2D-2000Hz 20G,4 min/X, V, Z
20000G,1 min/X, V, Z
225gr, 90° 3 times

1010,4

13

1011,3
2002,2
2005,1
2007,1
2001,2
2004,3

RELIABILITY AND QUALITY A S S U R A N C E - - - - - - - - - - - - - - - - 3.2 Reliability Test Results
3.2.1 Dynamic Life Test

The reliability for chip design is evaluated by dynamic life
test. The test results of HMCS6800 microcomputer family are

shown in Table 3. Depend on these test results, the 70°C
failure rate is determined 0.007%/1000hrs (confidence level
60%, activation energy 0.7eV)

Table 3 Dynamic Life Test Result

Device

----

Sample Size

Component Hour

Failure

H06800
H06802
H06809
H06801
H06803
H06805

248
452
85
146
45
114

248000
153712
85000
146000
45000
114000

0
1
0
0
0
0

H06821
H06850
HD6852
H06846

399
158
170
69

266368
158000
125816
69000

1
0
0
0

H~~

00

~~

0

80
88
64
140

69000
55000
64000
140000

0
0
0
0

2324

1793896

2

- - - - -- -- - -- - - - - -- -- - - - -- - - - - -- - - - -- - - ---- -- ---- - ----- - ---- --- ---MPUTotal
1090
791712
--- -- ---- - - - -- - - - -- - --- -------- - - - - - -- - -- ---- -- ----- - -- ------- --- - ---

H06844
H06845S
H06840
H046508

--------------------------------------------------------------------Peripheral Total
1234
1002184
- - -- - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- --

-- - - - - - - - - - - - - - -- - Total

3.2.2 Temperature-Humidity Bias Test
o

The moisture resistance of plastic package is evaluated by

temperature-humidity bias test, 8S C/8S% RH biased condition. The result of this test is shown in Table 4.

Table 4 85°C/85%RH Bias Test Result

Device

Sample Size

Component Hore

Failure

MPU
Peripheral

132
226

132000
204000

0
0

--------------------------------------------------------------------------Total
358
336000
0
3.2.3 Storage Life Test

These tests evaluate the effect of storage at high temperature, low temperature or high humidity without bias.
(I) Plastic Package

Table 5 Storage Life Test on Plastic Package

Test Items
High Temp, High Humidity
High Temp, High Humidity
Presser Cooker
High Temp, Storage
Low Temp, Storage

Condition

Sample Size

65°C/95%RH, 1000hrs
80°C/90%RH,1000hrs
2atm 121°C, 100hrs
Ta = 150°C, 1000hrs
Ta = -55°C, 1000hrs

14

288
88
266
85
34

Failure

o
o
o
o
o

Vee = 5.2. 10sec 1500G 0. Z 60Hz. 500 cycles -55°C"" 125°C. Constant Acceleration Solderability -55°C"" 150°C. 1000hrs Temperature Cycling (1) Temperature Cycling (2) Thermal Shock Soldering Heat Mechanical Shock Vibration Variable Freq.20G 32hrs/X.. Vee = 5..4 Mechanical & Environmental Test Table 7 Mechanical & Environmental Test Results Plastic Side-braze Test Item Condition Temperature Cycling _55° C . 10 sec 1500G. Storage Low Temp. 100"" 2000Hz 3 times/X. High Humidity High Temp...l min/X. Lead Integrity Sample Size Failure 65 pins Sample Size Failure 3.. 5 sec 15 20 0 105 45 22 22 22 22 22 22 0 0 0 0 0 0 0 0 . Z 20G. 150° C 200 cycles O°C"" 100°C 10 cycles 826 110 1 0 359 175 0 0 260°C..5V 1000hrs Ta = 150°C.5V 1000hrs 30 20 0 0 High Temperature Storage Ta = 295°C.R E L I A B I L I T Y AND QUALITY ASSURANCE (2) Side-braze Table 6 Storage Life Test on Side-braze Package Condition Test Items High Temp.5 ms 3 times/X.. Y.150°C 10 cycles 4159 0 4920 1 Thermal Shock _55° C ... Y.. Z 230°C.Z 20000G.. 1000hrs Failure o o o 90 313 86 3.. 10 cycles -20°C"" 125°C.. 1000hrs Ta = -55°C. 2000Hz 20G 4 min/X... 15 cycles 26(t C.. Y. Y....... Z Bending Tention Fatigue 180 110 0 0 117 189 0 0 110 0 167 0 110 0 167 0 0 102 pins 0 Soldering Heat Mechanical Shock Vibration Fatigue Vibration Variable Freq. 5 msec 3 times/X. 1000hrs Ta = 150°C.. Y.3 Reliability Test Results on 16-bit MPU Table 8 Reliability Test Results on 16-bit MPU HD68000 (Side-braze) Test Items Operation Life Test (1) Operation Life Test (2) Condition Sample Size Failures Ta = 125°C. Y. Storage Sample Size 65°C/95%RH. Z 20 .

. Examples of control items are shown in Figure 3 and Figure 4.4... AC & Functional test External visual 100% visual inspection Lot acceptance Warehouse Test/Inspection process Production process QC and QA operation Figure 3 Quality Plan in Plastic Package Process 16 ....RELIABILITY AND QUALITY A S S U R A N C E .. QUALITY CONTROL IN PROCESS Process quality control plays an extremely important role in Process Flow quality assurance for semiconductor devices..... Inspection & QC Item Wafer process Probe test 100% Electrical test Dicing/Break Chip visual 100% visual inspection Die bonding Patroll inspection once/day/machine visual Wire bonding once/day/machine visul1l once/week/machine bond dimension bond strength Internal visual 100% visual inspection Molding Temperature cycling Lead trim & form Solder dipping External visual 100% visual inspection Mark Burn-in 100% Burn-in..... 125°C static Electrical test 100% DC.

. 10 cycles Leak test 100% Fine leak (He) 100% Gross leak (Bubble) Plating Lead cutting External visual 100% visual inspection Mark Burn-in 100% Burn-in.150°C....R E L I A B I L I T Y AND QUALITY ASSURANCE Flow Process Inspection & QC Item Wafer process Probe test 100% Electrical test Dicing/Break Chip visual Die bonding 100% visual inspection Patrol inspection once/day/machine Visual Wire bonding Patrol inspection once/day/machine visual once/week/machine bond dimention bond strength Internal visual 100% visual inspection Seal Temperature cycling 100%... 125°C static Electrical test 100% DC...... Condo -55°C .... AC & Functional test External visual 100% visual inspection Lot acceptance Warehouse 8o Figure 4 Quality Plan in Side-braze Package Process 17 Test/Inspection process Production process QC and QA operation ....

(7) Take care not to allow condensation during storage due to rapid temperature changes. work bench. etc. free from dust and active gas.. Regardless of the soldering method.. 6. (3) Store in a container which does not induce static electricity. voltage built-up is prevented by shorting terminal circuit. soldering iron. while the devices are being tested. prevent the conveyor belt from being electrically charged by applying some surface treatment.5 mm away from the end of the device package. Quality information from the users are indispensable to the improvement of products quality.. (3) When transporting the printed circuit boards on which semiconductor devices are mounted. (4) Store without any physical load. 6. for example. The recommended soldering. or not to apply any abnornal voltage through a bad contact from a current source. (1) Store in an ambient temperature of 5 to 30°C. Therefore. Storage in nitrogen gas is desirable. The resistor of about 1 M ohm must be provided near the worker to protect from electric shock. dark.. make sure that no soldering bridge or foreign matter exists before turning on the power switch.. measuring instrument. Take care not to allow curve tracers..1 %) Poor Functional Test Pattern (1. and appearance. If chloric detergent is used for the plastic molded devices. ity as the result of vibration during transportation.. namely. D. or breakage. too: To insure the reliability of electronic systems. Use of a strong alkali or acid flux may corrode the leads. the following considerations must be given.. package corrosion may occur. semiconductor-incorporating units and other similar systems. Especially.4 Soldering Semiconductor devices should not be left at high temperatures for a long time. (4) When transporting semiconductor devices or printed circuit boards. Unpacked devices must not be stored for over 3 months. It is desirable to use an electrically conductive container or aluminium foil. iron is the type that is operated with a secondary voltage supplied by a transformer and grounded to protect from lead current. solderability. (2) In order to prevent device breakage from clothes-induced static electricity. their terminals are left open to provide the possibility that they may be accidentally touched by a worker. residual flux must be removed from circuit boards.C. minimize mechanical vibration and shock. (2) Store in a clean air environment. The device will fail if it touches something which leaks current or has a static charge.. (5) If semiconductor devices are stored for a long time. workers should be properly grounded with a resistor while handling devices. bent parts may corrode during storage.. stabilizing power supply units etc. Failure analysis result on 8-bit microcomputer returned to Hitachi from April '80 to March '8] is shown in Figure 5. noise and surge-voltage when semiconductor devices are measured.. 6. suitable preventive measures against static electricity induction must be taken. take care not to apply surge voltage from the tester. If their lead wires are formed beforehand. 260°C for 10 seconds and 350°C for 3 seconds at a point I to 1. When inspecting a printed circuit board. Since cleaning over extended periods or at high temperatures will 18 . failure analysis is conducted and the results are quickly fed back to the design and production divisions. deteriorating device characteristics. contact Hitachi for further details. When a belt conveyor is used. general precautions for other electronic component parts are applicable to the transportation of semiconductors. dry.. store them in a cool.. PRECAUTION 6. when the devices are to be measured or mounted.3 Handling for Measurement Chip Visual (2. store them in the unfabricated form. Past field data on similar devices provides the basis for this estimation. Solder the leads at the farthest point from the device package. synchroscopes. field data on products delivered to the users are followed up carefully. QUALITY DATA FROM FIELD USE (1) Use containers or jigs which will not induce static electric- Field failure rate is estimated in advance through produc· tion process evaluation and reliability tests. Avoid static electricity.5 Removing Residual Flux As with storage methods. and in a relative humidity of 40 to 60%. On the basis of infprmation furnished by the user. belt conveyor.1 Storage It is preferable to store semiconductor devices in the following ways to prevent detrioration in their electrical characteristics. (6) If the chips are unsealed. It is possible to prevent breakage by shorting their terminal circuits to equalize electrical potential during transportation.. pulse generators. Detergent or ultrasonic cleaning is usually applied.5. Since these precautions depend upon the types of semiconductor devices. avoid miswiring and short-circuiting.0%) Figure 5 Failure Analysis Result 6. Assemble them within 5 days after unpacking. soldering must be done in a short time and at the lowest possible temperature. In addition. to attach a clamping circuit to the tester.. They can be stored for 20 days or less in dry nitrogen gas with a dew point at -30°C or lower.2 Transportation 6. During measurement. to leak current through their terminals or housings.RELIABILITY AND QUALITY A S S U R A N C E . However. and dustless place. Soldering work must meet soldering heat test conditions.

...... Lotus Solvent and Dyfron Solvent are recommended as a detergent....... the following conditions are advisable: • Frequency: 28 to 29 kHz (to avoid device resonation) • Ultrasonic output: 15W/~ • Keep the devices out of direct contact with the power generator. For ultrasonic cleaning... • Cleaning time: Less than 30 seconds 19 . select the type of detergent and cleaning condition carefully. Do not use any trichloroethylene solvent....R E L I A B I L i T Y AND QUALITY ASSURANCE cause swollen chip coating due to solvent permeation.

I n this case. LSI is testatively produced and the sample is handed in to the user _After the user has evaluated the sample and confirmed that the program is correct. the evaluation kit and the evaluation board. I shows the typical program design procedure and Table 1 shows the system development support tools for the HD6801 and HD6805 Family which are used in these processes. to generate the object program. The consumers are able to choose the best suitable tool. The company provides three kinds of hardware. mass production is started. to generate a source program.--- ------~ Evaluation Kit Evaluation Board H68SD5 EPROM on the Package H D68POl SO HD68P01V05 HD68P01V07 [ HD68P05V05 HD68P05V07 (Explanation) CD When the user programs the system. @A flow chart is designed to achieve the predetermined functions and the flow chart is coded by using the prenumeric code_ @ The coded flow chart is punched into the card or the paper tape or written into the floppy disk. Fig. the predetermined functions are assigned to the I/O pin and the RAM before the programming.DESIGN PROCEDURE AND SUPPORT TOOLS FOR 8-BIT SINGLE-CHIP MICROCOMPUTER The cross assembler and the hardware simulator using various types of computer are prepared by the company as supporting systems to develop user's programs. (j) Options such as ROM is masked by the company. @) The source program is assembled by the resident system (evaluation kit) or the cross system. ® The completed program is sent to the company in the form of EPROM or the object tape. ® Hardware simulation is performed to confirm the program. Text Editor ( CRT Editor Evaluation Kit H68SD5 Intel MDS IBM370 ® Cross Assembler Evaluation Kit H68SD5 Intel MDS IBM370 No -. errors during the assembling are also detected.------. Figure 1 Program Design Procedure 20 . H68SD5. User's programs are mask programed into the ROM and delivered as the LSI by the company.

..D E S I G N PROCEDURE AND SUPPORT TOOLS FOR 8-BIT SINGLE-CHIP MICROCOMPUTER Table 1 System Development Support T 0015 Resident System Type No......... Evaluation Kit HD6801S0 HD6801S5 HD6801VO HD680'tV5 Evaluation Board Cross System H68SD5 + Emulator Set (Hardware + Software) ~ IBM370 Intel MDS220/230 H61 EVT2* (Hardware) + H61 EVOO* HD68P01S0 H68SD5 + H61MIX1* 0 0 H61 EV01 * HD68P01V05 HD68P01V07 H68SD5 + H61MIX1 * 0 0 H65EVOO* HD68P05V05 HD68P05V07 H68SD5 + H65MIX1 0 H65EV01* HD68P05V05 HD68P05V07 H68SD5 + H65M I X 1 0 H65EV02* - H68SD5 + H65MIX2 0 H31 EVOO* - H68SD5 + H31MIX1 * H3L5EVOO* - H68SD5 + H3L5MIX1* S31 MIX·R (Software) H61 EVT2* (Hardware) + S31MIX1·R (Software) H65EVT2 (Hardware) HD6805S1 + S65MIX1·R (Software) HD6805U1 HD6805V1 EPROM on the Package H65EVT2 (Hardware) + S65MIX1·R (Software) H65EVT3* (Hardware) HD6805WO + S65MIX1·R (Software) HD6301VO HD63A01VO HD63B01VO H31 EVT1 * (Hardware) + 0 0 S31MIX1·R (Software) H3L5EVT1 * (Hardware) HD63L05 + S65MIX1·R (Software) * Under development 21 0 .......

.... The EPROM Writer and the second Floppy disk driver are optionally available. Emulator and EPROM Writer controlled by FDOS·1I1 • 56k·byte RAMs • Allows linking between the H68SD5 and the I/O devices • Easy to debug user's prototype system using the Emulator (TTY and Printer) Features • • Supports the system development for 8·bit and 4·bit single Module chip microcomputers ... series. Assembler.FOR 8-BIT SINGLE-CHIP MICROCOMPUTER • Single. Disk based low cost system • Provides the CRT Editor...chip microcomputers.. It is an all·in-one type compact HD6800 based CRT/Key board microcomputer terminal with one Floppy disk driver and has standard interface for the TTY (RS·232C or TTL level) and printer (Centronics parallel interface).....Chip Microcomputer Development System The H68SDS is a development system for Hitachi 4·bit and 8·bit single.HD6801/6805 family and HMCS40 System Configuration H68SD5 FDD* FDD EPROM Writer* HD6801/6805 familY} Emulator Module* { HMCS40 series * Option 22 ..DESIGN PROCEDURE AND SUPPORT T O O L S .

.-J :2 w ~ :2~ O~ w _ 0 O~ w _ 0 ZX w _ 0 zX:2 zX :2_w _ w :2 _ZX w :2 _w :2 _0 _ _0: :2~ _0: :2~ _0: :2~ A+B--A Subtract Double Subtract with SBCA Carry SBCB Multiply MUl Decimal DAA Adjust A w HD6301V EORA EORB Complement COM 1's COMA COMB Complement NEG 2's (Negate) NEGA NEGB . 0 00 o O-+Q 00 OO!O Q.-..HMCS6800 FAMILY INSTRUCTION SET . Bit Test BITA BITB 00 00 0 0 0 00 00 0 0 0 00 00 00 00 00 00 00 00 00 00 0 0 00 0 00 0 0 00 00 00 00 00 00 00 00 0 00 00 0 0 0 00 0 0 00 00 00 00 00 00 00 00 00 00 0 0 0 0 00 0 00 00 00 00 0 0 00 00 00 00 0 0.-J ~o ~O x~ w w:2 o~ ww X:2 :2 _ 0:_ _0: o~ w 00 00 0 HD6809 HD6809E 01-0 00 00 0 0 00 00 00 00 0 0 00 000 .._-00 000 00 000 0 A-B 0 0 TST TSTA TSTB ANDA ANDB M-OO A-OO B-OO A'M--+A B· M--+B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 0 0"0 0 00 000 00 00 0 ORAA ORA A+M--+A 00 00 00 00 00 00 00 00 00 00 00 00 0 B+M--+B 00 00 00 00 NBM--+A BG3M--+B M--+M A--+A -S---+B OO-M--+M OO-A--+A OO-B--+B A·M B ·M 00 00 00 00 00 00 00 0 00 bo 0 00 00 0 00 00 ORAB ORB Exclusive Or 00 00 00 00 00 00 00 00 00 00 00 00 Decimal Adjust Accumulator M+1--+M A+1--+A B+1--B M-1--+M A-1--+A B-1--B O--+M O--+A O--B A-M B-M J w CMPD A:B-M:M+1 Compare Accumulators CBA Test Zero or Minus 00 00 00 00 00 00 A-B--+A A-M-C--+A B-M-C--+B AxB--+A:B w HD6800 HD6802 HD6802W HD63l05 > O~ O > O~ O > O~ o~ X Z x O x Z -J~ wU wU w Z -J~ wU -J~ wU o~o. -J:2 ~o.-J o..t-- + (to be continued) 23 . w ZI-J :2 w w o...Accumulator and Memory Operations HD6805S HD6805U HD6805V HD6805W HD6801S HD6801V HD6803 Operations Mnemonic Booleanl Arithmetic Operation Add ADDA A+M--+A ADDB B+M--B Add Double A:B+M:M+1 ADDD --+A:B Add Accumulators ABA Add with Carry Subtract ADCA ADCB SUBA SUBB A+M+C--+A B+M+C--+B A-M--+A B-M--+B A:B-M:M+1 SUBD --+A:B Subtract Accumulator SBA Increment Decrement Clear Compare Compare Double INC INCA INCB DEC DECA DECB ClR ClRA ClRB CMPA CMPB And Or 00 00 00 00 w ~O <w -J:2 w:2 0:_ 00 00 00 00 00 00 00 DO 00 00 00 00 00 00 00 00 0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0 00 00 00 00 00 00 00 000 00 000 00 000 00 00 00 00 0 0 0 0 00 00 0 00 0 0 00 00 00 00 00 0 00 00 0 0 00 00 0 0 00 00 00 00 00 00 0 0 0 0 0 0 00 00 00 00 00 00 00 00 0 0 0 0 00 000 00 000 0 00 00 00 0 0 00 00 00 00 0 0 0 0 000 000 000 000 0 00 00 0 00 00 00 00 00 00 000 0 00 w 0 0 00 00 ~ w > ~O ~x 0 0 ~x 0 U w Z-J <w U w ZZ -J~ ~o.-J :2 w O~ o.

1-------------- --.1--I--....._------ Shift Left Arithmetic ---------- Shift Right Arithmetic PUlU MU->RLJisters U+n-> ---- ASL 'A"SLA ~LB ASLD 'ASR-- ASRA 1------ tsLBlSR lSRA ~- A B 00 CI:iSJ--o ! RORB 0 0 0 00 00 0 0 00 0 0 0 00 00 0 0 0 0 00 00 00 0 0 0 0 MSB LSB 00 00 0 0 0 I'~ MSB LS6 C A:B ROl ROlA -----ROlB I-c-------. _ .._--.------------....---------... Bit (n) $<. _------_...-J ~w _0: 01- O wU X w Z ~~ 01_ w ~_ 0 zX > -J~ Il......1------- Registers-+Ms PSHS S--n->S 0 ----.._--..------ PSHU Registers-+Mu U-n->U ----~----- Pull Data 0 ---------1-- Ms->A S+1->S PULA ---- 0 0 0 0 0 0 -~----.-J ~w _0: > 01- X O wU w Z ~w 01~!:!: _ 0 ZX _w i= U w -J<t Il.1--------- Shift Left logical "r'M-l A B A:B I 0 I : l~ : l~ I--.-------...........HMCS6800 FAMILY INSTRUCTION S E T .-J ~w _0: 0 0 BelR n O->M ...-J zX _ w ~~w _0: 0 0 0 into A r...-J ~w _0 _0: ~!:!: ~w w e: > OlO wU X w Z ~-J~ 01.-----load lDAA M->A lDA 1----- 00 00 ------ Store 00 00 00 00 00 00 00 00 T06..1----- Shift Right logical o-cC:::rJ.- Ms-+B S+ 1->S PUlB -..1------Rotate left 00 0 0 0 1-- LS8 M C 0 00 MSB LS8 C MT .I--- 00 00 00 0 00 0 0 00 00 0 0 0 00 0 0 0 0 0 00 00 0 0 00 00 0 0 00 00 0 0 00 00 0 0 0 00 00 0 0 0 0 0 00 00 0 0 0 0 (to be continued) 24 ...- 00 00 STAA A->M STA 000 STAB STB B->M 000 000 A:B->M:M+ 1 000 000 --- ....Rotate Right ROR --RORA ----- 00 0 00 00 00 00 0 0 0 00 ~o C 00 0 0 0 LSRD ...... -_ .. - 00 00 f----- SID Transfer 00 00 -...---------------.....-Sign Extend B w w 01- O wU X w Z ~w 01~!:!: _w _ 0 zX > -J~ Il.B--+A TBA 00 00 0 TFR 0 0 f-=-------------....-_.0 C MSR A B ASRB lSl 1-----lSlA A B 1 ..- Ms->Registers S+n-+S PUlS _.----..._ . Bit(n) BSET-n '-->M ..1-----------..1-----------------A--->B TAB '=------....----~- lDAB M->B LDB Register 1 ->Register 2 EXG ------- 0 0 0 0 - 0 ..I-Il.HD6805S HD6805U HD6805V HD6805W HD6801S HD6801V HD6803 Operation Bit Clear Bit Set 1---------- Boolean/ Arithmetic Operation Mnemonic HD6301V HD6800 HD6802 HD6802W HD63l05 HD6809 HD6809E I- w w 01- X O wU w Z ~~ 01_ w ~_ 0 zX > -J~ Il.-J ~w _0: w 01- X O wU w Z ~w 01~!:!: _ W _ 0 zX > -J~ Il. ....1----- Exchange Push Data 00 000 00 00 00 000 000 00 000 000 000 000 00 00 000 00 00 Register 1 -+Register 2 --...~~M+ 1->A:B 00 00 .... A-+Ms PSHA S-1->S 0 0 0 B->Ms S-1->S 0 0 0 ------ PSHB ._---_ ..I-..--------....

..:.-1 01-0....- I I HD6800 HD6802 HD6802W HD63l05 HD6301V II w w I > 01.V)= 1 0 0 0 BHI 'lBHI Branch if Higher BHS or same(unsigned) 'lBHS BlS Branch if lower or Same Branch if lowe BlO (unsigned) 'lBlO BPl Branch if Plus BMI Branch if Minus 'lBMI BVC Branch if I Overflow Clear lBVC .-...0. -I~ a:0 1-0....-1 xx~w o~ ww_a: 00 00 00 00 M·IMMED->M M+MMED->M MlJIMMEO->M 1----M·IMMED .-1 ~UJ 01.. -I~ a:0 1-10.~- Boolean/ Arithmetic Operation HD6805S HD6805U HD6805V HD6805W -.-1 ~~~I...0..--- HD6801S HD6801V HD6803 '--.O ~ X Z 15 -I~ wU ~-I ~ ~w w 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -..----.-I ~-zx~w _O_w_a: HD6809 HD6809E I- w W!U w w 0 0 0 0 0 C=1 0 0 0 0 0 Z=1 0 0 0 0 0 tBNE- Z=O 0 0 0 0 0 BGE 'lBGE BGT N(t)V=O 0 0 0 Z+(N(£...~-Test Immediate TIM ~--.X 01 ~o I-x 0 O X wU wU X wU wZ-I !. -I w~!:f zX ~!:f zX ~w zX ~~ w _w_ a:_0 _0 zx~ _w ~w _a: ~-zx _o_w ~w _a: ~!:f _a: ~!:f _0 _w _ 0 _w a: ~w C=O Branch if Carry Clear I- u > > 01.- w I ~ JI.i..BVS Branch if Overflow Set lBVS C+Z=O 0 Branch if Half BHCC Carry Clear H=O Branch if Half BHCS Carry Set H=1 Branch if Interrupt BMC Mask Clear 1=0 Branch if Interrupt BMS Mask Set Branch if Interrupt BIH Line High ~~ Branch if Carry Set UcS lBCC BCS BEQ lBEQ Branch if Not BNE Equal Zero Branch if=Zero f--- Branch if. ~ 01.( -I~ w~ a: _ a:0 1-1-0.-...... -I ~w 01.... ~w 01-0.-..1-0.O ~o o ~ 0101..-1 ~!:f ~!:f x~w ~!:f _w ~w w~ w_ a:_ _a: _0 ~GS~ _0 _zx~ o~ GS~ ~~ o~ w_a: _0 zX w w HD6809 HD6809E w &3 1 w !:E > ~O I-x OC !..( wZ-I -I~ w ~w ~w 01-0.(w I-x Z Z-I!...(w ~w Z~-I!....Jump and Branch Instructions HD6801 S HD6801V HD6803 r----r--r~-.- Operations Mnemonic Branch Test olJ HD6805S HD6805U HD6805V HD6805W HD6301V H06800 H06802 H06802W HD63l05 -..N8:N= 1 Branch if.(w ~w Z-I !.( ~a:ol-o....Zero f-CBLE lBlT BlE Branch if Higher ULS UwL 0 0 0 C+Z=1 0 0 0 0 0 0 C=1 0 0 0 C=O N=O 0 0 0 0 0 N=1 0 0 0 0 0 V=O 0 0 0 V=1 0 0 0 0 0 0 0 0 0 1=1 0 0 INT=1 0 0 I w -I~w 01.....V)=O 0 0 0 0 0 0 Z+(N(£...O > o 1-' 10 w > ~ 01O X Z -I~ wux z -I~ 01wU GS~-I wU X Z 10 w ~ GSIZ -I !..GZero Branch if>Zero 1---- LBGT Branch if<Zero BlT ...H M C S 6 8 0 0 FAMILY INSTRUCTION SET Operations Mnemonic And Immediate AIM OR Immediate OIM EOR Immediate ElM f .0..I----- (to be continued) 25 ....0.

-J :!:w 01.O ~ 01...xio 01 11= 0 W ~ w'ZI~I-JI< :!:~ol-Q.25 Z _WjW _.. --- W-t+-~+rff: +..-Il--D C MSB MSB Shift Right logical lSRX LSB LSB C ~-rr:=::IJ._ a:_ _0 _ZX:!: 0 0 0 0 0 BRA laRA Branch Never BRN taRN Branch to Subroutine Jump Jump to Subroutine W > 01.Q.-J _ w :!:w zX ZX :!:w _0 zX _a: :!:~ _w :!:w _a: :!:~ _0 _w _a: BranchifBitnof BRCLRr M(n)=O MClear Branch Always H06809 H06809E I- 8ranch Test 01wU :!:w :!:~ _0 Branch if Interrupt Bil UneLow H06800 H06802 H06802W H063l05 H06301V W W > 05 1= ZZ -J< I-j: Q.Q.l-J W :i!: _ ~ 0 ~IXI:i!: _ w.. -J:i!: ~w ~o I-Q..---t-l i - '- I I I i I I iii ! i (to be continued) 26 ..a MSB LSB C HD6301V ------.-J Increment Decrement ADD with B Clear Negate Complement 1's Shift left Arithmetic Shift Right Arithmetic INX DEX ABX ClRX NEGX COMX X+ 1---X X-l---X B+X---X O---X OO-X---X FF-X--X ASlX o..r - w ~ JI- 0 HD6800 HD6802 HD6802W HD63l05 wU~z-J!..-J :i!: IX: 0ll-il-lQ.-J W 01- -'rrr: ~ frli1S ~I..-J :i!:~ol-Q.(w WW :!:w ~~-J ol-Q.--.-J ~i'J') :i!:w ~ -~ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .~ :i!: .-0 0 0 0 0 t---fc) 0 0 -0 0 0 0 0 0 ..( HD6809 HD6809E -r-T-.Q.0 (5 0 JMP 00 000 00 000 00 00 00 JSR 000 000 000 000 00 00 00 RTS 0 0 0 0 0 0 NOP SWI SWI2 SWI3 0 0 0 0 0 0 0 0 0 --~ " - RTI 0 WAI CWAI 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYNC SlP 0 .t r It+~ 0 0 I 0 0 0 10 i jI ! I I I I I .....J W W ~o I-x 0 ~o I01uX wU ~w Z-J !...--..a:==IJ-o ASRX CiJ::=.r---r--r-...~ 0 0 0 0 0 -.O > O X X Z -J~ wZ -J~ wU X wZ -J~ wU w 01.( a:ol-Q.-'-r-.( 0 ~ t1SZ~!( :!:~ol-Q...H06805S H06805U H06805V HD6805W H06801S H06801V H06803 Operations Mnemonic W W INT=O Branch if Bit nof BRSETn M(n)=1 MSet Re~urn from Su routine No Operation Software Interrupt Return from Interrupt Wait Synchronize to Interrupt Sleep BSR LBsR (.[ ~ 2!: 01- 0 wU~z-J!.HMCS8800 FAMILY INSTRUCTION S E T ..._ IX: X"x'i:i!: W ~25~~~~ ~25~~~~ ~25~~~~ ~ 25 ~ ~ ~..-- - I I~ll~ 2!: o I. -J:i!: ~o :!:~ _ 25~ w:i!: 25~ w_ w:i!: x:i!: a: w..-J :!:w 01.---r.ndex Register and Stack Pointer Instructions HD6805S H06805U H06805V HD6805W HD6801S H06801V HD6803 Operations Mnemonic Boolean/ Arithmetic Operation 01- 0 w ~ 01- ~~~Z-J!..-.

1 C ~ISH ISH TSTX X-OO CPX CMPX X-M:M+ 1 CMPY Y-M:M+ 1 LDX M:M+1---X LDY M:M+1---Y STX X---M:M+1 Y-M:M+1 STY LEAX LEAY 0 I c--. it 00 ~~~~~~:---U I t1 L I -- TG6x ACCD<-+X - 00 00 tt-j 00 00 I ......A TAX f-.- I 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I 0 0 .-_:o.0---1 (to be continued) 27 .-- Lou 0 10 I I 000 00 t---- I 0 -- () I __ ! 00 000 00 000 00 000 00 000 00 00 00 00 f 0 I .J ~~~~c[~ :Ea:o~~~.J -Iz X :E w ~-zX:Ew _O_w_a: _O_w_a: ~o~~GS~~ ~ °l~ ~ ~ ~ ~o~~~~ ~ 0 ~ ~I~ ~ :E Shift Left Logical D-U~ =:])--0 LSLX C MSH 0 01 LSH I f--- Rotate Left ROLX c.- ~fJ~~~~:---x t 00 00 00 00 00 00 I 0 .- 00 00 00 00 f-------.J~ wU~z..J a:o~~.JI~ r--'-~~~~- w o~ :Ea:o~~.. ~x X---A Transfer X.J o~ 2: 0 :E~o~~.... -i-if --to '0 00 I f- i ~~~~~~:---Y ~- I 00 00' 000 ....- 00 00 m-- Exchange I ' f--- Push PSHX X---Ms r-:--:-----Pull PULX Ms---X Transfer X..Boolean monic Operation CLC ~~~~lnterruPt CLI O---C -------_._. LEAU 00 100 00 0 - 000 +- 000 f--- .Condition Code Register Instructions HD6801S HD6801V HD6803 Operations Clear Carry HD6301V HD63L05 HD6800 HD6802 HD6802W HD6809 HD6809E Mne.--.f-00 00 (5 00 00 00 00 00 00 -- 000 ~ 0 I 0 10 I 0 0 0 -- 0 0 i ... ..S---M:M+1 Store U---M:M+1 -STU I Load effective Effective LEAS Address ---S Address '----- -=----_.QOO -f--- ~ 00 000 00 000 00 00 0 f--.:~:rr----=n:: C MSH I 10 LSH ...J~ ~~~Z..J~ w ~ ~ z ~ .. ~ Iw :rr~rT w ~ > o ~ 0 ~ i2: 0 2: O i= I Iw °IUX 0>-1 01 ~ ~~~Z.J-o:=._-- 0 I Rotate Right RORX Test Compare Load StC>re ~ective Address !..J~ w~~z...S TSX S---X TXS X---S Increment INS S+1---S S-1---S Decrement DES Reset RSP $7F---S Compare CMPS S-M:M+ 1 CMPU U-M:M+ 1 LDS Load M:M+1---S 00 M:M+1---U c--STS-......J a:o~~.H M C S 6 8 0 0 FAMILY INSTRUCTION SET HD6805S HD6805U HD6805V HD6805W HD6801S HD6801V HD6803 Operations Booleani Arithmetic Operation Mnemonic r-r-rrn0>-1 0 ~ HD6800 HD6802 HD6802W HD6301V HD63L05 f---~I~~I~ --'l--~rT- HD6809 HD6809E 0.

-J ~w 01....- w > w > > -:--r-r-r--r- - I~ I X O HD6809 HD6809E .- r-':I-~~~~--..Q. -. Accumulator! RELATiVE Relative 28 ~ g. w > O o X Z ~-J~ w 01.c---1-+V SEV TAP A-+CC ~PA "CC-+A c--------------. CC 0 0 0 0 0 0 0 0 LEGEND S U + + <!> M Ms Mu CC Accumulator A Accumulator B Index Register Index Register (6809 only) Stack Pointer User Stack Pointer (6809 only) Transfer into Arithmetic Plus Arithmetic Minus 800lean AND 800lean Inclusive OR Boolean Exclusive OR Connection Area Complement of M Stack area pointed by S.-J ~w 01.~.-J ~w ~2: ~2: ~w _ _0 zX _w ~w _a: ~2: _ 0 ZX _a: ~2: _w ~w _w ~w _a: ~2: _ 0 ZX _w _a: _a: ~2: _ 0 zX 0 zX _w ~w _0 Clear Overflow O-+V 0 r~et C~. Condition Code Register 0 0 0 0 0 0 'DRce A B X y 0 Half Carry from 3 bit H Interrupt Mask I Negative N Zero Z Overflow V Carry Bit from 7 bit C Most Signification bit MSB Least Signification bit LSB Immediate IMMED Direct DIRECT Indexed INDEX EXTND Extended EXT INDIRECT Extended indirect IMPL Implied (Inherent.c rsEc 0 0 0 0 1-+1 SEI ..- w w Boolean Operation > HD6800 HD6802 HD6802W HD63l05 HD6301V -r---T--r--r" ---1-.--.Q..Q.--.Q.!:L ___ 1--'---..And CC ~DCC CC·imm-+CC -6r-CC-CC+imm-->CC 0 0 0 0 ClV '--=:----~----- Set Interrupt Mask -------Set Overflow f----------Transfer A.-J ~w 01.J i= -J~ wU w Z Q.-r---r--r-..-J « wU w Z -J~ wU w Z -J~ wU w Z -J~ wU ~w 01~w w 01..~Q..-J zX _w w~~ . Stack area pointed by U..HMCS8800 FAMILY INSTRUCTION Operations Mnemonic SET-----------------HD6805S HD6805U HD6805V HD6801S HD6801V HD6803 -._..--.--r ---T----r~ 01010101o~ o~ O X O X O X O wU X Z .....-.

25V -40 .25V -40 .5V --40-+85°C 1.+8SoC DP-40 HD6809EPJ* HD68A09EPJ* HD68B09EPJ* Advanced Micro Processing Unit SV ± 0. 8·Bit programmable timer with 7·Bit programmable pre-scaler.1 64 20 8""" No 2 96 32 8""" No 4 4 2.25V -40 .25V ± 0.25V -40 .a-BIT MICROCOMPUTERS FOR INDUSTRIAL APPLICATION For industrial application which needs wider operating temperature range (from _40°C to +8S°C). So refer to each data sheet for details .25V ± O.5.25V ± O.0V -40 . Other Features HD6801S0PJ HD6801SOCJ NMOS DP-40 DC-40 5V ± O.25V i O.+8SoC DP-40 HD6840PJ HD68A40PJ HD68B40PJ Programmable Timer Module SV ± 0.25V ( Analog Input) 0 . "1" indicates industrial grade devices (Example HD6801 SOPJ).5V --40-+85°C 5V ± 0.25V -40 .2mA 10mA 2 128 29 16 Yes • Data Retention Capability 2.* 29 .5V -40-+85°C 800mW 5.2V 1.25V -40 .2mA 10mA 128 13 16 Yes • Multiplexed Address and Data • Vectored Interrupts • Self-<:heck Mode • Master Reset 4 96 32 S""" No • Voltage Comparator • Vectored Interrupts • Self-<:heck Mode • Master Reset • Voltage Comparator • Vectored Interrupts • Self-<:heck Mode • Master Reset • • • • 128 96 29 29 16 8"""x2 No Yes • Sleep Voltage Operation Comparator • Low power Vectored Interrupts Consumption Self-check Mode Master Reset * Preilmlnaly ".25V --40-+85°C HD6801VOPJ 2.+8SoC DP-40 Analog Data Acquisition Unit SV ± O.+8SoC DP-40 HD6809PJ* HD68A09PJ* HD68B09PJ* Advanced Micro Processing Unit SV ± 0.2V 1.+8SoC DP-40 HD6821PJ Peripheral Interface Adapter SV ± 0.25V -40 .+8SoC DP-40 HD6802WPJ Micro Processor with Clock and RAM (2S6 byte) SV ± 0.25V --40-+85°C HD6805S1PJ HD6805U1PJ HD6805V1PJ HD6805WOPJ" NMOS NMOS NMOS NMOS HD6301VOPJ" HD63A01VOPJ* CMOS DP·28 DP-40 DP-40 DP-40 DP-40 5.+8SoC DP-40 • Under development Electrical Characteristics shown here is for the industrial grade which is differant from standard specification.+8SoC DP-40 HD6802PJ Micro Processor with Clock and RAM (128 byte) SV ± 0.25V -40 . Process Package Vee Topr Electrical" " Characteristics Memory c 0 . • 8-BIT Multi-chip Microcomputer Characteristics Electrical Characteristics· * Type No.+8SoC HD46508PJ HD46S08PJ-1 HD46S08PAJ HD46508PAJ-1 1000mW DP-40 Analog Data Acquisition Unit SV ± O. Hitachi has the following devices for both the 8-bit single-chip microcomputers and the 8-bit multi-chip microcomputers.5V --40-+85°C 800mW 5.S.25V (AnalOg Input) 0 .OV -40 .25V --40-+85°C HD6803PJ HD6803CJ NMOS DP-40 DC-40 5V ± 0.2V 1. Electrical Characteristics shown here is for the industrial grade which is different from standard specification. Function Vee Topr Package Po HD6800PJ Micro Processing Unit SV ± 0.+8SoC DP-28 HD6846PJ Combination ROM 1/0 Timer SV ±0.5V --40-+85°C 800mW 5. .2mA 10mA 4 128 29 16 Yes • Data Retention Capability NMOS DP-40 5V ± 0. ••• Timer. • 8-BIT Single-chip Microcomputer Characteristics Type No.~ Po V1H IEXTAL) IlinIIEXTAL) ISBB ROM (k Byte) RAM (Byte) I/O Timer (bit) SCI u.

30 .

DATA SHEETS 8-BIT MICROCOMPUTE HMCS6800 SINGLE-CHI SERlE 31 .

Specifications and information are subject to change without notice. Advance Information data sheets herein contain information on a product under development.Preliminary data sheets herein contain information on new products. 32 . Hitachi reserves the right to change or discontinue these products without notice.

The HD6801S MCV is TTL compatible and requires one +5...chip microcomputer or be expanded to 65k words. The HD6801S MCV has 2k bytes of ROM and 128 bytes of RAM on chip.I.C.25 MHz .) Object Code Compatible With The HD6800 MPU • • 16-Bit Timer Single Chip Or Expandable To 65k Words • • 2k Bytes Of ROM 128 Bytes Of RAM (64 Bytes Retainable On Power Down) (DP-40) • 29 Parallel I/O Lines And 2 Handshake Control Lines • Internal Clock/Divided-By-Four Circuitry • TTL Compatible Inputs And Outputs • Interrupt Capability • Compatible with MC6801 • (DC·40) • PIN ARRANGEMENT BLOCK DIAGRAM Vee POl PO' ---.0 volt power supply.Jr. The H06801S MCV is object code compatible with the H06800 with improved execution times of key instructions plus several new l6-bit and 8·bit instructions including an 8x8 unsigned multiply with 16-bit result..._ _ _ _ _ _. I-----p" TYPE OF PRODUCTS MCU t----Pp 33 Bus Timing HD6801S0 1 MHz HD6801 S5 1.I.HD6801S5 MCU (Microcomputer Unit) The H06801S MCV is an 8·bit microcomputer system which is compatible with the HMCS6800 family of parts.HD6801S0. and parallel I/O as well as a three function 16-bit timer.).C..Vee Standby (Top View) t-----Pto I:===::~:~ • t-----Pu 1:===:: ~:. The HD6801S MCV can operate as a single . Features and Block diagram of the HD6801S include the following: HD6801S0P HD6801S5P • • FEATURES Expanded HMCS6800 Instruction Set • • • 8 x 8 Multiply On-Chip Serial Communications Interface (S. Serial Communications interface (S..

5 V 1. P47 . RES Ilinl Three State (Offset) Leakage Current PIO -P I7 .4V = -205 J.P37 . Ta = 25°C.4 2. Normal operation should be under recommended operating conditions.0 "Except Mode Programming Levels..l.0 Powerdown V SBB 4.4V V in = 0. HD6801S6---------------------------------------------• ABSOLUTE MAXIMUM RATINGS Item Vee V in Input Voltage Operating Temperature Unit V -0. E.P17 Power Dissipation P30 .0 - 10.0 MHz min typ max Unit 4.0 Symbol Supply Voltage Symbol RES Allinputs* Input Load Current P40 .l. SC 2 Other Outputs Output "Low" Voltage Input Capacitance Vee Standby Standby Current Test Condition V IL All Outputs IITslf Vin = 0.. IRQI.3 - Vee 0.5 J.0 - -0.0 mA mW - - 1200 - - 12.P47 SCt EXTAL Ilinl Input Leakage Current NMI.l.+7.P37 P40 .0 Operating V SB 4. it could affect reliability of LSI.5V I LOAD V OH VOL Darlington Drive Current PlO .5 - 0.A - V 2.5 - 2.75 - 5.25 Powerdown ISBB - - 8.P24 P30 .55 -+150 °c With respect to VSS (SYSTEM GND) (NOTE) Permanent LSI damage may occur if maximum ratings are exceeded.2. unless otherwise noted.) V 1H Other Inputs* Input "Low" Voltage Output "High" Voltage =0 - -loH I LOAD Po - P47 ..0 0 -+ 70 V °c ..0V 5. If these conditions are exceeded.8 mA 2.1.25 pF V mA .HD6801S0..A 10 100 J.0V±5%. SCI.5 - - 10.4 2.8 V - - 0. P40 Other Inputs o +70 C.P 30 -P 37 P20 .6 mA V out = 1. Vss = OV.Vee = 0"" 5.0 Vee V 2. 34 V SBB = 4.3 .25V V in V in = 0.l.+7.A I LOAD = -100 J.4 - - 0. Ta Item Input "High" Voltage - • • Topr Tstg Storage Temperature • Value -0. • ELECTRICAL CHARACTERISTICS • DC CHARACTERISTICS (Vee =5. SCI Cin Vin f = OV.A = -145J.8 0.A I LOAD = 1. = 1.3 .

-- +70°C. 6 200 - - ns tlH Fig.8 10 . 10 -- ~ 50 - Fig.) Symbol Cycle Time Test Condition HD6801S0 typ max 10 1 200 min Address Strobe Pulse Width "High" tCyc PW ASH Address Strobe Rise Time tAsr 5 Address Strobe Fall Time tASf tASD tEr tEf PWEH PW EL 5 60 Address Strobe Delay Time Enable Rise Time Enable Fall Time Enable Pulse Width "High" Time Enable Pulse Width "Low" Time Address Strobe to Enable .4 ns ns . Ta =0 - - 225 80 10 20 60 - (tACCN) (tACCM) i HD6801S5 typ max 0.* Port 2**. - Symbol Item . 3 Port 1. 6 50 - Fig. 3. 150 5 50 min ns . 2. Ta =0 - Item +70°C.. unless otherwise noted. Enable Positive Transition to 0S3 Positive Transition tos02 Fig.Delay Time Address Delay Time Address Delay Time for Latch (f = 1. Vss =OV.-"--m - - 200 Input Strobe Pulse Width - ns ns - 200 Fig. 5 Delay Time. unless otherwise noted.. 11 =5. 3 Delay Time.s tPWIS Fig. 2.------------------------------------------------HD6801S0.3. 1 Fig.4 - - 400 ns tCMos Fig.2 tRC tpcs 50 - 50 50 - - - - - - 260 270 - - - - 20 20 - - - - - (610\ (600) - - - - - _..3.'---ns Unit tposu t pOH Port 1. Vss =OV.0V±5%. HD6801S5 • AC CHARACTERISTICS BUS TIMING (Vee = 5. Enable Negative Transition to Peripheral CMOS Data Valid 50 50 - Fig.) Test Condition Peripheral Data Setup Time _.C--- - 200 5 30 - - Fig.4 tpwD .0MHz) Data Set-up Write Time Data Set-up Read Time Read Data Hold Time Write Address Set-up Time for Latch Address Hold Time for Latch Address Hold Time I J I Non-Multiplexed Bus Multiplexed Bus Oscillator stabilization Time Processor Control Set-up Time Peripheral Read Access Time I PERIPHERAL PORT TIMING (Vee tASED tAD tAOL tosw tOSR tHR tHW tASL tAHL tAH 5 5 450 450 60 - Fig.0 p.4 - - 2. 2*.- 5 5 340 350 f---. 6 20 - - ns Delay Time. 4 o· ns max min Peripheral Data Hold Time iJ~ -. Enable Positive Transition to 0S3 Negative Transition tOS01 Fig..•.0V ±5%. Enable Negative Transition to Peripheral Data Valid Port 1. 5 - Delay Time. 4 Input Data Hold Time port 3 Input Data Set-up Time Port 3 tiS -Except P21 ns ns ns ns ns - 260 260 - 115 70 10 20 50 115 -. - - ns - - 20 20 - - ns ns - - ns - - - - (410) (400) m - 100 - - - 200 - - ms ns typ - ns ns - 350 ns - - 350 ns Fig. -30 - - 100 50 - --10kO pull up register required for Port 2 35 Unit .

.0 - 1.6 t cvc tScvc =5..2V MPU Read 0.) Item Symbol Timer Input Pulse Width tpWT Delay Time. Enable Positive Transition to Timer Out t TOD SCI Input Clock Cycle Test Condition MODE PROGRAMMING (Vee typ max - - ns - 600 ns - Fig.- -tASr I-tASf tASO 2.8V Figure 1 Expanded Multiplexed Bus Timing 36 - O. unless otherwise noted. -PWASH - O.6V ) ~ 2. '""r PWEH .0V Data Valid O.-tEf ~ O.) min typ max Unit Mode Programming Input "Low" Voltage V MPL - - V Mode Programming Input "High" Voltage V MPH 4..6V tASL . -+ -tHW ~ ~ -tHR ~~ )~2.·tAHL t06w- -'I 2.6V -tAOL- . (Port 3) Data Valid -tOSR- }~iJ:ress \ ) Valid O...HD8801S0.-\ -.-A. Vss =OV.5V~r- - -tAO- (Sell' .. Ta = 0 '" +70°C..0V t5%. (Port 3) } ~ ...0 - - tcyc tcyc Symbol Item RES "Low" Test Condition Fig.. A.6V ~I .6V] .4 - 0. (tACCM) ~ t -tAH . SCI TIMING (Vee =5. .-0.. Ta =0 '" +70°C.0 tMPS t MPH Mode Programming Hold Time 150 - tc:yc: '7 Address Strobe (AS) .'fJ ~V PWEL O..2V ) - ~ Do-D..4 vj Enable (E) ~~ ASEC .. Vss =OV.2V Address \ Valid / O.A.-A. HD8801S6--------------------------------------------TIMER. -tEr }~2.7 - 3....~ V ns . 8 PW RSTL Pulse Width Mode Programming Set-up Time 2... 7 tscvc tpWSCK SCI Input Clock Pulse Width min tcyc +200 Unit 1 - - 0.0V t5%.. unless otherwise noted. ~ ~ Address Valid (Port4) MPU Write t\ - J \ R/W Ar-Ar.

Not applicable to P I 0) 3. 27vJ~ Enable lEI ~ .2V 0 t V I'd O...(Port4 ) ms (SC21 (SCI) 'f- :~ PWEH ~[ J --tAO- Rii/il . . o . HD8801S6 . tcyc - --tEr - -tEf -tAH -~I\ 2. \ Data Valid MPU Read _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _2_..-0.6V\.2V J-'" 0.SV Figure 2 Expanded Non-Multiplexed Bus Timing r r-MPURead Enable(E) MPUWrite Enable(E) --tcMos_1 P IO ." Port Outputs InpulS PJO . "]t..6V~ .0V ____~~~~________~~0~. Port 4 cannot be pulled above Vcc Figure 3 Data Set-up and Hold Times (MPU Read) Figure 4 Port Data Delay Timing (MPU Write) Addres..0_VO(I - -IHR Oala Valid 0.-( - PWEL 0. Bu..-0.p." -tHW -::l~ .8V ·Port 3 Non-Latched Operation (LATCH ENABLE = (NOTE) 1. 053-----..7 VCC 2.. . p)O - P)7 Inputs • Access matches Output Strobe Select (055 = 0. (Port 3) O.JAddress Valid O...P" Inputs· .---------------------------------------------HD6801S0. a read. 10 kn Pullup resistor required for Port 2 to reach 0.. 055 = 1..7 Vee 2. a write) Figure 5 Port 3 Output Strobe Timing (Single Chip Mode) Figure 6 37 Port 3 Latch Timing (Single Chip Mode) ..~ - -tosw- MPUWrite 2.6V a a a I 2...5V ~ Ao--A..'{_____ 0.P" P20 . (Port 3) O. -tOSA- ItACCNI .2V. _tpwo All Data .P2 • p..

....~: ~\\\\\\\\\\\\\\\\\\\10%\\\\\§\\\\\\S\S~ ~ ~ PCB-PCI5 PCO-PC7 Forst Instruction ~NotValtd Figure 11 Reset Timing 38 ... . p..:"'_ _ _ _ _""'. Cvcle L....-p".J''-_~_ _........ Internal InterruPt\'"-------------------~1 Figure 10 Interrupt Sequence E Va. u..-_v--'V'--"'- Da . C R C· 90 pF fo.......-p".. = 30 pF for P._-~.... p..-""""... J'. -p •• (a) CMOS Load (b) TTL Load Figure 9 Bus Timing Test Loads I . ~~ ~ FFFEFFFE \\\\\\\\\\\\§\\\\\\\'{ ~\S\S\\\\\\\\\SSS\\\\\\\\S\Y ~ :::x=r- ~:tt:r.A.I P" Output Figure 8 Mode Programming Timing Figure 7 Timer Output Timing Vcc Test Point RLZ2.J'--..J'~_~_ _ J\ _ _''''_ _'''''_ _'''"_...~I VMPH ~._ _ 'iRQ.2kO O..._ _"-_ _"-_.jjIf'" VMPL (P._ J ' .-----r.. . .... p.... . SC" SC..HD6801S0. E. 1._ _J\..-P"........ p. *----... *'\\\\%\\\\\\~ }\\\\\\\\\\\\\\\\\ ~ ~ f1-f1JlS" ~4..~t----------------~.J'\_--l"""_-4"-...--_v--_v--'V'--"""\.J\_ _''''_ _J\.·rn:._. -p"..-"'""\..... HD6801S6---------------------------------------------Enable (E) Timer Counter ------' Mode Inputs _ _ _ _ _...A . ·24 kO for P.TvtPCS ~ --------1....10-\--------------1. E.._-~--'\r--'\r-..: -. .......rnal RIW \\\\\\\\\\\\\\\\\\\\\~ }ss§\\\\\S\\S\\\\\\\Ss\\\\sv---V~.... •• P"..75V -5. Bu... SC" SC. -p..~ 7"'I.J'-_.... _ _' ' " ' _ Internal R/ii *IRQ2 ...J''-_-J'-_-J'-_...._J\. In.-----oL. R· 12 kO for p.130PF Test Point m lS2074 ® Or Equlv...._ J \_ _.. p. -P"..t_PCS_____ ~ . ....... Instructoon _ _ Internal Add' ..25V . Bu. o. .' I "I tAC--------.- A.. -p". NMlor IRO) Inlernal~r--~..P...J''--J\-_J\.

Rs son max. when brought "Low". and 0 are latched into programmed 60ntrol bits PC2. An address loaded at these locations causes the MPU to branch to a non-maskable interrupt service r01Jtine in memory. 4) The interrupt mask bit is set. so a 4 MHz crystal may be used to run the system at 1 MHz. Progr. This disables the standby RAM. It is not restricted to 4 MHz. must be cleared before the MPU can recognize maskable interrupts. if the interrupt mask bit in the Condition Code Register is not set. The voltage supplied will be +5 volts ±5%. the processor will complete the current instruction that is being executed before it recognizes the NMI signal. An address loaded at these locations causes the MPU to branch to an interrupt routine in memory. It is a single phase. Program Counter. RES. and Condition Code Register are stored on the stack. and will be the divide by 4 result of the crystal frequency. The Index Register.7 pF max. A 3. IRQl will have priority over IRQ 2 if both occur at the same time. The processor will wait until it completes the current instruction that it being executed before it recognizes the request. The first 64 bytes of RAM will be maintained in the power down mode with 8 rnA current max. At the end of the sequence. During operation. • Vee and Vss These two pins are used to supply power and ground to the chip. PC 1 and PeO. the reset must be held "Low" for at least 100 ms. Vee Standby Figure 13 Battery Backup for Vee Standby 39 . resulting from a power failure or an initial startup of the processor. It will drive one TTL load and 90 pF. the·ma.3 kn external resister to Vee which should be used for wire-OR and optimum control of interrupts. RAM E. Item XTAL~--~------~ CJ EXTAL I .------------------------------------------------HD6801S0. XTAL must be grounded if an external clock is used. As with interrupt Request signal.2 . and Condition Code Register are stored on the stack. When a "High" level is detected.un Counter. a 16-bit address will be loaded that points to a vectoring address located in memory locations $FFFC and $FFFD.. must be held "Low" at least 3 clock cycles.chine will begin an interrupt sequence. Divide by 4 circuitry is included with the internal clock. EXT AL may be driven by an external clock source at a 4 MHz rate to run at 1 MHz with a 40/60% duty cycle. This pin will supply +5 volts ±5% to the standby RAM on the chip. Inputs IRQl and NMI are hardware interrupt lines that are sampled during E and will start the interrupt routine on the E following the completion of an instruction. • Non-Maskable Interrupt (NMI) A low-going edge on this input requests that a non-maskableinterrupt sequence be generated within the processor. thereby protecting it at power down. At that time. On power up. 4. The Interrupt Mask Bit in the condition code register masks both interrupts (See Table 1). At the end of the cycle.. • XTAL and EXTAL These connections are for a parallel resonant fundamental crystal.3 kn external resistor to Vee should be used for wire-OR and optimum control of interrupts.-. Accumulators. a 16-bit address will be loaded that points to a vectoring address which is located in memory locations $FFF8 and $FFF9. Next the MPU will respond to the interrupt request by setting the interrupt mask bit "High" so that no further maskable interrupts may occur. The circuit of figure 13 can be utilized to assure that Vee Standby does not go below V SBB during power down.~ C L1 = C L2 =22pF ± 20% (3. the MPU does the following: I) All the higher order address lines will be forced "High". Two 22pF capacitors are needed from the two crystal pins to ground to insure reliable operation. as it will divide by 4 any frequency less than or equal to 4 MHz. The following are the recommended crystal parameters: Nominal Crystal Parameter ~ 4 MHz 5 MHz Co 7 pF max. 30ntyp. $FFFF) locations in memory will be used to load the program addressed by the program counter. The interrupt mask bit in the Condition Code Register has no effect on NMI. +r CL1 tL2 Figure 12 Crystal Interface • Vee Standby • Interrupt Request (lRa t ) This level sensitiv~ input requests that an interrupt sequence be generated within the machine. To retain information in the RAM during power down the following procedure is necessary: 1) Write "0" into the RAM enable bit... The divide by 4 circuitry allows for use of the inexpensive 3.. HD6801S6 • SIGNAL DESCRIPTIONS • Reset (RES) This input is used to reset and start the MPU from a power down condition. Internal Interrupts will use an internal interrupt line (IRQ2)' This interrupt will operate the same as IRQ1 except that it will use the vector address of $FFFO through $FFF7. In response to an NMI interrupt.5 MHz) [Note] These are representative AT cut parallel resonance crystal parameters. the Index Register. Accumulators. 3) The last two ($FFFE. TTL compatible clock. • Enable (E) This supplies the external clock for the rest of the system when the internal oscillator is used. 2) I/O Port 2 bits. RAM E is bit 6 of the RAM Control Register at location $0014.58 MHz Color TV crystal for non-time critical applications. AT cut. 2. 2) Keep Vee Standby greater than VSBB. The IRQt requires a 3. I.

5 V to directly drive a Darlington base. In all three modes. the voltage on the input lines must be greater than 2. this strobe will latch the input data from another device when that device has indicated that it has valid data. allOWing them to enter a high impedance state when the peripheral data lines are used as inputs. Port 2 can be configured as I/O and provides access to the Serial Communications Interface and the Timer. • I/O Port 3 This is an 8·bit port that can be configured as I/O. A "I" in the corresponding Data Direction Register bit will cause that I/O line to be an output. the voltage on the input lines must be greater than 2. 1/0 Port 3 1/0 Port 4 Data Direction Register Address $0000 $0001 $0004 $0005 • I/O Port 1 This is an 8·bit port whose individual bits may be defined as inputs or outputs by the corresponding bit in its data direction register. If the latch enable bit in the I/O Port 3 Control/Status Register is set. indicating valid data is on the I/O pins. Ports Port Address I/O Port 1 $0002 $0003 $0006 $0007 1/0 Port 2 • Input Strobe (lS3) (SCI) This sets an interrupt for the processor when the IS3 Enable bit is set. Interrupt MSB LSB FFFE FFFF rn FFFC FFFO NMI FFFA FFFB FFF8 FFF9 IRQ. and are associated with Port 3 only. Port 2. The timing for this singal is shown in Figure 1 of Bus Timing. This signal is also used to disable the address from the multiplexed bus allowing a deselect time. After Reset. • Reld/Write (R/W) (SC2 ) This TTL compatible output signals the peripherals and memory devices whether the MPU is in a Read ("High") or a Write ("Low") state.depending on the mode of operation hardware programmed by the user at reset. The 5 output buffers have three-state capability. Port 3 is bi-directional. The timing diagrams are shown as figure 2.8 V for a logic "0". After Reset. Table 2 Port and Data Direction Register Addresses The following pins are available in the Single Chip Mode. For driving CMOS inpu~s.8 V for a logic • I/O Strobe (iOS) (SCI) In the expanded non·multiplexed mode of operation.!!!B. • I/O Port 2 This port has five lines that may be defined as inputs or outputs by its data direction register. allowing them to enter a high impedance state when used as an input. Port 3. In order to be read properly. greater than 2. the I/O lines are configured as inputs. as shown in figure 19.HD8801S0. An 8-bit latch is utilized in conjunction with Address Strobe. The following pins are available in the Expanded Modes.0 V for a logic "1" and less than 0. This output is capable of driving one TTL load and 90pF. • Output Strobe (Oil) (SC 2 ) This signal is used by the processor to strobe an external device. (or IS3) FFF6 FFF7 ICF (Input Capture) OCF (Output Compare) Software Interrupt (SWII FFF4 FFF5 FFF2 FFF3 TOF (Timer Overflow) FFFO FFFl SCI (RORF + ORFE + TORE) * The only exception is bit 1 of Port 2. A "0" in the corresponding Data Direction Register bit will cause that I/O line to be an input. The timing for the Output Strobe is shown in Figure 5 I/O Port 3 Con troll Status Register is discussed in the following section. As outputs. IS3 will faU tIS minimum after data is valid on Port 3. The normal standby state of this signal is Read ("High"). This is explained in th~ Mode Selection Section.. • Addr. a data bus. The values of these pins at reset are latched into the three MSB's (bits 7 6 and 5) of Port 2 which are read only. Their addresses and the addresses of their Data Direction registers are given in Table 2. which can either be data input or Timer output. or an address bus multiplexed with the data bus . that is. Three pins on Port 2 (pins 10. Each port has an associated write only Data Direction Register which allows each I/O line to be programmed to act as an input or an output*. As outputs.8 V for a logic "0". external pullup resistors are required. t ASD before the data is enabled to the bus.0 V for a logic "1" and less than 0. This allows external access of the 256 locations from $0100 to SOIFF. Expanded Multiplexed Mode. There are four ports: Port 1. these lines are TTL compatible and may also be used as a source of up to 1 rnA at 1. There are two control lines associated with one of the 8·bit ports. Address Strobe signals the latch when it is time to latch the address lines so the lines can become data bus lines during the E pulse. and Port 4. 9. As a data bus. this port has no internal pullup resistors but will drive TTL inputs directly. the I/O lines are configured as inputs. As an input for peripherals.. Bit 1 is the only pin restricted to data input or Timer output. The 8 output buffers have three-state capability. it must be supplied regular TTL levels. Strobe (AS) (SCI) In the expanded multiplexed mode of operation address strobe is output on this pin. an interrupt will occur. If IS3 Enable is set in the 110 Port 3 Control/Status Register. three 8·bit ports and one 5-bit port. In order to be read properly. This signal is used to latch the 8 LSB's of address which are multiplexed with data on Port 3. "0" 40 . As shown in Figure 6 Input Strobe Tim. Port 1 is always parallel I/O.0 V for a logic "1" and less than 0. and 8 of the chip) are used to program the mode of operation during reset. lOS internally decodes A9 through Au as zero's and As as a one. HD8801S6---------------------------------------------Table 1 Interrupt Vector Location Vector Highest Priority Lowest Priority • PORTS There are four I/O ports on the HD680lS MCU. In all three modes.

(2) OS3 can be generated by either an MPV read or write to Port 3's Data Register. In the three modes. • I/O Port 4 This is an 8-bit port that can be configured as I/O or as address lines depending on the mode of operation. (1) Single Chip Mode. They are latched into programmed control bits PC2. Port 4 becomes the Ao-A 7 address bus or partial address and I/O (inputs only). the remaining lines. Port 4 is configured as the lower order address lines (A o-A 7) by writing one's to the data direction register. 76543210 I/O PORT 3 CONTROL/STATUS REGISTER 7 load and 90 pF. (2) Expanded. starting with the most significant bit. Port 3 will have two associated control lines. LATCH ENABLE. therefore.----------------------------------------------HD8801S0. and I/O 0 respectively) of Port 2. • Expanded Non-Multiplexed Mode In this mode the HD6801S will directly address HMCS6800 peripherals with no external logic. This is a read only status bit that is set by the falling edge of the input strobe. the mode cannot be changed through software.8 V for a logic "0" As outputs. may be used as I/O (inputs only). after reset. and (3) and IRQ7 interrept can be enabled by an IS3 nagative edge. 6. each line is TTL compatible and can drive 1 TTL 41 . In this mode the HD6801Sis expandable to 256 locations. may be used as I/O (inputs only). they should be programmed as outputs. IS3 (SCd. Expanded Non-Multiplexed Mode: In this mode. the data direction register is inhibited and data flow depends on' the state of the R/W line. Expanded Multiplexed Mode: In this mode. IS3 FLAG. The input strobe (IS3) and the output strobe (OS3) used for handshaking are explained later. 5 and Fig. Bit 1. 6 and 7 of Port 2 are read only. The HDI4053B provides the isolation between the peripheral device and MCV during Reset. when clear. In this mode Port 3 becomes the data bus. 14. • Single Chip Mode In the Single Chip Mode the Ports are configured for I/O. Bit 2. the lines are configured as inputs. Three options of Port 3 operations are sumarized as follows: (1) Port 3 input data can be latched using IS3 (SC 1) as a control signal. If this bit is set "High" the input data will be latched with the falling edge of the Input Strobe. I/O 1. After reset. To use the pins as addresses. the remaining lines. an input strobe and an output strobe. I/O Port 2 Register is shown below. the voltage on the input lines must be greater than 2. and 8 of the chip. interrupt is inhibited. PCI. When this bit is cleared the strobe is generated by a read Port 3. Port 3 assumes the following characteristics: Single Chip Mode: Parallel Inputs/Outputs as programmed by its associated Data Direction Register. Bit 3. IS3 $OOOF Bit 0. interrupt will be enabled whenever IS3 FLAG is set. When set. Bit 5. Port 2 can be parallel I/O. The mode selections are shown in Table 3. As bits 5. Bit 4. Port 4 is configured as the higher order address lines (A 8 -A 1s ) by writing one's to the data direction register.0 V for a logic "1" and less than 0. It is cleared by a read of the Control/Status Register followed by a read or write of I/O Port 3. An example of external hardware that could be used for Mode Selection is shown in Fig. iS3 IRQl ENABLE. Port 3 becomes the data bus (Do -D 7). IS3. This is shown in Figure 16 the single Chip Mode. FLAG 6 5 4 3 2 IS3 X OSS LATCH X PORT 2 DATA REGISTER $0003 o X PC21 PC1 I PCO 11/0411/0311/0211/0 1 1110 0 X IRQ1 ENABLE • OPERATION MODES The mode of operation that HD6801 S will operate in after Reset is detennined by hardware that the user must wire on pins 10. Port 3 becomes both the data bus (Do -D 7) and lower bits of the address bus (Ao-A7)' An address strobe output is true when the address is on the port. In this mode. or any combination of them. The HD6801S is capable of operating in three basic modes. ENABLE Not used. HD8801S6 Its TTL compatible three-state output buffers are capable of driving one TTL load and 90 pF. Reset will clear this bit. OSS. that can be used for handshaking. This controls the input latch for I/O Port 3. This bit is cleared by RES. This bit is cleared by reset. serial I/O. Not used. and PCO when reset goes high. In the Expanded Modes. which is necessary if data conflict can occur between peripheral device and Mode generation circuit. Not used. Bit 6. The eight address lines associated with Port 4 may be substituted for I/O (inputs only) if a fewer number of address lines will satisfy the application (See Figure 17). Not used. These pins are the three LSB's (I/O 2. (Output Strobe Select) This bit will select if the Output Strobe should be generated at 053 (SC 1 ) by a write to I/O Port 3 or a read ofI/O Port 3. In the three modes. Bit 7. When this bit is set the strobe is generated by a write Port 3. 9. Multiplexed Mode (compatible with HMCS6800 peripheral family) (3) Expanded NonMultiplexed Mode. Timer. starting with the most significant bit. When all eight address lines are not needed. There are two control lines associated with this port in this mode. They are controlled by the I/O Port 3 Control/Status Register explained at the end of this section. Expanded Multiplexed Mode: In this mode. Port 1 is parallel I/O only. Port 4 assumes the following characteristics: Single Chip Mode: Parallel Inputs/Outputs as programmed by its associated Data Direction Register. When all eight address lines are not needed. and the latch is "re-opened" with MCV read Port 3. an input strobe and an output strobe for handshaking data. In order to be read properly. Port 3 latch and strobe timing is shown in Fig. Expanded Non-Multiplexed Mode: In this mode.

( C· I (. Y I X. ~ •> R. Z 8 PlO (PCO) 9 Pl. HD6801S6---------------------------------------------Vee ( R~ . R. ( ??? ~ Mode Control Switch HD14053B Inh J. Xo 0 0 1 1 Zo Y I X. 1) Mode 7 as shown 2) RC""Reset time constant 3) RI =10kS1 (NOTES) Figure 14 Recommended Circuit for Mode Selection Truth Table Control Input Inh Select Inhibit A 8 C C B A Xo XI Yo YI Zo ZI X Y Z On Switch HD14053B 0 0 0 0 Zo Yo Xu 0 0 0 1 Zo Yo XI 0 0 1 0 Zo Y. 1 X X X 1 - Figure 15 HD14053B Multiplexers/Demultiplexers Vee Vee 2 7 40 Enable Enable Port 1 8 Parallel I/O Port 3 8110 Lines Port 1 8110 Lines Port 2 5 Parallel 110 SCI Timer Port 2 5110 Lines Port 4 8110 Lines Vss SCI Timer Figure 16 HD6801S MCU Single-Chip Mode Port 3 8 Data Lines Port 4 To 8 Address Lines or To 7 I/O Lines (Inputs Only) Figure 17 HD6801S MCU Expanded Non-Multiplexed Mode 42 . (PC1) 10 Pl2 (PC2) Y.· R. 0 1 0 0 ZI Yo Xo 0 1 0 1 ZI Yo "XI 0 1 1 0 ZI YI Xo 0 1 1 Z.HD6801S0. Z. 6 RES I I I A B C HD6801S Xo - Yo X Zo Y X.

Port 1 is 8 Parallel I/O lines. Timer. Port 2 is 5 lines of Parallel I/O. Aead/Write 105" 1/0 Select 43 ..----------------------------------------------HD6801SQ.. I .. Figure 19 Latch Connection • Mode and Port Summary MeU Signal Description This section gives a description of the MCU signals for the various modes. HD6801S6 • Expanded Multiplexed Mode In this mode Port 4 becomes higher order address lines with an alternative of substituting some of the address lines for I/O (inputs only). Vee Enable • Lower order Address Bus Latches Since the data bus is multiplexed with the lower order address bus in Port 3.-A. Figure 19 shows how to connect the latch to the H06801S. 74LS373 Output Control 08 1 G Enable 0 Output 0 L L L H H H H L L H X X X L 00 Z 0 . SCI. Port 3 is the data bus multiplexed with the lower order address lines differentiated by an output called Address Strobe. The 74LS373 Transparent octal D-type latch can be used with the H06801S to latch the least significant address byte. PORT 1 Eight Lines PORT 2 Five Lines PORT3 Eight Lines PORT4 Eight Lines SCI SCl SINGLE CHIP I/O I/O I/O I/O IS3 (I) OS3(0) EXPANDED MUX I/O I/O ADDRESS BUS (Ao-A7 l DATA BUS (0 0 -0 7 ) ADDRESS BUS· (As-Au) AS(O) R/W(O) EXPANDED NON-MUX I/O I/O DATA BUS (0 0 -0 7 ) ADDRESS BUS· (Ao-A 7 ) 10S(0) R/W"(O) MODE -These lines can be substituted for I/O (Input Only) statting with the most significant address line. In this mode it is expandable to 65k words.. Input m = Input Strobe SC . Port 3 Address/Data [ G OC 0. (See Figure 18). 0. A. Port 1 8 I/O Lines 8 Lines Multiplexed Data I Address Address Strobe Port 2 Port 4 To 8 Address Lines or To 7 110 Lines (Inputs Only) 51/0 Lines SCI Timer Figure 18 HD6801S MCU Expanded Multiplexed Mode GND AS J 0. Output Strobe AS = Address Strobe ANI .-0. . 1 08 Function Table Add.. or any combination of them. Strobe Control o ..Output 0S3 . latches are required to latch those address bits. The output control to the 74LS373 may be connected to ground. SCI and SCl are signals which vary with the mode that the chip is in...

" 2.2. HD8801S6------------------------------------------~Table 3 Mode Selection Summary Mode 7 6 5 4 3 2 1 0 (~t22) P21 (PC1) H H H H L L L L H H L L H H L L P (P~O) ROM RAM H L H I I I I I I L H L H L 1(2) 1(1) E E I I E I I I LEGEND: I .3.Multiplexed NMUX . 1.HD8801S0.2. . The fust 32 locations of each map are reserved for the MeV's internal register area.6. O-Input- 44 • INTERRUPT FLOWCHART The Interrupt flow chart is depicted in Figure 24 and is common to every interrupt excluding reset. cannot be accessed in Mode 5 (No. as shown in Table 4. address output is optional by writing to Port 4 Data Direction Register • MEMORY MAPS The MeV can provide up to 65k byte address space depending on the operating mode.Non-Multiplexed L . A memory map for each operating mode is shown in Figure 20. With exceptions as indicated.Internal E .3 ••• 1-output. Port Port Port Port Bus Mode 09 OA OB 14 15-1F • External address in Mode~ 1. Register 1 Date Direction Register··· 2 Data Direction Register··· 1 Data Register 2 Data Register Port Port Port Port 3 Data Direction Register· -4 Data Direction Register··· 3 Data Register 4 Data Register Address 00 01 02 03 0405·· 06· 07·· Timer Control and Status Register Counter (High Byte) Counter (Low Byte) Output Compare Register (High Byte) 08 Output Compare Register (Low Byte) Input Capture Register (High Byte) Input Capture Register (Low Byte) Port 3 Control and Status Register OC 00 OE OF- Rate and Mode Control Register Transmit/Receive Control and Status Register Receive Data Register Transmit Data Register 10 11 12 13 RAM Control Register Reserved I MUX(S) NMUX(S) I MUX MUX MUX MUX Operating Mode Single Chip Multiplexed/Partial Decode Non-Multiplexed/Partial Decode Single Chip Test Multiplexed/No RAM & ROM Multiplexed/RAM Multiplexed/RAM & ROM Multiplexed Test (NOTES) 1) Internal RAM is addressed at $XX80 2) Internal ROM is disabled 3) RES vector is externai for 2 cycles after RES goes "High" 4) Addresses associated with Ports 3 and 4 are considered external in Modes 0. 5.Logic "0" H . IO~) •• External addresses in Modes 0.External MUX . and 3 5) Addresses associated with Port 3 are considered external in Modes 5 and 6 6) Port 4 default is user data input.Logic "1" Interrupt Vectors I I I I E E E 1(3) Table 4 Internal Register Are.

$07 and $OF. HD8801S6 HD6801S Mode o HD6801S Mode 1 Multiplexed/RAM & ROM Multiplexed Test mode $0000(1 ) $0000(1) Internal Registers Internal Registers $001F $001F External Memory Space External Memory Space $0080 $0080 Internal RAM Internal RAM $OOFF $OOFF External Memory Space External Memory Space $F800 $F800 Internal ROM $FFEF Internal ROM $FFFO $FFFF(2) Internal Interrupt Vectors(2 [NOTES) 1) Excludes the following addresses which may be used externally: $04. $07 and $OF.. 4) This mode is the only mode which may be used to examine the interrupt vectors in internal ROM using an external Reset vector.. External Interrupt Vectors $ F F F F .-. $06.. Figure 20 HD6801S Memory Maps 45 . [NOTES) 1) Excludes the following addresses which may be used externally: $04.. there must be no overlapping of internal and external memory spaces to avoid driving the data bus with more than one device. 2) Internal ROM addresses $FFFO to $FFFF are not usable.. $06. $05. $05. 3) After 2 MPU cycles.---------------------------------------------HD8801S0. 2) Addresses $FFFE and $FFFF are considered external if accessed within 2 cycles alter a positive edge of RES and internal at all other times.

.... $05.... and $OF.... $FFFO 1-----4~} $FFFF '--_ _ _. Figure 20 HD6801S Memory Maps 46 (Continued) .- HD6801S Mode 2 HD6801S Mode Multiplexed/RAM 3 Multiplexed/No RAM or ROM $0000(1) $0000(1) } Internal Registers Internal Registers $OO1F $001F External Memory Space $0080 Internal RAM $OOFF External Memory Space External Memory Space . (NOTE] 1) Excludes the fOllowing addresses which may be used externally: $04..... H D 6 8 0 1 S 6 ...I $FFFO ~----1 $FFFF _ _ _ _.. $06... $06.HD6801S0. $07 and $OF.. } External I nterrupt Vectors External Interrupt Vectors (NOTE] 1) Excludes the following addresses which may be used externally: $04..... $07. $05.

$06. These address lines will assert "1's" until made outputs by writing the Data Direction Register. (No IDS) 2) This mode may be entered without going through RES by using Mode 4 and subsequently writing a "1" into the peo bit of Port 2 Data Register. will not contain addresses until the Data Direction Register for Port 4 has been written with "1 '5" in the appropriate bits..rnal Registers Internal Registers $001F $0080 } Internal RAM $OOFF $0100 $01 FF _ _. 2) Mode 4 may be changed to Mode 5 without having to assert RESET by writing a "1" into the peo bit of Port 2 Data Register.A. Internal Interrupt Vectors [NOTES] 1) Excludes the following addresses which may not be used externally: $04. 3) Address lines Ao .--_" U } External Memory Space 1)(4) $F800 Internal ROM $XX80 $XXFF Internal RAM } Internal Interrupt Vectors $FFFF [NOTES] 1) The internal ROM is disabled. and $OF. 3) Addresses As to AI 5 are treated as "don't cares" to decode internal RAM.----------------------------------------------HD8801S0. Figure 20 HD6801S Memory Maps (Continued) 47 . HD8801S6 HD6801S Mode 4 HD6801S Mode 5 Single Chip Test $0000 } Intp. 4) Internal RAM will appear at $XX80 to $XXFF.

2) Address lines As-A. HD8801S6--------------------------------------------- HD6801S Mode 6 HD6801S Mode Single Chip Multiplexed/Partial Decode $0000(1) $001F 7 $0000 Internal Registers } Internal Registers $001F External Memory Space $0080 $0080 Internal RAM } Internal RAM $OOFF $OOFF External Memory Space $F800 $FFFF Internal ROM Internal ROM Internal Interrupt Vectors Int.ernal Interrupt Vectors $FFFF [NOTES) 1) Excludes the following address which may be used externally: $04. $06.HD8801S0. $OF. Figure 20 HD6801S Memory Maps (Continued) 48 . These address lines will assert "1's" until made outputs by writing the "Data Direction Register.! will not contain addresses until the Data Direction Register for Port 4 has been written with "1's" in the appropriate bits.

OE Output Input Level Edge B.. Bit 1 contains a "1" (Output). • Free Running Counter ($0009:000A) The key element in the programmable timer is a 16-bit free running counter which is driven to increasing values by E (Enable). • a 16-bit free running counter. Each of the flags· may be enabled onto the HD6801 internal bus (IRQ2) with an individual Enable bit in the TCSR. If the H068D1 S Internal Bus r--..~=-.. • a match has been found between the value in the free running counter and the output compare register. and • when $0000 is in the free running counter. Any MPU write to the counter's address ($09) will always result in preset value of $FFF8 being loaded into the counter regardless of the value involved in the write.t' Bit 0 Po. The counter is cleared to zero on RES and may be considered a read-only register with one exception.. Pulse widths for both input and output signals may vary from a few microseconds to many seconds. the output level register value will appear on the pin for Port 2 Bit I.t 2 Pon 2 Figure 21 Block Diagram of Programable Timer 49 . shouId* be clear (zero) in order to gate in the external input signal to the edge detect unit in the timer. The counter value may be read by the MPU software at any time. HD6801S5 • PROGRAMMABLE TIMER The HD680 I S contains an on-chip 16-bit programmable timer which may be used to perform measurements on an input waveform while independently generating an output waveform. but may be of value in some applications. • Input Capture Register ($OOOD:OOOE) The Input Capture Register is a J6-bit read-only register used to store the current value of the free running counter when the proper transition of an external input signal occurs. * With Port 2 Bit 0 configured as an output and set to "1".. The Compare function is inhibited for one cycle following a write to the high byte of the Output Compare Register to insure a valid l6-bit value is in the register before a compare is made. When a match is found. • Output Compare Register ($OOOB:OOOC) The Output Compare Register is a 16-bit read/write register which is used to control an output waveform. The input transition change required to trigger the counter transfer is controlled by the input Edge bit (IEDG) in the TCSR. a flag is set (OCF) in the Timer Control and Status Register (TCSR) and the current value of the Output Level bit (OLVL) in the TCSR is clocked to the Output Level Register. the external input will still be seen by the edge detect unit. • a 16-bit output compare register. The Output Compare Register is set to $FFFF during RES.. This preset figure is intended for testing operation of the part. The values in the Output Compare Register and Output level bit may then be changed to con trol the ou tpu t level on the next compare value. The timer hardware consists of • an 8-bit control and status register. The Data Direction Register bit for Port 2 Bit 0.----------------------------------------------HD6801S0. The upper three bits contain read-only timer status information and indicate that: • a proper transition has taken place on the input pin with a subsequent transfer of the current counter value to the input capture register. • Timer Control and Status Register (TCSR) ($0008) The Timer Control and Status Register consists of an 8-bit register of which all 8 bits are readable but only the low order 5 bits may be written. and • a 16-bit input capture register A block diagram of the timer registets is shown in Figure 21. Providing the Data Direction Register for Port 2. The contents of this register are constantly compared with the current value of the free running counter.

software. the serial I/O section utilizes bit 3 (serial input) and bit 4 (serial output) of Port 2. The hardware. it is cleared by a read of the TCSR (with ICF set) followed by an MPU read of the Input Capture Register ($00). It is cleared by a read of the TCSR (with TOF set) followed by an MPU read of the Counter ($09). Bit 2 of Port 2 is utilized if the internal-clock-out or external-clock-in options are selected . Bit 1 IEDG Input Edge . when clear the interrupt is inhibited. • SERIAL COMMUNICATIONS INTERFACE The HD6801S contains a full-duplex asynchronous serial communications interface (SCI) on chip.HD6801S0. IEDG = 1 Transfer takes place on a positive edge ("Low" -to-"High" transition). 3. when clear the interrupt is inhibited. .This read-only status bit is set by a proper transition on the input.This read-only bit is set when the counter contains $0000. It is cleared by a read of the TCSR (with OCF set) followed by an MPU write to the output compare register ($OB or SOC). If the DDR for Port 2 bit 1 is set.enabled or disabled • Interrupt requests . Bit 5 TOF Timer Overflow Flag . Bit 7 ICF Input Capture Flag .When set.external or internal • baud rate . • Programmable Options The following features of the HD680 I S serial I/O section are programmable: · format . The DDR for Port 2 Bit o must be clear for this function to operate. Bit 2 ETOI Enable Timer Overflow Interrupt .dedicated or not dedicated to serial I/O individually for transmitter and receiver. HD6801S6--------------------------------------------Timer Control and Status Register 7 5 6 ICF I OCF TOF 4 I I EICI 3 2 1 EOCI I ETOII'EOG I 0 OLVLI $0008 MPU via the data bus and with the outside world via pins 2.to-"Low" transition). the hardware re-enables (or "wakes-up") the for the next message. Bit 3 EOCI Enable Output Compare Interrupt .This value is clocked to the output level register on a successful output compare. Bit 4 EICI Enable input Capture Interrupt . a priority vectored interrupt will occur corresponding to the flag bites) set. IEDG = 0 Transfer takes place on a negative edge ("High" . In addition to the four registers.This read-only bit is set when a match is found between the output compare register and the free running counter. The bits in the TRCS register are defined as follows: Transmit/Receive Control and Status Register I 76543210 ROREI ORFE I I I I I I wu I TORE RIE RE 50 TIE TE AOOR : $0011 . this bit enables IRQ 2 to occur on the internal bus for a TOF interrupt. the value will appear on the output pin. this bit enables IRQ2 to appear on the internal bus for an output compare interrupt. The registers include: • an 8-bit control and status register • a 4-bit rate and mode control register (write only) • an 8-bit read only receive data register and • an 8-bit write only transmit data register. • Wake-Up Feature In a typical multi-processor application.When set. The register is initialized to $20 on RES. The "wake-up" is automatically triggered by a string of ten consecutive l's which indicates an idle transmit line. In order to permit non-selected MPU's to ignore the remainder of the message. and 4 of Port 2. The software protocol must provide for the short idle period between any two consecutive messages. A description for each bit follows: Bit 0 OLVL Output Level .enabled or masked individually for transmitter and receiver data registers • clock output . the software protocol will usually contain a destination address in the initial byte(s) of the message.internal clock enabled or disabled to Port 2 (Bit 2) • Port 2 (bits 3 and 4) . a wake-up feature is included whereby all further interrupt processing may be optionally inhibited until the beginning of the next message.This bit controls which transition of an input will trigger a transfer of the counter to the input capture register. this bit enables IRQ2 to occur on the internal bus for an input capture interrupt. • Serial Communications Hardware The serial communications hardware is controlled by 4 registers as shown in Figure 22. and registers are explained in the following paragraphs. Both transmitter and receiver communicate with the Transmit/Receive Control and Status (TRCS) Register The TRCS register consists of an 8-bit register of which all 8 bits may be read while only bits 0-4 may be written.one of 4 per given MPU <P2 clock frequency or external clock x8 input • wake-up feature . When the next message appears.When set.standard mark/space (NRZ) • Clock . The controller comprises a transmitter and a receiver which operate independently or each other but in the same data format and at the same data rate. when clear the interrupt is inhibited. I-bit in the HD6801S Condition Code register has been cleared. Bit 6 OCF Output Compare Flag .

set by HD6801S software and cleared by hardware on receipt of ten consecutive 1's or reset of RE flag. Bit 5 TORE Transmit Data Register Empty . The TDRE bit is cleared by reading the status register. The two low order bits control the bit rate for internal clocking and the remaining two bits control the format and clock select logic. TE set should be after at least one bit time of data transmit rate from the set-up of transmit data rate and mode. The RDRF bit is cleared by reading the status register. then reading the Receive Data Register. serial 1/0 has no effect on Port 2 bit 3. will permit Bit 2 TIE an IRQ2 interrupt to occur when bit 5 (TDRE) is set.:c-_ _____ 14----E ~ 2 Transmit Shift Register Tx Bit 4 12 $13 Transmit Data Register Figure 22 Serial I/O Registers Bit OWU "Wake-up" on Next Message . and • Port 2 bit 2 configuration The register consists of 4 bits all of which are write-only and cleared on RES. Bit 7 RORF Receiver Data Register Full . when clear. Transmit Interrupt Enable .----------------------------------------------HD6801S0. bit 4 regardless of the DDR value corresponding to this bit. or by RES. Receiver Interrupt Enable . The ORFE bit is cleared by reading the status register. when clear. Bit 6 ORFE Over-Run-Framing Error . HD6801S6 Bit 7 I Rate and Mode Control Register I I I I CCI CCO SSl Bit 0 SSO 1$10 Transmit/Receive Control and Status Register $12 Port 2 Receive Shift Register Clock 10 Bit . when clear.Set by hardware when a transfer from the input shift register to the receiver data register is made.set by hardware when an overrun or framing error occurs (receive only). serial I/O has no effect on Port 2 bit 4. Rate and Mode Control Register The Rate and Mode Control register controls the follOWing serial I/O variables: • Baud rate • format • clocking source. will permit Bit 4 RIE an IRQ2 interrupt to occur when bit 7 (RDRF) or bit 6 (ORFE) is set. The register definition is as follows: Rate and Mode Control Register 7 X 6 X I 5 4 X X 3 2 CC1 cco 51 0 SS1 sso ADDR : $0010 .set by hardware when a transfer is made from the transmit data register to the output shift register.---':. TORE is initialized to 1 by RES. gates Port 2 bit 3 to Bit 3 RE input of receiver regardless of DDR value for this bit. the TDRE value is masked from the bus. then writing a new byte into the transmit data register. then reading the Receive Data Register. A framing error has occurred when the byte boundaries in bit stream are not synchronized to bit counter. The 4 bits in the register may be considered as a pair of 2-bit fields. or by RES.. I t should be noted that RE flag should be set in advance of MPU set of WU flag. An overrun is defined as a new byte received with last byte still in Data Register/Buffer. when clear.when set. Bit 1 TE Transmit Enable .set by HD6801S to produce pre am ble of nine consecutive l's and to enable gating of transmitter output to Port 2..when set.when set. the interrupt is masked.. Receiver Enable ..

When the Transmitter Data Register has be~n emptied.400 Baud 16 J. a continuous string of ones will be sent indicating an idle line.3 J.0 MHz 1. o writing the desired operation control bits to the Rate and Mode Control Register and o writing the desired operational control bits in the Transmit/ Receive Control and Status Register.6 Baud 33. The four rates which may be selected are a func.33 ms/300 Baud * HD6801S5 Only Table 6 SCI Format and Clock Source Control CC1. I nternally Generated Clock If the user wishes for the serial I/O to furnish a clock.800 Baud 0 1 E". CCO.4576 MHz 4." 128 208 J. o the clock will be at Ix the bit rate and will have a rising edge at mid-bit. CCO must be set to 10 o the maximum clock rate will be E"'" 16.4 kHz 4. bit 4 is used for serial output if TE '" "1" in TRCS.2288 MHz E". Bit 4. followed by more 1's until more data is supplied to the data register. Table 5 SCI Bit Times and Rates XTAL SSl : SSO 0 0 E 2. 01 NRZ * Port 2 Bit 2 Port 2 Bit 3 - - ** ** Internal Not Used ** ** Clock Source Port 2 Bit 4 10 NRZ Internal Output* ** ** 11 NRZ External Input ** ** Clock output is available regardless of values for bits RE and TE.this 2-bit field Bit 3 CCl controls the format and clock select logic. the 0 start bit is first transmitted.9152 MHz* 1. At this point one of two situation exist: I) if the Transmit Data Register is empty (TORE = 1). the hardware sets the TORE flag bit.024 ms/976. This sequence will normally consist of. Setting the TE bit during this procedure initiates the serial output by first transmitting a ten-bit preamble of 1'so Following the preamble. o the external clock must be set to 8 times (x8) the desired baud rate and o the maximum external clock frequency is 1. CCO Format 00 . Table 5 lists the available Baud rates.2 J.LsI76. (TORE is still set when the next normal transfer from th~ parallel data register to the serial output register should occur) then a 1 will be sent (instead of a 0) at "Start" bit time. Table 6 defines the bit field. If the HD680IS fails to respond to the flag within the proper time. o CCI. Bit 3 is used for serial input if RE '" "1" in TRCS. internal synchronization is established and the transmitter section is ready for operation." 16 26 J. or.1 Baud 3.0 MHz.Ls/7812.Ls/4. gates the output of the serial transmit shift register to Port 2 Bit 4 and takes unconditional control over the Data Direction Register value for Port 2.500 Baud 13 J. Transmit Operations The transmit operation is enabled by the TE bit in the Transmit/Receive Control and Status Register.67 ms/150 Baud 4.800 Baud 128 J.096 ms/244. • Serial Operations The serial I/O hardware should be initialized by the HD6801 S software prior to operation. The Transmitter Enable (TE) and Receiver Enable (RE) bits may be left set for dedicated operations. 2) if data has been loaded into the Transmit Data Register (TORE = 0)..67 ms/600 Baud 1. Then the 8 data bits (beginning with bit 0) followed by the stop bit are transmitted. Bit 0 SSO Bit 1 SSl HD6801S6----------------~--------------------------- Speed Select .Ls/l .Ls/62." 4096 6. Following a RES the user should configure both the Rate and Mode Control Register and the Transmit/Receive Control and Status Register for desired operation. the word is transferred to the output shift register and transmission of the data word will begin. Bit 2 CCO Clock Control and Format Select . field in the Rate and Mode Control Register must be set to II. the following requirements are applicable: o the values of RE and TE are immaterial.HD6801S0.200 Baud 1 1 E".These bits select the Baud rate for the internal clock. Externally Generated Clock If the user wishes to provide an external clock for the serial I/O. During the transfer itself. No O's will be sent while TORE remains a I.600 Baud 1 0 E"'" 1024 1.0 MHz 614.tion of the MPU CP2 clock frequency. 52 .5 Baud 104. the following requirements are applicable: o the CC 1.Ls/38.Ls/9. This bit when set.

When the RAM is disabled. thereby protecting it at power down if Vee Standby is held greater than VSBB volts. the data is transferred to the Receive Data Register. Bit 1 Not used. Big 7 STBY The Standby Power bit is cleared when the standPWR by voltage is removed. either accumulator A or accumulator B is specified. A 0 in the RAM enable bit (RAM E) will disable the standby RAM. Accumulator (ACCX) Addressing In accumulator only addressing. the operand is contained in the second byte of the instruction except LDS and LDX which have the operand in the second and third bytes of the instruction. In the NRZ Mode. The double (D) accumulator is physically the same as the Accumulator A concatenated with the Accumulator B so that any operation using accumulator 0 will destroy information in A and B.----------------------------------------------HD6801S0.t Accumulators A and B Or 16·Bit Double Accumulator D Inde. HD8801S6 • Condition code register manipulation instructions . The MCV addresses this location when it fetches the immediate instruction for execution. In addition.Table 8 • Jump and branch instructions . indicating an over-run has occurred. Bit 2 Not used. This bit is a read/write status flag that the user can read which indicates that the standby RAM voltage has been applied. data is read from external memory. Included in the instruction set section are the following: • MPU Programming Model (Figure 23) • Addressing modes • Accumulator and memory instructions . 8·8.nter ISP) 115 PC 0 1 Program Counter (PC) • RAM CONTROL REGISTER This register.Table 12 · Op codes Map . These are one-byte instructions. Cond'tion Code Register ICCR) Carry/Borrow from MSB RAM Control Register Overflow Zero Negative Interrupt Half Carry IFrom Bit 3) Bit 0 Not used. which is addressed at $0014. the received bit stream is synchronized by the first 0 (space) encountered.Table 13 • MPU Programming Model The programming model for the HD6801S is shown in Figure 23. gives status information about the standby RAM. GENERAL DESCRIPTION OF INSTRUCTION SET The HD6801S is upward object code compatible with the HD6800 as it implements the full HMCS6800 instruction set. Immediate Addressing In immediate addressing.Table Receive Operation The receive operation is enabled by the RE bit which gates in the serial input through Port 2 Bit 3. If the tenth bit is not a 1 (stop bit) a framing error is assumed.Table 9 53 . The receiver section operation is conditioned by the contents of the Transmit/ Receive Control and Status Register and the Rate and Mode Control Register. these times would be microseconds. This bit is set to a logic "I" by RES which enables the standby RAM and can be written to one or zero uner program control. and the data in the standby RAM is valid. and interrupt flag RDRF is set. Bit 6 RAME The RAM Enable control bit allows the user the ability to disable the standby RAM. The approximate center of each bit time is strobed during the next 10 bits. A summary of the addressing modes for a particular instruction . These are two or three-byte instructions. Bit 3 Not used. Bit 5 Not used. When the HD6801S responds to either flag (RDRF or ORFE) by reading the status register followed by reading the Data Register. as explained previously in the signal description for Vee Standby. and bit ORFE is set. ORFE will be set. If RDRF is still set at the next tenth bit time.Table 10 • Instructions Execution times in machine cycles . Bit 4 Not used.can be found in Table 11 along with the associated instruction execution time that is given in machine cycles.Table 7 • New instructions • Index register and stack manipulations instructions . these include 16-bit operations and a hardware multiply. II • Summary of cycle by cycle operation . RDRF (or ORFE) will be cleared. The execution times of key instructions have been reduced to increase throughout. With a clock frequency of 4 MHz. • Figure 23 MCU Programming Model • MPU Addressing Modes The HD6801S eight-bit microcomputer unit has seven address modes that can be used by a programmer. with the addressing mode a function of both the type of instruction and the coding with~ the instruction. The receiver bit interval is divided into 8 sub-intervals for internal synchronization. Register IX) 115 X 0 1 1 15 SP 0 1 Stack Po. new instructions have been added. If the tenth bit as aI.

M 3 A ... DIAECT Aegister ------. A COMA 43 2 1 COMB 53 2 1 B -+ B 60 6 2 70 6 3 40 2 1 50 2 1 19 2 1 DECA 4A 2 1 DECB 5A 2 1 DAA I 6A DEC 6 2 7A 6 3 EOAA 88 2 2 98 3 2 A8 4 2 B8 4 3 EOAB C8 2 2 D8 3 2 E8 4 2 F8 4 3 6C 6 2 7C 6 3 INCA 4C 2 1 INCB 5C 2 1 lDAA 86 2 2 9... B • • Converts binary add of BCD • • characters into BCD format M-1 ....... B • • A@M ...... B ADDD C3 4 3 D3 ..... A Add Accumulators ABA Add With Carry ADCA 89 ADCB C9 2 2 ANDA 84 2 ANDB C4 2 2 D4 3 2 E4 BITA 85 2 2 95 3 2 A5 4 2 B5 4 3 A·M BIT B C5 2 2 D5 3 2 E5 4 2 F5 4 3 6F 6 2 7F 6 3 B·M 00 .1 -+ SP • • SP + 1 -+ SP... B... B f 2 94 3 2 A4 4 4 3 A·M .5 2 i:3 6 2 F3 6 3 A:B+M:M+1 .. HD8801S6----------------------------------------------Table 7 Accumulator & Memory Instructions Condition Code Addressing Modes Operations Add Add Double Mnemonic ~---r----- IMMED........... ~ A A t f t f C .HD8801S0.. • ~ • ~ : • ~ : • : f • f f • A S • A S • A S A-M INC Aotate Aight • : 4 3 NEGA NEGB Aotate left f f t f B1 (Negate) Pull Data f f f f f f 2 NEG Push Data ~ ~ 4 Complement.6 3 2 A6 4 2 B6 4 3 lDAB C6 2 2 D6 3 2 E6 4 2 F6 4 3 load Double Accumulator lDD CC 3 3 DC 4 2 EC 5 2 FC 5 3 Multiplv Unsigned MUl OA. A 4 2 B4 2 F4 4 3 B·M . A t 3 2 E9 4 2 F9 4 3 B+M+C ... B • • • • • • • • - # OP 1B 2 H # 1 A + B . A • • AxB-+A:B • • A+M-+A • • B + M-+ B • • A -+ Msp. B • CMPB C1 2 2 3 . M . 2's load Accumulator ~ ~ A1 COM Increment ~ 2 Complement. M • • A . SP ....-INDEX EXTEND IMPLIED - # OP - # OP - # ADDA 8B 2 2 9B 3 2 AB 4 2 BB 4 3 A+ B .... A 5 OP OP - Boolean/ Arithmetic Operation • • • • OO-M ...... 1's Exclusive OA • • • • f • 3 11 AOA 66 6 2 76 6 3 1 0 ~ 2 91 3 2 ~ 2 D1 3 I N Z V 81 CBA Decrement 4 CMPA Compare Accumulators Decimal Adjust.. M AND Bit Test ClA Clear Compare ClAA 4F 2 1 00 ..... Msp ..l .... A • • B-1 ... Inclusive OAAA 2 9A 3 CA 2 2 DA 3 2 AA 4 2 BA 4 3 2 EA 4 2 FA 4 3 OAAB 3D 10 1 8A 2 PSHA' 36 3 1 PSHB 37 3 1 PULA 32 4 1 PUlB 33 4 1 49 2 1 59 2 1 AOAA 46 2 1 AOAB 56 2 1 AOl 69 6 2 79 6 3 AOlA AOLB . A:B 2 99 2 D9 3 2 A9 4 2 B9 4 3 A+M+C .... B • • • • ~} lo-1 I I i I I I liJ • • bo B C b7 • • • • :} 4}:j I I I I I I liJ • • bO B C b7 • • · · f f : ~ A A A A 54 ~ f f f f • • • • A A A A f f t f f f t A S t t t t f A S t A S ~ CV@ (j)@ t t t \V @ ~ f t @ t t t t @ • f f @ • @ • t t t t A t A • • t @ • t t t t t t @ • t t A t t A • • • • • • ® ~ ~ • • • • t t t @ • A A A • • • • • • • • • • • • • • t (§) f t t (~ f t t ® t t ~ (§) t t f (§) t t t 11 t (Continued) The Condition Code Aeglster notes are listed after Table 10..... A ClAB 5F 2 1 00 ... A • B 0 M-+ B • • M+1-+M • • A+1-+A • • B+1-+B • • M-+A • • M-+B • • M + 1 ...... A ADDB CB 2 2 DB 3 2 EB 4 2 FB 4 3 B+M .1 -+ SP • B -+ Msp..2 E1 4 2 Fl 4 B-M • • A-B • • • • 63 6 2 73 6 2 1 M .......... Msp -+ A • • SP + 1 -+ SP.. A • • OO-B . M • • OO-A ......... SP ..

.§. This is an absolute address in memory.\ the second byte of the instruction.. locations zero through 255.... stack pOinter. the address contained in the second byte of the instruction is added to the program counter's lowest eight bits plus two. Direct addressing allows the user to directly address the lowest 256 bytes in the machine i. These are two-byte instructions.. OP Shift Left Arithmetic Double Shift Left. The carry or borrow is then added to the high eight bits....e.. it should be a random access memory.. The carry is then added to the higher order eight bits of the index register. M+ 1 Subtract SUBA 80 2 2 90 3 2 AO 4 2 BO 4 3 A-M .. Indexed Addressing In indexed addressing. A SUBB CO 2 2 DO 3 2 EO 4 2 FO 4 3 B -M ... M B . M Store Double Accumulator STD DO 4 2 ED 5 2 FD 5 3 A ...----------------------------------------------HD6801S0.. * • • t t @ t • • t 6 t • • *t * @t • • t * @t • • t * @t • • R * @t • • t *R • • • t t R • • • • • • t t *t t • t t t t t t t t *t tt ·• '•..Iister notes are listed after Table 10.. HD6801S6 Table 7 Accumulator & Memory Instructions (Continued) Condition Code Register Addressing Modes Operations Mnemonic IMMED... etc. Arithmetic Shift Right Arithmetic Shift Right Logical Double Shift Right Logical - # INDEX DIRECT OP - # OP 68 ASL EXTEND IMPLIED - # OP - # OP 6 2 78 6 3 ASLA Booleanl Arithmetic Operation 48 2 1 M} __ D--I II II I II A C B ASLB 58 2 1 ASLD 05 3 1 ~ 67 6 2 77 6 3 ASRA 47 2 1 ASRB 57 2 1 44 2 1 64 LSR 6 2 74 6 LSRB 54 2 1 LSRD 04 3 1 - AO 87 ~} C?I B b7 _ Ao-oillllllll-\J B b7 0--1 - ACC A7 97 3 2 A7 4 2 B7 4 3 STAB 07 3 2 E7 4 2 F7 4 3 B . A Subtract With Carry SBCA 82 2 2 92 3 2 A2 4 2 B2 4 3 A-M-C-+A SBCB C2 2 2 02 3 2 E2 4 2 F2 4 3 B-M-C-+B Trensfer Accumulators TAB 16 2 1 A-+B TBA 17 2 1 B-+A Test Zero or Minus TST TSTA 40 2 1 A -00 TSTB 50 2 1 B - 6 2 70 The Condition Code Re!. Enhanced execution times are achieved by storing data in these locations..e. B Double Subtract SUBD 83 4 3 93 5 2 A3 6 2 B3 6 3 Subtract Accu mu lators SBA bO ACeS AI AO STAA 87 2 1 A-B . Extended Addressing In extended addressing. The modified address is held in a temporary address register so there is no change to the index register. This result is then used to address memory.)..... Direct Addressing In direct addressing. Relative Addressing In relative addressing.. A:B 10 60 80 IIIII !bO~ A . Implied Addressing In the implied addressing mode the instruction gives the address (i.. 6 ~ 80 A:B-M:M+1 .. These are one-byte instructions.. This allows the user to address data within a range of -126 to + 129 bytes of the present instruction.. Xl'!l'! II ]-0 A7 ASR M-OO 3 5 H # 00 4 3 2 I N Z • • • • t • • • • • t t 1 0 V C ®* @* * * • • * * ®* • • t t @* • • * * !. The third byte of the instruction is used as the lower eight-bits of the address for the operand. index register. In most configurations. the address contained in the second byte of the instruction is added to the index register's lowest 55 . These are three-byte instructions. M Store Accumulator 1-0 bO - M} 3 LSRA b7 Al'!l'! 'lJ. These are two-byte instructions. the address contained in the second byte of the instruction is used as the higher eight-bits of the address of the operand..... These are two-byte instructions. * • • R t t t t t t t t t R t t R t t R R t R R • • • • • • * • • *t • • R R eight bits in the Meu. the address of the operand is contained D.

The C bit is loaded from the most significant bit of ACCD..(j) f • (j)f R R • • • • I(j) f R • • • • • • R • • • • • • • • • • • • • • • • • • • • • .. Bit 15 is loaded with zero. the following new instructions are incorporated in the HD6801S Microcomputer. LDD Loads the contents of double precision memory location into the double accumulator A:B. BRN Never branches. XH SP + 1 . SP .. The C bit is loaded from the least significant bit to ACCD.HD6801S0.. Table 8 Index Register and Stack Manipulation Instructions Condition Code Register Addressing Modes Pointer Operations Mnemonic IMMED.. The stack pointer is decremented by 2. The stack pointer is incremented by 2 in total. HD6801S6---------------------------------------------• New Instructions In addition to the existing 6800 Instruction Set. ACCA contains MSB of result. XL -+ (M + 1) 5 3 SPH-+M. DIRECT - # OP - # OP - 8C 4 3 9C 5 2 AC 6 IMPLIED EXTND INDEX OP # OP - 2 BC 6 # Boolean! Arithmetic Operation OP - # 09 3 1 1 SP .1 -+ SP Pull Data PULX 38 5 1 SP + 1 -+ SP. Msp .(j) + . M sp . X Increment Stack Pntr INS 31 3 1 SP + 1 -+ SP Load Index Reg LOX CE 3 3 Load Stack Pntr LOS 8E 3 3 Store I ndex Reg STX 2 EE 5 2 FE AE 5 2 BE OF 4 2 EF 5 2 FF 9F 4 2 AF 5 2 BF DE 4 9E 4 2 X-M: M + 1 X-1-+X 5 3 M-+ XH.. PSHX The contents of the index register is pushed onto the stack at the address contained in the stack pointer. SUBD Subtracts the contents of M:M + I from the contents of double accumulator AB and places the result in ACCD.. LSRD Shifts all bits of ACCD one place to the right. this instruction can be considered a two byte NOP (No operation) requiring three cycles for execution.SP L .. The contents of ACCD remain unchanged. The A-accumulator is the most significant byte.. *ACCD is the 16 bit register (A:B) formed by concatenating the A and B accumulators. 56 ~ XL 2 5 4 3 H I N Z • f • • • • • • • • • • • • • f 1 0 V C f t • • • • • • • • • f • • f • • • • • • • .. XL 5 3 M -+ SP H .1 -+ SP X H . Msp The Condition Code Register notes are listed after Table 10. If effect. SP .1 -+ SP 3 Compare Index Reg CPX Decrement Index Reg DEX Decrement Stack Pntr DES 34 3 Increment Index Reg INX 08 3 1 X + 1 . PULX The index register is pulled from the stack' beginning at the current address contained in the stack pointer + 1. The condition codes are set according to the data. Bit 0 is loaded with zero..... ASLD Shifts all bits of ACCD one place to the left.. ABX Adds the 8-bit unsigned accumulator B to the 16-bit X-Register taking into account the possible carry out of the low order byte of the X-Register... MUL Multiplies the 8 bits in accumulator A with the 8 bits in accumulator B to obtain a 16-bit unsigned number in A:B. ADDD Adds the double precision ACCD* to the double precision value M: M+ 1 and places the results in ACCD. STD Stores the contents of double accumulator A:B in memory. (M+ 1) .. SP. (M+ 1) -+ SP L 5 3 X H -+ M. (M+1) Store Stack Pntr STS Index Reg -+ Stack Pntr TXS 35 3 1 X-1-+SP Stack Pntr -+ Index Reg TSX 30 3 1 SP + 1 -+ X Add ABX 3A 3 1 B+X-+X Push Data PSHX 3C 4 1 XL -+ M sp . CPX Internal processing modified to permit its use with any conditional branch instruction.

. Test: Result less than zero? (Bit 15 = 1) Load Condition Code Register from Stack..... CCR TAP 06 2 1 A . Zero BGE 2C 3 2 N(±)V=O > Zero BGT 2E 3 2 Z+(N(±)V)=O Branch If Higher BHI 22 3 2 Branch If 0. 2 1 Advances Prog..----------------------------------------------HD6801SQ. 5o... HD6801S6 Table 9 Jump and Branch Instructions Condition Code Register Addressing Modes Operations Mnemonic .A • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • · ·· ·· · ·• · · · • • ·• ·· · · • • • · • • • • • • S • • • • • ®....1 0. Set equal to result of Bit 7 (AccB) 57 0 • • • • S • • S • R • • • • • • Condition Code Register Notes: (Bit set it test is true and cleared otherwise) (Bit V) (Bit C) (Bit C) (Bit V) (Bit V) (Bit V) (Bit N) (All) (Bit I) @ (All) ® (Bit C) C • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • Condition Code Register Boolean Operation IMPLIED CLC @ @ @ @ @ (j) @ @ 0 Condition Code Register Manipulation Instructions Clear Carry CD 1 V --@- IAddressingModes Operations 2 N Z • • • • Z + (N Gl V) = 1 BLS 3 I ·• C+Z=O BLT 4 • • • • • None --r--- 5 H ... (See Special Operations) Set when interrupt occurs.d.. Only 1 Mnemonic See Special Operations 1 OP ~ OC 2 1 # Clear Interrupt Mask Cli OE 2 1 0-1 Clear Overflow CLV OA 2 1 O-V Set Carry SEC 00 2 1 l-C Set Interrupt Mask SEI OF 2 1 1-1 Set Overflow SEV OB 2 1 l-V Accumulator A .i---- 23 3 2 C+ Z = 1 2D 3 2 NGlV=l Branch If Minus BMI 2B 3 2 N= 1 Branch If Not Equal Zero BNE 26 3 2 Z=O Branch If Overflow Clear BVC 28 3 2 v=o Branch If Overflow Set BVS 29 3 2 V =1 Branch If Plus BPL 2A 3 2 N=O 80 6 2 Branch To Subroutine BSR Jump JMP Jump To Subroutine JSR No Operation NOP 01 Return From InterruptI RTI 3B 10 1 Return From Subroutine RTS 39 5 Software Interrupt SWI 3F 12 1 Wait for Interrupt WAI 3E 9 3 2 7E 3 3 AD 6 2 BD 6 3 6E 90 Table10 5 2 )s. Set according to the contents of Accumulator A."'.------. a Non-Maskable Interrupt is required to exit the wait state.0..----- RELATIVE OP ~ # DIRECT OP # ~ INDEX OP EXTND # ~ OP ~ Branch Test IMPLIED OP # ~ # Branch Always BRA Branch Never BRN 21 3 2 Branch If Carry Clear BCC 24 3 2 C=O Branch If Carry Set BCS 25 3 2 C=l Z=l 20 3 2 None Branch If = Zero BEQ 27 3 2 Branch If . Accumulator A TPA 07 2 1 CCR . • • • O-+C 5 4 3 2 1 H I N Z V C • • • • R • • • • • • • • S • • • • • • • • R ··· @) Test: Result = 10000000? Test: Result ~ OOOOOOOO? Test: Decimal value of most significant BCD Character greater than nine? (Not cleared if previously set) Test: Operand = 10000000 prior to execution? Test: Operand = 01111111 prior to execution? Test: Set equal to result of NE!:)C after shift has occurred. CCR CCR . If previously set. Cntr. Zero BLE 2F 3 2 Branch If Branch If Lower Or Same Branch If < Zerc r-.

HD880186--------------------------------------------Table 11 ABA ABX ADC ADD ADDD AND ACCX I~::- • • • • • • • ASL 2 ASLD • ASR BCC BCS BEQ BGE BGT BHI BIT BLE BLS BLT BMI BNE BPL BRA BRN BSR BVC BVS CBA CLC CLI CLR CLV CMP COM CPX DAA DEC 2 • • f • • • • • • • • • • • • • • • • • • 2 • • 2 • • 2 EOR • • • INC 2 INS • DES DEX • 2 2 4 2 • • • • • • • • • Direct • • 3 3 5 3 • • • • • • te~~~ Indexed • 2 4 • 4 3 • 4 4 • 6 6 • 4 4 • 6 6 • • 6 3 • • • • • • • • • 6 • • • • • • • 2 3 4 4 • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 6 6 • • • • • • • 2 3 4 4 • • 6 6 4 5 6 6 • • • • • • • • 6 6 • • • • • • 2 3 4 4 • • • 6 6 • • • 1mplied • • • • • • Instruction Execution Times in Machine Cycles • • • • • • • • • • • • • • 2 2 2 • 2 • • • 2 • 3 3 • • 3 Relative ACCX • • • INX JMP JSR • LOA • • • LDD LOS LOX LSR • LSRD • • • • • • • 2 • • 3 MUL NEG 3 NOP 3 ORA 3 PSH 3 3 PSHX • 3 PUL PULX ROL ROR • 3 RTI 3 3 3 3 6 3 3 RTS 3 3 3 SBA SBC SEC SEI SEV STA • • STD STS • STX • • • • • • • SUB SUBD SWI TAB TAP • • • • • 4 • 2 2 • • • • • • • • • • • • • • • • TBA TPA TST • • TSX • • • TXS WAI 58 2 • • 2 • • • 2 3 3 3 • • • 3 3 5 3 6 6 4 4 4 5 5 5 5 5 5 6 4 4 • • Implied Relative 3 • • • • • • • • • • • • • • • • • • • 6 6 • • • 2 3 4 4 • • • • • • • • • • .'• • • • • 6 6 6 6 • • • • • • • • • 10 5 2 2 3 4 4 • • • • • • • • • • • • • • • • 3 4 4 4 5 5 5 5 5 5 4 6 • • • • • 4 4 4 3 5 • • • • • • • • • • • • • • • • • • 2 6 • 4 6 • • • • • • • • • • • • 6 6 • • • • • • • • • • 3 10 • 2 • • 4 • 5 • 2 2 2 • • • • • • 12 2 2 2 • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 2 • 3 3 9 • • • • .HD880180.

~-~ STS STX STD 4 1 2 3 4 CPX SUBD ADDD 5 1 2 3 4 5 JSR 5 1 2 3 4 5 0 0 (Continued) 59 . instructions with the same addressing mode and number of cycles execute in the same manner. (In general. This information is useful in comparing actual with expected results during debug of both software and hardware as the control program is executed.-~ . and the Read/Write line (R/W) during each cycle for each instruction. HD8801S6 • Summary of Cycle by Cycle Operation Table 12 provides a detailed description of the information present on the Address Bus._-------- ------- DIRECT ADC ADD AND BIT CMP EOR LOA ORA SBC SUB 3 1 2 3 --r----- STA 3 LDS LDX LDD 4 1 2 3 1 2 3 4 Op Code Address Op Code Address + 1 Destination Address 0 Op Code Destination Address Data from Accumulator Op Code Address Op Code Address + 1 Address of Operand Operand Address + 1 1 1 1 1 Op Code Address of Operand Operand Data (High Order Byte) Operand Data (Low Order Byte) Op Code Address Op Code Address + 1 Address of Operand Address of Operand + 1 1 1 0 0 Op Code Address of Operand Register Data (High Order Byte) Register Data (Low Order Byte) Op Code Address Op Code Address + 1 Operand Address Operand Address + 1 Address Bus F F F F 1 1 1 1 1 Op Code Address of Operand Operand Data (High Order Byte) Operand Data (Low Order Byte) Low Byte of Restart Vector Op Code Address Op Code Address + 1 Subroutine Address Stack Pointer Stack Pointer + 1 1 1 1 Op Code Irrelevant Data First Subroutine Op Code Return Address (Low Order Byte) Return Address (High Order Byte) .. - -- 1 1 1 Op Code Operand Data (High Order Byte) Operand Data (Low Order Byte) Op Code Address Op Code Address + 1 Op Code Address + 2 Address Bus F F F F 1 1 1 1 Op Code Operand Data (High Order Byte) Operand Data (Low Order Byte) Low Byte of Restart Vector Op Code Address Op Code Address + 1 Address of Operand 1 1 1 Op Code Address of Operand Operand Data 1 1 ------. exceptions are indicated in the table). Table 12 Cycle by Cycle Operation Address Mode & Instructions Addres~ Bus Data Bus IMMEDIATE ADC ADD AND BIT CMP EOR LOA ORA SBC SUB 2 1 2 Op Code Address Op Code Address + 1 LOS LOX 3 1 2 Op Code Address Op Code Address + 1 Op Code Address + 2 CPX SUBD ADDD 4 -------- 3 1 2 3 4 Op Code Operand Data 1 1 ---~- ---. Data Bus.. The information is categorized in groups according to addressing mode and number of cycles per instruction.----------------------·-------------------------HD8801S0..

- -------- Op Code Address Op Code Address + 1 Address Bus FFFF Index Register Plus Offset Index Register Plus Offset + 1 .._------ Op Code Add ress Op Code Address + 1 Address Bus F F F F Index Register Plus Offset Index Register Plus Offset + 1 Op Code Offset Low Byte of Restart Vector Current Operand Data Low Byte of Restart Vector New Operand Data Op Code Address Op Code Address + 1 Address Bus FFFF Index Register Plus Offset Address Bus F F F F Index Register Plus Offset 1 -1 1 1 1 0 Op Code Address Op Code Address + 1 Address Bus F F F F Index Register + Offset Index Register + Offset + 1 Address Bus F F F F 1 1 1 1 1 1 Op Code Offset Low Byte of Restart Vector Operand Data (High Order Byte) Operand Data (Low Order Byte) Low Byte of Restart Vector Op Code Address Op Code Address + 1 Address Bus F F F F Index Register + Offset Stack Pointer Stack Pointer .. R/iN line of the sixth cycle is "1" level. (Continued) . and AB 60 = FFFF.. _ ._..1 1 1 1 1 0 0 Op Code Offset Low Byte of Restart Vector First Subroutine Op Code Return Address (Low Order Byte) Return Address (High Order Byte) *In the TST instruction... HD8801S6---------------------------------------------Table 12 Cycle by Cycle Operation (Continued) Address Mode & Instructions Address Bus Data Bus INDEXED JMP 3 1 2 3 ADC ADD AND BIT CMP EOR LOA ORA SBC SUB 4 3 4 4 STA 1 2 1 2 3 4 LOS LDX LDO 5 STS STX STD 5 ASL ASR CLR COM DEC INC 1 2 3 4 5 1 2 3 4 5 LSR NEG ROL ROR TST* 6 1 2 3 4 5 6 CPX SUBD AODD 6 JSR 6 1 2 3 4 5 6 1 2 3 4 5 6 Op Code Address Op Code Address + 1 Address Bus F F F F 1 1 1 Op Code Offset Low Byte of Restart Vector Op Code Address Op Code Address + 1 Address Bus FFFF Index Register Plus Offset 1 1 1 1 Op Code Offset Low Byte of Restart Vector Operand Data Op Code Address Op Code Address + 1 Address Bus FFFF Index Register Plus Offset 1 1 1 0 Op Code Offset Low Byte of Restart Vector Operand Data 1 1 1 1 1 Op Code Offset Low Byte of Restart Vector Operand Data (High Order Byte) Operand Data (Low Order Byte) 1 1 1 0 0 Op Code Offset Low Byte of Restart Vector Operand Data (High Order Byte) Operand Data (Low Order Byte) - ..HD8801S0. DB = Low Byte of Reset Vector......---- _..

1 1 1 1 1 1 a a "In the TST instruction.f------Op Code Address of Operand Address of Operand (Low Order Byte) Operand Data Op Code Destination Address (High Order Byte) .. HD6801S6 Table 12 Cycle by Cycle Operation (Continued) Address Mode & Instructions Address Bus Data Bus EXTENDED 3 JMP 1 2 -- ADC ADD AND BIT CMP EOR LOA ORA SBC SUB STA A STA B 4 3 1 2 1 2 3 4 LOS LOX LDD 5 STS STX STD 5 ASL ASR CLR COM DEC INC 1 2 3 4 5 1 2 3 4 5 LSR NEG ROL ROR TST* 6 1 2 3 4 5 6 CPX SUBD ADDD 6 JSR 6 1 1 1 Op Code Addre~s Op Code Address + 1 Op Code Address + 2 Address of Operand 1 1 1 1 ~--- 3 4 4 Op Code Address Op Code Address + 1 Op Code Address + 2 1 2 3 4 5 6 1 2 3 4 5 6 Op Code Op Code Op Code Operand Address Address + 1 Address + 2 Destination Address I 1 1 1 0 Op Code Jump Address (High Order Byte) Jump Address (Low Order Byte) .----------------------------------------------HD6801S0. and AB=FFFF. R/W line of the sixth cycle is "'" level. DB=Low Byte of Reset Vector. 61 (Continued) . Destination Address (Low Order Byte) Data from Accumulator Op Code Address Op Code Address + 1 Op Code Address + 2 Address of Operand Address of Operand + 1 1 1 1 1 1 Op Code Address of Operand Address of Operand Operand Data (High Operand Data (Low (High Order Byte) (Low Order Byte) Order Byte) Order Byte) Op Code Address Op Code Address + 1 Op Code Address + 2 Address of Operand Address of Operand + 1 1 1 1 Op Code Address of Operand Address of Operand Operand Data (High Operand Data (Low (High Order Byte) (Low Order Byte) Order Byte) Order Byte) 0 0 Op Code Address Op Code Address + 1 Op Code Address + 2 Address of Operand Address Bus FFFF Address of Operand 0 Op Code Address of Operand (High Order Byte) Address of Operand (Low Order Byte) Current Operand Data Low Byte of Restart Vector New Operand Data Op Code Address Op Code Address + 1 Op Code Address + 2 Operand Address Operand Address + 1 Address Bus FFFF 1 1 1 1 1 1 Op Code Operand Address (High Order Byte) Operand Address (Low Order Byte) Operand Data (High Order Byte) Operand Data (Low Order Byte) Low Byte of Restart Vector 1 1 1 1 Op Code Address of Subroutine (High Order Byte) Address of Subroutine (Low Order Byte) Op Code of Next Instruction Return Address (Low Order Byte) Address of Operand (High Order Byte) -Op Code Address Op Code Address + 1 Op Code Address + 2 Subroutine Starting Address Stack Point~r Stack Pointer .

1 1 1 Op Code Irrelevant Data Index Register (Low Order Byte) Index Register (High Order Byte) 0 0 3 4 5 1 2 3 4 1 1 1 1 1 1 1 1 1 5 Stack Pointer + 2 1 1 2 Op Code Address Op Code Address + 1 Stack Pointer Stack Pointer .HD8801S0.1 1 1 3 4 Op Code Irrelevant Data Low Byte of Restart Vector Op Code Address Op Code Address + 1 Stack Pointer Op Code Address Op Code Address + 1 Stack Pointer Stack Pointer + 1 Stack Pointer +2 Op Code Address Op Code Address + 1 Stack Pointer Stack Pointer + 1 1 2 RTS Op Code Address Op Code Address + 1 62 0 0 OpCode Irrelevant Data Irrelevant Data Index Register (High Order Byte) Index Register (Low Order Byte) Op Code Irrelevant Data Irrelevant Data Address of Next Instruction (High Order Byte) Address of Next Instruction (Low Order Byte) Op Code Op Code of Next Instruction Return Address (Low Order Byte) Return Address IHiah Order Bvtel (Continued) .ddress + 1 Address Bus F F F F Op Code Address Op Code Address + 1 Previous Register Contents Op Code Address Op Code Address + 1 Address Bus F FFF Op Code Op Code of Next Instruction Low Byte of Restart Vector 0 Op Code Op Code of Next Instruction Accumulator Data Op Code Address Op Code Address + 1 Stack Pointer 1 1 1 Op Code Op Code of Next Instruction Irrelevant Data Op Code Address Op Code Address + 1 Address Bus F F F F 1 1 1 Op Code Op Code of Next Instruction Low Byte of Restart Vector Op Code Address Op Code Address + 1 Stack Pointer Stack Pointer + 1 1 1 1 1 Op Code Op Code of Next Instruction Irrelevant Data Op Code Address Op Code Address + 1 Stack Pointer Stack Pointer . HD8801S6--------------------------------------------Table 12 Cycle by Cycle Operation (Continued) Address Mode & Instructions Data Bus Address Bus IMPLIED ABA ASL ASR CBA CLC CLI CLR CLV COM DAA DEC INC LSR NEG NOP ROL ROR SBA SEC SEI SEV TAB TAP TBA TPA TST 2 1 2 ABX 3 ASLD LSRD 3 DES INS 3 INX DEX 3 PSHA PSHB 3 TSX 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 TXS 3 1 2 3 PULA PULB 4 1 2 3 4 PSHX 4 1 2 3 4 PULX 5 WAI** 5 9 1 1 Op Code Op Code of Next Instruction Op Code Address Op Code Address + 1 Address Bus F F F F 1 1 1 1 1 1 Op Code Irrelevant Data Low Byte of Restart Vector 1 1 1 1 1 1 Op Code Op Code of Next Instruction Irrelevant Data 1 1 Op Code Address Op Code A.

its bus state will appear as a series of MPU reads of an address which is seven locations less than the original contents of the Stack Pointer.1 1 1 0 0 5 6 7 10 11 Stack Pointer Stack Pointer Stack Pointer Stack Pointer Stack Pointer Stack Pointer Vector Address 2 3 4 5 6 7 FFFA (Hex) 0 0 0 0 0 1 1 12 Vector Address FFFB (Hex) 1 1 2 3 4 5 6 7 8 9 RTI Address Bus 10 1 2 3 4 8 9 Data of Restart of Restart of Restart of Restart of Restart of Restart of Restart of Restart Vector Vector Vector Vector Vector Vector Vector Vector Op Code Irrelevant Data Return Address (Low Order Byte) Return Address (High Order Byte) Index Register (Low Order Byte) Index Register (High Order Byte) Contents of Accumulator A Contents of Accumulator B Contents of Condo Code Register Irrelevant Data Address of Subroutine (High Order Byte) Address of Subroutine (Low Order Byte) **While the MPU is in the "Wait" state. from Stack Contents of Accumulator B from Stack Contents of Accumulator A from Stack Index Register from Stack (High Order Byte) Index Register from Stack (Low Order Byte) Next Instruction Address from Stack (High Order Byte) Next Instruction Address from Stack (Low Order Byte) 1 2 3 4 Op Code Address Op Code Address + 1 Stack Pointer Stack Pointer . Cycle # 5 6 7 8 9 MUL 10 SWI 10 12 Stack Stack Stack Stack Stack Pointer Pointer Pointer Pointer Pointer - 2 3 4 5 6 R/W Line 0 0 0 0 0 Data Bus Index Register (Low Order Byte) Index Register (High Order Byte) Contents of Accumulator A Contents of Accumulator B Contents of Condo Code Register Op Code Address Op Code Address + 1 Address Bus F F F F Address Bus F F F F Address Bus F F F F Address Bus F F F F Address Bus F F F F Address Bus FFFF Address Bus FFFF Address Bus F F F F 1 1 1 1 1 1 1 1 1 1 Op Code Irrelevant Low Byte Low Byte Low Byte Low Byte Low Byte Low Byte Low Byte Low Byte Op Code Address Op Code Address + 1 Stack Pointer Stack Pointer + 1 1 1 1 1 5 Stack Pointer + 2 1 6 Stack Pointer + 3 1 7 Stack Pointer + 4 1 8 Stack Pointer + 5 1 9 Stack Pointer + 6 1 10 Stack Pointer + 7 1 OpCode Irrelevant Data Irrelevant Data Contents of Condo Code Reg. (Continued) 63 . none of the ports are driven to the high impedance state by a WAI instruction. HD8801S6 Table 12 Cycle by Cycle Operation (Continued) Address Mode & Instructions WAI** Cycles. Contrary to the HD6800.-------------------------------------------HD8B01S0.

and undefined op codes (SF. COM CMP 1 SBC 2 SUBD (+2) ·: ADDD (+2) 3 4 LSR AND BIT 5 ROR LDA 6 ASR / / STA STA 7 EOR ASL 8 ROL ADC 9 DEC ORA A INC TST --. Table 13 H06aal S ACC A ~ 0000 0 0001 1 2 0010 0011 3 0100 4 0101 5 0110 6 ------- 0001 0 0010 3 TSX CBA BRN INS ~ BHI PULA (+1) ~ BLS PULB (+1) ~ BCC DES ASLD (+1) ~ BCS TXS TAP TAB BNE PSHA 0111 7 TPA TBA BEQ PSHB 1000 S INX (+1) ~ BVC PULX (+2) 1001 9 DEX (+1) DAA BVS RTS (+2) 1010 A CLV ~ BPL ABX 1011 B SEV ABA BMI RTI (+7) 1100 C CLC ~ BGE PSHX (+1) 1101 0 SEC /' BLT MUL (+7) / 1110 E CLI BGT WAI (+6) 1111 F SEI ~ BLE SWI (+9) 112 1/2 2/3 1/3 BYTE/CYCLE [NOTES) 1) Undefined Op codes are marked with 2) ( ACCA orSP EXT -----------4 2 BRA -- ACC IND B 0100 0101 0110 0111 1 LSRD (+1) Op codes Map 0011 SBA NOP LSI.. --- JMP (-3) 1/2 2/6 ADD CPX (+2) r. These op codes are used to test the The HD6801 S has 36 undefmed instructions.HD6801S0. 5E) are used to execute.". the MPU continues to increase the program counter and it will not stop until the Reset signal enters. Immediate addressing mode of SUBD. CF). When these are carried out. JSR (+2) 3/6 2/2 2/4 " 3/4 2/2 F STX(+l1 2/3 ~. CPX. the contents of Register and Memory in MPU change at random. C STD(+l1 • (+11 STS (+1) 2/3 · · B LDD(+1) : (+1) LDS (+1) : (+1) CLR 1/2 . MICROCOMPUTER INSTRUCTIONS OP CODE 0000 a a 5 6 IMM DIR IND 1000 1001 8 7 ACCB or X EXT 1010 1011 A 9 IMM DIR IND 1100 1101 B D C EXT 1110 1111 E F 0 SUB NEG =------== . LDD and LDX instructions.. ADDD. 64 D E LOX (+1) ) indicate that the number in parenthesis must be added to the cycle count for that instruction. and are marked with " •• ". 5E) are 1 byte/oo cycles instructions. 3) The instructions shown below are all 3 bytes and are marked with ".4~ . HD6801S6---------------------------------------------Table 12 Cycle by Cycle Operation (Continued) Address Mode & Instructions Data Bus Address Bus RELATIVE Bce BCS BEQ BGE BGT BRN BHT BlE BLS BlT BMT 3 BNE BPL BRA BVC BVS BSR 6 1 2 3 Op Code Address Op Code Address + 1 Address Bus FFFF 1 1 1 Op Code Branch Offset Low Byte of Restart Vector 1 Op Code Address 2 3 4 Op Code Address + 1 Address Bus FFFF Subroutine Starting Address Stack Pointer Stack Pointer . CD. 4) The Op codes (4E.1 1 1 1 1 Op Code Branch Offset Low Byte of Restart Vector Op Code of Next Instruction Return Address (Low Order Byte) Return Address (High Order Byte) 5 6 • Summary of Undefined Instruction Operations When the op codes (4E. LOS. 2/4 3/4 .

PC NMI FFFC FFFO Non-Maskable Interrupt SWI FFFA FFFB Software Interrupt IRQ... ICF OCF TOF SCI FFF8 FFF9 Maskable Interrupt Request 1 Input Capture Interrupt Output Compare Interrupt Timer Overflow Interrupt FFF6 FFF4 FFF2 FFFO FFF7 FFF5 FFF3 FFF1 SCI Interrupt (TORE + RORF + ORFE) :r: c m CO o ( I) ~ :r: c m CO o Figure 24 Interrupt Flowchart ( I) en ..en 01 *SCI = TIE·TORE + RIE·(RORF + ORFE) Vector .

Vee Standby Port 3 8 Transfer RES Lines Port 1 8110 Port 1 8110 L.HD6801SQ.nes Lines Port 2 51/0 Lines Port 4 8 I/O Lines SCI Vss VSS Figure 25 Port 4 8110 Lohes Port 2 5110 Lines SCI H06801 S MCU Single-Chip Dual Processor Configuration HD6801S MCU Address Bus Data Bus Figure 26 H06801 S MCU Expanded Non-Multiplexed Mode Address Bus Data Bus Figure 27 H06801 S MCU Expanded Multiplexed Mode 66 . HD6801S6 vee vee t::I Enable Enable NMI iiiMi IRQ.

The HD6801V MCV is object code compatible with the HD6800 with improved execution times of key instructions plus several new 16-bit and 8-bit instructions including an 8x8 unsigned multiply with 16-bit result. The H0680 1V MCV has 4k bytes of ROM and 128 bytes of RAM on chip. P 17 p.t-P23 P2. Features and Block diagram of the HD6801V include the following: -PRELIMINARY- HD6801VOP HD6801V5P (DP-40) • • FEATURES Expanded HMCS6800 Instruction Set • • 8 x 8 Multiply On-Chip Serial Communications Interface (SCI) • Object Code Compatible With The HD6800 MPU • • 16-Bit Timer Single Chip Or Expandable To 65k Words • • 4k Bytes Of ROM 128 Bytes Of RAM (64 Bytes Retainable On Power Down) • • 29 Parallel I/O Lines And 2 Handshake Control Lines Internal Clock/Divided-By-Four Circuitry P" • • TT L Compatible I nputs And Outputs Interrupt Capability P" P lO P" • Compatible with MC6801 (except ROM size) P" P" • BLOCK DIAGRAM • PIN ARRANGEMENT SC.25 MHz .HD6801V5 MCU (Microcomputer Unit) The HD6801V MCV is an 8-bit microcomputer system which is compatible with the HD6801S except the ROM size.0 volt power supply.. and parallel I/O as well as a three function 16-bit timer. TYPE OF PRODUCTS MCU 67 Bus Timing HD6801VO 1 MHz HD6801V5 1.P20 • ~~---+-P21 ~1-r-------P22 1--Hf-+. P" P" P" P" P" P'6 P. The HD6801V MCV is TTL compatible and requires one +5. The HD6801V MCV can operate as a single chip microcomputer or be expanded to 65k words.. SC..HD6801VO. Serial Communications interface (SCI). P 'O P" P" P" P" HD6801V P" 1 P.. 1 Vcc Standby (Top View) ~--+-j---+.

IRQI.PI?.8 - - V 0. Ta = 25°C.0 V in = 0.0 V V 0.3 .3 - Vee 0. SCI Cin Operating VSBB V SB Powerdown ISBB *Except Mode Programming Levels.P47 SCI EXTAL Ilinl lIinl VIL Input Leakage Current NMI.5.+7. Vss = OV. Normal operation should be under recommended operating conditions. RES PIO .8 - Vin = 0 . • ELECTRICAL CHARACTERISTICS • DC CHARACTERISTICS (Vee =5.5 10 p.0 MHz - V SBB = 4. 68 mA 2.+70°C. P40 Other Inputs Powerdown typ max - Vee 2.0V±5%.4 2.5 .55 -+150 °c Symbol Supply Voltage With respect to VSS (SYSTEM GND) [NOTE] Permanent LSI damage may occur if maximum ratings are exceeded. P30 . Ta = 0.A 2.25 - - 8.4V V in = 0 .4 2.A I LOAD = -145p. SC 2 All Outputs Darlington Drive Current PIO Power Dissipation Input Capacitance Vee Standby Standby Current - Pl7 P30 . SCI. HD6801V5---------------------------------------------• ABSOLUTE MAXIMUM RATINGS Item Vee V in Input Voltage Operating Temperature * * Topr Tstg .2. If these conditions are exceeded. E.A 100 - 1. it could affect reliability of LSI.3 .6 mA -IOH V out = 1.HD6801VO.75 - 5.P37 P20 .0 V -0.0 0 -+70 V °c .5 4.) Itel7l Input "High" Voltage Symbol RES V 1H Other Inputs* Input "Low" Voltage All Inputs* I nput Load Current P40 .0 - 5.0 10.4 VOL I LOAD = -100 p.5 - Po "'" - Unit p.0 pF V rnA .+7.5 V 10.A V 0.8 0. unless otherwise noted.P24 Output "High" Voltage P30 P40 - P37 P47 .Vee Three State (Offset) Leakage Current - Test Condition P47 . - f = 1.25V IITsd V in = 0.5V pther Outputs Output "Low" Voltage min 4.P37 .0 - -0.25 4.0 V in = OV.0 mA - 1200 mW 12.2.4V - V OH I LOAD = -205p.A I LOAD = 1. Storage Temperature * Value Unit -0.

) Symbol Item Cycle Time Address Strobe Pulse Width "High" tCYC PW ASH Address Strobe Rise Time tASr Address Strobe Fall Time tASf tASD Address Strobe Delay Time Enable Rise Time tEr tEf PW EH PW EL Enable Fall Time Enable Pulse Width "High" Time Enable Pulse Width "Low" Time Address Strobe to Enable Delay Time Address Delay Time Address Delay Time for Latch Data Set-up Write Time I I I Non-Multiplexed Bus I Multiplexed Bus Oscillator stabilization Time PERIPHERAL PORT TIMING (Vee 50 5 - - 60 5 5 - 50 - 50 50 30 - - 50 50 - 5 5 340 350 - 50 - 50 - 30 - - - - - - 260 260 - - 60 - - - - tDSR tHR tHW 80 10 ns ns - ns - - - - 20 50 - - ns - 20 - - ns - 10 20 60 - - - 20 - - - - - ns 20 - - ns - - (410) (400) ns - 100 - - ms - 200 - - ns - - (tACCM) - - (610) (600) 100 ns ns -- - 200 liS - - - 115 70 20 =5. unless otherwise noted. 2*. 5 - - 350 ns Delay Time.3. Vss =OV. Ta = 0 .4 - - 2.3. 10 Fig. 1 Fig.0V±5%. Enable Positive Transition to 053 Negative Transition tOS01 Fig. 6 20 *Except P 2t **10kn pull up register required for Port 2 69 Unit ns ns . Enable Negative Transition to Peripheral CMOS Data Valid * Port 2**.ls - - ns Item tPWIS Fig.+70°C. 6 50 Input Data Set·up Time Port 3 tiS Fig. 2 tADL Read Write min 1 450 450 tASED tAD Data Set-up Read Time Data Hold Time Test Condition +70°C. Enable Negative Transition to Peripheral Data Valid Port 1.4 tpwo Fig.3. Ta = 0 - 5 5 - - 260 270 - Fig. 3 200 - - ns Peripheral Data Hold Time Port 1.4 tpOH Fig.4 t posu Fig. HD8801V5 • AC CHARACTERISTICS BUS TIMING (Vee = 5.0 /. 11 150 Unit ns ns ns ns ns ns ns ns (tACCN) tRC tpcs Processor Control Set-up Time - - tAHL tAH Address Hold Time 5 - tASL HD6801V5 typ max 10 - 225 Address Hold Time for Latch min 0. 6 200 Input Data Hold Time Input Strobe Pulse Width port 3 tlH Fig. Vss = OV. 4 tCMos Fig.4 - - 400 ns Delay Time.8 - tDsw Address Set-up Time for Latch Peripheral Read Access Time HD6801VO typ max 10 200 Fig.) Symbol Test Condition min typ max Peripheral Data Setup Time Port 1. unless otherwise noted. 5 - - 350 ns Delay Time. 2. 3 200 - - ns Delay Time. Enable Positive Transition to 053 Positive Transition tOS02 Fig.----------------------------------------------HD6801VO.0V ±5%. 2.

Ta = 0'" +70°C.HD6801VO.) Item Timer Input Pulse Width Delay Time.2V Enable (EI R/Vii. unless otherwise noted. Enable Positive Transition to Timer Out SCI Input Clock Cycle SCI Input Clock Pulse Width MODE PROGRAMMING (Vee Symbol Test Condition tpWT Fig. 8 min 4.0V ±5%.0 3.7 -. HD6801V5---------------------------------------------TIMER. Ta = 0'" +70°C. (Pori 31" Figure 1 Expanded Multiplexed Bus Timing 70 typ - - max 1. (Pori 31 MPU Read 0.0 2. Vss = OV. SCI TIMING (Vee = 5.. Vss =OV.) Item Mode Programming Input "Low" Voltage Mode Programming Input "High" Voltage RES "Low" Pulse Width Mode Programming Set-up Time Mode Programming Hold Time Symbol VMPL VMPH PW RSTL t MPS tMPH Test Condition Fig.6 tcyC tScYc 0.4 tPWSCK =5.-A.-A. - Unit V V tcyC tcyc ns .-0.0V ±5%. 7 tTOD tSCyc max - Unit ns - - 600 ns 1 - 0. Ar-Ae (SC~ typ - min 2t cyc +200 (port41 MPUWrite Do-D"A. unless otherwise noted.0 150 ~---------------------t~----------------------~ Address Strobe (ASI 2. A.

(Port3) 0.6V' -tosw- MPUWrite 2. 0) Figure 3 kn Pullup resistor required for Port 2 to reach 0.PI' P.7 Vee 2. 10 'Port 3 Non·Latched Operation (LATCH ENABLE. Port 4 cannot be pulled above Vee Data Set-up and Hold Times (MPU Read) Figure 4 Port Data Delay Timing (MPU Write) Enable(E) Address Sus 0 5 3 . Not applicable to P I 3..4V Enable (EI . p...5V-~ I+--tAO- -'r- PWEH - -- I+-tEr -'~ -tEf 1- 2.----------------------------------------------HD6801VO.P" Inputs" (Note) 1..-.. 2V f" j 0..2V~"" \.0V ------------------------------------------(1 -tHW .. All Data Port Outputs Inputs _ _ _ _ _ _ _J ~. HD6801V6 L tcyc '(. 2.p .SV I'-------------Jj Figure 2 Expanded Non-Multiplexed Bus Timing rMPUWrite r-MPURead Enable(E) Enable(E) PIO . 2..(Port4 ) Rfji iOS (5C2) (5C.-0. Address Valid l 0.. (Port 3) -. PSO - P" Inputs Figure 5 Figure 6 Port 3 Output Strobe Timing (Single Chip Mode) 71 Port 3 Latch Timing (Single Chip Mode) .. / PWEL Ao--A.~ - -tHR Data Valid O.6V\+--tOSR- 0.~~ Data Valid P so . o ..o ..) \ -J O. Data Valid .P. (tACCNI MPU Read -tAH ~ .-0.

.._.J'."__ _''__.--''----''-_''__ _''___ _''_~r'__. SC..*\\\\\\§\\\\\\\\SSSS\\\\\\\\\\'X:! ...1 M3 I .....-<:1 i"""------JJ P" Output Figure 8 Mode Programming Timing Figure 7 Vee Test Point O-----r. E......_....... Op Code Inlt... SC.'___ *----. ... SC. SC...2kO Test Point 130PF lS2074 ® or Equlv..".. H D 8 8 0 1 V 5 .. 30 pF for P IO -PI '7' P u -PH R· 12 kO lor p •• -p......-p"..__J\..nal R/ii * IRQ2 .HD8801V'O..'--_".._.. a ·24 kn for P10-P I" PJO-P H (a) CMOS Load (b) TTL Load Figure 9 Bus Timing Test Loads Lo.A.- Enable (E) Timer Counter ----oJ (~~~....-''--.J'__ _ _''_~~_....J'Io.. PCS-PCIS Pca-PC] F"" InstruCllon ~NOlvarld Figure 11 Reset Timing 72 ~ ...'~. J ' ' _ _ _ ' ' ' _ _ Irrelltvant Data ACeS \~----------------------------~I Vector MSB Vector LSB First Inst..- =.-"'-_~"--.....e" NMi or 8Ui-"'---+'~ _ _+'.~: m\\\\\\\\\%\\\\\\'{ . I Inleo...r.':'.... of Interrupt Routine Figure 10 Interrupt Sequence ~.....' ' _ _ . p •• -p"... Cycl~ I ~ ..-- Internal Interrupt "--"---r'---.' In"'uwon _I . p•• -p"...... C R C' 90 pF lor p...nal Add. IRO: ~ !--'PCS Data 8us. m RL =2..:..... E.~:: 1-----...~--"--..

Two 22pF capacitors are needed from the two crystal pins to ground to insure reliable operation. The Index Register. 4) The interrupt mask bit is set. The following are the recommended crystal parameters: Nominal Crystal Parameter ~ 4 MHz 5 MHz Co 7 pF max. 1.) This level sensitiv~ input requests that an interrupt sequence be generated within the machine. The voltage supplied will be +5 volts ±5%. The first 64 bytes of RAM will be maintained in the power down mode with 8 rnA current max. As with interrupt Request signal. 2) I/O Port 2 bits. It is a single phase. PC 1 and PCO. On power up. Divide by 4 circuitry is included with the internal clock. the-machine will begin an interrupt sequence. Program Counter. the processor will complete the current instruction that is being executed before it recognizes the NMI signal. An address loaded at these locations causes the MPU to branch to a non-maskable interrupt service routine in memory. XTAL must be grounded if an external clock is used. when brought "Low" must be held "Low" at least 3 clock cycles. The processor will wait until it completes the current instruction that it being executed before it recognizes the request. Inputs IRQ.------------------------------------------------HD6801VO. Progr. The IRQ. It will divide by 4 any frequency less than or equal to 5 MHz. At that time. Figure 13 Battery Backup for Vee Standby Reset (RES) This input is used to reset and start the MPU from a power down condition. This disables the standby RAM. A 3. . An address loaded at these locations causes the MPU to branch to an interrupt routine in memory. RAM E. • XT AL and EXT AL These connections are for a parallel resonant fundamental crystal. RAM E is bit 6 of the RAM Control Register at location $0014. In response to an NMJ interrupt. IRQ! will have priority over IRQ2 if both occur at the same time. 2. ___--. so a 4 MHz crystal may be used to run the system at 1 MHz. a 16-bit address will be loaded that points to a vectoring address located in memory locations $FFFC and $FFFD.58 MHz Color TV crystal for non-time critical applications. resulting from a power failure or an initial startup of the processor. thereby protecting it at power down. HD6801V5 • SIGNAL DESCRIPTIONS • Vcc and • vss These two pins are used to supply power and ground to the chip. At the end of the cycle. The Interrupt Mask Bit in the condition code register masks both interrupts (See Table 1). a 16-bit address will be loaded that points to a vectoring address which is located in memory locations $FFF8 and $FFF9. EXT AL may be driven by an external TTL compatible clock source with a 50% (±10%) duty cycle. At the end of the sequence. and NMI are hardware interrupt lines that are sampled during E and will start the interrupt routine on the E following the completion of an instruction. • Enable (E) This supplies the external clock for the rest of the system when the internal oscillator is used. Rs 60n max. The divide by 4 circuitry allows for use of the inexpensive 3.7 pF max. RES. 3) The last two ($FFFE. TTL compatible clock. The circuit of figure 13 can be utilized to assure that Vee Standby does not go below VSBB during power down. The interrupt mask bit in the Condition Code Register has no effect on NMI. and will be the divide by 4 result of the crystal frequency.5 MHz) EXT A L ~-- [Note] These are representative AT cut parallel resonance crystal parameters.3 krl external resister to Vee which should be used for wire-OR and optimum control of int~ts. and Condition Code Register are stored on the stack. must be cleared before the MPU can recognize maskable interrupts.am Counter. Accumulators. To retain information in the RAM during power down the following procedure is necessary: 1) Write "0" into the RAM enable bit. During operation. • Non-Maskable Interrupt (NMI) A low-going edge on this input requests that a non-maskableinterrupt sequence be generated within the processor.2 . and Condition Code Register are stored on the stack. and 0 are latched into programmed control bits PC2. the Index Register. 2) Keep Vee Standby greater than VSBB. $FFFF) locations in memory will be used to load the program addressed by the program counter. This interrupt will operate the same as IRQ! except that it will use the vector address of $ FFFO through $ FFF7. Jr CL1 tL2 Figure 12 Crystal Interface • Vcc Standby This pin will supply +5 volts ±5% to the standby RAM on the chip. AT cut. It will drive one TTL load and 90 pF. Accumulators. • Interrupt Request (IRQ. the MPU does the following: I) All the higher order address lines will be forced "High". Next the MPU will respond to the interrupt request by setting the interrupt mask bit "High" so that no further maskable interrupts may occur. Internal Interrupts will use an internal interrupt line (lRQ2). requires a 3. if the interrupt mask bit in the Condition Code Register is not set. When a "High" level is detected. 4. the reset must be held "Low" for at least 100 ms. 30n typo Item XTAL~--~------~ c L1 = CL2 = 22pF ± 20% (3.3 krl external resistor to Vee should be used for wire-OR and optimum control of interrupts.

the voltage on the input lines must be greater than 2.8 V for a logic "0". The timing for this singal is shown in Figure 1 of Bus Timing. This allows external access of the 256 locations from $0100 to $01 FF. Each port has an associated write only Data Direction Register which allows each I/O line to be programmed to act as an input or an output*. • Output Strobe (OS3) (SC 2 ) This signal is used by the processor to strobe an external device. Table 2 Port and Data Direction Register Addresses The following pins are available in the Single Chip Mode. The timing condition of the IS3 signal that is necessary to be latched the input data normally is shown in Figure 6. that is. as shown. indicating valid data is on the I/O pins. This signal is also used to disable the address from the multiplexed bus allowing a deselect time. (or IS3) FFF6 FFF7 ICF (Input Capture) FFF4 FFF5 OCF (Output Compare) FFF2 FFF3 TOF (Timer Overflow) FFFO FFF1 SCI (RDRF + ORFE + TDRE) Software Interrupt (SWI) * The only exception is bit 1 of Port 2. 9. Port Address Data Direction Register Address 1/0 Port 1 $0002 $0000 1/0 Port 2 $0003 $0001 1/0 Port 3 $0006 $0004 I/O Port 4 $0007 $0005 • I/O Port 1 This is an 8-bit port whose individual bits may be defined as inputs or outputs by the corresponding bit in its data direction register. lOS internally decodes A9 through AI5 as zero's and As as a one. This output is capable of driving one TTL load and 90 pF. As outputs these Jines are TTL compatible and may also be used as a source of up to 1 rnA at 1. There are four ports: Port 1. an interrupt will occur by the fall of the IS3 signal. external pull up resistors are required. This signal is used to latch the 8 LSB's of address which are mUltiplexed with data on Port 3.0 V for a logic "I" and less than 0. Three pins on Port 2 (pins 10. Address Strobe signals the latch when it is time to latch the address lines so the lines can become data bus lines during the E pulse.8 V for a logic "0" 74 . and are associated with Port 3 only. As an input for peripherals.0 V for a logic "1" and less than 0. • I/O Strobe (lOS) (SCI) In the expanded non-multiplexed mode of operation. A "1" in the corresponding Data Direction Register bit will cause that I/O line to be an output. three 8-bit ports and one 5-bit port. For driving CMOS inputs. As outputs.0 V for a logic "1" and less than 0.HD6801VO. The 5 output buffers have three-state capability. which can either be data input or Timer output. and Port 4. After Reset. the I/O lines are configured as inputs. Their addresses and the addresses of their Data Direction registers are given in Table 2. t ASD before the data is enabled to the bus. allowing them to enter a high impedance state when the peripheral data lines are used as inputs. Port 2 can be configured as I/O and provides access to the Serial Communications Interface and the Timer. this port has no internal pullup resistors but will drive TTL inputs directly. • I/O Port 2 This port has five lines that may be defined as inputs or outputs by its data direction register. If the latch enable bit is set. in figure 19. In all three modes.depending on the mode of operation hardware programmed by the user at reset. the data in the I/O Port 3 will be latched at the I/O Port 3 Data Register. HD6801V5----------------------------------------------Table 1 Interr UlJt Vector Location Vector MSB Highest Priority Lowest Priority • PORTS There are four I/O ports on the HD680 1V MCV. or an address bus multiplexed with the data bus .8 V for a logic "0". In order to be read properly. greater than 2. Ports • Input Strobe (lS3) (SCI) The function of the IS3 signal depends on the I/O Port 3 Control/Status Register. it must be supplied regular TTL levels. If IS3 Enable bit is set. Port 3. the I/O lines are configured as inputs. a data bus. A "0" in the corresponding Data Direction Register bit will cause that I/O line to be an input. As a data bus. The timing diagrams are shown as figure 2. Bit 1 is the only pin restricted to data input or Timer output. The timing for the Output Strobe is shown in Figure 5 I/O Port 3 Control/ Status Register is discussed in the following section. After Reset. • I/O Port 3 This is an 8-bit port that can be configured as I/O. The normal standby state of this signal is Read ("High"). In all three modes. the voltage on the input lines must be greater than 2. There are two control lines associated with one of the 8-bit ports. The 8 output buffers have three-state capability. • Address Strobe (AS) (SCI) In the expanded multiplexed mode of operation address strobe is output on this pin. Expanded Multiplexed Mode. Port 2. The values of these pins at reset are latched into the three MSB's (bits 7 6 and 5) of Port 2 which are read only. The following pins are available in the Expanded Modes. allowing them to enter a high impedance state when used as an input. In order to be read properly. • ReadlWrite (R/W) (SC 2 ) This TTL compatible output signals the peripherals and memory devices whether the MPV is in a Read ("High") or a Write ("Low") state. Port 3 is bi-directional. This is explained in ~h~ Mode Selection Section. An 8-bit latch is utilized in conjunction with Address Strobe. and 8 of the chi p) are used to program the mode of operation during reset. Interrupt LSB FFFE FFFF RES FFFC FFFD NMI FFFA FFFB FFF8 FFF9 IRQ.5 V to directly drive a Darlington base. Port 1 is always parallel I/O.

may be used as I/O (inputs only).0 V for a logic "1" and less than 0. The input strobe (IS3) and the output strobe (OS3) used for handshaking are explained later. After reset. Bit 5. I/O 1. It is cleared by a read of the Control/Status Register followed by a read or write of I/O Port 3. may be used as I/O (inputs only). ENABLE Not used. LATCH ENABLE. This bit is cleared by RES. There are two control lines associated with this port in this mode. In this mode. They are latched into programmed control bits PC2. IS3 (SC d. that can be used for handshaking. IS3 FLAG. In order to be read properly. I/O Port 2 Register is shown below. This is shown in Figure 16 the single Chip Mode. Port 3 will have two associated. The HDI4053B provides the isolation between the peripheral device and MCV during Reset. therefore. To use the pins as addresses. Not used. Reset will clear this bit. ) by writing one's to the data direction register. Port 4 is configured as the lower order address lines (Ao . the mode cannot be changed through software. When all eight address lines are not needed. Expanded Non-Multiplexed Mode: In this mode. and I/O 0 respectively) of Port 2. and (3) and IRQ. 153 $ooOF Bit 0. 6. when clear. after reset. and 8 of the chip. Three options of Port 3 operations are sumarized as follows: (1) Port 3 input data can be latched using IS3 (SC. Not used. If this bit is set "High" the input data will be latched with the falling edge of the Input Strobe. In the Expanded Modes.. (2) Expanded Multiplexed Mode (compatible with HMCS6800 peripheral family) (3) Expanded NonMultiplexed Mode. the data direction register is inhibited and data flow depends on the state of the R/W line. Port 4 is configured as the higher order address lines (A s . In the three modes. HD6801V5 Its TTL compatible three-state output buffers are capable of driving one TTL load and 90 pF.. interrupt will be enabled whenever IS3 FLAG is set. starting with the most Significant bit.----------------------------------------------HD6801VO. In this mode the HD6801V is expandable to 256 locations.. and PCO when reset goes high. control lines. Expanded Non-Multiplexed Mode: In this mode. Bit 3. PC 1. Port 3 latch and strobe timing is shown in Fig. These pins are the three LSB's (I/O 2.. (Output Strobe Select) This bit will select if the Output Strobe should be generated at OS3 (SC 2 ) by a write to I/O Port 3 or a read of I/O Port 3. each line is TTL compatible and can drive 1 TTL 75 . 5 and Fig. The eight address lines associated with Port 4 may be substituted for I/O (inputs only) if a fewer number of address lines will satisfy the application (See Figure 17). 9. the remaining lines. and the latch is "re-opened" with MCV read Port 3. • Single Chip Mode In the Single Chip Mode the Ports are configured for I/O. Timer. • FLAG 6 5 4 3 2 153 X 055 LATCH X IRQ l ENABLE • The mode of operation that HD680 1V will operate in after Reset is determined by hardware that the user must wire on pins 10. This controls the input latch for I/O Port 3.. interrupt is inhibited.. Not used. Expanded Multiplexed Mode: In this mode. or any combination of them.. Port 4 assumes the following characteristics: Single Chip Mode: Parallel Inputs/Outputs as programmed by its associated Data Direction Register.. Bit 6. • Expanded Non-Multiplexed Mode In this mode the HD6801V will directly address HMCS6800 peripherals with no external logic. Bit 2. (2) OS) can be generated by eithe~ MPV read or write to Port 3's Data Register. IS3. When all eight address lines are not needed. interrupt can be enabled by an IS3 negative edge.. address bus or partial address and I/O (inputs only). A. serial I/O. PC2 PCl I IlIa PCO 210 411/0 311/0 211/0 1 IlIa 0 X An example of external hardware that could be used for Mode Seiection is shown in Fig 14. an input strobe and an output strobe. As outputs.) as a control signal. an input strobe and an output strobe for handshaking data. When this bit is set the strobe is generated by a write Port 3. PORT 2 DATA REGISTER $0003 o X OPERATION MODES 7654 I/O PORT 3 CONTROL/STATUS REGISTER 7 load and 90 pF.8 V for a logic "0". I/O Port 4 This is an 8-bit port that can be configured as I/O or as address lines depending on the mode of operation. 6 and 7 of Port 2 are read only. the remaining lines.. Expanded Multiplexed Mode: In this mode. Port 2 can be parallel I/O. This is a read only status bit that is set by the falling edge of the input strobe. Bit 4. The mode selections are shown in Table 3. Port 3 assumes the following characteristics: Single Chip Mode: Parallel Inputs/Outputs as programmed by its associated Data Direction Register. which is necessary if data conflict can occur between peripheral device and Mode generation circuit. they should be programmed as outputs. Port 3 becomes the data bus (Do -D 7). Port 3 becomes both the data bus (D o-D 7) and lower bits of the address bus (Ao-A7)' An address strobe output is true when the address is on the port. the lines are configured as inputs. In the three modes. IS3 IRQl ENABLE.. Bit 1.. Port 4 becomes the Ao . When set. This bit is cleared by reset.. As bits 5. When this bit is cleared the strobe is generated by a read Port 3. They are controlled by the I/O Port 3 Control/Status Register explained at the end of this section. Bit 7. starting with the most Significant bit.. A.. (1) Single Chip Mode. A1s ) by writing one's to the data direction register. OSS. In this mode Port 3 becomes the data bus. The HD6801V is capable of operating in three basic modes. Port 1 is parallel I/O only. the voltage on the input lines must be greater than 2.

-- Yo X Zo Y XI Z RES 8 9 10 P20 (PCO) P21 (PC1) P22 (PC2) YI ZI C I ??? ~ Mode Control Switch HD14053B Inh [NOTES) Jr 1) Mode 7 as shown 2) RC'-'Reset time constant 3) R I =10kn Figure 14 Recommended Circuit for Mode Selection Truth Table Control Input Inh Binary to 1-of-2 Decoder with Inhibit A B C Xocr-----------------K~~~+-~~ XI~------------------~~-+~--~ Y0 )------------K':>I+--I--+_~ ylcr-----------------~~~-~ Zocr------------------~~--. Zlcr-------------------------~~~ x y Z On Switch Select Inhibit HD14053B C B A 0 0 0 0 0 0 0 1 Zo Yo XI 0 0 1 0 Zo Y I Xo 0 0 1 1 Zo VI XI 0 1 0 0 ZI Yo Xo 0 1 0 1 ZI Yo XI 0 1 1 0 ZI Y I Xo 0 1 1 ZI Y I XI 1 X X X 1 Zo Yo Xu - Figure 15 HD140538 Multiplexers/Demultiplexers Vee Vee 40 2 Port 1 8 I/O Lines Port 3 8 I/O Lines Port 4 8 I/O Lines Port 2 5 I/O Lines Vss Enable Enable SCI Timer Port 1 8 Parallel I/O Port 3 8 Data Lines Port 2 5 Parallel I/O SCI Timer Port 4 To 8 Address Lines or To 7 I/O Lines (Inputs Onlv) Figure 17 HD6801V MCU Expanded Non-Multiplexed Mode Figure 16 HD6801V MCU Single-Chip Mode 76 ..HD6801VO. HD6801V5-----------------------------------------------Vee 0 R .. ') RI RI RI 6 IJI A B C HD6801V Xo .

The 74LS373 Transparent octal D-type latch can be used with the HD680 1V to latch the least significant address byte.-D. Port 1 is 8 Parallel I/O lines. Vee Enable • Lower order Address Bus Latches Since the data bus is multipiexed with the lower order address bus in Port 3. Figure 19 Latch Connection • Mode and Port Summary MCU Signal Description This section gives a description of the MCU signals for the various modes.. -A. SCI. The output control to the 74LS373 may be connected to ground. MODE SINGLE CHIP PORT 1 Eight Lines PORT 2 Five Lines I/O PORT 3 Eight Lines PORT 4 Eight Lines SCI SC 2 I/O I/O I/O IS3 (I) OS3 (0) ADDRESS BUS* (As-A Is ) AS(O) Rm(O) ADDRESS BUS* (Ao -A 7 ) 10S(0) RIW(O) EXPANDED MUX I/O I/O ADDRESS BUS (Ao -A7 ) DATA BUS (0 0 -0 7 ) EXPANDED 'NON-MUX I/O I/O DATA BUS (0 0 -0 7 ) *These lines can be substituted for 110 (Input Only) starting with the most significant address line. 74LS373 Qs 1 Output Control G Enable 0 Q L L L H H L H H H X Output L L X X Q Z D". 8 lines Multiplexed Data/Address Port 1 8 I/O Lines Port 2 5 I/O Lines SCI Timer Port 4 To 8 Address Lines or To 7 I/O Lines (Inputs Only) Vss Figure 18 HD6801V MCU Expanded Multiplexed Mode GND AS l G DC 0. Figure 19 shows how to connect the latch to the HD6801V. Port 3 is the data bus multiplexed with the lower order address lines differentiated by an output called Address Strobe.or any combination of them.------------------------------------------------HD6801VO. (See Figure 18). HD6801V5 • Expanded MUltiplexed Mode In this mode Port 4 becomes higher order address lines with an alternative of substituting some of the address lines for I/O (inputs only). latches are required to latch those address bits. Port 2 is 5 lines of Parallel I/O. Timer. I = Input 153 = Input Strobe SC = Strobe Control o = Output OS3 = Output Strobe AS = Address Strobe R/W = Read/Write IDS = 110 Select 77 o . Port 3 Address/Data [ Q. 1 Os Function Table Add"" A. In this mode it is expandable to 65k words. SCI and SC 2 are signals which vary with the mode that the chip is in. D.

Q. The rust 32 locations of each map are reserved for the MCU's internal register area.2. 3 *** 1=Output.Logic "0" H .2.External MUX . 1.Non-Multiplexed L ..6. A memory map for each operating mode is shown in Figure 20. lOS) ** External addresses in Modes O. address output is optional by writing to Port 4 Data Direction Register The MCU can provide up to 65k byte address space depending on the operating mode. 1. Table 4 Internal Register Area RAM Control Register Reserved Operating Mode [NOTES) 1) Internal RAM is addressed at $XX80 2) Internal ROM is disabled 3) RES vector is external for 2 cycles after RES goes "High" 4) Addresses associated with Ports 3 and 4 are considered external in Modes O. and 3 5) Addresses associated with Port 3 are considered external in Modes 5 and 6 6) Port 4 default is user data input. With exceptions as indicated.3.Logic "1" • Interrupt Vectors MEMORY MAPS • Single Chip Multiplexed/Partial Decode Non-Multiplexed/Partial Decode Single Chip Test Register Address Port Port Port Port 1 Data 2 Data 1 Data 2 Data Direction Register*** Direction Register*** Register Register 00 01 02 03 Port Port Port Port 3 4 3 4 Direction Register*** Direction Register*" Register Register 04* 05** 06* 07** Timer Control and Status Register Counter (High Byte) Counter (Low Byte) Output Compare Register (High Byte) 08 09 OA OB Output Compare Register (Low Byte) Input Capture Register (High Byte) Input Capture Register (Low Byte) Port 3 Control and Status Register OC 00 OE OF* Rate and Mode Control Register Transmit/Receive Control and Status Register Receive Data Register Transmit Data Register 10 11 12 13 INTERRUPT FLOWCHART The Interrupt flowchart is depicted in Figure 24 and is common to every interrupt excluding reset.Multiplexed NMUX . O=lnput. 78 . as shown in Table 4. cannot be accessed in Mode 5 (No. 2. HD6801V5----~-----------------------------------------Table 3 Mode Selection Summary P11 (PC2) P11 (PClI P20 (PCO) ROM RAM H H H H I I I 6 H L I I I I MUX(6) 5 H L H I I I NMUX(6) 4 H L L 1(2) 1(1) I I 3 L H H E E E MUX Multiplexed/No RAM & ROM 2 L H L E I E MUX Multiplexed/RAM 1 L L H I I E MUX Multiplexed/RAM & ROM L L L I I 1(3) MUX Multiplexed Test MoCile 7 0 ! LEGEND: I-Internal E .HD6801VO.5. 1. Data Data Data Data Bus Mode 14 15-1F * External address in Mode!.

1) Excludes the ~ollowing addresses which may be used externally. $04. Figure 20 HD6801V Memory Maps 79 . $04. $06. 3) After 2 MPU cycles.------------------------------------------------HD6801VO. $07 and $OF 2) Addresses $FFFE and $FFFF are considered external if accessed within 2 cycles alter a positive edge of RES and internal at all other times. HD6801V5 HD6801V Mode o HD6B01V Mode 1 Multiplexed/RAM & ROM Multiplexed Test mode $0000(1) $0000(1) Internal Registers Internal Registers $001F $001F External Memory Space External Memory Space $0080 $0080 Internal RAM Internal RAM $OOFF $OOFF External Memory Space External Memory Space $FOOO Internal ROM $FFEF Internal ROM $FFFO Internal Interrupt Vectors(2 [NOTES) External Interrupt Vectors $FFFF----- [NOTES] 1) Excludes the following addresses which may be used externally. $05. 4) This mode is the only mode which may be used to examine the interrupt vectors in internal ROM using an external Reset vector. there must be no over· lapping of internal and external memory spaces to avoid driving the data bus with more than one device. $07 and $OF. $06. 2) Internal ROM addresses $FFFOto $FFFF are not usable. $05.

. ~} $FFFF ..._ _ _ _ External Interrupt Vectors $FFFO 1 .. $06.-.... and External Interrupt Vectors [NOTE] 1) Excludes the following addresses which may be used externally: $04. $06.. $FFFF ' -_ _ _.. $05.. $OF.. $07... $05. HD8801V6---------------------------------------------- HD6801V Mode 2 HD6801V Mode Multiplexed/RAM 3 Multiplexed/No RAM or ROM $0000(1) $0000(1) } Internal Registers Internal Registers $001F $OOlF External Memory Space $0080 Internal RAM $OOFF External Memory Space External Memory Space $FFFO ....HD8801VO...1 . $07 and $OF.. } [NOTE] 1) Excludes the following addresses which may be used externally: $04. Figure 20 HD6801V Memory Maps (Continued) 80 ..

Figure 20 HD6801V Memory Maps (Continued) 81 .. and $OF. HD6801V5 HD6801V HD6801V4 Mode Mode Single Chip Test 5 Non-Multiplexed/Partial Decode $0000(1) $0000 Internal Registers Internal Registers $001F $001F $0080 } $OOFF $0100 $01 FF U } Internal RAM External Memory Space ~_. These address lines will assert "1's" until made outputs by writing the Data Direction Register. $06. (No 105) 2) This mode may be entered without going through RES by using Mode 4 and subsequently writing a "1" into the PCO bit of Port 2 Data Register. 2) Mode 4 may be changed to Mode 5 without having to assert RESET by writing a "1" into the PCO bit of Port 2 Data Register. 4) Internal RAM will appear at $XX80 to $XXF F. (NOTES] 1) The internal ROM is disabled. 3) Address lines Ao -A? will not contain addresses until the Data Direction Register for Port 4 has been written with "1's" in the appropriate bits. 3) Addresses As to AI5 are treated as "don't cares" to decode internal RAM.------------------------------------------------HD6801VO.-_"" (1)(4) $FOOO Internal ROM $XX80 $XXFF Internal RAM Internal Interrupt Vectors $FFFF Internal Interrupt Vectors (NOTES] 1) Excludes the following addresses which may not be used externally': $04.

s will not contain addresses until the Data Direction Register for Port 4 has been written with "l's" in the appropriate bits. 2) Address lines A8 -A. $OF. These address lilies will assert "l's" until made outputs by writing the Data Direction Register.f!rnal Interrupt Vectors $FFFF [NOTES] 1) Excludes the following address which may be used externally: $04.HD6801VO. HD6801V5---------------------------------------------- HD6801V7 Mode HD6801V6 Mode Single Chip Multiplexed/Partial Decode $0000(1) $OOlF Internal Registers Internal Registers External Memory Space $0080 $0080 Internal RAM $OOFF $OOFF External Memory Space $FOOO $FFFF $FOOO Internal ROM Internal ROM Internal Interrupt Vectors Int. Figure 20 HD6801V Memory Maps (Continued) 82 . $06.

and • a 16-bit input capture register A block diagram of the timer registers is shown in Figure 21. The Data Direction Register bit for Port 2 Bit 0. HD6801V Internal Bus . The HD6801V contains an on-chip 16-bit programmable timer which may be used to perform measurements on an input waveform while independently generating an output waveform. and • when $0000 is in the free running counter. The upper three bits contain read-only timer status information and indicate that: . Bit 1 contains a "1" (Output). • a proper transition has taken place on the input pin with a subsequent transfer of the current counter value to the input capture register. Input Capture Register ($OOOD:OOOE) The Input Capture Register is a 16-bit read-only register used to store the current value of the free running counter when the proper transition of an external input signal occurs. • a 16-bit free running counter. The Compare function is inhibited for one cycle following a write to the high byte of the Output Compare Register to insure a valid 16-bit value is in the register before a compare is made. • • Free Running Counter ($O009:000A) The key element in the programmable timer is a 16-bit free running counter which is driven to increasing values by E (Enable). The counter value may be read by the MPU software at any time.-_ _ _-. This preset figure is intended for testing operation of the part. The counter is cleared to zero on RES and may be considered a read-only register with one exception. the external input will still be seen by the edge detect unit. IRO. Each of the flags may be enabled onto the HD680 1V internal bus (IRQ2) with an individual Enable bit in the TCSR. HD6801V5 • PROGRAMMABLE TIMER the output level register value will appear on the pin for Port 2 Bit 1. When a match is found. The Output Compare Register is set to $FFFF during RES. Timer Control and Status Register (TCSR) ($0008) The Timer Control and Status Register consists of an 8-bit register of which all 8 bits are readable but only the low order 5 bits may be written. Any MPU write to the counter's address ($09) will always result in preset value of $FFF8 being loaded into the counter regardless of the value involved in the write. OE Output Input Level Edge Bit 1 Bit 0 Port 2 Port 2 Figure 21 Block Diagram of Programmable Timer 83 . • a match has been found between the value in the free running counter and the output compare register. Pulse widths for both input and output signals may vary from a few microseconds to many seconds. The timer hardware consists of • an 8-bit control and status register. should* be clear (zero) in order to gate in the external input signal to the edge detect unit in the timer. • * • With Port 2 Bit 0 configured as an output and set to "1".------------------------------------------------HD6801VO. Providing the Data Direction Register for Port 2. The input transition change required to trigger the counter transfer is controlled by the input Edge bit (IEDG) in the TCSR. a flag is set (OCF) in the Timer Control and Status Register (TCSR) and the current value of the Output Level bit (OLVL) in the TCSR is clocked to the Output Level Regis~er. but may be of value in some applications... • a 16-bit output compare register. The contents of this register are constantly compared with the current value of the free running counter. The values in the Output Compare Register and Output level bit may then be changed to control the output level on the next compare value. If the Output Compare Register ($OOOB:OOOC) The Output Compare Register is a 16-bit read/write register which is used to control an output waveform.

I_R_'E---li. this bit enables IRQ2 to appear on the internal bus for an output compare interrupt.. Bit 2 of Port 2 is utilized if the internal-clock-out or external-clock-in options are selected . this bit enables IRQ2 to occur on the internal bus for a TOF interrupt..When set.. • Programmable Options The following features of the HD680 1V serial I/O section are programmable: · format . The hardware. When the next message appears.. • SERIAL COMMUNICATIONS INTERFACE The HD6801V contains a full-duplex asynchronous serial communications interface (SCI) on chip. and 4 of Port 2.-. IEDG = 1 Transfer takes place on a positive edge ("Low" -to-"High" transition). Bit 5 TOF Timer Overflow Flag .-I 84 . The controller comprises a transmitter and a receiver which operate independently or each other but in the same data format and at the same data rate. when clear the interrupt is inhibited.This read-only status bit is set by a proper transition on the input. when clear the interrupt is inhibited. and registers are explained in the following paragraphs. a wake-up feature is included whereby all further interrupt processing may be optionally inhibited until the beginning of the next message. Bit 2 ETOI Enable Timer Overflow Interrupt . The "wake-up" is automatically triggered by a string of ten consecutive 1's which indicates an idle transmit line. I_T_D_R_E. software.o_R_F_E.internal clock enabled or disabled to Port 2 (Bit 2) • Port 2 (bits 3 and 4) .. It is cleared by a read of the TCSR (with TOF set) followed by an MPU read of the Counter ($09). the software protocol will usually contain a destination address in the initial byte(s) of the message. it is cleared by a read of the TCSR (with ICF set) followed by an MPU read of the Input Capture Register ($OD). IEDG = 0 Transfer takes place on a negative edge ("High" -to-"Low" transition). The bits in the TRCS register are defined as follows: Transmit/Receive Control and Status Register 765432 0 _W_u---'1 AD DR : $0011 R_D_R_FI.external or internal • baud rate ... A description for each bit follows: Bit 0 OL VL Output Level .This read-only bit is set when a match is found between the output compare register and the free running counter..This value is clocked to the output level register on a successful output compare. • Serial Communications Hardware The serial communications hardware is controlled by 4 registers as shown in Figure 22. Transmit/Receive Control and Status (TRCS) Register The TRCS register consists of an 8-bit register of which all 8 bits may be read while only bits 0"'4 may be written. . The register is initialized to $20 on RES.R_E_ _T_'_E-""_T_E. Both transmitter and receiver communicate with the I 0 OLVLI $0008 MPU via the data bus and with the outside world via pins 2. The registers include: • an 8-bit control and status register • a 4-bit rate and mode control register (write only) • an 8-bit read only receive data register and • an 8-bit write only transmit data register.. the hardware re-enables (or "wakes-up") for the next message.one of 4 per given MPU ¢2 clock frequency or external clock x8 input • wake-up feature . a priority vectored interrupt will occur corresponding to the flag bites) set. The software protocol must provide for the short idle period between any two consecutive messages. the serial I/O section utilizes bit 3 (serial input) and bit 4 (serial output) of Port 2.This read-only bit is set when the counter contains $0000. • Wake-Up Feature In a typical multi-processor application.When set. when clear the interrupt is inhibited. Bit 1 IEDG Input Edge . Bit 4 EICI Enable input Capture Interrupt .standard mark/space (NRZ) • Clock .enabled or masked individually for transmitter and receiver data registers • clock output . The DDR for Port 2 Bit o must be clear for this function to operate.3. In order to permit non-selected MPU's to ignore the remainder of the message. this bit enables IRQ2 to occur on the internal bus for an input capture interrupt.. It is cleared by a read of the TCSR (with OCF set) followed by an MPU write to the output compare register ($OB or $OC).. In addition to the four registers.dedicated or not dedicated to serial I/O individually for transmitter and receiver.This bit controls which transition of an input will trigger a transfer of the counter to the input capture register.. HD6801V5-----------------------------------------------Timer Control and Status Register 7 ICF I 5 6 OCF 4 3 2 1 TOF I =ICI I EOCI I ETOII'EDG I-bit in the HD6801V Condition Code register has been cleared. the value will appear on the output pin. Bit 3 EOCI Enable Output Compare Interrupt . If the DDR for Port 2 bit 1 is set.When set.enabled or disabled • Interrupt requests . Bit 7 ICF Input Capture Flag . Bit 6 OCF Output Compare Flag .HD6801VO.

then writing a new byte into the transmit data register. and • Port 2 bit 2 configuration The register consists of 4 bits all of which are write-only and cleared on RES. IfWU flag is set. when clear.set by hardware when a transfer is made from the trllnsmit data register to the output shift register. Receiver Interrupt Enable . or by RES. when clear. The TDRE bit is cleared by reading the status register. then reading the Receive Data Register.set by HD6801V to produce Bit 1 TE preamble of nine consecutive 1's and to enable gating of transmitter output to Port 2. Bit 7 RDRF Receiver Data Register Full . the TDRE value is masked from the bus. If WU flag is set. A ~raming error has occurred when the byte boundaries in bit stream are not synchronized to bit counter.E Tx Bit 12 4 $13 Transmit Data Register Figure 22 Serial lID Registers TDRE is initialized to 1 by RES. Bit 0 WU "Wake-up" on Next Message . then reading the Receive Data Register. An overrun is defined as a new byte received with last byte still in Data Register/Buffer.set by HD6801V software and cleared by hardware on receipt of ten consecutive 1's or reset of RE flag. The RDRF bit is cleared by reading the status register. or by RES. the interrupt is masked..set by hardware when an overrun or framing error occurs (receive only). The two low order bits control the bit rate for internal clocking and the remaining two bits control the format and clock select logic.. the RDRF bit will not be set. Transmit Interrupt Enable .set by hardware when a transfer from the input shift register to the receiver data register is made. will permit Bit 4 RIE an IRQ2 interrupt to occur when bit 7 (RDRF) or bit 6 (ORFE) is set. will permit Bit 2 TIE an IRQ2 interrupt to occur when bit 5 (TDRE) is set. Transmit Enable . when clear. HD6801V5 Bit 7 Rate and Mode Control Register I I I I I CCl CCO SSl Bit 0 SSO 1$10 Transmit/Receive Control and Status Register $12 Port 2 Receive Shift Register . serial I/O has no effect on Port 2 bit 4. It should be noted that RE flag should be set in advance of MPU set of WU flag. the ORFE bit will not be set. The ORFE bit is cleared by reading the status register. Receiver Enable . TE set should be after at least one bit time of data transmit rate from the set-up of transmit data rate and mode. gates Port 2 bit 3 to Bit 3 RE input of receiver regardless of DDR value for this bit. The 4 bits in the register may be considered as a pair of 2-bit fields. Bit 5 TORE Transmit Data Register Empty .when set. when clear. serial I/O has no effect on Port 2 bit 3..------------------------------------------------HD6801VO.when &et. Rate and Mode Control Register The Rate and Mode Control register controls the following serial I/O variables: • Baud rate • format • clocking source.when set.. The register definition is as follows: Rate and Mode Control Register 7 6 5 4 3 2 x x x x CC1 cco 85 o SS1 SSO ADDR : $0010 .. bit 4 regardless of the DDR value corresponding to this bit.. Bit 6 ORFE Over· Run-Framing Error .

During the transfer itself.200 Baud 6. the following requirements are applicable: • the values of RE and TE are immaterial. followeq by more 1's until more data is supplied to the data register.0 MHz SSl : SSO 0 0 1 0 1 0 E + 16 E + 128 E + 1024 1 1 E +4096 4.16. Externally Generated Clock . The Transmitter Enable (TE) and Receiver Enable (RE) bits may be left set for dedicated operations. a continuous string of ones will be sent indicating an idle line. If the HD680 1V fails to respond to the flag within the proper time. • the external clock must be set to 8 times (x 8) the desired baud rate and • the maximum external clock frequency is 1.600 Baud 33. When the Transmitter Data Register has be~n emptied.500 Baud 26 ps/38. 86 Transmit Operations The transmit operation is enabled by the TE bit in the Transmit/Receive Control and Status Register. The four rates which may be selected are a function of the MPU </>2 clock frequency.096 ms/244. 2) if data has been loaded into the Transmit Data Register (TDRE = 0). • writing the desired operation control bits to the Rate and Mode Control Register and • writing the desired operational control bits in the Transmit/ Receive Control and Status Register.2 ps/9. CCO must be set to 10 • the maximum clock rate will be E. the hardware sets the TDRE flag bit. internal synchronization is established and the transmitter section is ready for operation.67 ms/150 Baud 4. (TDRE is still set when the next nonnal transfer from the parallel data register to the serial output register should occur) then a 1 will be sent (instead of a 0) at "Start" bit time. Table 5 SCI Bit Times and Rates XTAL 2. Bit 3 is used for serial input if AE = "1" in TACS.4 kHz 1. field in the Rate and Mode Control Register must be set to 11.67 ms/600 Baud 128 ps/7812.4576 MHz 4..3 ps/l. the 0 start bit is first transmitted. Setting the TE bit during this procedure initiates the serial output by first transmitting a ten-bit preamble of 1'so Following the preamble. Bit 4. the word is transferred to the output shift registtr and transmission of the data word will begin.0 MHz.400 Baud 208 ps/4. No O's will be sent while TDRE remains a 1. Table 5 lists the available Baud rates. • Serial Operations The serial I/O hardware should be initialized by the HD6801V software prior to operation.024 ms/976.6 Baud 13 ps/76. This bit when set.1 Baud 3. At this point one of two situation exist: 1) if the Transmit Data Register is empty (TDRE = 1).800 Baud 1. CCO. or.9152 MHz* 1. Table 6 defines the bit field. gates the output of the serial transmit shift register to Port 2 Bit 4 and takes unconditional control over the Data Direction Register value for Port 2. Then the 8 data bits (beginning with bit 0) followed by the stop bit are transmitted.this 2·bit field controls the fonnat and clock select logic.800 Baud 104. Speed Select .0 MHz E 614.33 ms/300 Baud *HD6801 V5 Only Table 6 SCI Format and Clock Source Control CC1.HD6801V5------------------------------~---------------- HD6801VO. Following a RES the user should configure both the Rate and Mode Control Register and the Transmit/Receive Control and Status Register for desired operation. . Bit 0 S50 Bit 1 S51 Bit 2 Bit 3 ceo eel Clock Control and Fonnat Select . If the user wishes to provide an external clock for the serial I/O.. CCO * Format Clock Source Port 2 Bit 2 Port 2 Bit 3 Port 2 Bit 4 Not Used Output* ** ** ** ** ** ** ** 00 - - 01 10 11 NRZ NRZ NRZ Internal Internal External Input ** Clock output is available regardless of values for bits AE and TE.These bits select the Baud rate for the internal clock. bit 4 is used for serial output if TE = "1" in TACS. the following requirements are applicable: • the CCl. • the clock will be at Ix the bit rate and will have a rising edge at mid-bit.2288 MHz 16 ps/62.5 Baud 1. This sequence will nonnally consist of. InternaUy Generated Clock If the user wishes for the serial I/O to furnish a clock. • CCI.

these include 16-bit operations and a hardware multiply. Included in the instruction set section are the following: • MPU Programming Model (Figure 23) • Addressing modes • Accumulator and memory instructions . If the tenth bit is not a 1 (stop bit) a framing error is assumed. The MCU addresses this location when it fetches the immediate instruction for execution. ORFE will be set. The receiver bit interval is divided into 8 sub-intervals for internal synchronization.Table 8 • Jump and branch instructions . the operand is contained in the second byte of the instruction except LDS and LDX which have the operand in the second and third bytes of the instruction. Bit 1 Not used. thereby protectillg it at power down if Vee Standby is held greater than VSBB volts. Index Register (X) 15 X 0 1 1 15 SP 0 1 Stack Pointer (SP) 115 PC 0 1 Program Counter (PC) 1 RAM CONTROL REGISTER Condition Code Register (CCR) RAM Control Register Carry/Borrow from MSB Overflow Zero Negative Interrupt Half Carry (From Bit 3) Bit 0 Not used. When the RAM is disabled. If the tenth bit as aI. RDRF (or ORFE) will be cleared. When the HD6801V responds to either flag (RDRF or ORFE) by reading the status register followed by reading the Data Register. gives status information about the standby RAM. and interrupt flag RDRF is set. GENERAL DESCRIPTION OF INSTRUCTION . The approximate center of each bit time is strobed during the next 10 bits. Accumulator (ACCX) Addressing In accumulator only addressing. Bit 6 RAME The RAM Enable control bit allows the user the ability to disable the standby RAM. A summary of the addressing modes for a particular instruction can be found in Table 11 along with the associated instruction execution time that is given in machine cycles. • Figure 23 MCU Programming Model • MPU Addressing Modes The HD680 1V eight-bit microcomputer unit has seven address modes that can be used by a programmer. These are two or three-byte instructions.Table 11 • Summary of cycle by cycle operation . and the data in the standby RAM is valid. and bit ORFE is set. With a clock frequency of 4 MHz. • • MPU Programming Model The programming model for the HD680 I V is shown in Figure 23. Immediate Addressing In immediate addressing. These are one-byte instructions. The execution times of key instructions have been reduced to increase throughout. Big 7 STBV The Standby Power bit is cleared when the standPWR by voltage is removed. The receiver section operation is conditioned by the contents of the Transmit/ Receive Control and Status Register and the Rate and Mode Control Register. the received bit stream is synchronized by the first 0 (space) encountered.Table 12 • Summary of undefined instructions operation • Op codes Map . these times would be microseconds.Table 10 • Instructions Execution times in machine cycles. The double (D) accumulator is physically the same as the Accumulator A concatenated with the Accumulator B so that any operation using accumulator D will destroy information in A and B. This bit is a read/write status flag that the user can read which indicates that the standby RAM voltage has been applied.Table 13 Receive Operation The receive operation is enabled by the RE bit which gates in the serial input through Port 2 Bit 3. In addition. This bit is set to a logic" 1" by RES which enables the standby RAM and can be written to one or zero under program control.Table 7 • New instructions • Index register and stack manipulations instructions . indicating an over-run has occurred. the data is transferred to the Receive Data Register.t Doubh! Accumulator D This register. Bit 2 Not used.------------------------------------------------HD6801VO. Bit 4 Not used. with the addressing mode a function of both the type of instruction and the coding within the instruction. 8-Bit Accumulators A and B Or 16·B. new instructions have been added. either accumulator A or accumulator B is specified. as explained previously in the signal description for Vee Standby. A 0 in the RAM enable bit (RAM E) will disable the standby RAM. Bit 5 Not used. which is addressed at $0014.Table 9 87 . HD6801V5 • Condition code register manipulation instructions . data is read from external memory. In the NRZ Mode. If RDRF is still set at the next tenth bit time.SET The HD6801V is upward object code compatible with the HD6800 as it implements the full HMCS6800 instruction set. Bit 3 Not used.

. A:B A+M . SP 32 4 1 SP + 1 ... A 3D 10 1 Push Data .. A 5C 2 1 B+1-+B 4 3 M ....... Inclusive ORAA 8A ORAB CA 3 DC 4 2 EC 5 2 2 2 9A 3 2 AA 4 2 2 DA 3 2 EA 4 FA 4 1 A ... SP . A 4 1 SP + 1 ..2's Increment OP 5 3 4 "3 COMA Exclusive OR - # 99 2 Boolean/ Arithmetic Operation IMPLIED 1B CLR Compare Register EXTEND INDEX DIRECT OP Add Accumulators AND IMMED.. SP .... B. 1's OP - # 4 2 BB 4 3 A+B-+A EB 4 2 FB 4 3 B+M-+B E3 6 2 F3 6 3 A9 4 B9 4 3 2 F9 4 3 2 B4 4 3 2 2 2 2 09 3 2 E9 4 2 2 94 3 2 A4 4 C4 2 2 04 3 2 E4 4 2 BITA 85 2 2 95 3 2 A5 4 2 BIT B C5 2 2 05 3 2 E5 4 6F 6 2 7F F4 B5 4 3 A·M 2 F5 4 3 B·M 6 3 B·M -+ B 00 -+ M CMPA 81 2 2 91 3 2 A1 4 2 B1 4 3 A-M CMPB C1 2 2 01 3 . B CC 3 FC 5 3 86 LDAB Load Double Accumulator LDD Multiply Unsigned MUL OR.HD6801VO.... liJ bo I I I I I I~ bo • • • • t R • • • • • • • • • • • • • • • t t @ t · ·• ·• • • • • • • t t t t t t t t <t @ t t t (~j t (6) @ '6 t t (Continued) ... Msp... SP 37 3 1 B -+ Msp......... A C6 4 3 M ... A 2 BA 4 3 2 ·• ·• M + 1 .. Msp .. Converts binary add of BCD 2 2 96 3 2 A6 4 2 B6 2 2 06 3 2 E6 4 2 F6 LDAA ......... SP. M . B 3 t t t t • • t t R • • • • • ® • • t t R • AxB .. SP... Msp .. A DAA Decrement DEC 2 73 6 2 70 6 6 2 7A 6 EORB C8 43 2 1 53 2 1 40 2 1 OO-A-+A 50 2 1 19 2 1 characters into BCD format 4A 2 1 A-1-+A 5A 2 1 B-1-+B M-1-+M B8 4 3 A@M-+A 4 2 F8 4 3 B @ M-+ B 6C 6 2 7C 6 3 M+1-+M 4C 2 1 A+ 1 ...... 88 6 3 ~J C{j:i I C b7 B t t t t i III t t t t t R R R t t t • • • • R f R S R R R S R R R S R R t t t t t t t t t t t t t t t t R S t t R S t t CD@) t t CD® t t CD@) R S t t t t t t t t t t t t 3 36 PSHA t t t t t t t t @ t @ • t @ • t @ • t R t R • • t ® • t ® • t ® • t R t R • • • ·• ·• • • • ·• B + M . HD6801V5---------------------------------------------Table 7 Accumulator & Memory Instructions Condition Code Addressing Modes Mnemonic Operations Add ~ 3 2 AB DB 3 2 03 5 2 OP ADDA 8B 2 2 9B ADDB CB 2 2 C3 4 3 ADDD ABA Add With Carry ADCA Clear OP # Add Double Bit Test - # ~ 89 2 ADCB C9 ANDA 84 ANDB Compare Accumulators Complement.1 ... B ~} lG-i II B C b7 PSHB Pull Data PULA PULB 33 69 6 2 79 6 3 ROLA 49 2 1 ROLB 59 2 1 RORA 46 2 1 RORB 56 2 1 66 6 2 76 The Condition Code Register notes are listed after Table 10 ... OO-B-+B 2 INCB ROR B -+ B OO-M-+M 4 INC Rotate Right A -+A 2 98 3 2 A8 2 2 08 3 2 E8 2 INCA ROL A-B M-+M 3 DECB 88 1 3 DECA EORA 2 3 I 6A t t t t t t t 1 00 -+ B (Negate) • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • t t t • • • • • • • • • • • • • • • • • • • • • • • • • 2 6 C t t B+M+C-+B 5F 60 0 V t t A+M+C-+A CLRB 6 1 N Z • 1 00 -+ A 63 2 I A+B-+A 2 COM 3 H A:B+M:M+1-+A:B 4F NEG Rotate Left 1 4 A·M -+ A COMB Load Accumulator 2 # CLRA Complement.1 ..2 E1 4 2 F1 4 3 B-M 11 CBA NEGA NEGB Decimal Adjust...

The carry is then added to the higher order eight bits of the index register. I ndexed Addressing In indexed addressing. The carry or borrow is then added to the high eight bits. These are three-byte instructions. the address contained in the second byte of the instruction is used as the higher eight-bits of the address of the operand.----------------------------------------------HD6801VO. In most configurations. the address contained in the second byte of the instruction is added to the index register's lowest 89 eight bits in the Mev. Direct Addressing In direct addressing. These are one-byte instructions. These are two-byte instructions. Implied Addressing In the implied addressing mode the instruction gives the address (Le.00 60 6 2 70 6 M -00 3 4 • A [J+111111111-0 • B C • ~ A~~ A7 A~~ Ei 1_0 • M} ASLB 5 H # ASLA ASRB Shift Right Logical Boolean! Arithmetic Operation • • • ·• ·• • • • • • • • • • • • • • • • · ·• ·• • • • • • • ·• ·• • • • • • • • • 3 2 N Z 1 0 V C t t @t t t @t t t ~t t t ® ® ® ® t t t t t t t t t t t t §) t t t ® t t t @ t R t @ t t t R t t R t t R • • • t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t R R • • R R R R R R The Condition Code Register notes are listed after Table 10. OP Shift Left Arithmetic Double Shift Left.M Double Subtract SUBD 83 4 3 93 5 2 A3 6 2 B3 6 3 A:B-M:M+1-+A:B Subtract Accu mu lators SBA 10 2 1 A - B~ A Subtract With Carry SBCA 82 2 2 92 3 2 A2 4 2 B2 4 3 A-M-C~A SBCB C2 2 2 02 3 2 E2 4 2 F2 4 3 B-M-C-+B Transfer Accumulators TAB 16 2 1 A~B TBA 17 2 1 B~A Test Zero or Minus TST TSTA 40 2 1 A -00 TSTB 50 2 1 B . These are two-byte instructions. it should be a random access memory. Enhanced execution times are achieved by storing data in these locations. index register. Arithmetic Shift Right Arithmetic - # INDEX DIRECT OP - # ASL EXTEND OP - # OP - # 68 6 2 78 6 3 Double Shift Right Logical IMPLIED OP - 48 2 1 58 2 1 ASLD 05 3 1 I • __ b7 67 6 2 77 6 3 47 2 1 57 2 1 LSRA 44 2 1 LSRB 54 2 1 ASRA 64 LSR 6 2 74 6 3 04 LSRD 3 1 AO B7 - 1I1111f-... Direct addressing allows the user to directly address the lowest 256 bytes in the machine Le. locations zero through 255. . This is an absolute address in memory. the address of the operand is contained in the second byte of the instruction. etc. the address contained in the second byte of the instruction is added to the program counter's lowest eight bits plus two. This allows the user to address data within a range of -126 to + 129 bytes of the present instruction. HD6801V5 Table 7 Accumulator & Memory Instructions (Continued) Condition Code Register Addressing Modes Operations Mnemonic IMMED. The modified address is held in a temporary address register so there is no change to the index register. The third byte of the instruction is used as the lower eight-bits of the address for the operand.Q bO ~104j B I I I II b7 I b7 - o~ A7 AO 97 3 2 A7 4 2 B7 4 3 A~M 07 3 2 E7 4 2 F7 4 3 B~M Store Double Accumulator STD DO 4 2 ED 5 2 FD 5 3 A~M B ~ M+1 Subtract SUBA 90 3 2 AO 4 2 BO 4 3 A-M ~A ~B 2 2 "--9 bO -----+ ACC AI ACCB STAB 80 BO ~} C?I B STAA Store Accumulator bO - A7 ASR B7 ~ BO SUBB CO 2 2 DO 3 2 EO 4 2 FO 4 3 B . Relative Addressing In relative addressing. These are two-byte instructions.). stack pointer. This result is then used to address memory. Extended Addressing In extended addressing.

The A-accumulator is the most significant byte. The condition codes are set according to the data.HD6801VO. SP L -+ (M+ 11 Index Reg -+ Stack Pntr TXS 35 3 1 X-1-+SP Stack Pntr -+ Index Reg TSX 30 3 1 SP+1-+X Add ABX 3A 3 1 B+X-+X Push Data PSHX 3C 4 1 XL -+ Msp. LSRD Shifts all bits of ACCD one place to the right. ACCA contains MSB of result. MUL Multiplies the 8 bits in accumulator A with the 8 bits in accumulator B to obtain a 16-bit unsigned number in A:B. this instruction can be considered a two byte NOP (No operation) requiring three cycles for execution.1 -+ SP Increment Index Reg INX 08 3 1 X+1-+X Increment Stack Pntr INS 31 3 1 SP + 1 -+ SP Load Index Reg LOX CE 3 3 Load Stack Pntr LOS 8E 3 3 Store Index Reg STX Store Stack Pntr STS DE 4 9E 4 2 2 OF 4 2 9F 4 2 X-1-+X EE 5 FE 5 3 M-+XH. LDD Loads the contents of double precision memory location into the double accumulator A:B. 90 • • • • • • . ADDD Adds the double precision ACCD* to the double precision value M:M+I and places the results in ACCD. BRN Never branches. the following new instructions are incorporated in the HD6801V Microcomputer. STD Stores the contents of double accumulator A:B in memory. SUBD Subtracts the contents of M:M + 1 from the contents of double accumulator AB and places the result in ACCD. (M+1)-+SP L 2 2 EF 5 2 AF 5 2 FF 5 3 XH-+M. DIRECT INDEX - IMPLIED EXTND OP - # OP - # 8C 4 3 9C 5 2 AC 6 2 BC 6 3 OP # OP - # OP - Arithmetic Operation # X-M:M+1 Compare Index Reg CPX Decrement Index Reg DEX 09 3 1 Decrement Stack Pntr DES 34 3 1 SP .(f) t . PSHX The contents of the index register is pushed onto the stack at the address contained in the stack pointer.index register is pulled from the stack beginning at the current address contained in the stack pointer +1. *ACCD is the 16 bit register (A:B) formed by concatenating the A and B accumulators. SP .(f) t R • (f) t . SP -1-+ SP Pull Data PULX 38 5 1 SP + 1 -+ SP.1 -+ SP 1 0 4 I N Z V • • 3 2 5 H t t C t ~ • • • t • • • • • • • • • • • t • • • • • • • • • • • · . The contents of ACCD remain unchanged. The C bit is loaded from the least significant bit to ACCD. CPX Internal processing modified to permit its use with any conditional branch instruction. Msp -+ X H SP + 1 -+ SP. Msp -+ XL The Condition Code Register notes are listed after Table 10. The stack pointer is decremented by 2.(M+1)-+XL AE 5 BE 5 3 M-+ SP H . ABX Adds the 8-bit unsigned accumulator B to the 16-bit X-Register taking into account the possible carry out of the low order byte of the X-Register. HD6801V5-----------------------------------------------• New Instructions In addition to the existing 6800 Instruction Set.I~ t R • • • • • • • • • • • 0 R R • • • • • • • • • • • • • • • • XH-+ Msp. Bit 15 is loaded with zero. Bit 0 is loaded with zero.XL-+(M+1) BF 5 3 SPH -+ M. ASLD Shifts all bits of ACCD one place to the left. Table 8 Index Register and Stack Manipulation Instructions Condition Code Register Addressing Modes Pointer Operations Mnemonic Booleanl IMMED. If effect. PULX The . The stack pointer is incremented by 2 in total. The C bit is loaded from the most significant bit of ACCD.

If previously set..... (See Special Operations) Set when interrupt occurs.. HD6801V6 Table 9 Jump and Branch Instructions Condition Code Register Addressing Modes Mnemonic Operations RELATIVE OP - # DIRECT OP - INDEX # OP - EXTND # OP - Branch Test IMPLIED # - OP # Branch Always BRA 20 3 2 Branch Never BRN 21 3 2 None Branch If Carry Clear BCC 24 3 2 C=O Branch If Carry Set BCS 25 3 2 C=1 Branch If = Zero BEQ 27 3 2 Z=1 None Branch If ~ Zero BGE 2C 3 2 N(±)V=O Branch If > Zero BGT 2E 3 2 Z + (N (±) V) = 0 Branch If Higher BHI 22 3 2 C+Z=O Branch If" Zero BlE 2F 3 2 Z + (N (±) V) = 1 Branch If lower Or Same BlS 23 3 2 C+Z=1 BlT 2D 3 2 N(±)V=1 Branch If Minus BMI 2B 3 2 N= 1 Branch If Not Equal Zero BNE 26 3 2 Z=O Branch If Overflow Clear V=O Branch If < Zero BVC 28 3 2 Branch If Overflow Set BVS 29 3 2 V= 1 Branch If Plus BPl 2A 3 2 N=O 8D 6 2 Branch To Subroutine BSR Jump JMP Jump To Subroutine JSR No Operation NOP 01 Return From Interrupti 3 2 7E 3 3 AD 6 2 BD 6 3 6E 9D 2 5 ilSee Special Operations 2 1 RTI 3B 10 1 Return From Subroutine RTS 39 software Interrupt SWI 3F 12 1 Wait for Interrupt WAI 3E 5 9 Advances Prog..------------------------------------------------HD6801VO.... V Accumulator A . CCR CCR ........... • • • Table10 Condition Code Register Manipulation Instructions iAddressingModes Operations Mnemonic OP - Condition Code Register Boolean Operation IMPLIED # Clear Carry ClC OC Clear Interrupt Mask CLI OE 2 1 0 . a Non-Maskable Interrupt is required to exit the wait state... 1 2 1 O .... 1 Clear Overflow ClV OA 2 1 Set Carry SEC OC... Accumulator A TPA 07 2 1 CCR ... C Set Overflow SEV OB 2 1 1 ..... Test: Result less than zero? (Bit15=1) load Condition Code Register from Stack... A 5 4 3 2 1 H I N Z V C • • • • • R • • • • • • • R • • • • • • S • • • • • • • S R ---@ Test: Result = 10000000? Test: Result = OOOOOOOO? Test: Decimal value of most significant BCD Character greater than nine? (Not cleared if previously set) Test: Operand = 10000000 prior to execution? Test: Operand = 01111111 prior to execution? Test: Set equal to result to N <±> C after shift has occurred.. Only 1 5 4 3 2 1 0 H I N Z V C • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • · -@See Special Operations 1 • • • • • • • S • • • • • ®....... Set according to the contents of Accumulator Ai Set equal to result of Bit 7 (AccB) 91 • • S • • • • • • • • Condition Code Register Notes: (Bit set it test is true and cleared otherwise) CD (Bit V) ® (Bit C) @ (Bit C) @ (Bit V) @ (Bit V) @ (Bit V) CJ) (BitN) ® (All) ® (Bit I) @> (All) ® (Bit C) · 0 .> 2 1 0""" V 1 ... C Set Interrupt Mask SEI OF 2 1 1 . Cntr. CCR TAP 06 2 1 A ...

Direct tended dexed ABA ABX ADC ADD AD DO AND ASL ASLD ASR BCC BCS BEQ BGE BGT BHI BIT BLE BLS BLT BMI • • • • • • 2 • 2 • • • • • • • • • • • • • • • 2 2 3 4 4 4 4 4 3 5 6 6 2 3 4 4 • • • • • 6 6 • • 6 6 • • • • • • • • • • • • • • • • • • • 2 3 4 4 • • • • • • • • • • • • • • • • • • • avc • • • • • BVS CBA CLC CLI CLR CLV CMP COM CPX DAA DEC DES DEX EOR • • • 2 • • 2 • • 2 • • • INC 2 INS • • • BNE BPL BRA BRN BSR • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 6 2 3 • • • • • 3 • • • • • • • • • • • • • • • • • • • 6 • • • 3 4 4 • • 6 6 4 5 6 6 • • • 6 6 • • • • • • • • • • 2 3 4 4 • • • 6 6 • • • Implied • • • • • • • • • • • 2 • Instruction Execution Times in Machine Cycle 2 2 2 • 2 • • • 2 • 3 3 • • 3 Re- ACCX lative • • • • • • • • • INX JMP JSR LOA LGD LOS LOX LSR LSRD MUL NEG NOP ORA 3 3 3 3 3 3 • 3 3 3 3 3 3 6 3 3 • • • • • • • • • • • • • • • • • • 2 • • 2 • • 3 PSHX • STX SUB SUBD SWI TAB TAP TBA TPA TST TSX TXS WAI 92 • • PSH PUL PULX ROL ROR RTI RTS SBA SBC SEC SEI SEV STA STD STS 3 3 • • 4 • 2 2 • • • • • • • • • • • • • • • • • 2 • • • Implied lative 3 • • • • • 3 3 5 6 6 4 4 3 3 3 3 4 4 4 5 5 5 5 5 5 • • • • • • • • • • • 6 6 • • • • 3 10 6 6 • • • 2 3 4 4 • • • • • • • • • • • • • • • • • • • • • • • • 2 • • • 2 • • • 6 6 • • • • • 2 • • 4 • 5 • • 6 6 • • • • • • 3 4 4 • • • • • • • • • • • • • • 2 3 4 4 • 4 5 5 5 5 5 2 3 5 4 4 6 6 • • • • • • • • • • • • • • 6 6 • • • • • • 4 • • • • • • • • • 4 4 • • • • • • • 5 10 5 2 • 2 2 • • • • • 12 2 2 2 2 • 3 3 9 Re- • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • . HD6801V5----------------------------------------------Table 11 ExInACCX I~~:.HD6801VO.

--------~--------------------------------------HD6801VO. instructions with the same addressing mode and number of cycles execute in the same manner. Table 12 Cycle by Cycle Operation Address Mode & Instructions Address Bus Data Bus IMMEDIATE ADC ADD AND BIT CMP EOR LOA ORA SBC SUB 2 1 2 Op Code Address Op Code Address + 1 1 1 Op Code Operand Data LOS LOX 3 1 2 Op Code Address Op Code Address + 1 Op Gode Address + 2 1 1 1 Op Code Operand Data (High Order Byte) Operand Data (Low Order Byte) CPX SUBD ADDD 4 Op Code Address Op Code Address + 1 Op Code Address + 2 Address Bus FFFF 1 1 1 1 Op Code Operand Data (High Order Byte) Operand Data (Low Order Byte) Low Byte of Restart Vector Op Code Address Op Code Address + 1 Address of Operand 1 1 1 Op Code Address of Operand Operand Data Op Code Address Op Code Address + 1 Destination Address 1 1 0 Op Code Destination Address Data from Accumulator Op Code Address Op Code Address + 1 Address of Operand Operand Address + 1 1 1 1 1 Op Code Address of Operand Operand Data (High Order Byte) Operand Data (Low Order Byte) Op Code Address Op Code Address + 1 Address of Operand Address of Operand + 1 1 1 0 0 Op Code Address of Operand Register Data (High Order Byte) Register Data (Low Order Byte) Op Code Address Op Code Address + 1 Operand Address Operand Address + 1 Address Bus FFFF 1 1 1 1 1 Op Code Address of Operand Operand Data (High Order Byte) Operand Data (Low Order Byte) Low Byte of Restart Vector Op Code Address Op Code Address + 1 Subroutine Address Stack Pointer Stack Pointer + 1 1 1 1 0 0 Op Code Irrelevant Data First Subroutine Op Code Return Address (Low Order Byte) Return Address (High Order Byte) 3 1 2 3 4 DIRECT ADC ADD AND BIT CMP EOR LOA ORA SBC SUB 3 1 2 3 STA 3 LOS LOX LDD 4 STS STX STD 4 CPX SUBD ADDD 5 JSR 5 1 2 3 1 2 3 4 1 2 3 4 1 2 3 4 5 1 2 3 4 5 (Continued) 93 . Data Bus. exceptions are indicated in the table). This information is useful in comparing actual with expected results during debug of both software and hardware as the HD6801V5 control program is executed. (In general. and the Read/Write line (R/W) during each cycle for each instruction. The information is categorized in groups according to addressing mode and number of cycles per instruction. • Summary of Cycle by Cycle Operation Table 12 provides a detailed description of the information present on the Address Bus.

R/W line of the sixth cycle is "1" level.HD6801VO. 94 (Continued) .1 1 1 1 1 0 0 Op Code Offset Low Byte of Restart Vector First Subroutine Op Code Return Address (Low Order Byte) Return Address (High Order Byte) 1 1 1 1 1 * In the TST instruction. HD6801V5---------------------------------------------Table 12 Cycle by Cycle Operation (Continued) Address Mode & Instructions Address Bus Data Bus INDEXED 3 1 2 3 Op Code Address Op Code Address + 1 Address Bus FFFF 1 1 1 Op Code Offset Low Byte of Restart Vector 4 1 2 3 4 Op Code Address Op Code Address + 1 Address Bus FFFF Index Register Plus Offset 1 1 1 1 Op Code Offset Low Byte of Restart Vector Operand Data STA 4 1 2 3 4 Op Code Address Op Code Address + 1 Address Bus FFFF Index Register Plus Offset 1 1 1 0 Op Code Offset Low Byte of Restart Vector Operand Data LDS LDX LDD 5 1 2 3 4 5 Op Code Address Op Code Address + 1 Address Bus FFFF Index Register Plus Offset Index Register Plus Offset + 1 1 1 1 1 1 Op Code Offset Low Byte of Restart Vector Operand Data (High Order Byte) Operand Data (Low Order Byte) STS STX STD 5 1 2 3 4 Op Code Address Op Code Address + 1 Address Bus FFFF Index Register Plus Offset Index Register Plus Offset + 1 1 1 1 Op Code Offset Low Byte of Restart Vector Operand Data (High Order Byte) Operand Data (Low Order Byte) JMP ADC ADD AND BIT CMP EOR LDA ORA SBC SUB 5 ASL ASR CLR COM DEC INC LSR NEG ROL ROR TST* CPX SUBD ADDO 6 1 2 3 4 5 6 6 1 2 3 4 5 6 JSR 6 1 2 3 4 5 6 0 0 Op Code Address Op Code Address + 1 Address Bus F F F F Index Register Plus Offset Address Bus FFFF Index Register Plus Offset 0 Op Code Offset Low Byte of Restart Vector Current Operand Data Low Byte of Restart Vector New Operand Data Op Code Address Op Code Address + 1 Address Bus FFFF Index Register + Offset Index Register + Offset + 1 Address Bus F F F F 1 1 1 1 1 1· Op Code Offset Low Byte of Restart Vector Operand Data (High Order Byte) Operand Data (Low Order Byte) Low Byte of Restart Vector Op Code Address Op Code Address + 1 Address Bus F F F F Index Register + Offset Stack Pointer Stack Pointer . DB=Low Byte of Reset Vector. and AB=FFFF.

HD6801V5 Table 12 Cycle by Cycle Operation (Continued) Address Mode & Instructions Data Bus Address Bus EXTENDED ADC ADD AND BIT CMP 3 Op Code Address Op Code Address + 1 Op Code Address + 2 1 1 1 Op Code Jump Address (High Order Byte) Jump Address (Low Order Byte) 4 1 2 3 4 Op Code Address Op Code Address + 1 Op Code Address + 2 Address of Operand 1 1 1 1 Op Code Address of Operand Address of Operand (Low Order Byte) Operand Data 4 1 2 Op Code Op Code Op Code Operand 1 1 1 0 Op Code Destination Address (High Order Byte) Destination Address (Low Order Byte) Data from Accumulator Op Code Address Op Code Address + 1 Op Code Address + 2 Address of Operand Address of Operand + 1 1 1 1 1 1 Op Code Address of Operand Address of Operand Operand Data (High Operand Data (Low (High Order Byte) (Low Order Byte) Order Byte) Order Byte) Op Code Address Op Code Address + 1 Op Code Address + 2 Address of Operand Address of Operand + 1 1 1 1 Op Code Address of Operand Address of Operand Operand Data (High Operand Data (Low (High Order Byte) (Low Order Byte) Order Byte) Order Byte) 3 JMP EOR LDA ORA SBC SUB STA A STA B 1 2 3 4 LDS LDX LDD 5 STS STX STD 5 ASL ASR CLR COM DEC INC 1 2 3 4 5 1 2 3 4 5 LSR NEG ROL ROR TST* 6 1 2 3 4 5 6 CPX SUBD ADDD 6 JSR 6 1 2 3 4 5 6 1 2 3 4 5 6 Address Address + 1 Address + 2 Destination Address 0 0 Op Code Address Op Code Address + 1 Op Code Address + 2 Address of Operand Address Bus F F F F Address of Operand 0 Op Code Address of Operand (High Order Byte) Address of Operand (Low Order Byte) Current Operand Data Low Byte of Restart Vector New Operand Data Op Code Address Op Code Address + 1 Op Code Address + 2 Operand Address Operand Address + 1 Address Bus F FF F 1 1 1 1 1 1 Op Code Operand Address (High Order Byte) Operand Address (Low Order Byte) Operand Data (High Order Byte) Operand Data (Low Order Byte) Low Byte of Restart Vector Op Code Address Op Code Address + 1 Op Code Address + 2 Subroutine Starting Address Stack Pointer Stack Pointer . and AB = FFFF.------------------------------------------------HD6801VO. DB = Low Byte of Reset Vector. 95 (Continued) . RtW line of the sixth cycle is "1" level.1 1 1 1 1 Op Code Address of Subroutine (High Order Byte) Address of Subroutine (Low Order Byte) Op Code of Next Instruction Return Address (Low Order Byte) Address of Operand (High Order Byte) 1 1 1 1 1 0 0 * In the TST instruction.

HD6801VO. + 1 Address Bus F F F F Op Code Address Op Code Address + 1 Stack Pointer Stack Pointer + 1 1 1 1 1 1 1 -P-S-H-X------~--4--~--1-~-O-p-C-o-de--A-d-d-re-s-s--------~---1-- 2 3 4 PULX 5 1 2 3 4 Op Code Address Op Code Address + 1 Stack Pointer Stack Pointer + 1 Stack Pointer +2 Op Code Address Op Code Address + 1 Stack Pointer Stack Pointer + 1 5 Stack Pointer + 2 1 2 3 4 Op Code Address C p Code Address + 1 Stack Pointer Stack Pointer .1 96 II 1 Op Code Op Code of Next Instruction Low Byte of Restart Vector Op Code Op Code of Next Instruction Irrelevant Data ---L I O--~·---C-od-e--------------- 1 0 I Irrelevant Data 0 I 1 1 1 1 1 1 1 1 1 1 1 o o Index Register (Low Order Byte) Index Register (High Order Byte) Op Code Irrelevant Data Irrelevant Data Index Register (High Order Byte) Index Register (Low Order Byte) Op Code Irrelevant Data Irrelevant Data Address of Next Instruction (High Order Byte) Address of Next Instruction (Low Order Byte) Op Code Op Code of Next Instruction Return Address (Low Order Byte) Return Address (Hiah Order Bvte] (Continued) .rrelevant Data I Low Byte of Restart Vector I Irrelevant Data DES 1 Op Code Address 1 i Op Code 3 2 Op Code Address + 1 1 Op Code of Next Instruction INS ______________~--------~-3~--+_P-re-v-io-u~s-R-e~gLis~t-er--C-o-nt-e_n_ts~1_--~l--_+-'-rr-e-'e--vantData 1 Op Code Address 1 Op Code INX 3 DEX 2 Op Code Address + 1 1 Op Code of Next Instruction 1 Low Byte of Restart Vector 3 Address Bus F F F F PSHA 1 Op Code Address 1 Op Code 3 PSHB 2 Op Code Address + 1 1 Op Code of Next Instruction Stack Pointer 0 Accumulator Data 3 1 Op Code Address 1 Op Code TSX 3 2 Op Code Address + 1 1 Op Code of Next Instruction Stack Pointer 1 Irrelevant D_a_t_a___________ 3 TXS PULA PULB 3 1 4 2 3 1 2 3 4 Op Code Address Op Code Address. HD6801V6----------------------------------------------Table 12 Cycle by Cycle Operation (Continued) Address Mode & Instructions Data Bus Address Bus IMPLIED ABA ASL ASR CBA CLC CLI CLR DAA DEC INC LSR NEG NOP ROL CLV ROR COM SBA ABX ASLD LSRD SEC SEI SEV TAB TAP TBA TPA TST Op Code Op Code of Next Instruction 2 Op Code Address Op Code Address + 1 3 1 2 3 Op Code Address Op Code Address + 1 Address Bus FFFF 1 1 3 1 Op Code Address Op Code Address + 1 Address Bus FFFF 1 I Op Code 1 1 I Low Byte of Restart Vector 2 1 2 3 1 i Op Code !.1 1 2 3 4 5 RTS WAI** 5 9 ! Op Code Address + 1 Stack Pointer Stack Pointer .

HD6801V5 Table 12 Cycle by Cycle Operation (Continued) Address Mode & Instructions Cycles Cycle # 5 6 7 WAI** 8 9 MUL 10 SWI 10 12 Stack Stack Stack Stack Stack Pointer Pointer Pointer Pointer Pointer - 2 3 4 5 6 R/W Line 0 0 0 0 0 Data Bus Index Register (Low Order Byte) Index Register (High Order Byte) Contents of Accumu lator A Contents of Accumulator B Contents of Condo Code Register 10 Op Code Address Op Code Address + 1 Address Bus FFFF Address Bus F F F F Address Bus FFFF Address Bus FFFF Address Bus FFFF Address Bus F F F F Address Bus FFFF Address Bus FFFF 1 1 1 1 1 1 1 1 1 1 Op Code Irrelevant Low Byte Low Byte Low Byte Low Byte Low Byte Low Byte Low Byte Low Byte 1 2 3 4 Op Code Address Op Code Address + 1 Stack Pointer Stack Pointer + 1 1 1 1 1 5 Stack Pointer + 2 1 6 Stack Pointer + 3 1 7 Stack Pointer + 4 1 8 Stack Pointer + 5 1 9 Stack Pointer + 6 1 10 Stack Pointer + 7 1 Op Code Irrelevant Data Irrelevant Data Contents of Condo Code Reg.1 1 1 0 0 5 6 7 10 11 Stack Pointer Stack Pointer Stack Pointer Stack Pointer Stack Pointer Stack Pointer Vector Address 2 3 4 5 6 7 F F FA (Hex) 0 0 0 0 0 1 1 12 Vector Address FFFB (Hex) 1 1 2 3 4 5 6 7 8 9 RTI Address Bus 8 9 Data of Restart of Restart of Restart of Restart of Restart of Restart of Restart of Restart Vector Vector Vector Vector Vector Vector Vector Vector Op Code Irrelevant Data Retu rn Address (Low Order Byte) Return Address (High Order Byte) Index Register (Low Order Byte) Index Register (High Order Byte) Contents of Accumulator A Contents of Accumulator B Contents of Condo Code Register Irrelevant Data Address of Subroutine (High Order Byte) Address of Subroutine (Low Order Byte) **While the MPU is in the "Wait" state. its bus state will appear as a series of MPU reads of an address which is seven locations less than the original contents of the Stack Pointer. from Stack Contents of Accumulator B from Stack Contents of Accumulator A from Stack Index Register from Stack (High Order Byte) Index Register from Stack (Low Order Byte) Next Instruction Address from Stack (High Order Byte) Next Instruction Address from Stack (Low Order Byte) 1 2 3 4 Op Code Address Op Code Address + 1 Stack Pointer Stack Pointer . Contrary to the HD6800.------------------------------------------------HD6801VO. (Continued) 97 . none of the ports are driven to the high impedance state by a WAI instruction.

. LOO and LOX instructions.1 1 1 1 1 0 0 Op Code Branch Offset Low Byte of Restart Vector Op Code of Next Instruction Return Address (Low Order Byte) Return Address (High Order Byte) 4 5 6 When the op codes (4E. 5E) are 1 byte/oo cycles instructions. Table 13 Op codes Map HD6801V MICROCOMPUTER INSTRUCTIONS OP CODE ACC A :~~ 0000 0 0001 1 0010 2 0011 3 0100 4 0000 0001 0 1 2 3 BRA TSX CBA BRN INS ~ BHI PULA (+1) NOP LSRO (+1) 0011 SBA ~ ---------- 0010 ~ BLS PULB (+1) ~ BCC DES 0101 5 ASLO (+1) ~ BCS TXS 0110 6 TAP TAB BNE PSHA 0111 7 8 TPA TBA BEQ PSHB INX (+1) ~ BVC PULX (+2) 1001 9 DEX (+1) OAA BVS RTS (+2) 1010 A CLV ~ BPL ABX 1000 1011 B SEV ABA BMI RTI (+7) 1100 C CLC ~ BGE PSHX (+1) 1101 0 SEC BLT MUL (+7) 1110 E CLI ---1--- 1111 F -----------BYTE/CYCLE [NOTES] /' / BGT WAI (+6) SEI ~ BLE SWI (+9) 1/2 1/2 2/3 1/3 ACC IND B ACCA or SP EXT 0100 0101 0110 0111 4 5 IMM INO 1000 1001 7 6 OIR 8 1010 1011 A 9 ----=-= ~ -----COM OIR INO 1100 1101 B C E 0 F 0 * CMP 1 SBC 2 SUBO (+2) * : AOOO (+2) 3 4 AND BIT 5 ROR LOA 6 / ----- / STA 7 8 STA EOR ASL ROL AOC 9 DEC ORA A * TST ~. HD6801V5---------------------------------------------Table 12 Cycle by Cycle Operation (Continued) Address Mode & Instruction Data Bus Address Bus RELATIVE BCC BHT BNE 3 BCS BlE BPL BEQ BLS BRA BGE BL T BVC BGT BMT BVS BRN ------------.(+1) CLR 1/2 B ADD INC 2/2 2/3 ) indicate that the number in parenthesis must be added to the cycle count for that instruction. the MPU continues to increase the program counter and it will not stop until the Reset signal enters. and undefined op codes (SF. 98 "**". These op codes are used to test the • Summary of Undefined Instruction Operations The HD6801 V has 36 undefined instructions. When these are carried out. Immediate addressing mode of SUBD. 4) The Op codes (4E.HD6801VO. CPX. 5E) are used to execute. 2) ( EXT 1110 1111 LSR ASR 1/2 IMM SUB NEG - ACCB or X EXT 2/4 3/4 . the contents of Register and Memory in MPU change at random.BSR 6 I 1 2 3 Op Code Address Op Code Address + 1 Address Bus FFFF 1 1 1 Op Code Branch Offset Low Byte of Restart Vector 1 2 3 Op Code Address Op Code Address + 1 Address Bus FFFF Subroutine Starting Address Stack Pointer Stack Pointer . LOS. and are marked with E LOX (+1) :(+1) 3/4 C 0 STO (+1) 1) Undefined Op codes are marked with ~.47 JMP (-3) **- 2/6 * CPX (+2) 3/6 2/2 * * LOS (+1) STS (+1) 2/3 2/4 LOO (+1) ~ (+1) JSR (+2) :. AOOO. F STX (+1) 3) The instructions shown below are all 3 bytes and are marked with "*". CFI. LSI. CD.

FFFA FFFB FFF8 FFF9 ICF OCF TOF SCI FFF6 FFF4 FFF2 FFFO Software Interrupt Maskable Interrupt Request 1 Input Capture Interrupt Output Compare Interrupt Timer Overflow Interrupt FFF7 FFF5 FFF3 FFF1 SCI Interrupt (TORE + RORF + ORFE) :l: C ~ CO o.....a Figure 24 Interrupt Flowchart < CJI .a < o :l: C G) CO o.co co *SCI Vector -> = TIE-TORE + RIE-(RORF + ORFE) PC NMI FFFC FFFD Non-Maskable Interrupt SWI IRQ.

HD6801VS---------------------------------------------Vee Vee Enable Enable Vee Standby NMI Port 3 8 Transfer Lines RES Port 1 81/0 Lines Port 1 8 I/O Lines Port 2 S I/O lines Port 4 81/0 Lines Port 4 8110 Lones Port 2 S I/O lines SCI SCI 16 Bit Timer Vss Figure 25 Vss HD6801V MCU Single-Chip Dual Processor Configuration HD6801V MCU Address Bus Data Bus Figure 26 HD6801V MCU Expanded Non-Multiplexed Mode Address Bus Data Bus Figure 27 HD6801V MCU Expanded Multiplexed Mode 100 .HD6801VO.

-. Pll AI2 .. Serial Communications interface (S. The H06803 MPU is object code compatible with the H06800 with improved execution times of key instructions plus several new 16-bit and 8-bit instructions including an 8 x 8 unsigned multiply with 16-bit result.).. OslAs D6'A.. The H06803 MPU has 128 bytes of RAM...I.. The H06803 MPU can be expanded to 65k words. lA.25MHz . Features and Block diagram of the H06803 include the following: HD6803C (DC-40) • • FEATURES Expanded HMCS6800 Instruction Set • • • 8 x 8 Multiply On-Chip Serial Communications Interface (S.. A.0 volt power supply. The H06803 MPU is TTL compatible and requires one +5..) Object Code Compatible With The HD6800 MPU • • • • 16-Bit Timer Expandable to 65k Words Multiplexed Address and Data 128 Bytes Of RAM (64 Bytes Retainable On Power Down) • • • • • 13 Parallel I/O Lines Internal Clock/Divided-By-Four TTL Compatible Inputs And Outputs Interrupt Capability Compatible with MC6803 HD6803P HD6803P-l (DP·40) • PIN ARRANGEMENT E AS RM • BLOCK DIAGRAM 0'0 lAo DI'AI D2/A2 D3. and parallel I/O as well as a three function 16-bit timer...-.-. PI2 t ..C...r... Ag AIO All t .-. P" As Ag AI" POl P" P.Vee Standby (Top View) A.I...C.. p\O t-----Pll t .H06803... A" PI' ~_ _ _ _ _ _.. H06803-1 M PU (Micro Processing Unit) The H06803 MPU is an 8-bit microcomputer system which is compatible with the HMCS6800 family of parts...0MHz HD6803-1 1. t-----Pl~ 101 • TYPE OF PRODUCTS Type No. Bus Timing HD6803 1.. Pll All Als . 0.P I 4 Au 1------PI6 I .. PIS AI..'A3 D.

Vss Item Input "High" Voltage .1A 100 2. E.25 Powerdown V SBB 4.0 Operating Temperature Topr V °c Storage Temperature Tstg Supply Voltage * '" + 70 °c .f .4V I LOAD = -205 JJ.• ABSOLUTE MAXIMUM RATINGS Item Symbol Value Unit -0.5 V 1. unless otherwise noted. If these conditions are exceeded.0V - 5.-0.0 - 5. R/W.6 mA V out = 1.0 mA 1200 mW - Operating *Except Mode Programming Levels.5V V in = OV.4 2.4 0. typ 4.3 0.1A 2:~ f------10 J.V in = 0 .A VOL -loH PD Cin I LOAD = 1. Normal operation should be under recommended operating conditions. AS II Ts " Do/Ao .H06803.A V OH I LOAD = -145/lA ILOAD = -100 JJ.0 10.0 pF V mA . f = 1.D7/A7 Other Outputs Output" Low" Voltage All Outputs Darlington Drive Current PlO Power Dissipation - P17 Input Capacitance Vee Standby Standby Current V in = 0.Vee V in = 0'" 5.8 V 0. IRQt.4 V 2.25 8.A t5 . • ELECTRICAL CHARACTERISTICS • DC CHARACTERISTICS (Vee =5.0 MHz - - 10. Ta = O-+70°C. Ta = 25°C. H06803-1------------------------------------------------.0V±5%.0 V Input Voltage Vee * V in * -0.0 V SB 4. RES Ilinl ---.5 .+150 With respect to VSS (SYSTEM GND) [NOTE) Permanent LSI damage may occur if maximum ratings are exceeded. it could affect reliability of LSI.3'" +7.55 .3'" +7.8 mA ----------J.- 0 =OV.2..75 Powerdown ISBB 102 max Unit Vee V 2.25V Ilinl Three State (Offset) PlO - Leakage Current P20 - Output "High" Voltage As .0 Vee -..) Symbol RES Other Inputs* Test Condition V 1H Allinputs* V 1L Input Load Current EXTAL Input Leakage Current NMI.0 Input "Low" Voltage Pt7 P24 min VSBB = 4.

) Item Symbol Cycle Time 'tcYc Address Strobe Pulse Width "High" PW ASH Address Strobe Rise Time tAs r t ASf Address Strobe Fall Time Address Strobe Delay Time Test Condition HD6803 min Enable Fall Time HD6803-1 max ns 50 5 5 - 50 5 - 50 60 - 30 - - ns 5 - 5 - 50 ns 5 - 50 ns 340 - ns 115 - 70 - 10 - 5 450 Address Strobe to Enable Delay Time t ASED Address Delay Time Fig.0V ± 5%. Vss = OV.) Item Symbol Test Condition min typ max Unit Peripheral Data Setup Time Port 1.2 tpDH Fig. Enable Negative Transition to Peripheral Data Valid Port 1. 7 100 Fig.--------------------------------------------------HD6803.3 - - 400 ns * Except P21 103 ns . 1 60 10 - 50 - tAD - - 260 tADL - 270 Data Set-up Write Time tDS W t DSR Read tHR 10 - Write 20 - Address Set-up Time for Latch tHW t ASL 60 Address Hold Time for Latch tAHL 20 Address Hold Time tAH 20 Peripheral Read Access Time (Multiplexed Bus) (tACCM) - 225 80 Fig. Vss = OV.2* tpWD Fig.2 200 - ns Peripheral Data Hold Time - Delay Time. Ta = 0'" +70°C.8 200 150 50 Address Delay Time for Latch Processor Control Set-up Time ns - PW EL tRc. unless otherwise noted. HD6803-1 • AC CHARACTERISTICS BUS TIMING (Vee = 5. Ta = 0'" +70°C.8 max - tEf PW EH I I typ 1 Enable Pulse Width "High" Time Data Set-up Read Time Unit min 200 tAS D t Er Enable Rise Time typ (600) - 350 30 - 20 50 20 20 100 200 10 ps - ns - ns 260 ns 260 ns - ns - ns (410) - ns ns ns ns ns ms ns PERIPHERAL PORT TIMING (Vee = 5. unless otherwise noted.2 t pDSU Fig.2 200 Port 1. t pcs ns 50 5 - Enable Pulse Width "Low" Time Oscillator stabilization Time - - 450 Data Hold Time 0.0V ± 5%.

.0 - Mode Programming Hold Time tMPH 150 - RES "Low" Pulse Width 3.f V tcyc ns . 4 SCI Input Clock Cycle tSCYC SCI Input Clock Pulse Width tPWSCK MODE PROGRAMMING (Vee Test Condition Unit =5.~ .. SCI TIMING (Vee =5.D7/A7 (Port 3) 1\ - I--tEr I--tEf - 2..6V l+- tASL- '- ~tAHL )~ ~. Ta = 0'" +70°C..6V . Enable Positive Transition to Timer Out t TOD typ max - - ns - - 600 ns 1 - -- tcyC 0. I-tHR .V PWEL j. unless otherwise noted.0V ±5%. - -tAD- j \ MPU Write Do/A" .6V ) ~2.) Item Symbol Timer Input Pulse Width tpWT Delay Time. Vss =OV. Ta =0'" +70°C..2V -tAH .2.H06803. Vss =OV. Data Valid .---tOSR---" } ~J:ress ~~ ~ -tDSW- j ~ -tADLMPU Read Do Ao-07 A7 (Port 3) '\ J \ I -'~ PWEH ~ -.0V ...4 - 0..0V ±5%..8V -.. H06803-1---------------------------------------------------TIMER.0 - tcyc Item Symbol Test Condition Mode Programming Set-up Time t MPS 2.4 V~ Enable (E) -- -- \ O... -PW ASH - 06Vt- 2.6 tScyC min 2t cyc +200 Fig. \ Address Valid { O.6V . (tACCM) \ { ~~O.... 5 - tcyc ''I Address Strobe (AS) .) min typ max Unit Mode Programming Input "Low" Voltage V MPL - 1.0 Fig.If - O. tASD -.7 V Mode Programming Input "High" Voltage VMPH PW RSTL 4.2V Valid O..ASED '--..... Figure 1 Expanded Multiplexed Bus Timing 104 ~tHW Data Valid }.5V - -tASr ~~ I--tASf l . unless otherwise noted.:'ess ~~ ) Valid O.

A.D..o -P. AS.~..-+ lS2074 ® or Equlv C C=90pFforD"/A"--D..o -P.. R W = 24 kn for P .-A".2~V----_ All Oat: Port Outputs Figure 3 Port Data Delay Timing (MPU Write) Enable (E) Timer Counter (~~~~.:..--------------------------------------------------H06803. RW = 30 pF for P ..o -P... -A. TTL Load Figure 6 Bus Timing Test Loads 105 .6V Data Valid • Not applicable to P 21 Figure 2 Data Set-up and Hold Times (MPU Read) X ~2-. . A.. E.. H06803-1 r r-MPU Read Enable (E) MPUWrite os:'t:::.I~~~:: )_______ """"< ~------------~ P" Output Figure 5 Mode Programming Timing Figure 4 Timer Output Timing Vee Test POlOt o-.. R = 12 kl1 for Do/A" . 7' P.wo I Enable (E) O.A. AS.. 7' P..o -P...... E. A..

EXTAL may be driven by an external TTL compatible source with a 50% (±lo%) duty cycle.. 30n typo XTA L 1----. 4 MHz ~I ~"!1 These two pins are used to supply power and ground to the chip.. RS I 60n max...: ~ o... The voltage supplied will be +5 volts ±5%. The following are the recommended crystal parameters: 106 I 5 MHz ~~~J??~~~_X'14.....- RES Internal Rm \\\\\\\\\\\\\\\\\\\\\:.~OV.... It will devided by 4 any frequency less than or equal to 5 MHz.25V or ...--'"'V--"'V"--""--~....... Two 22pF capacitors are needed from the two crystal pins to ground to insure reliable operation....-__... • XTAL and EXTAL These connections are for a parallel resonant fundamental crystal.....\\\\\\\\§\\\\\\\\\\\(1 5\s\\\\\\\\SS\\\\\\S\\\\\\\w----V '--I'~--"'--...t '1 ~ ~Jeo-T4." . Data Bus ... Internal interrupt Figure 7 Interrupt Sequence ~~\\~\\\\\\\~ ~\\\\%\\\\"\\ LJlJ4 -----------~S v~ ~. \ * r-- Internal...5 MHz) EXT A L 1 .---'·"F-ir-st-In-st'...~_4_.H06803..-_.. H06803-1------------------------------------------------- Last Instruction ~ Cycle #.58 MHz Color TV crystal for non-time critical applications... AT cut..J s '''-A-C-CA-'--A-CC-B-'''----'''-lr-re-lev-an-tJ'--ve-ct-o-r' ..2 ..-tP-cs-------.... The de vide by 4 circuitry allows for use of the inexpensive 3.__--.. PC-O---PCJ 7 "P-CS---PC-.r_-_... tL2 [NOTE] AT cut parallel resonance parameters ~CLl Figure 9 Crystal Interface .....7PF max...7_5V_____________________ -S.r----. ..-..."s .......-_..v--..-. )-\ r- tRC f1-fl-fl-J .x-O---X7-" '-x-a_-x-.J'\_-I'___ -"'-----'''-_'''-_.I"'-_~ NMI or IRG._-"_\.sv tpcs _''__"'''''l l\S\\\\\S\\\\\\\\\\\\\\\S\\\y 6~t~r.J"--_"-_ ss "'~ ~FFFE . XTAL must be grounded if an external clock is used........-__--.... Devided by 4 circuitry is included with the internal clock..--"o-P-c-o-de ...~! ~\\\\\\\\\\\\\\\\\\\1 J\\\\\\\\\\\\\\\\\\\\\\\\\\~ c...__-""\~--..t --------------~l~l--------------------------~5~ Ad~r~rn:~s ..J . Enable (El Internal Address Bus -"-....'o~fData MSB Interrupt Routine \~ Internal R/W J ______________________________-JI * Enable(EI IRQ.._~ pc::x:::x:: Instruction ~NotValid Figure 8 Reset Timing • SIGNAL DESCRIPTIONS • Nominal Crystal Parameter Vee andVSS --. C Ll = C L2 = 22pF ± 20% (3.. so a 4 MHz crystal may be used to run the system at 1 MHz.o-p-C-od-e" ..

4) The interrupt mask bit is set. It will drive one TTL load and 90 pF. Next the MPU will respond to the interrupt request by setting the interrupt mask bit "High" so that no further maskable interrupts may occur. The circuit of figure 13 can be utilized to assure that Vee Standby does not go below V SBB during power down. RAM E. An address loaded at these locations causes the MPU to branch to an interrupt routine in memory. in figure 11. Expanded Multiplexed Mode. the Index Register. 2) Keep Vee Standby greater than VSBB. This output is capable of driving one TTL load and 90 pF. PC 1 and PCO. Accumulators. a 16-bit address will be loaded that points to a vectoring address located in memory locations $FFFC and $FFFD. In response to an NMI interrupt. The Index Register. It is a single phase. a 16-bit address will be loaded that points to a vectoring address which is located in memory locations $FFF8 and $FFF9. $FFFF) locations in memory will be used to load the program addressed by the program counter. TTL compatible clock. An 8-bit latch is utilized in conjunction with Address Strobe. 2) I/O Port 2 bits. At the end of the sequence. 107 • ReadlWrite (RM) This TTL compatible output signals the peripherals and memory devices whether the MPU is in a Read ("High") or a Write ("Low") state. The timing for this singal is shown in Figure I of Bus 'Piming. as shown. This signal is used to latch the 8 LSB's of address which are multiplexed with data on Port 3.--------------------------------------------------HD6803. Internal Interrupts will use an internal interrupt line (IRQ2)' This interrupt will operate the same as IRQ 1 except that it will use the vector address of $FFFO through $FFF7. thereby protecting it at power down. • • Non-Maskable Interrupt (NMJ) A low-going edge on this input requests that a non-maskableinterrypt sequence be generated within the processor. one 8-bit port and one 5-bit port. RAM E is bit 6 of the RAM Control Register at location $0014. must be held "Low" at least 3 clock cycles. resulting from a power failure or an initial startup of the processor. if the interrupt mask bit in the Condition Code Register is not set. when brought "Low". the MPU does the following: 1) All the higher order address lines will be forced "High". must be cleared before the MPU can recognize maskable interrupts. Reset (RES) This input is used to reset and start the MPU from a power down condition. tASD before the data is enabled to the bus. The interrupt mask bit in the Condition Code Register has no effect on NMI. An address loaded at these locations causes the MPU to branch to a non-maskable interrupt service routine in memory. When a "High" level is detected. The first 64 bytes of RAM will be maintained in the power down mode with 8 rnA current max. • Interrupt Request (tRO l This level sensitive input requests that an interrupt sequence be generated within the machine. and Condition Code Register are stored on the stack. Program Counter. • Address Strobe (AS) In the expanded multiplexed mode of operation address strobe is output on this pin. This signal is also used to disable the address from the multiplexed bus allowing a deselect time. A 3. Figure 10 Battery Backup for Vee Standby • ) Table 1 Interrupt Vector Location Vector Highest Priority Lowest Priority MSB LSB FFFE FFFF FFFC FFFO FFFA FFFB Interrupt RES NMI Software Interrupt (SWI) FFF8 FFF9 IRQ l FFF6 FFF7 ICF (Input Capture) FFF4 FFF5 OCF (Output Compare) FFF2 FFF3 TOF (Timer Overflow) FFFO FFF1 SCI (RORF + ORFE + TORE) Enable (E) This supplies the external clock for the rest of the system when the internal oscillator is used. Accumulators. the processor will complete the current instruction that is being executed before it recognizes the NMI signal. 2. 3) The last two ($FFFE. RES. Each port has an associated write . On power up. 1. The processor will wait until it completes the current instruction that it being executed before it recognizes the request. Address Strobe signals the latch when it is time to latch the address lines so the lines can become data bus lines during the E pulse. At the end of the cycle. • PORTS There are two I/O ports on the HD6803 MPU.3 kU external resister to Vee which should be used for wire-OR and optimum control of inte~ts. The Interrupt Mask Bit in the condition code register masks both interrupts (See Table 1). The normal standby state of this signal is Read ("High"). During operation. This disables the standby RAM. and 0 are latched into programmed control bits PC2. IRQ l will have priority over IRQ2 if both occur at the same time. and Condition Code Register are stored on the stack. The IRQl requires a 3. Program Counter. At that time. As with interrupt Request signal. the-machine will begin an interrupt sequence.3 kU external resistor to Vee should be used for wire-OR and optimum control of interrupts. and will be the divide by 4 result of the crystal frequency. Inputs IRQl and NMI are hardware interrupt lines that are sampled during E and will start the interrupt routine on the E following the completion of an instruction. the reset must be held "Low" for at least 100 ms. H06803-1 • Vee Standby This pin will supply +5 volts ±5% to the standby RAM on the chip. To retain information in the RAM during power down the following procedure is necessary: 1) Write "0" into the RAM enable bit.

The values of above three pins during reset are latched into the three MSBs (Bit 5.8 V for a logic "0". The output control to the 74LS373 may be connected to ground. The 5 output buffers have three-state capability. A "I" in the corresponding Data Direction Register bit will cause that I/O line to be an output. There are two ports: Port I. 1 Functi0'l Table Add. -A.. GND AS l DJ .0 V for a logic "1" and less than 0. latches are required to latch those address bits. The 74LS373 Transparent Octal D-type latch can be used with the HD6803 to latch the least significant address byte. Port 2 can be configured as I/O and provides access to the Serial Communications Interface and the Timer. As outputs. this port has no internal pullup resistors but will drive TTL inputs directly. D.. The 8 output buffers have three-state capability. these lines are TTL compatible and may also be used as a source of up to I rnA at 1. Logical "0" H. the I/O lines are configured as inputs. Three pins on Port 2 (pin 8. After Reset. Port 2.5 V to directly drive a Darlington base. the voltage on the input lines must be greater than 2.0 V for a 10gic"I" and less than 0. 6 and 7) of Port 2 which are read only. In order to be read properly. state when used as an input. Bit 1 is the only pin restricted to data input or Timer output. A. Output Control a.. -0. allowing them to enter a high impedance state when the peripheral data lines are used as inputs. Their addresses and the addresses of their Data Direction registers are given in Table 2. Figure 11 Latch Connection 108 L L L H Enable Output G D a H H L H L H L x x ao x Z . Figure II shows how to connect the latch to the HD6803. G OC aJ 74LS373 D.9 and 10 of the chip) are requested to set following values (Table 3) during reset.HD6803. For driving CMOS inputs.8 V {or a logic "0". Logical "1" • Data/Address (Lower Order Address Bus Latches) Since the data bus is multiplexed with the lower order address bus in Data/Address. As outputs. In order to be read properly.. HD6803-1------------------------------------------------only Data Direction Register which allows each I/O line to be programmed to act as an input or an output*. which can either be data input or Timer output. I/O Port 2 This port has five lines that may be defined as inputs or outputs by its data direction register. A "0" in the corresponding Data Direction Register bit will cause that I/O line to be an input. * The only exception is bit 1 of Port 2. • [NOTES] L L. external pullup resistors are required. the voltage on the input lines must be greater than 2. Table 2 Port and Data Direction Register Addresses Ports Port Address Data Direction Register Address I/O Port 1 $0002 $0000 I/O Port 2 $0003 $0001 Table 3 The Values of three pins Pin Number Value 8 9 H 10 L • I/O Port 1 This is an 8-bit port whose individual bits may be defined as inputs or outputs by the corresponding bit in its data direction register. allowing them to enter a high impedance • INTERRUPT FLOWCHART The Interrupt flowchart is depicted in Figure 16 and is common to every interrupt excluding reset. 1 Dot. the I/O lines are configured as inputs. After Reset.

Table 4 Internal Register Area Port Port Port Port 1 2 1 2 Data Data Data Data Not Not Not Not Used Used Used Used Register Direction Register** Direction Register** Register Register Address 00 01 02 03 • Timer Control and Status Register Counter (High Byte) Counter (Low Byte) Output Compare Register (High Byte) 08 09 OA OB Output Compare Register (Low Byte) Input Capture Register (High Byte) Input Capture Register (Low Byte) Not Used OC 00 OE OF* Rate and Mode Control Register Transmit/Receive Control and Status Register Receive Data Register Transmit Data Register 10 11 12 13 RAM Control Register Reserved • Output Compare Register ($OOOB:OOOC) The Output Compare Register is a 16-bit read/write register which is used to control an output waveform. many seconds. The contents of this register are constantly compared with the current value of the free running counter. $06. $05. • a 16-bit output compare register. • a 16-bit free running counter. The Data Direction Register hit for Port 2 Bit 0. External Memory Space $FFFO I-----I~ _ _ __ } External Interrupt Vectors $FFFF~ [NOTE] Excludes the following addresses which may be used externally: $04. Input Multiplexed/RAM $0000 Free Running Counter ($0009:000A) The key element in the programmable timer is a 16-bit free running counter which is driven to increasing values by E (Enable). but may be of value in some applications. A memory map is shown in Figure 12. 14 15-1F * External Address ** 1. as shown in Table 4 with exceptions as indicated. the output level register value will appear on the pin for Port 2 Bit 1. Pulse widths for both input and output signals may vary from a few microseconds to. and • a 16-bit input capture register A block diagram of the timer registers is shown in Figure 13. When a match is found. a flag is set (OCF) in the Timer Control and Status Register (TCSR) and the current value of the Output Level bit (OLVL) in the TCSR is clocked to the Output Level Register. 04* 05* 06* 07* Internal Registers • $001F Input Capture Register ($OOOD:OOOE) The Input Capture Register is a 16-bit read-only register used to store the current value of the free running counter when the proper transition of an external input signal occurs. The Compare function is inhibited for one cycle following a write to the high byte of the Output Compare Register to insure a valid 16-bit value is in the register before a compare is made. The input transition change required to trigger the counter transfer is controlled by the input Edge bit (IEDG) in the TCSR. External Memory Space $0080 Internal RAM $OOFF • With Port 2 Bit 0 conitgured as an output and set to "I". Output. Providing the Data Direction Register for Port 2. and $OF. The counter is cleared to zero on RES and may be considered a read-only register with one exception. Bit 1 contains a "1" (Output). $07. The first 32 locations are reserved for the MPU's internal register area. Any MPU write to the counter's address ($09) will always result in preset value of $FFF8 being loaded into the counter regardless of the value involved in the write. HD6803-1 • MEMORY MAP • PROGRAMMABLE TIMER The MPU can provide up to 65k byte address space. The Output Compare Register is set to $FFFF during RES. should *Obe clear (zero) in order to gate in the external input signal to the edge detect unit in the timer.--------------------------------------------------HD6803. 0. The timer hardware consists of • an 8-bit control arid status register. The HD6803 contains an on-chip 16-bit programmable timer which may be used to perform measurements on an input waveform while independently generating an output waveform. This preset figure is intended for testing operation of the part. The values in the Output Compare Register and Output Level bit may then be changed to control the output level on the next compare value. The counter value may be read by the MPU software at any time. Figure 12 HD6803 Memory Map 109 . the external input will still be seen by the edge detect unit.

Bit 4 EICI Enable input Capture Interrupt . • a match has been found between the value in the free running counter and the output compare register.This read-only bit is set when a match is found between the output compare register and the free running counter.HD6803. this bit enables IRQ2 to appear on the internal 'bus for an output compare interrupt. The upper three bits contain read-only timer status information and indicate that: • a proper transition has taken place on the input pin with a subsequent transfer of the current counter value to the input capture register. If the DDR for Port 2 bit 1 is set.When set. It is cleared by a read of the TCSR (with OCF set) followed by an MPU write to the output compare register ($OB or SOC). If the I-bit in the HD6803 Condition Code register has been cleared. when clear the interrupt is inhibited. Bit 6 OCF Output Compare Flag . when clear the interrupt is inhibited. IEDG = 0 Transfer takes place on a negative edge ("High" -to-"Low" transition).This value is clocked to the output level register on 'a successful output compare. this bit enables IRQ 2 to occur on the internal bus for a TOF interrupt. Bit 5 TOF Timer Overflow Flag . a priority vectored interrupt will occur corresponding to the flag bit(s) set. Bit 7 ICF Input Capture Flag . when clear the interrupt is inhibited. . Bit 3 EOCI Enable Output Compare Interrupt .This bit controls which transition of an input will trigger a transfer of the counter to the input capture register.) with an individual Enable bit in the TCSR. Bit 1 IEDG Input Edge .This read-only bit is set when the counter contains $0000. it is cleared by a read of the TCSR (with ICF set) followed by an MPU read of the Input Capture Register ($OD). IEDG = 1 Transfer takes place on a positive edge 110 ("Low" -to-"High" transition). the value will appear on the output pin. and when $0000 is in the free running counter.This read-only status bit is set by a proper transition on the input. this bit enables IRQ2 to occur on the internal bus for an input capture interrupt. Each of the flags may be enabled onto the HD6803 internal bus (IRQ.When set. Bit 2 ETOI Enable Timer Overflow Interrupt . A description for each bit follows: Bit 0 OLVL Output Level . The DDR for Port 2 Bit o must be clear for this function to operate.When set. It is cleared by a read of the TCSR (with TOF set) followed by an MPU read of the Counter ($09). HD6803-1------------------------------------------------- HD6803 Internal Bus Output Input Level Edge Bit 1 Bit 0 Port 2 Port 2 Figure 13 Block Diagram of Programmable Timer Timer Control and Status Register 76543210 ICF • I I I OCF TOF EICI I EOCI I ETOIIIEDG I OLVLI $0008 Timer Control and Status Register (TCSR) ($0008) The Timer Control and Status Register consists of an 8-bit register of which all 8 bits are readable but only the low order 5 bits may be written.

:... The hardware. TE set should be alter at least one bit time of data transmit rate from the set-up of transmit data rate and mode. a wake-up feature is included whereby all further interrupt processing may be optionally inhibited until the beginning of the next message..external or internal • baud rate . the hardware re-enables (or "wakes-up") for the next message.when set. The software protocol must provide for the short idle period between any two consecutive messages.enabled or disabled • Interrupt requests -enabled or masked individually for transmitter and receiver data registers • clock output . bit 4 regardless of the DDR value corresponding to this bit. It should be noted that RE flag should be set in advance of MPU set of WU flag.:::-. In addition to the four registers. when clear. when clear. gates Port 2 bit 3 to input of receiver regardless of DDR value for this bit. serial I/O has no effect on Port 2 bit 3. Receiver Enable .when set. and 4 of Port 2. the serial I/O ~ction utilizes bit 3 (serial input) and bit 4 (serial output) of Port 2.-----~ "'---E Transmit Shift Register Tx Bit 4 12 $13 Programmable Options The following features of the HD6803 serial I/O· section are programmable: • format . and registers are explained in the following paragraphs. Bit 2 TI E Bit 3 RE Transmit/Receive Control and Status (TRCS) Register The TRCS register consists of an 8-bit register of which all 8 bits may be read while only bits 0-4 may be written. The bits in the TRCS register are defmed as follows: Bit 4 RIE "Wake-up" on Next Message . Receiver Interrupt Enable . • SSl Transmit/Receive Control and Status Register • Wake-Up Feature • cco Transmit Data Register Figure 14 Serial I/O Registers Bit 0 WU Bit 1 TE Serial Communications Hardware The serial communications hardware is controlled by 4 registers as shown in Figure 14. when clear. In order to permit non-selected MPU's to ignore the remainder of the message. Bit 2 of Port 2 is utilized if the internal-clock-out or external-clock-in options are selected. The registers include: • an 8-bit control and status register • a 4-bit rate and mode control register (write only) • an 8-bit read only receive data register and • an 8-bit write only transmit data register.one of 4 per given MPU tP2 clock frequency or external clock x8 input • wake-up feature . Transmit/Receive Control and Status Register 76543210 IROR3 ORFE' TORE' RIE I I RE 111 TIE' TE I I WU AOOR: $0011 .------------------------------------------------H08803. The "wake-up" is automatically triggered by a string of ten consecutive 1's which indicates an idle transmit line. Transmit Interrupt Enable . the interrupt is masked. Clock Bit 2 10 N-.set by HD6803 to produce pre am ble of nine consecutive 1's and to enable gating of transmitter output to Port 2.internal clock enabled or disabled to Port 2 (Bit 2) • Port 2 (bits 3 and 4) . The controller comprises a transmitter and a receiver which operate independently or each other but in the same data format and at the same data rate. will permit an IRQ2 interrupt to occur when bit 5 (TDRE) is set. I I I I CCl Bit 0 sso 1$10 $12 Port 2 (Not Addressable) Receive Shift Register In a typical multi-processor application. H08803-1 • SERIAL COMMUNICATIONS INTERFACE Bit 7 Rate and Mode Control Register I The HD6803 contains a full-duplex asynchronous serial communications interface (SCI) on chip.. When the next message appears. serial I/O has no effect on Port 2 bit 4. Transmit Enable ... The register is initialized to $20 on RES. Both transmitter and receiver communicate with the MPU via the data bus and with the outside world via pins 2.set by HD6803 software and cleared by hardware on receipt of ten consecutive 1's or reset of RE flag. the software protocol will usually contain a destination address in the initial byte(s) of the message.. 3.when set.standard mark/space (NRZ) • Clock .. when clear. will permit an IRQ2 interrupt to occur when bit 7 (RDRF) or bit 6 (ORFE) is set.dedicated or not dedicated to serial I/O individually for transmitter and receiver. software. the TDRE value is masked from the bus.

096 ms/244.800 Baud 128 ~s/7812. • the clock will be at Ix the bit rate and will have a rising edge at mid-bit.4 kHz 4.LS/4.200 Baud 1 1 E + 4096 6.5 Baud 1 0 E + 1024 1 .2 J. .3 J. The 4 bits in the register may be considered as a pair of 2-bit fields. Rate and Mode Control Register The Rate and Mode Control register controls the following serial I/O variables: • Baud rate • format • clocking source. or by RES.2288 MHz E + 16 26 J. and • Port 2 bit 2 configuration The register consists of 4 bits all of which are write-only and cleared on RES. or by RES. the following requirements are applicable: • the CCI. the following requirements are applicable: • the values of RE and TE are immaterial.These bits select the Baud rate for Bit 1 SS1 the internal clock.0 J.800 Baud 0 1 E + 128 208 J.500 Baud 13. the RDRF bit will not be set. Bit 6 ORFE Over-Run-Framing Error .this 2-bit field Bit 3 CC1 controls the format and clock select logic.CCO * Format Clock Source Port 2 Bit 2 Port 2 Bit 3. then reading the Receive Data Register. A framing error has occured when the byte boundaries in bit stream are not synchronized to bit counter. the ORFE bit will not be set.1 Baud 3. The ORFE bit is cleard by reading the status register. Bit 2 CCO Clock Control and Format Select .0 MHz.400 Baud 16 J.0 MHz 614. Bit 7 RORF Receiver Data Register Full-set by hardware when a transfer from the input shift register to the receiver data register is made. CCO must be set to 10 • the maximum clock rate will be E + 16.set by hardware when an overrun or framing error occurs (receive only) Rate and Mode Control Register 7 6 5 4 X X X X 3 2 CC1 CCO I I I 0 S51 SSO ADDR : $0010 An overrun is defined as a new byte received with last byte still in Dat Register/Buffer.Ls/76.set by hardware when a transfer is made from the transmit data register to the output shift register.024 ms/976. The TDRE bit is cleared by reading the status register. 'Table 5 SCI Bit Times and Rates XTAL 551 : SSO 0 0 E 2.67 ms/150 Baud 4. HD8803-1------------------------------------------------- Bit 5 TORE Transmit Data Register Empty .33 ms/300 Baud * HD6803-1 Only Table 6 SCI Format and Clock Source Control CC1. Table 6 defines the bit field.LS/38. then writing a new byte into the transmit data register.Ls/1 . • the external clock must be set to 8 times (X 8) the desired baud rate and • the maximum external clock frequency is 1. The four rates which may be selected are a function of the MPU fP2 clock frequency.0 MHz 1.4576 MHz 4.LS/9. Table 5 lists the available Baud rates.9152 MHz* 1. • CCI. If WU-flag is set.600 Baud 833. 112 Externally Generated Clock If the user wishes to provide an external clock for the serial I/O. Bit 3 is used for serial input if R E = "1" in TRCS.67 ms/600 Baud 1. If WU-flag is set.Ls/62. then reading the Receive Data Register. field in the Rate and Mode Control Register must be set to 11. Internally Generated Clock If the user wishes for the serial I/O to furnish a clock.HD8803. The two low order bits control the bit rate for internal clocking and the remaining tWQ bits control the format and clock select logic. The RDRF bit is cleared by reading the status register. The register definition is as follows: Bit 0 SSO Speed Select . CCO. TDRE is initialized to 1 by RES. bit 4 is used for serial output 'if TE = "1" in TRCS. Port 2 Bit 4 00 - - - ** ** 01 NRZ Internal Not Used ** ** 10 NRZ Internal Output* ** ** 11 NRZ External Input ** ** Clock output is available regardless of values for bits RE and TE.6 Baud 104.

mternal. Bit 1 Not used. This bit when ~t. $001. Transmit Operations The transmit operation is enabled by the TE bit in the Transmit/Receive Control and Status Register. • GENERAL DESCRIPTION OF INSTRUCTION SET The 006803 is upward object code compatible with the HD6800 as it implements the full HMCS6800 instruction set.ndby is held greater than VSBB volts. Bit 5 Not used. 2) if data has been loaded into the Transmit Data Register (TDRE = 0). During the transfer itself. At this point one of two situation exist: 1) if t~e Transmit Data Register is empty (TDRE = 1). Then the 8 data bits (beginning with bit 0) followed by the stop bit. In addition. The approximate center of each bit time is strobed during the next 10 bits. new instructions have been added. Bit 6 RAME The RAM Enable control bit allows the user the ability to disable the standby RAM. RAM enable bit (RAM E) will disable the standby RAM. • RAM CONTROL REGISTER This register. and bit ORFE is set. synchronization is established and the transmitter section is ready for operation. If the tenth bit is not a 1 (stop bit) a framing error is assumed. and inte:rupt flag RDRF is set. The receiver section operation is conditioned by the contents of the Transmit/ Receive Control and Status Register and the Rate and Mode Control Register. as explamed preViOusly m the signal description for Vee Standby. are transmitted. The double (D) accumulator is physically the same as the Accumulator A concatenated with the Accumulator B so that any operation using accumulator D will destroy information in A and B. This sequence will normally consist of.Table 12 • Summary of undefined instructions . and the data in the standby RAM is valid.Table 11 • Summary of cycle by cycle operation . Bit 2 Not used.Table 7 • New instructions • Index register and stack manipulations instructions . Bit 4. The receiver bit interval is divided into 8 sub-intervals for internal synchronization. (TDRE is still set when the next normal transfer from the parallel data register to the serial output register should occu() then a 1 will be sent (insteaq of a 0) at "Start" bit time. Following a RES the user should configure both the Rate and Mode Control Register and the Transmit/Receive Control and. Statu~ Register for desired operation. ~s proce~ure initiates the serial output by first ~ransm1tt1Dg a ten-bIt preamble of 1'so Following the preamble. Bit 3 Not used. No O's will be sent while TDRE remains a 1. the word is transferred to the output shift register and transmission of the data word will begin. the hardware sets the TDRE flag bit. the 0 start bit is first transmitted. If the HD6803 fails to respond to the flag within the proper time. data is read from external memory. Bit 7 STBY The Standby Power bit is cleared when the standPWR by voltage is removed. If the tenth bit as a 1 the data is transferred to the Receive Data Register. which is addressed at $0014 gives status information about the standby RAM. • writing the desired operation control bits to the Rate and Mode Control Register and • writing the desired operational control bits in the Transmit/ Receive Control and Status Register. these include 16-bit operations and a hardware multiply. This bit is set to a logic" 1" by RES which enables the standby RAM and can be written to one or zero under program control. Included in the instruction set section are the following: • MPU Programming Model (Figure 15) • Addressing modes • Accumulator and memory instructions . Bit 4 Not used. a contmuous string of ones will be sent indicating an idle line. HD6803-1 • Serial Operations The serial I/O hardware should be initialized by the HD6803 software prior to operation. or. This bit is a read/write status flag that the user can read which indicates that the standby RAM voltage has been applied. The Transmitter Enable (TE) and Receiver Enable (RE) bits may be left set for dedicated operations. thereby protecting 113 it at power d?wn if V~c Sta. The execution times of key instructions have been reduced to increase throughout. When the Transmitter Data Register has been emptied. When the RAM is disabled. Setting the TE bit dunng. If RDRF is still set at the next tenth bit time ORFE will be set. Receive Operation The receive operation is enabled by the RE bit which gates in the serial input through Port 2. A 0 in th. I . Bit 3.Table 8 • Jump and branch instructions .Table 9 • Condition code register manipulation instructions . followed by more I's until more data is supplied to the data register.Table 10 • Instructions Execution times in machine cycles .Table 13 • MPU Programming Model The programming model for the HD6803 is shown in Figure 15.------------------------------------------------HD6803. In the NRZ Mode. gates the output of the serial transmit shift register to Port 2 BIt 4 and takes unconditional control over the Data Direction Register value for Port 2. When th~ HD6803 responds to either flag (RDRF or ORFE) by reading the status register followed by reading the Data Register RDRF ' (or ORFE) will be cleared. the received bit stream is synchronized by the first 0 (space) encountered.1 S:J: IRAM:FT~ Rt: 1 X 1X X Bit 0 Not used. indicating an overrun has occurred.

HD8803. These are one-byte instructions. The MPU addresses this location when it fetches the immediate instruction for execution. either accumulator A or accumulator B is specified. Condition Code Register (CCR) Immediate Addressing eerry/Borrow from MSB Overflow Zaro Negative Interrupt Half eerry (From Bit 3) In immediate addressing. Accumulator (ACCX) Addressing In accumulator pnly addressing. HD8803-1-----------------------------------------------• MPU Addressing Modes 8-Bit Accumulators A and 8 Or 16-Bit Double Accumulator D 115 X 01 Index Register (X) 1 15 SP oJ Stack Pointer (SP) 115 PC 01 Program Counter (PC) The HD6803 8-bit micro processing unit has seven address modes that can be used by a programmer. With a clock frequency of 4 MHz. the operand is contained in the second byte Qf the instruction except LOS and LDX which have the operand in the second and third bytes of the instruction. These are two or three-byte instructions. A summary of the addressing modes for a particular instruction can be found in Table 11 along with the associated instruction execution time that is given in machine cycles. with the addressing mode a function of both the type of instruction and the coding within the instruction. these times would be microseconds. Figure 15 MPU Programming Model 114 .

1's Complement.1 .--------------------------------------------------HD6803..o-l C b7I I I I I I liJ • • I I I I I . SP • SP + 1-+ SP. - # OP 2 2 9B CB 2 C3 4 OP ADDA 8B ADDB INDEX DIRECT Register EXTEND IMPLIED - Boolean/ Arithmetic Operation - # OP - # 4 2 BB 4 3 A+M->A EB 4 2 FB 4 3 B+M->B E3 6 2 F3 6 3 - # OP 3 2 AB 2 DB 3 2 3 D3 2 OP # 4 H I N Z V C ~ ~ ~ ~ t ~ ~ ~ ~ A:B+M:M+1 .HI ~}~bj • bO B • M-+A PSHB ROL A+1-+A 4C 3D 10 1 8A ..... Inclusive Push Data ~ • • • 2 INCB Load Double Accumulator t ~ t t t ~ t t ~ t t t t 81 INCA Load Accumulator • • CMPA OECB Increment 1 CLRA OECA Exclusive OR 2 2 t Add Accumulators 5 3 1 0 5 • • • • ~ ~ R 115 • R 5 R R R 5 R R R 5 R R t t t ~ ~ ~ t ~ R 5 ~ t R 5 t R S t ~ t t ~ t t t t t t t <D@ <D@ t <D@ ~ t t ~ @ • t @ • t t t t t t t ~ t t @ @ • t R R • • @ • t @ • t t t t t t @ • t t R R R • • • • • t t R • t t R • • • • • • • • • • • • • • • • • t t @ • t t @ • t t @ • t t @ • t t @ • t t @ (Continued) The Condition Code Register notes are listed after Table 10 • • • • • • • ® • • • • • • t t t + t t ..1 . SP . t t t t • • 2 MUL Rotate Right R 3 ORAA Rotate Left R ~ 91 Multiply Unsigned Pull Data ~ t 2 OR... A:B • • • • A+B->A t ~ ~ Add Double ADDD ABA Add With Carry ADCA 89 2 2 99 3 2 A9 4 2 B9 4 3 A+M+C->A ADCB C9 2 2 D9 3 2 E9 4 2 F9 4 3 B+M+C->B t ANDA 84 2 2 94 3 2 A4 4 2 B4 4 3 A·M -> A ANDB C4 2 2 D4 3 2 E4 4 2 F4 4 3 B·M -+ B BIT A 85 2 2 95 3 2 A5 4 2 B5 4 3 A·M BIT B C5 2 2 D5 3 2 E5 4 2 F5 4 3 B·M • • • • 6F 6 2 7F 6 3 00-+ M AND Bit Test Clear 1B CLR Compare Compare Accumulators Complement.M->A • AxB-+A:B • A + M-+ A • B + M-+ B • A -+ Msp. SP .. Msp-> A • SP + 1 -+ SP. HD6803-1 Table 7 Accumulator & Memory Instructions Condition Code Addressing Modes Operations Add Mnemonic IMMED. 2's (Negate) Decimal Adjust. SP • B -+ Msp.. A Decrement 4F 2 1 00 -+ A CLRB 5F 2 1 00 -+ B R • • • • • • • • A1 4 2 B1 4 3 A-M CMPB C1 2 2 D1 3 2 E1 4 2 F1 4 3 B-M • • A-B 2 73 • • • • • • 11 CBA 63 COM 6 6 2 1 M-+M 3 A -+A COMA 43 2 1 COMB 53 2 1 B -+B 40 2 1 OO-A-+A 50 2 1 OO-B-+B NEG 60 6 2 70 6 OO-M-+M 3 NEGA NEGB DAA 19 6A DEC 2 1 6 2 7A 6 3 Converts binary add of BCD characters into BCD format M-1-+M 4A 2 1 A-1-+A 5A 2 1 B-1-+B EORA 88 2 2 98 3 2 A8 4 2 B8 4 3 A(j)M-+A EORB C8 2 2 08 3 2 E8 4 2 F8 4 3 B <±> M-+ B 6C 6 2 7C 6 3 INC LDAA 86 2 2 96 3 2 A6 4 2 B6 4 3 LOAB C6 2 2 06 3 2 E6 4 2 F6 4 3 LOO CC 3 3 DC 4 2 EC 5 2 FC 5 3 2 2 9A 3 2 AA 4 2 BA 4 3 OA 3 2 EA 4 2 FA 4 3 M+1 -+M ORAB CA 2 2 2 1 5C 2 1 B+1-+B PSHA 36 3 1 37 3 1 PULA 32 4 1 PULB 33 4 1 49 2 1 59 2 1 RORA 46 2 1 RORB 56 2 1 69 6 2 79 6 3 ROLA ROLB ROR 66 6 2 76 6 3 • • • • • • • • • • • • • • • • • • • • • • • • • • M->B • M+1-+8. Msp-> B • • :} • 60 B I.

..... M+ 1 Subtract SUBA 2 AO 4 2 BO 4 3 A-M . This result is then used to address memory.. Direct Addressing In direct addressing.. These are three-byte instructions.e. A Store Accumulator 80 2 2 90 3 bO A7 67 ASRA LSR Arithmetic Operation • ~ A~~ 'AZ 'A~~ g 1_0 • A7 AO 87 80 • ~}B [(Ib7 1!iTi IbO~ • • • ~}O-+l I 1111111. the address of the operand is contained in the second byte of the instruction.. The carry is then added to the higher order 8-bits of the index register. Extended Addressing In extended addressing. the address contained in the second byte of the instruction is added to the program counter's lowest 8-bits plus two...e. stack pointer. The carry or borrow is then added to the high 8-bits. In most configurations. This allows the user to address data within a range of -126 to +129 bytes of the present instruction. M • ASRB Shift Right Log ice I 5 # IMPLIED OP ASLA ASR Booleanl SUBB CO 2 2 DO 3 2 EO 4 2 FO 4 3 B . A SBCB C2 2 2 D2 3 2 E2 4 2 F2 4 3 B-M-C-+B Transfer Accumulators TAB 16 2 TBA 17 2 Test Zero or Minus TST 10 6D 6 2 7D 6 2 1 1 1 A .00 .o A B C b7 4 2 B7 4 3 6 2 77 6 3 64 6 2 74 6 3 LSRA 44 2 1 LSRB 54 2 1 04 3 1 LSRD - - STAA 97 3 2 STAB D7 3 2 E7 4 2 F7 4 3 B .. B Double Subtract SUBD 83 4 3 93 5 2 A3 6 2 B3 6 3 A:B-M:M+1-+A:B Subtract Accu mu lators SBA Subtract With Carry SBCA 82 2 2 92 3 2 A2 4 2 B2 4 3 A-M-C .. Direct addressing allows the user to directly address the lowest 256 bytes in the machine i.. The Condition Code ReDlster notes are listed after Table 10 . This is an absolute address in memory. Arithmetic Shift Right Arithmetic - # INDEX DIRECT OP - # ASL EXTEND OP - # OP - # 68 6 2 78 6 3 Double Shift Right Logical - 4 H I N Z • • • • 48 2 1 ASLB 58 2 1 ASLD 05 3 1 47 2 1 57 2 1 M} D-1llllllll... These are two-byte instructions. etc. These are twobyte instructions.M .. M B . These are one-byte instructions.. the address contained in the secdnd byte of the instruction is added to the index register's lowest 116 • ·• • • • • • • • • • • • • • • • • • • • • • • • • • 3 2 1 0 V C t t @t t t @t t t @t t t @ t t t t t t t t R t ® t t t t t t ® t ® t ® t §) t ®t @ t t t t t R t t R R • • • t t t t t t t t t t t t • t t t t • t t t t t t t t t t R • t t R • t t R R t t R R t t -R R • • • • • • 8-bits in the MPU... Indexed Addressing In indexed addressing.... These are two-byte instructions. Implied Addressing In the implied addressing mode the instruction gives the address (i. M Store Double Accumulator STD DD 4 2 ED 5 2 FD 5 3 A . locations zero through 255..). OP Shift Left Arithmetic Double Shift Left. The third byte of the instruction is used as the lower 8-bits of the address for the operand. it should be a random access memory.HD6803. Enhanced execution times are achieved by storing data in these locations... Relative Addressing In relative addressing. HD6803-1---------------------------------------------------------------------------Table 7 Accumulator & Memory Instructions (Continued) Condition Code Register Addressing Modes Operations Mnemonic IMMED. the address contained in the second byte of the instruction is used as the higher 8-bits of the address of the operand..g • bO B b7 • o-oj ACC AI ACCB ~ • A7 AO 87 80 A .B-+ A A-+B B-+A M-OO 3 A -00 TSTA 4D 2 1 TSTB 5D 2 1 B . The modified address is held in a temporary address register so there is no change to the index register. . index register.

The contents of ACCD remain unchanged. SP ..... The C bit is loaded from the most significant bit of ACCD. MS!)..--------------------------------------------------HD6803.. LSRD Shifts all bits of ACCD one place to the right... this instruction can be considered a two byte NOP (No operation) requiring three cycles for execution. CPX Internal processing modified to permit its use with any conditional branch instruction. (M+ 1) . Adds the 8-bit unsigned accumulator B to the 16-bit X. The A-accumu· latoris the most significant byte. XH.index register is pulled from the stack beginning at the current address contained in the stack pointer +1... M.. ASLD Shifts all bits of ACCD one place to the left. The stack pointer is decremented by 2. Bit 0 is loaded with zero.. SP 4 3 2 1 0 I N Z • • V C ~ ~ • • • ~ • • • • • • • • • ~ • • • • • • • • • • • • • • • • • • • • • • • • • • ~ (J) (j) (j) (j) • • • • ~ ~ ~ f f • • • • R R R R • • • • • • • • • • • • XH'" Msp . (M+1) Store Stack Pntr STS Index Reg ...X L . The C bit is loaded from the... (M+1) BF 5 3 SPH . ACCA contains MSB of result.. OP Compare Index Reg CPX Decrement Index Reg DEX BC 4 DIRECT # OP 3 9C - INDEX - # OP 5 2 AC 6 IMPLIED EXTND - # OP # OP 2 BC 6 3 - Boolean! Arithmetic Operation X-M:M+1 09 3 1 X-1"'X Decrement Stack Pntr DES 34 3 1 SP -1'" SP Increment Index Reg INX 08 3 1 X+ 1 . Table 8 Index Register and Stack Manipulation Instructions Condition Code Register Addressing Modes Pointer Operations Mnemonic IMMED... SP H .... PULX The . MUL Multiplies the 8 bits in accumulator A with the 8 bits in accumulator B to obtain a 16-bit unsigned number in A:B. Bit 15 is loaded with zero.. Msp'" XL • • • • • • . (M+1)"'SPL FF 5 3 XH"'M.Register taking into account the possible carry out of the low order byte of the X-Register. If effect. HD6803-1 • New Instructions In addition to the existing 6800 Instruction Set...... 117 5 1 SP + 1'" SP. BRN Never branches. LDD Loads the contents of double precision memory location into the double accumulator A:B. Stack Pntr TXS 35 3 1 X-1"'SP Stack Pntr .1 . The condition codes are set according to the data..... SUBD Subtracts the contents of M:M + 1 from the contents of double accumulator AB and places the result in ACCD. SP .... The stack pointer is incremented by 2 in total. X Push Data PSHX 3C 4 1 XL ...1 . least significant bit to ACCD. SP Pull Data 38 PULX The Condition Code Register notes are listed after Table 1 O. Index Reg TSX 30 3 1 SP+ 1'" X Add ABX 3A 3 1 B + X .. the following new instructions are incorporated in the HD6803 Microcomputer. Msp'" X H SP + 1'" SP. PSHX The contents of the index register is pushed onto the stack at the address contained in the stack pointer. XL BE 5 3 M . STD Stores the contents pf double accumulator A:B in memory.. ADDD Adds the double precision ACCD* to the double precision value M:M+I and places the results in ACCD. X Increment Stack Pntr INS 31 3 1 SP + 1'" SP Load Index Reg LOX CE 3 3 Load Stack Pntr LOS BE 3 3 Store Index Reg STX 2 EE 5 2 AE 5 2 OF 4 2 EF 5 2 9F 4 2 AF 5 2 DE 4 9E 4 2 5 H # FE 5 3 M .. ABX *ACCO'is the 16 bit register (A:B) formed by concatenating the A and B accumulators...SP L .

.. C Set Interrupt Mask SEI OF 2 1 1 -+ I Set Overflow OB 06 2 2 1 Accumulator A . Only • • • • IMPLIED Sae Special Operations 1 . If previously set. # Branch Always BRA 20 3 2 None Branch Never BRN 21 3 2 None Branch If Carry Clear BCC 24 3 2 C=O Branch If Carry Set BCS 25 3 2 C=1 Branch If = Zero BEQ 27 3 2 Z=1 Branch If :> Zero BGE 2C 3 2 N~ V=O Branch If > Zero BGT 2E 3 2 Z+ (N ~ V) = 0 Branch If Higher BHI 22 3 2 C+Z=O Branch If . # OP .... IMPLIED EXTND # OP .... A 5 4 3 2 1 0 H I N Z V C • • • • • R • R • • • • • • • • R • • • • • • S • S • • • • • • • • S • @ • • • • • • Condition Code Register Notes: (Bit set it test is true and cleared otherwise) t (Bit V) (Bit C) (Bit C) (Bit VI (Bit V) (Bit V) (Bit N) (All) (Bit I) (All) (Bit C) Test: Result = 10oooo00? Test: Result = 00000000? Test: Decimal value of most significant BCD Character greater than nine? (Not cleared if previously set) Test: Operand = 10000000 prior to execution? Test: Operand = 01111111 prior to execution? Test: Set equal to result of N ~ C after shift has occurred.HOS803.... Set equal to result of Bit 7 (AccB) 118 • • • • • • • • • S • • • • • @• • • • Condition Code Register Boolean Operation OP • • -@- AddressingModes Mnemonic • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • Table10 Condition Code Register Manipulation Instructions Operations • • • • .... Cntr.... (See Special Operations) Set when interrupt occurs. Branch To Subroutine BSR Jump JMP Jump To Subroutine JSR No Operation NOP 01 Return From Interrupt RT! 3B 10 1 Return From Subroutine RTS 39 Software Interrupt SWI 3F 12 1 Wait for Interrupt WAI 3E 90 6E 3 2 7E 3 3 2 AD 6 2 BD 6 3 5 5 9 1 1 4 2 1 0 I N Z V C • • • • • • • • 3 • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • See Special Operations 2 5 H Advances Prog.... 1 Branch If Not Equal Zero BNE 26 3 2 Z=O Branch If Overflow Clear BVC 28 3 2 V=O 29 3 2 V=1 2A 3 2 N=O 80 6 2 Branch If Overflow Set BVS Branch If Plus BPl .. CCR SEV TAP 1 1-+V A . V Set Carry SEC 00 2 1 1 ... Zero BlE 2F 3 2 Z+ (N ~ V) = 1 Branch If lower Or Same BlS 23 3 2 C+Z=1 Branch If < Zero BlT 20 3 2 N~V=1 Branch If Minus BMI 2B 3 2 N .....0. CCR CCR -+ Accumulator A TPA 07 2 1 CCR . Set according to the contents of Accumulator A. HOS803-1------------------------------------------------Table 9 Jump and Branch Instructions Condition Code Register Addressing Modes Operations Mnemonic RELATIVE DIRECT OP .. Branch Test # OP .. # OC 2 1 O-+C Clear Carry ClC Clear Interrupt Mask Cli OE 2 1 0-+1 Clear Overflow ClV OA 2 1 0 .. INDEX # OP ... a Non-Maskable Interrupt is required to exit the wait state.... Test: Result less than zero? (Bit 15 = 1) load Condition Code Register from Stack...

Table 11 Instruction Execution Times in Machine Cycle ACCX I~~:.Direct te~~~d dexed plied In- ABA ABX ADC ADD ADDD AND ASL ASLD ASR BCC BCS BEQ BGE BGT BHI BIT BLE BLS BLT BMI BNE BPL BRA BRN BSR BVC BVS CBA CLC • • • • • • 2 • 2 • • t • • • • • • • • • • • • • • • • • CLI • CLR CLV 2 • CMP COM • CPX DAA DEC DES DEX EOR • • • • INC 2 INS • 2 • 2 • • 2 2 4 2 • • • • • • • • • • • • 3 3 5 3 4 • • • • • • • • • • • • 4 4 4 6 6 4 4 6 6 • • 6 6 • • • • • • • • • • • • 2 3 4 4 • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 3 • • • • • • • • • • • • • • • • • • • 2 • • 6 6 • • • 2 3 4 4 • • 6 6 4 5 6 6 • • • • • • • • 6 6 • • • • • • 2 3 4 4 • • • 2 3 2 • • Im- • • • 6 6 • • HD8803-1 2 2 • • • 2 • 3 3 • • 3 Relative • • • • • • • • • 3 3 3 3 3 3 • 3 3 3 3 3 3 3 3 6 3 3 • • • • • • • • • • • • • • • 119 INX JMP JSR LOA LDD LOS LOX LSR LSRD MUL NEG NOP ORA PSH PSHX PUL PULX ROL ROR RTI RTS SBA SBC SEC SEI SEV STA STD STS STX SUB SUBD SWI TAB TAP TBA TPA TST TSX TXS WAI • • • • • • • 3 3 6 6 2 5 3 • • • • • • 2 • • • • • • • • 2 • • 3 • 4 • 2 2 3 3 3 2 • • • • • • 4 4 4 • • • • 4 • • • • • • 6 6 • 3 4 4 • • • • • • • • • • • • • 6 6 6 6 • • • • • • • • • • • 2 3 4 4 • • • • • • • • • • • • • • • • • • • • • • • • • • • • 2 • • • • • 3 4 4 • 4 5 5 5 2 4 3 4 • • • • • • 4 4 5 5 5 4 5 6 6 • • • • • • • • • • • • • • • • • • 5 5 5 • • 3 • • 4 • • lative 5 5 5 6 6 • • • 3 10 • 2 • • 4 • 5 • • 10 5 2 • 2 2 2 • • • • • • 12 • • 2 • 2 • • • 6 6 • • • • • • • • Re- Implied 2 2 • 3 3 9 • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • .-------------------------------------------------HD8803.

Table 12 Cycle by Cycle Operation Address Mode & Instructions Data Bus Address Bus IMMEDIATE 2 1 2 Op Code Address Op Code Address + 1 1 1 Op Code Operand Data LDS LDX 3 1 2 Op Code Address Op Code Address + 1 Op Code Address + 2 1 1 1 Op Code Operand Data (High Order Byte) Operand Data (Low Order Byte) CPX SUBD ADDD 4 Op Code Address Op Code Address + 1 Op Code Address + 2 Address Bus F F F F 1 1 1 1 Op Code Operand Data (High Order Byte) Operand Data (Low Order Byte) Low Byte of Restart Vector Op Code Address Op Code Address + 1 Address of Operand 1 1 1 Op Code Address of Operand Operand Data Op Code Address Op Code Address + 1 Destination Address 1 1 0 Op Code Destination Address Data from Accumulator Op Code Address Op Code Address + 1 Address of Operand Operand Address + 1 1 1 1 1 Op Code Address of Operand Operand Data (High Order Byte) Operand Data (Low Order Byte) Op Code Address Op Code Address + 1 Address of Operand Address of Operand + 1 1 1 0 0 Op Code Address of Operand Register Data (High Order Byte) Register Data (Low Order Byte) Op Code Address Op Code Address + 1 Operand Address Operand Address + 1 Address Bus F F F F 1 1 1 1 1 Op Code Address of Operand Operand Data (High Order Byte) Operand Data (Low Order Byte) Low Byte of Restart Vector Op Code Address Op Code Address + 1 Subroutine Address Stack Pointer Stack Pointer + 1 1 1 1 Op Code Irrelevant Data First Subroutine Op Code Return Address (Low Order Byte) Return Address (High Order Byte) ADC ADD AND BIT CMP EOR LDA ORA SBC SUB 3 1 2 3 4 DIRECT ADC ADD AND BIT CMP EOR LDA ORA SBC SUB STA 3 1 2 3 3 1 2 3 LDS LDX LDD 4 STS STX STD 4 CPX SUBD ADDD 5 JSR 5 1 2 3 4 1 2 3 4 1 2 3 4 5 1 2 3 4 5 0 0 (Continued) 120 . The information is categorized in groups according to addressing mode and number of cycles per instruction. This information is useful in comparing actual with expected results during debug of both software and hardware as the control program is executed. (In general. exceptions are indicated in the table). Data Bus. and the Read/Write line (R/W) during each cycle for each instruction. HD6803-1------------------------------------------------- • Summary of Cycle by Cycle Operation Table 12 provides a detailed description of the information present on the Address Bus. instructions with the same addressing mode and number of cycles execute in the same manner.HD6803.

and AB = FFFF.-------------------------------------------------HD6803. 121 (Continued) . R/W line of the sixth cycle is "1" level. DB = Low Byte of Reset Vector. HD6803-1 Table 12 Cycle by Cycle Operation (Continued) Address Mode & Instructions Data Bus Address Bus INDEXED JMP 3 1 2 3 ADC ADD AND BIT CMP EOR LDA ORA SBC SUB STA 4 1 2 3 4 4 1 2 3 4 LDS LDX LDD 5 STS STX STD 5 ASL ASR CLR COM DEC INC 1 2 3 4 5 1 2 3 4 5 LSR NEG ROL ROR TST* 6 1 2 3 4 5 6 CPX SUBD ADDD 6 JSR 6 1 2 3 4 5 6 1 2 3 4 5 6 Op Code Address Op Code Address + 1 Address Bus FFFF 1 1 1 Op Code Offset Low Byte of Restart Vector Op Code Address Op Code Address + 1 Address Bus F F F F Index Register Plus Offset 1 1 1 1 Op Code Offset Low Byte of Restart Vector Operand Data Op Code Address Op Code Address + 1 Address Bus F F F F Index Register Plus Offset 1 1 1 0 Op Code Offset Low Byte of Restart Vector Operand Data Op Code Address Op Code Address + 1 Address Bus FFFF Index Register Plus Offset Index Register Plus Offset + 1 1 1 1 1 1 Op Code Offset Low Byte of Restart Vector Operand Data (High Order Byte) Operand Data (Low Order Byte) Op Code Address Op Code Address + 1 Address Bus FFFF Index Register Plus Offset Index Register Plus Offset + 1 1 1 1 0 0 Op Code Offset Low Byte of Restart Vector Operand Data (High Order Byte) Operand Data (Low Order Byte) Op Code Address Op Code Address + 1 Address Bus FFFF Index Register Plus Offset Address Bus FFFF Index Register Plus Offset 1 1 1 1 1 0 Op Code Offset Low Byte of Restart Vector Current Operand Data Low Byte of Restart Vector New Operand Data Op Code Address Op Code Address + 1 Address Bus F F F F Index Register + Offset Index Register + Offset + 1 Address Bus F F F F 1 1 1 1 1 1 Op Code Offset Low Byte of Restart Vector Operand Data (High Order Byte) Operand Data (Low Order Byte) Low Byte of Restart Vector Op Code Address Op Code Address + 1 Address Bus FFFF Index Register + Offset Stack Pointer Stack Pointer .1 1 1 1 1 0 0 Op Code Offset Low Byte of Restart Vector First Subroutine Op Code Return Address (Low Order Byte) Return Address (High Order Byte) * In the TST instruction.

DB = Low Byte of Reset Vector.1 0 0 • In the TST instruction. 122 (Continued) . Op Code Address + 2 Operand Address Operand Address + 1 Address Bus FFFF 1 1 1 1 1 1 Op Code Operand Address (High Order Byte) Operand Address (Low Order Byte) Operand Data (High Order Byte) Operand Data (Low Order Byte) Low Byte of Restart Vector 1 1 1 1 Op Code Address of Subroutine (High Order Byte) Address of Subroutine (Low Order Byte) Op Code of Next Instruction Return Address (Low Order Byte) Address of Operand (High Order Byte) Op Code Address Op Code Address + 1 Op Code Address + 2 Subroutine Starting Address Stack Pointer Stack Pointer . HD6803-1------------------------------------------------Table 12 Cycle by Cycle Operation (Continued) Address Mode & Instructions Data Bus Address Bus EXTENDED 3 JMP 1 2 3 ADC ADD AND BIT CMP 4 EOR LOA ORA SBC SUB 1 2 3 4 4 STA A STA B 1 2 3 4 5 LOS LOX LDD 1 2 3 4 5 5 STS STX STD 1 2 3 4 5 ASL ASR CLR COM DEC INC 6 LSR NEG ROL ROR TST* 1 2 3 4 5 6 6 CPX SUBD ADDD 1 2 3 4 5 6 JSR 6 1 2 3 4 - 5 6 Op Code Address Op Code Address + 1 Op Code Address + 2 1 1 1 Op Code Jump Address (High Order Byte) Jump Address (Low Order Byte) Op Code Address Op Code Address + 1 Op Code Address + 2 Address of Operand 1 1 1 1 Op Code Address of Operand Address of Operand (Low Order Byte) Operand Data Op Code Address Op Code Address + 1 Op Code Address + 2 Operand Destination Address 1 1 1 0 Op Code Destination Address (High Order Byte) Destination Address (Low Order Byte) Data from Accumulator Op Code Address Op Code Address + 1 Op Code Address + 2 Address of Operand Address of Operand + 1 1 1 1 1 1 Op Code Address of Operand Address of Operand Operand Data (High Operand Data (Low (High Order Byte) (Low Order Byte) Order Byte) Order Byte) Op Code Address Op Code Address + 1 Op Code Address + 2 Address of Operand Address of Operand + 1 1 1 1 0 0 Op Code Address of Operand Address of Operand Operand Data (High Operand Data (Low (High Order Byte) (Low Order Byte) Order Byte) Order Byte) Op Code Address Op Code Address + 1 Op Code Address + 2 Address of Operand Address Bus FFFF Address of Operand 1 1 1 1 1 0 Op Code Address of Operand (High Order Byte) Address of Operand (Low Order Byte) Current Operand Data Low Byte of Restart Vector New Operand Data Op Code Address Op Code Address + 1 . and AB =FFFF. R/W line of the sixth cycle is "1" level.HD6803.

HD8803-1 Table 12 Cycle by Cycle Operation (Continued) Address Mode & Instructions Address Bus Data Bus IMPLIED ABA ASL ASR CBA CLC CLI CLR CLV COM DAA DEC INC LSR NEG NOP ROL ROR SBA SEC SEI SEV TAB TAP TBA TPA TST 2 1 2 ABX 3 ASLD LSRD 3 DES INS 3 INX DEX 3 PSHA PSHB 3 TSX 3 TXS 3 PULA PULB 4 1 2 3 1 2 3 1 2 3 1 2 3 Op Code Irrelevant Data Low Byte of Restart Vector Op Code Address Op Code Address + 1 Previous Register Contents 1 1 1 1 1 1 Op Code Op Code of Next Instruction Irrelevant Data 1 1 Op Code Address Op Code Address + 1 Address Bus F F F F Op Code Op Code of Next Instruction Low Byte of Restart Vector 1 1 1 Op Code Op Code of Next Instruction Low Byte of Restart Vector Op Code Address Op Code Address + 1 Stack Pointer Stack Pointer + 1 1 1 1 1 Op Code Op Code of Next Instruction Irrelevant Data Op Code Address Op Code Address + 1 Stack Pointer Stack Pointer .1 1 1 1 2 1 2 1 2 3 4 5 9 1 1 1 Op Code Address Op Code Address + 1 Address Bus FFFF 1 2 4 WAI** Op Code Address Op Code Address + 1 Address Bus FFFF Op Code Op Code of Next Instruction Irrelevant Data 3 5 Op Code Irrelevant Data Low Byte of Restart Vector 1 1 1 3 RTS 1 1 1 0 4 5 Op Code Address Op Code Address + 1 Address Bus F F F F Op Code Address Op Code Address + 1 Stack Pointer 1 2 3 PULX Op Code Op Code of Next Instruction Op Code Op Code of Next Instruction Accumulator Data 3 4 1 1 Op Code Address Op Code Address + 1 Stack Pointer 1 2 3 PSHX Op Code Address Op Code Address + 1 1 2 3 4 123 0 0 Op Code Irrelevant Data Irrelevant Data Index Register (High Order Byte) Index Register (Low Order Byte) Op Code Irrelevant Data Irrelevant Data Address of Next Instruction (High Order Byte) Address of Next Instruction (Low Order Byte) Op Code Op Code of Next Instruction Return Address (Low Order Byt~) Return Address (High Order Byte) (Continued) .-------------------------------------------------HD8803.1 1 1 0 0 Op Code Irrelevant Data Index Register (Low Order Byte) Index Register (High Order Byte) 2 3 4 Op Code Address Op Code Address + 1 Stack Pointer Stack Pointer + 1 Stack Pointer +2 Op Code Address Op Code Add ress + 1 Stack Pointer Stack Pointer + 1 1 1 1 1 1 1 1 1 1 5 Stack Pointer + 2 1 1 Op Code Address Op Code Address + 1 Stack Pointer Stack Pointer .

1 1 1 0 0 5 6 7 10 11 Stack Pointer Stack Pointer Stack Pointer Stack Pointer Stack Pointer Stack Pointer Vector Address 2 3 4 5 6 7 FFFA (Hex) 0 0 0 0 0 1 1 12 Vector Address FFFB (Hel<) 1 8 9 RTI Address Bus 8 9 Vector Vector Vector Vector Vector Vector Vector Vector Op Code Irrelevant Data Return Address (low Order Byte) Return Address (High Order Byte) Index Register (low Order Byte) Index Register (High Order Byte) Contents of Accumulator A Contents of Accumulator B Contents of Cond.HD8803. Code Register Irrelevant Data Address of Subroutine (High Order Byte) Address of Subroutine (low Order Byte) (Continued) ** While the MPU is in the "Wait" state. from Stack Contents of Accumulator B from Stack Contents of Accumulator A from Stack Index Register from Stack (High Order Byte) Index Register from Stack (low Order Byte) Next Instruction Address from Stack (High Order Byte) Next Instruction Address from Stack (low Order Byte) 1 2 3 4 Op Code Address Op Code Address + 1 Stack Pointer Stack Pointer . its bus state will appear as a series of MPU reads of an address which is seven locations less than the original contents of the Stack Pointer. HD8803-1------------------------------------------------Table 12 Cycle by Cycle Operation (Continued) Address Mode & Instructions Cycles Cycle # 5 6 7 WAI** 8 9 MUL 10 1 2 3 4 5 6 7 SWI 10 12 Stack Stack Stack Stack Stack Pointer Pointer Pointer Pointer Pointer - 2 3 4 5 6 RIW Line 0 0 0 0 0 Data Bus Index Register (low Order Byte) Index Register (High Order Byte) Contents of Accumulator A Contents of Accumulator B Contents of Condo Code Register 10 Op Code Address Op Code Address + 1 Address Bus FFFF Address Bus F F F F Address Bus FFFF Address Bus FFFF Address Bus FFFF Address Bus F F F F Address Bus FFFF Address Bus FFFF 1 1 1 1 1 1 1 1 1 1 Op Code Irrelevant Data low Byte of Restart low Byte of Restart low Byte of Restart low Byte of Restart low Byte of Restart low Byte of Restart low Byte of Restart low Byte of Restart 1 2 3 4 Op Code Address Op Code Address + 1 Stack Pointer Stack Pointer + 1 1 1 1 1 5 Stack Pointer + 2 1 6 Stack Pointer + 3 1 7 Stack Pointer + 4 1 8 Stack Pointer + 5 1 9 Stack Pointer + 6 1 10 Stack Pointer + 7 1 Up Code Irrelevant Data Irrelevant Data Contents of Condo Code Reg. none of the ports are driven to the high impedance state by a WAI instruction. Contrary to the HD6800. 124 .

LDD and LOX instructions. LOS. 5E) are 1 byte/ oo cycles instructions.. and are marked with " •• " C 0 STD (+1) ~(+1) STS (+1) 2/3 · . These op codes are used to test the The HD6803 has 36 underfined instructions. Immediate addressing mode of SUBD. When these are carried out. the contents of Register and Memory in MPU change at random.-------------------------------------------------HD6803. ADDD.". and undefined op codes (8F. ~:4~ . CPX. Table 13 Op codes Map HD6803 MICROCOMPUTER INSTRUCTIONS OP CODE ACC A ~ LO 0000 0 0001 1 2 0010 0000 ------------- 0001 0 0010 0011 1 2 3 SBA BRA TSX CBA BRN INS ~ BHI PULA (+1) BLS PULB (+1) ~ BCC DES ASLD(+1) ~ BCS TXS TAP TAB BNE PSHA NOP ~ 0011 3 0100 4 0101 5 0110 6 0111 7 TPA TBA BEQ PSHB 1000 8 INX (+1) ~ BVC PULX (+2) LSRD (+1) 1001 9 DEX (+1) DAA BVf RTS (+2) 1010 A CLV ~ BPL ABX 1011 B SEV ABA BMI RTI (+7) 1100 C CLC ~ BGE PSHX (+1) 1101 0 SEC 1110 E CLI 1111 F SEI 1/2 BYTE/CYCLE [NOTES] / BLT MUL (+7) BGT WAI (+6) ~ BLE SWI (+9) 1/2 2/3 1/3 / ACC INO B ACCA orSP EXT 0100 0101 0110 0111 ------------4 5 6 IMM OIR 1000 1001 7 8 9 INO OIR INO 1010 1011 1100 1101 A NEG C B E 0 F 0 . the MPU continues to increase the program counter and it will not stop until the Reset signal enters. CD. 125 E F STX (+1) 3) The instructions shown below are all 3 bytes and are marked with ". CFI. 4) The Op codes (4E. LSI.. 2) ( EXT 1110 1111 SUB COM 1/2 ACCB or X EXT IMM 2/4 3/4 .: (+1) B LDD(+1) 1) Undefined Op codes are marked with ~. HD6803-1 Table 12 Cycle by Cycle Operation (Continued) RELATIVE Address Mode & Instructions BCC BHT BNE BCS BLE BPL BEQ BLS BRA BGE BL T BVC BGT BMT BVS BRN Cycles Cycle 3 1 2 3 BSR 1 6 2 3 4 5 6 R/W line 1 1 1 Address Bus # Op Code Address Op Code Address + 1 Address Bus FFFF Op Code Address Op Code Address + 1 Address Bus FFFF Subroutine Starting Address Stack Pointer Stack Pointer . CMP 1 SSC 2 SUBO (+2) · : AODD (+2) 3 4 LSR AND BIT 5 ROR LOA 6 ASR / ~ STA 7 STA EOR ASL ROL ADC 8 9 DEC ORA A INC TST --.1 • Summary of Undefined Instruction Operations Data Bus Op Code Branch Offset Low Byte of Restart Vector 1 1 1 1 0 0 Op Code Branch Offset Low Byte of Restart Vector Op Code of Next Instruction Return Address (Low Order Byte) Return Address (High Order Byte) When the op codes (4E. SE) are used to execute. (+1) JSR (+2) . ADD CPX (+2) 3/6 2/2 LOS (+1) 2/4 · LOX (+1) 3/4 2/2 2/3 ) indicate that the number in parenthesis must be added to the cycle count for that instruction. --- JMP (-3) CLR 1/2 2/6 .

. I\) 0) *SCI = TlE·TORE + RIE·(RORF + ORFE) Vector-.. PC Figure 16 Interrupt Flowchart NMI FFFC FFFO Non-Maskable Interrupt SWI IRQ J ICF OCF TOF SCI FFFA FFFB FFF8 FFF9 FFF6 FFF7 FFF4 FFF5 j FFF2 FFF3 FFFO FFFl : Software Interrupt Maskable Interrupt Request 1 Input Capture Interrupt Output Compare Interrupt Timer Overflow Interrupt i SCI Interrupt (TORE + RORF + ORFE) ...:z: c G» CD o W :z: c G» CD o W I .

------------------------------------------------HD8803. HD8803-1 Address Bus Data Bus Figure 17 HD6803 MPU Expanded Multiplexed Bus 127 .

A. NUM A.. C C. ROM. RAM and I/O Compatible with MC6805P2 1 INT A7 Vee A. P. B. A. It is designed for the user who needs an economical microcomputer with the proven capabilities of the HD 6800-based instruction set. B.. I/O C. 8 Lines LED Compatible (DP-28) • PIN ARRANGEMENT Vss On-Chip Clock Circuit Self-Check Mode Master Reset Low Voltage Inhibit Complete Development System. B. A. CPU Stack 5 Pointer SP Program Count.-t :: I/O B. XTAL As EXTAL A.r Ao A. Li .r "High" PCH Program Counter "Low" PCL 1100.. lines A.a Oir Reg 5 Data Dir Condition Code Regilter CC Port I Reg I. RAM. Li . The following are some of the hardware and software highlights of the M CU.External and Timer 20 TTL/CMOS Compatible I/O Lines. B. B.8 ROM Self check ROM 128 ALU Co Port C. (Top View) • BLOCK DIAGRAM Accumulator A CPU Control Inde. A2 TIMER HD6805S1 Co C. on-chip clock. Reg Regist.. A. . Support by Evaluation kit • • • • • 5 Vdc Single Supply Compatible with MC6805P2 SOFTWARE FEATURES Similar to HD6800 Byte Efficient Instruction Set • • • • • • • • • • • Easy to Program True Bit Manipulation Bit Test and Branch Instructions Versatile Interrupt Handing Powerful Indexed Addressing for Tables Full Set of Conditional Branches Memory Usable as Registers/Flags Single I nstruction Memory Examine/Change TIMER 10 Powerful Addressing Modes All Addressing Modes Apply to ROM. Ao C2 B7 C3 Bo B. Port A Port A Reg Da. B. B.. • • • • • • • • • • • • • HD6805S1P HARDWARE FEATURES 8-Bit Architecture 64 Bytes of RAM ~emory Mapped I/O 1100 Bytes of User ROM Internal 8-Bit Timer with 7-Bit Prescaler Vectored Interrupts . I/O and timer.HD6805S1 MCU (Microcomputer Unit) The HD680SS1 is the 8-bit Microcomputer Unit (MCU) which contains a CPU.. I/O A.

) Item Input "High" Voltage Symbol min typ - Vee V INT 3. = 2.0 -0.0 Power Dissipation INT Vin =O.0 0.25V ± O.0 V -0.A -1200 - 50 p. Ta=G-+70°C.4 - Cycle Time 1.A -20 IlL V - TIMER Input Leak Current V -50 • AC CHARACTERISTICS (Vcc=5. unless otherwise noted.3 .0 MHz INT Pulse Width tlWL - - ns RES Pulse Width tRWL tcye+ 250 t eye + 250 - - ns TIMER Pulse Width tTWL t eye + 250 - - ns - - 100 ms 100 - - ms - 25 - 6 35 10 pF pF Oscillation Start-up Time (Crystal Mode) Delay Time Reset Input Capacitance l I EXTAL All Other Rep =15.5V.3 - 0. Vss=GND.0 All Other Input "High" Voltage Timer Test Condition RES XT AL(Crystal Mode) All Other V IL -0.3-+7.8 V V V IH Timer Mode Self-Check Mode RES INT Input "Low" Voltage max Unit 4.0 MHz . Rs =60n max.5V.25V ± O.+7.0 - Vee V 2.8 Low Voltage Recover Po LVR - 400 700 4.0 Vee 11.2 p. If these conditions are exceeded. Normal operation should be under recommended operating conditions. Vss=GND.0 9. Ta=O .+70°C.3 -0.55-+150 °c With respect to (NOTE) Vss (SYSTEM GND) Permanent LSI damage may occur if maximum ratings are exceeded.0 V Operating Temperature Top' o -+70 °c Storage Temperature T stg .) Item Symbol Test Condition min typ max Unit Clock Frequency fel 0.3 -+12.4V-V ee XT AL(Crystal Mode) V V V mW V V - 20 p.F Cin Vin=OV tose 129 4. it could affect reliability of LSI. unless otherwise noted.7 - 4. External Cap.8 0.A 0 p.75 Low Voltage Inhibit LVI - 4.0 - 10 p.3 - Vee 2.0 V -0.6 - 0.0H2±1% tRHL CL=22pF±20%.--------------------------------------------------------HD6806S1 • ABSOLUTE MAXIMUM RATINGS Vee * Input Voltage (EXCEPT TIMER) V ln * Input Voltage (TIMER) • Unit Value Symbol Item Supply Voltage -0.3 -0.s Oscillation Frequency (External Resister Mode) teye f EXT 2. • ELECTRICAL CHARACTERISTICS • DC CHARACTERISTICS (Vcc=5.

) typ max Unit Symbol Test Condition min Item IOH = -10.5V. B.. VCC is +5. Vi 30 pF 40pF 24 kn.. (Port B) - - V V V V V 0.5 IOH = -100.5 V.4 V 0. e3 ) These 20 lines are arranged into tow 8-bit ports (A and B) and one 4-bit port (C). C Yin = 0.HD6806S1-------------------------------------------------------• PORT ELECTRICAL CHARACTERISTICS (Vee = 5. Ta = 0"" +70°C unless otherwise noted. • INT This pin provides the capability for applying an external interrupt to the MCU Refer to INTERRUPTS for additional information • XTAl and EXTAl These pins provide control input for the on-chip clock circuit.. Refer to INPUTS/OUTPUTS for additional information.6 mA Test Point Test Point 2. Figure 1 Bus Timing Test loads • SIGNAL DESCRIPTION • The input and output signals for the MCU shown in PIN ARRANGEMENT are described in the following paragraphs.uA 2..uA 20 .4 Port A and C IOL = 1.. • Vee andVss Power is supplied to the MCU using these two pins. • Input/Output lines (Ao '" A" Bo .uA 2. 4 MHz maximum) or a resistor can be connected to these pins to provide the internal oscillator with varying degrees of stability.4kn. 2.8V -500 Yin = 2V -300 Yin = 0. Refer to INTERNAL OSCILLATOR OPTIONS for recommendations about these inputs. Refer to RESETS for additional information. Co . .0 V Vee V 0.2kn.2 mA VOL IOL = 10mA VIH 2.. A crystal (AT cut. This pin allows an external input to be used to decrement the internal timer circuitry.5 Port C IOH . (Port A and C) 1.4 IOH = -1 mA 1. Refer to TIMER for additional information about the timer circuitry.uA 3. -100.... Load capacitance includes the floating capacitance of the probe and the jig etc. 130 TIMER • RES • NUM This pin allows resetting of the MCU at times other than the automatic resetting capability already in the MCU.uA .0 Port A.uA TTL Equiv. . VSS is the ground connection..3 VIL Port A Input Leak Current - IlL Port B. Ii = 1. Vss = GND. All diodes are 152074 (8) or equivalent.4 IOH = -200.20 TTL Equiv.25 V ±O.8 V ..6 mA Port A Output "High" Voltage Output "low" Voltage Port B Port B Input "High" Voltage Input "low" Voltage VO H - IOL = 3. This pin is not for user application and should be connected to ground. All lines are programmable as either inputs or outputs under software control of the data direction registers.25V ± 0.uA 2. B. (NOTE) 1. C -0.4 V 1.4V '" Vee .

5 4 Register Program Counter 1 .°..°1 Accumulator A 1...1___s_p___I Stack Pointer n"+5 ' ' Condition Code Register Push • For subroutine calls....._ _ _ _ _ _PC _ _ _ _ _ _ _... This ensures that the program counter is loaded correctly as the stack pointer increments when it pulls data from the stack: A subroutine call will cause only the program counter (PCH... then the high o 7 000 7 $00o I/O Ports Timer RAM (128 Bytes) 127 128 255 ! 256 $0 F $10o Not Used ROM (704 Bytes) 959 960 $3B F $3C o $783 $7 84 Self Check ROM (116 Bytes) 2039 2040 2 3 0 $000 1 Port B $001 1 1 1 1 I $002 Port C 3 Not Used 4 Port A DDR $004* 5 Port B DDR $005* I $006* Not Used 6 Main ROM (964 Bytes) 1923 1924 o 4 Port A 2 $07 F Page Zero ROM (128 Bytes) 5 6 0 $003 Port C DDR 7 Not Used 8 Timer Data Reg $008 9 Timer CTR L Reg $009 $007 0 $OOA Not Used (54 Bytes) $7F 7 $7F 8 Interrupt Vectors ROM (8 Bytes) 63 6 ~ t 12 $7F F 2047 $03F $040 RAM (64 Bytes) Stack $07F *Write only registers Figure 2 MCU Memory Configuration 7 n-4 6 1 5 1 4 3 7 2 Condition 11 Code Register Accumu lator n-3 ° . ..... .°.---------------------------------------------------------HD6805S1 • order three bits (PCH) are stacked. the low order byte (PCL) of the program counter is stacked first...1... the contents of the MCU registers are pushed onto the stack in the order shown in Figure 3. MEMORY The MCU memory is configured as shown in Figure 2..1_.________ Pull n+1 7 n+2 I ° L..1.1_1. only PCH and PCl are stacked Carry/Borrow Figure 3 Interrupt Stacking Order Zero Negative Interrupt Mask Half Carry Figure 4 Programming Model 131 .. DUring the processing of an interrupt........ Since the stack pointer decrements during pushes.llndex 10 n-2 n-1 n Index Register 1 1 1 1 11 PCl* PCH* n+3 I n+4 10 °I ° L. PeL) contents to be pushed onto the stack.°--'-'_°.._ _ _ _ X_ _ _ _......

-. • Zero (Z) Used to indicate that the result of the last arithmetic. When the timer reaches zero the timer interrupt request bit (bit 7) in the timer control register is set..:-. fetching the timer interrupt vector from locations $7F8 and $7F9 and executing the interrupt routine. the index register can be used as a temporary storage area. Stack Pointer (SP) The stack pointer is an 11·bit register that contains the address of the next free location on the stack. The index register can also be used for limited calculations and data manipulations when using read/modify/write instructions. • TIMER The MeU timer circuitry is shown in Figure 5. Subroutines and interrupts may be nested down to location $061 which allows the programmer to use up to 15 levels of subroutine calls. • Accumulator (A) The accumulator is a general purpose 8·bit register used to hold operands and results of arithmetic calculations or data manipulations. IL _____ . During a MeV reset or the reset stack pointer (RSP) instruction. The interrupt bit (l bit) in the condition code register will also prevent a timer interrupt from being processed. • Negative (N) Used to indicate that the result of the last arithmetic... The 8·bit counter is loaded under program control and counts down toward zero as soon as the clock input is applied. If an interrupt occurs while this bit is set it is latched and will be processed as soon as the interrupt bit is reset. Time Out Timer t----=!!Oot-~-6-~ Interrupt Req... The timer interrupt can be masked by setting the timer interrupt mask bit (bit 6) in the timer control register.2 signal is used as the source it can be gated by an input applied to the TIMER input pin allowing the user to easily perform pulse-width measurements. Initially. • Program Counter (PC) The program counter is an 11·bit register that contains the address of the next instruction to be executed. ...logica1 or data manipulation was negative (bit 7 in result equal to a logical one).. Condition Code Register (CC) The condition code register is a 5·bit register in which each bit is used to indicate or flag the results of the instruction just executed. and rotates.HD8806S1-------------------------------------------------------• • REGISTERS The MeU has five registers available to the programmer. The clock input to the timer can be from an external source applied to the TIMER input pin or it can be the internal q.Interrupt Mask N o Write Read T U Timer Control Register S E o o Figure 5 Timer Block Diagram 132 . This bit is also affected during bit test and branch instructions. • Index Register (X) The index register is an 8·bit register used for the indexed addressing mode.. The MeU responds to this interrupt by saving the present MeU state in the stack. They are shown in Figure 4 and are explained in the following paragraphs. the stack pointer is set to location $07F and is decremented as data is being pushed onto the stack and incremented as data is being pulled from the stack. The six most significant bits of the stack pointer are permanently set to 000011.JI• Manufacturing Mask Options 7 . • Half Carry (H) Used during arithmetic operations (ADD and ADC) to indicate that a carry occurred between bits 3 and 4. Timer t-~. Each individual condition code register bit is explained in the following paragraphs. • I I . Note that when the q.2 signal. . It contains an 8·bit address that may be added to an offset value to create an effective address. When not required by a code sequence being executed. The <1>2 (Internal) Timer Input Pin r-----.. • Carry/Borrow (C) Used to indicate that a carry or borrow out of the arithmetic logic unit (ALU) occurred during the last arithmetic operation. shifts. the stack pointer is set to location $07F. These bits can be individually tested by a program and specific action taken as a result of their state. • • I nterrupt (I) This bit is set to mask the timer and external interrupt (INT).logical or data manipulation was zero.

This time allows the internal crystal oscillator to stabilize. Bo 12 3 Vss = Pin 1 * Refer to Figure 9 about crystal option Figure 6 Self Check Connections 5V -------------~-------__. Connecting a capacitor to the RES input as shown in Figure 8 will provide sufficient delay. This prescaling option must also be specified before manufacturing begins.2~F A4 24 A2 22 +9V B6 18 Vee Bs 17 B4 16 Vee = Pin 8 Co 9 B. Vee LVR OV---------J RES Pin ---------------r Internal Reset Figure 7 Power Up and RES Timing 133 . This allows a program to determine the length of time since a timer interrupt has occured and not disturb the counting process.. All the I/O port are initialized to Input mode (DDR's are cleared) during RESET.---------------------------------------------------------HD6806S1 source of the clock input is one of the options that has to be specified before manufacture of the MCV. the timer interrupt request bit (bit 7) is cleared and the timer interrupt request mask bit (bit 6) is set. Connect the MCV as shown in Figure 6 and monitor the output of port C bit 3 for an oscillation of approximately three hertz . a minimum of 100 milliseconds is needed before allowing the reset input to go "High" . B2 14 10 C2 B. (mask option) see Figure 7. 15 C. 27 INT A6 26 28 RES As 25 4 XTAL A. 2 • SELF CHECK The self check capability of the MCV provides an internal check to determine if the part is functional. 19 6 NUM :c 2. A prescaler option can be applied to the clock input that extends the timing interval up to a maximum of 128 counts before being applied to the counter. Vpon power up. The timer continues to count past zero and its present count can be monitored at any time by monitoring the timer data register. by the external reset input (RES) and by an internal low voltage detect circuit. At power up or reset the prescaler and counter are initiallied with all logical ones. A. 21 7 TIMER Ao 20 HD6805S1 (Register optioni B. 13 11 C. • RESETS The MCV can be reset three ways: by initial powerup. 23 5 EXTAL A.

25V TA = 25°C - ~ 45 50 . The use of a crystal (AT cut. Crystal specifications are given in Figure 10. The different connection methods are shown in Figure 9.:. f = 4 MHz IC. =22pF±20%1 Rs = 60n max.2/ol F Part of HD6805S1 MCU Figure 8 Power Up Reset Delay Circuit P EXTAL 5 EXTAL 4~a~Z CJ HD6805S1 MCU 4 XTAL HD6805S1 MCU 4 XTAL 22PF±20%I Approximately 25% Accuracy External: Jumper 5 EXTAL 5 EXTAL External Clock Input - R 4 XTAL HD6805S1 MCU XTAL 4 HD6805S1 MCU No Connection External Clock Approximately 15% Accuracy External Resistor CRYSTAL OPTIONS RESISTOR OPTIONS Figure 9 Internal Osci lIator Options 5 ~~ XTAL~~EXTAL 4 ~f-----J \ N J: ~ 5 >u I [\ 4 3 ~ \ c: \II . A resistor selection graph is given in Figure 11.Cut Parallel Resonance Crystal Co = 7 pF max. E LL 2 ~ ~ ~ . 4 MHz max) or a resistor is sufficient to drive the internal oscillator with varying degrees of stability.HD6806S1-----------------------------------------------------• INTERNAL OSCILLATOR OPTIONS 220 kn The internal oscillator· circuit has been designed to require a minimum of external components. Vee--~AJ\~--~--~ r 2 . ~ Figure 10 Crystal Parameters o 5 10 15 20 25 30 Resistance Iknl 35 40 Figure 11 Typical Resistor Selection Graph 134 J. Vee = 5. C" AT . A manufacturing mask option is available to provide better matching between the external components and the internal oscillator.

----------------------------------------------------------HD6805S1 1-+1 7F -+SP o -+DDR's Stack PC. A. CC CLR INT Logic FF -+Timer 7F -+ Prescaler 7F -+ TCR TIMER Load PC From Reset: 7FE: 7FF Load PC From SWI: 7FC. X. 7FD mT':7FA.7FB TIMER: 7F8. 7F9 Fetch Instruction SWI Y Execute Instruction Figure 12 Interrupt Processing Flowchart Output Data Bit 1/0 Pin Data Direction Register Bit Output Data Bit Output State Input to MCU 0 0 0 x 3·State Pin 1 0 Figure 13 Typical Port I/O Circuitry 135 .

When any interrupt occurs. and the vector address that contain-the starting address of the appropriate interrupt routine.. BCLR). the internal timer interrupt request. Ic) Figure 14 Typical Port Connections 136 . Ib) +V +V R Port B ··•· ·• - Port C 10mA max ·••• ·••• t . When port B is programmed for outputs. The interrupt service routines normally end with a return from interrupt (RTI) instruction which allows the MCV to resume processing of the program prior to the interrupt. All pins are programmable as either inputs or outputs under software control of the data direction registers. The timer could also be incorporated to provide turn-on at some later time which would permit pulse-width modulation of the controlled power. This program... and the program branches as a result of its state. the present MCU state is pushed onto the stack.HD8806S1-------------------------------------------------------• • INTERRUPTS • Priority Vector Address RES SWI INT TIMER 1 2 $7FE and $7FF $7FC and $7FD $7FA and $7FB $7F8 and $7F9 3 4 BIT MANIPULATION The MCU has the ability to set or clear any single random access memory or input/output bit (except the data direction registers) with a single instruction (BSET. Assume that bit 0 of port A is connected to a zero crossing detector circuit and that bit 1 of port A is connected to the trigger of a TRIAC which powers the controlled hardware. A flowchart of the interrupt processing sequence is given in Figure 12.. Port A Programmed as outputls) driving CMOS and TTL Load directlv. When programmed as outputs. The example in Figure 15 illustrates the usefulness of the bit manipulation and test instructions. Table 1 Interrupt Priorities Interrupt INPUT/OUTPUT There are 20 input/output pins. Any bit in the page zero read only memory can be tested. CMOS Inverter C3 B. and a software interrupt instruction (SWI).-.. Port CProgrammed as outputls) driving CMOS using external pull-up resistors. Ao ··• ·•• Port A Port B • ··•• ·· B. their priority... using the BRSET and BRCLR instructions. A. Table 1 provides a listing of the interrupts. processing is suspended. All input/output lines are TTL compatible as both inputs and outputs. Figure 14 provides some examples of port connections. provides tum-on of the TRIAC within 14 microseconds of the zero crossing. all I/O pins read latched output data regardless of the logic level at the output pin due to output loading (see Figure 13). ROM or I/O allows the user to have individual flags in RAM or to handle single I/O bits as control lines. which uses only seven ROM locations. Port A lines are CMOS compatible as outputs while port B and Clines are CMOS compatible as inputs. The MeU can be inte[fNJI)ed three different ways: through the external interrupt input pin. the interrupt bit (I) in the condition code register is set. and the interrupt routine is executed. la) Port B Programmed as outputls) driving Darlington base directly. it is capable of sinking 10 millamperes on each pin (VOL = 1V max). Id) Port B Programmed as outputls) driving LED Is) directly. This capability to work with any bit in RAM. the address of the interrupt routine is obtained from the appropriate interrupt vector address.

• Implied Refer to Figure 25. and write the modified value back to memory or to the register. • Immediate Refer to Figure 16.somewhere within the range of +129 bytes to -127 of the present instruction. Refer to Table 3. Such instructions are two bytes long. The implied mode of addressing has no EA. The other operand is obtained from memory using one of the addressing modes. Refer to Table 2. Refer to Table 5. Direct addressing allows the user to directly address the lowest 256 bytes in memory. Thus. The effective address (EA) is the PC and the operand is fetched from the byte following the opcode. SELF 1 BSET 1. One group either sets or clears. . • Read/Modity!Write Instructions These instructions read a memory location or a register. the address of the operand is contained in the second byte of the instruction. 137 Refer to Figure 23. • Bit Manipulation Instructions These instructions are used on any bit in the first 256 bytes of the memory. Extended addressing is used to reference any location in memory space. when a branch takes place. This addressing mode calculates the EA by adding the contents of the two bytes following the opcode to the index register. The value of the bit tested is written to the carry bit in the condition code register. and control. One operand is either the accumulator or the index register. The immediate addressing mode accesses constants which do not change during program execution. ReI is the contents of the location following the instruction opcode with bit 7 being the Sign bit. Refer to Table 4. • Register/Memory Instructions Most of these instructions use two operands. EA=(pc)+2+Rel. The test for negative or zero (TST) instruction is an exception to the read/modify/write instructions since it does not perform the write. the program goes to . 511 low memory locations are accessable. They can be divided into five different types: register/memory. The EA is calculated by adding the contents of the byte following the opcode to the contents of the index register. • INSTRUCTION SET The MCU has a set of 59 basic instructions. • Indexed (No Offset) Refer to Figure 20. All the instructions within a given type are presented in individual tables. • Control Instructions The control instructions control the MCU operations during program execution. • Alphabetical Listing The complete instruction set is given in alphabetical order in Table 7. These instructions are three bytes long. All implied addressing instructions are one byte long. • Opcode Map Table 8 is an opcode map for the instructions used on the MCU.--------------------------------------------------------HD8806S1 SELF 1 ·•• ··· • Bit Set/Clear BRCLR 0. control instructions such as SWI. modify or test its contents. • Bit Test and Branch Refer to Figure 24. The EA is the contents of the two bytes following the opcode. In this mode. All the information necessary to execute an instruction is contained in the opcode. I/O registers and 128 bytes of ROM are located in page zero to take advantage of this efficient memory addressing mode. • Extended Refer to Figure 18. In this mode the contents of the byte following the opcode is added to the program counter when the branch is taken. bit manipulation. This mode of addressing applies to instructions which can set or clear any bit on page zero. All RAM space. branch. Direct operations on the accumulator and the index register are included in this mode of addressing. In direct addressing. • Direct Refer to Figure 17. PORT A. The relative addressing mode applies only to the branch instructions. The other group performs the bit test and branch operations. The following paragraphs briefly explain each type. These instructions occupy two bytes. They are explained and illustrated briefly in the following paragraphs. RTI belong to this group. This mode of addressing accesses the lowest 256 bytes of memory. The jump unconditional (JMP) and jump to subroutine (JSR) instructions have no register operand. • Indexed (8-bit Offset) Refer to Figure 21. The third byte is the relative address to be added to the program counter if the branch condition is met. PORT A BCLR 1. • Indexed (16-bit Offset) Refer to Figure 22. Refer to Table 6. • Relative Refer to Figure 19. • Branch Instructions The branch instructions cause a branch from the program when a certain condition is met. This mode of addressing applies to instructions which can test any bit in the first 256 locations ($OO-$FF) and branch to any location relative to the PC. If the branch is not taken Rel=O. Instructions which use this addressing mode are three bytes long. PORT A ·•• · Figure 15 Bit Manipulation Example • ADDRESSING MODES The MCU has ten addressing modes available for use by the programmer. read/modify/ write. The individual bit within that byte to be tested is addressed by the lower three bits of the opcode. Extended addressing instructions are three bytes long. The byte to be tested is addressed by the byte following the opcode. the entire memory space may be accessed. In addition. These instructions are one byte long and their EA is the contents of the index register. The lower three bits in the opcode specify the bit to be set or cleared while the byte following the opcode specifies the address in page zero. These instructions are two bytes long.

HD8806S1-------------------------------------------------------EA Memory i I I I I ~ A F8 Index eo I Stack Point I PROG LOA #$F8 05BE 05BF Prog Count A6 1-------4 05CO F8 CC I I § I I I Figure 16 Immediate Addressing Example I i •• I I I I I I I • CAT FCB 32 LOA CAT I OO4B /' Adder '" ol • I PROG I 20 OO4B . Figure 17 Direct Addressing Example 138 I . lEA + Memory 0520 B6 052E 4B A J I I Stack Point I I 052F CC § • I • I I I I I 1 I I Prog Count I I 20 Index Reg • • .

Memory I I I I ~ I PROG LOA CAT ~~ J O4OA 06 040B E5 64 40 Index Reg Stack Point I t FCB A I Prog Count I I CAT 0000 06E5 040C 40 CC Figure 18 Extended Addressing Example Memory i I § A Index Reg Stack Point I I PROG BEQ PROG2 04A 7 1-_ _ _2_7_ _-I 04A8 0000 18 04C1 §@ .--------------------------------------------------------HD8806S1 . Figure 19 Relative Addressing Example 139 .I I.

I I Prog Count I. X 075B E6 075C 89 I I I I § I.HD8806S1--------------------------------------------------------- EA OOB8 Memory A TABL FCC t Lit OOB8 4C 4C 49 Index Reg B8 I PROG LOA X I Stack Point 05F4~ Prog Count 05F5 CC § Figure 20 Indexed (No Offset) Addressing Example JEA Melory i i I I FCB #BF 0089 BF FCB #86 008A 86 FCB #DB 008B DB FCB #CF 008C CF /' Adder J t I • i I PROG 008C I I TABL I '" _. Figure 21 Indexed (8·Bit Offset) Addressing Example 140 075E CC I .A l CF J Index Reg I I 03 I Stack Point LOA TABL.

Memory I ~ I PROG LOA TABL. PORT B 058F J-_ _ _ 10 _ _--I 0590 Stack Point 01 Prog Count 0591 I I CC § I I . X 0692 0693 A DB Index Reg I 02 ~6 Stack Point 07 ~---~ 7E 0694 Prog Count 0695 I TABL CC I BF FCB #BF 077E FCB #86 077F 86 FCB #OB 0780 DB FCB #CF 0781 CF Figure 22 Indexed (16-Bit Offset) Addressing Example Memory PORTB Eau BF 0001 A 0000 Index Reg PROG BCLR 6. I Figure 23 Bit Set/Clear Addressing Example 141 .--------------------------------------------------------HD8806S1 .

. PROG 2 0574 0575 0576 . PORT C.. 0594 cc c Figure 24 Bit Test and Branch Addressing Example Memory i I I I § A E5 Index Reg I E5 I PROG TAX O~A~ Prog Count 05BB cc I I § Figure 25 Implied Addressing Example 142 ..HD8806S1--------------------------------------------------------- PORT C eau 0002 2 FO Index Reg 0000 Stack Point PROG BRCLR 2.. 05 Prog Count ----~ 0000 02 ----~ 10 .....

--------------------------------------------------------HD8806S1 Table 2 Register/Memory Instructions Addressing Modes Function Mnemonic Op Op Op # # # # Code Bytes CVetes Code Bytes Cycles Code Indexed (8·Bit Offset) Indexed (No Offset) Extended Direct Immediate Op # # Bytes Cycles Code Op # # Bytes Cycles Code Indexed (l6-Bit Offset) Op # # Bytes Cycles Code # # Bytes Cycles Load A from Memory LOA A6 2 2 B6 2 4 C6 3 5 F6 1 4 E6 2 5 06 3 6 Load X from Memory LOX AE 2 2 BE 2 4 CE 3 5 FE 1 4 EE 2 5 DE 3 6 Store A in Memory STA - 2 5 C7 3 6 F7 1 5 E7 2 6 07 3 7 STX - 87 Store X in Memory - BF 2 5 CF 3 6 FF 1 5 EF 2 6 OF 3 7 Add Mllmory to A ADD AB 2 2 BB 2 4 CB 3 5 FB 1 4 EB 2 5 DB 3 6 Add Memory and Carry to A AOC A9 2 2 B9 2 4 C9 3 5 F9 1 4 E9 2 5 09 3 6 5 FO 1 4 EO 2 5 DO 3 6 4 CO 3 2 4 C2 3 5 F2 1 4 E2 2 5 02 3 6 2 4 C4 3 5 F4 1 4 E4 2 5 04 3 6 BA 2 4 CA 3 5 FA 1 4 EA 2 5 OA 3 6 2 B8 2 4 C8 3 5 F8 1 4 E8 2 5 08 3 6 2 2 B1 2 4 C1 3 5 F1 1 4 E1 2 5 01 3 6 A3 2 2 B3 2 4 C3 3 5 F3 1 4 E3 2 5 03 3 6 BIT A5 2 2 B5 2 4 C5 3 5 F5 1 4 E5 2 5 05 3 6 Jump Unconditional JMP - BC 2 3 CC 3 1 3 EC 2 4 DC 3 5 JSR - FC Jump to Subroutine - 4 - BO 2 7 CD 3 8 FO 1 7 ED 2 8 DO 3 9 Subtract Memory Subtract Memory from A with Borrow AND Memory to A OR Memory with A EXClusive OR Memory with A Arithmetic Compare A with Memory Arithmetic Compare X with Memory Bit Test Memory with A (Logical Compare) 2 BO 2 2 2 B2 2 2 B4 AA 2 2 EOR A8 2 CMP A1 CPX SUB AO 2 SBC A2 AND A4 ORA Table 3 Read/ModifyIWrite Instructions Addressing Modes Function Implied (A) Mnemonic Op Code Implied (X) Op # # Bytes Cycles Code Indexed (No Offset) Direct Op # # Bytes Cycles Code Op # # Bytes Cycles Code Indexed (8·Bit Offset) Op # # Bytes Cycles Code # # Bytes Cycles Increment INC 4C 1 4 5C 1 4 3C 2 6 7C 1 6 6C 2 7 Decrement DEC 4A 1 4 5A 1 4 3A 2 6 7A 1 6 6A 2 7 Clear CLR 4F 1 4 5F 1 4 3F 2 6 7F 1 6 6F 2 7 Complement COM 43 1 4 53 1 4 33 2 6 73 1 6 63 2 7 Negate (2's Complement) NEG 40 1 4 50 1 4 30 2 6 70 1 6 60 2 7 Rotate Left Thru Carry ROL 49 1 4 59 1 4 39 2 6 79 1 6 69 2 7 Rotate Right Thru Carry ROR 46 1 4 56 1 4 36 2 6 76 1 6 66 2 7 Logical Shift Left LSL 48 1 4 58 1 4 38 2 6 78 1 6 68 2 7 Logical Shift Right LSR 44 1 4 54 1 4 34 2 6 74 1 6 64 2 7 Arithmetic Shift Right ASR 47 1 4 57 1 4 37 2 6 77 1 6 67 2 7 Arithmetic Shift Left ASL 48 1 4 58 1 4 38 2 6 78 1 6 68 2 7 Test for Negative or Zero TST 40 1 4 50 1 4 3D 2 6 70 1 6 60 2 7 143 .

.. 7) 11+2 n 2 7 - - - 0 0 0 0 - Table 6 Control Instructions Implied Function Mnemonic Op Code # # Bytes Cycles 2 Transfer A to X TAX 97 1 Transfer X to A TXA 9F 1 2 Set Carry Bit SEC 99 1 2 Clear Carry Bit ClC 98 1 2 Set Interrupt Mask Bit SEI 9B 1 2 Clear Interrupt Mask Bit CLI 9A 1 2 Software Interrupt SWI 83 1 11 Return from Subroutine RTS 81 1 6 Return from Interrupt RTI 80 1 9 Reset Stack Pointer RSP 9C 1 2 No-Operation NOP 90 1 2 144 ..HD8806S1-------------------------------------------------------Table 4 Branch Instructions Relative Addressini Mode Function Mnemonic Op Code # # Bytes Cycles 4 Branch Always BRA 20 2 Branch Never BRN 21 2 4 Branch IF Higher BHI 22 2 4 Branch I F lower or Same BlS 23 2 4 Branch I F Carry Clear BCC 24 2 4 4 (Branch IF Higher or Same) (BHS) 24 2 Branch I F Carry Set BCS 25 2 4 (Branch IF lower) (BlO) 25 2 4 4 Branch I F Not Equal BNE 26 2 Branch I F Equal BEQ 27 2 4 Branch I F Half Carry Clear BHCC 28 2 4 Branch I F Half Carry Set BHCS 29 2 4 Branch IF Plus BPl 2A 2 4 Branch I F Minus BMI 2B 2 4 Branch IF Interrupt Mask Bit is Clear BMC 2C 2 4 Branch IF Interrupt Mask Bit is Set BMS 20 2 4 Branch IF Interrupt Line is low Bil 2E 2 4 Branch IF Interrupt Line is High BIH 2F 2 4 Branch to Subroutine BSR AD 2 8 Table 5 Bit Manipulation Instructions Addressing Modes Function Mnemonic Bit Set/Clear Op Code Bit Test and Branch # # 8ytes # # Cycles Op Code Bytes Cycles Branch IF Bit n is set BRSET n (n=O . 7) - - 3 10 BRClR n(n=O ....• 7) 10+2 n 2 7 - Clear bit n BClR n (n=O ..... 7) - - - 2 n Branch I F Bit n is clear 01+2 n 3 10 Set Bit n BSET n (n=O ......

Cleared Otherwise Not Affected 145 .---------------------------------------------------------HD6805S1 Table 7 Instruction Set Mnemonic Implied ADC ADD AND ASL ASR BCC BClR BCS BEQ BHCC BHCS BHI BHS BIH Bil BIT BlO BlS BMC BMI BMS BNE BPl BRA BRN BRClR BRSET BSET BSR ClC CLI ClR CMP COM CPX DEC EOR INC JMP JSR lOA lOX Immediate x x x x x Direct x x x x x Extended Relative x x x Addressing Modes Indexed Indexed Indexed (No (8 Bits) (16 Bits) Offset) x x x x x x x x x x x x x Condition Code Bit Setl Clear Bit Test & Branch 1\ 1\ x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Condition Code Symbols: H Half Carry (From Bit 3) I Interrupt Mask N Negative (Sign Bit) Z Zero x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x H x x x x x x x • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • I N Z • 1\ 1\ 1\ 1\ 1\ 1\ 1\ 1\ 1\ • 1\ 1\ 1\ 1\ 1\ • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 1\ • • • • • • • • • • • • • • • • • • • • 1\ • 1\ • • • • • 0 • • 1 • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 0 • • • • • • • • • • • 1\ • • • • • • • • • • • • • • • C 0 1\ 1\ 1\ 1\ 1 1\ 1\ 1\ 1\ • • 1\ 1\ • • • • • • • 1\ 1\ • 1\ 1\ • 1\ 1\ 1\ 1\ (to be continued) C 1\ • Carry Borrow Test and Set if True.

Cleared Otherwise Not Affected Load CC Register From Stack 146 I N Z C • 1\ 1\ 1\ • 0 1\ 1\ • 1\ 1\ 1\ • • • • • 1\ 1\ • • 1\ 1\ 1\ • 1\ 1\ 1\ • • • • ? ? ? ? • • • • • 1\ 1\ 1\ • • • 1 1 • • • • 1\ 1\ • • 1\ 1\ • • 1\ 1\ 1\ 1 • • • • • • • • 1\ 1\ • • • • • .HD8806S1-----------------------------------------------------Table 7 Instruction Set Addressing Modes Mnemonic LSL LSR NEG NOP ORA ROL ROR RSP RTI RTS SBC SEC SEI STA STX SUB SWI TAX TST TXA Implied Immediate x x x x Zero Extended Relative x x x x x x x x x x x x x x x x x x x Bit Set/ Clear x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Condition Code Symbols: H Half Carry (From Bit 3) I I nterrupt Mask N Negative (Sign Bit) Z Direct Condition Code Indexed Indexed Indexed (No (8 Bits) (16 Bits) Offset) x x x x x x x x x Bit Test & Branch H • • • • • • • • ? • • • • • • • • • • • C 1\ • ? Carry/Borrow Test and Set if True.

.XO I C I 0 I E I F . HIGH RTI* - RTS* - CMP 1 - SBC 2 - CPX 3 L AND 4 o BIT 5 W LOA 6 SWI* - SUB - 0 - TAX ROL - SEC DEC - CLI SEI ADD B JMP(-1) C JSR(-3) 0 E CLR 2/6 IMP - 4 3/10 .---------------------------------------------------------HD6805S1 Table 8 Bit Manipulation Test & Branch Set/ Clear Rei olR 3 I I A 4 I I X 5 0 1 2 BSETO BRA NEG 1 BRCLRO BCLRO BRN - BRSET1 BSET1 BHI - 2 I I 3 BRCLR1 BCLR1 BLS COM BRSET2 BSET2 BCC LSR 5 BRCLR2 BCLR2 BCS - 6 BRSET3 BSET3 BNE ROR 7 BRCLR3 BCLR3 BEQ ASR 8 9 A B C 0 E BRSET4 BSET4 BHCC LSL/ASL BRCLR4 BCLR4 BHCS BRSET5 BSET5 BPL BRCLR5 BCLR5 BMI - BRSET6 BSET6 BMC INC BRCLR6 BCLR6 BMS TST BRSET7 BSET7 BIL - F BRCLR7 BCLR7 BIH (NOTE) 2/7 2/4 6 I . reQuire a different number of cycles as follows: RTI 9 RTS 6 SWI 11 BSR 8 3.... 2.. The number at the bottom of each column denote the number of bytes and the number of cycles reQuired (Bytes/Cycles). Undefined opcodes are marked with "-". Mnemonics followed by a .. 147 F ..XO 1 7 I 1/4 I 8 IMP IMM J olR 9 A J B I EXT I . ( indicate that the number in parenthesis must be added to the cycle count for that instruction..X1 Register /Memory Control Read/Modify /Write Branch BRSETO 0 Opcode Map 1/4 I 2/7 I 1/6 - I CLC RSP J BSR* I - - NOP - TXA - 1/* 1/2 2/2 - STA(+1) 7 EOR AoC 8 9 ORA A LOX I I STX(+1) 2/4 I 3/5 I 3/6 I 2/5 I 1/4 1.X2 I )<1 I .

. "H. C. RAM. D. AlU C. Accumuiltor A B. A.External and Timer • 24 I/O Ports + 8 Input Port (8 Lines LED Compatible. B.8 ROM D.r CC 5 Stack POint. C. C. BLOCK DIAGRAM TIMER 8. 148 . (Top View) CPU C. 8. A. C. C. c. 7 Voltage Comparator Inputs) • On·Chip Clock Circuit • Self·Check Mode • Master Reset • Low Voltage Inhibit • Complete Development System Support by Evaluation Kit • 5 Vdc Single Supply (DP·40) • • SOFTWARE FEATURES • Similar to HD6800 • Byte Efficient Instruction Set • Easy to Program • True Bit Manipulation • Bit Test and Branch Instructions • Versatile Interrupt Handing • Powerful Indexed Addressing for Tables • Full Set of Conditional Branches • Memory Usable as Registers/Flags • Single Instruction Memory Examine/Change • 10 Powerful Addressing Modes • All Addressing Modes Apply to ROM. on·chip clock. A. D. A. B. CPU ContrOl I. Bu D.HD6805U1 MCU (Microcomputer Unit) The HD6805Ul is the 8-bit Microcomputer Unit (MCU) which contains a CPU. C. Soffcllock ROM D. A. Input D. ROM. c- 5 4 B. B. Condition Port A Rot C. A. Port C 1/0 Lints "Low" PCl D. D. RAM and I/O Compatible Instruction Set with MC6805P2 • PIN ARRANGEMENT A. c. POtt B I/O Oa'i Ott RI9 Reglst. B. Sp Program Count. It is designed for the user who needs an economical microcomputer with the proven capabilities of the H06800· based instruction set. C. 8. A1 A. Port A 1/0 A. B. A. The following are some of the hardware and software high· lights of the MCU. D. B.. D. A.. Lints D. lin•• A. HD6805U1P • HARDWARE FEATURES • 8·Bit Architecture • 96 Bytes of RAM • Memory Mapped I/O • 2056 Bytes of User ROM • Internal 8-Bit Timer with 7·Bit Prescaler • Vectored Interrupts . Port 20&6. C. 8. Lines A.g/I" PCH Progrlm Count. A. I/O and timer. D. D D. • B. C. C. A.

25V ± O.4V-V ee -50 XT AL(Crystal Mode) -1200 max Unit Vee V Vee V Vee V V Vee 11.55 .3 -0.--------------------------------------------------------HD8806U1 • ABSOLUTE MAXIMUM RATINGS Value Symbol Item Supply Voltage Unit Vee * -0. unless otherwise noted.+150 °c Input Voltage (TIMER) * With respect to Vss (SYSTEM GND) (NOTE) Permanent LSI damage may occur if maximum ratings are exceeded.75 V 4. A 0 /J.+7.25V ± O. Rs =60n max.0 - -0.3 - -0.) Item Symbol Input "High" Voltage I Input "High" Voltage Timer Test Condition min typ RES 4.s 2.) Item Symbol min Test Condition Clock Frequency fel 0.3 .0 MHz t cye + 250 - - ns - - ns 4.0 0.0 V -0. it could affect reliability of LSI. = 2.0 Self·Check Mode RES INT Input "Low" Voltage - V IL 9.0 Input Voltage (EXCEPT TIMER) Yin Operating Temperature T opr o -+70 V °c Storage Temperature T stg . Vss=GND. External Cap.0 All Other V IH 2. A • AC CHARACTERISTICS (Vcc=5. • ELECTRICAL CHARACTERISTICS • DC CHARACTERISTICS (VCC=5. If these conditions are exceeded. Ta=G-+70°C.3 -+12. unless otherwise noted.A 50 /J.0 - V - 20 p. VSS=GND.8 V V 400 700 mW 4.7 - 4.4 Cycle Time teyc 1.2 /J.0 Timer Mode 2.8 V 0. Ta=O '" +70°C.3 - Low Voltage Recover Po LVR - - Low Voltage Inhibit LVI - Power Dissipation -20 TIMER INT I nput Leak Current IlL V in =0.0 Oscillation Frequency (External Resister Mode) fexT INT Pulse Width tl WL R ep =15.0 INT 3. I I EXTAL All Other Cin 149 C L=22pF±20%.':t.0kn±1 % typ max Unit 10 /J.5V.0 MHz RES Pulse Width tRWL t cye + 250 TIMER Pulse Width tTWL t eye + 250 - - ns Oscillation Start-up Time (Crystal Mode) tose - - 100 ms Delay Time Reset tRHL 100 - - ms - 25 35 - 6 10 pF pF Input Capacitance i\.8 V V 0.0 V * -0.6 0.+7. Normal operation should be under recommended operating conditions.3 XT AL(Crystal Mode) All Other -0.3.5V.F Vin=OV .

Refer to INTERNAL OSCIL- 150 • RES This pin allows resetting of the MCU at times other than the automatic resetting capability already in the MCU.2 - V VTH 0 0. (Port A and C) TTL Equiv.6 mA IOL = 3. Vss = GNO.6 rnA Test Point 30 pF 12 kfl 2. A crystal (AT cut. SIGNAL DESCRIPTION The input and output signals for the MCU shown in PIN ARRANGEMENT are described in the following paragraphs.) Port VOH a Port C Port A and C Output "Low" Voltage Input "High" Voltage Input "Low" Voltage Port VOL a Threshold Voltage * Port 0 .5V.2 rnA . • • TIMER This pin allows an external input to be used to decrement the internal timer circuitry.25V ±05V. C. Load capacitance includes the floating capacitance of tt. (Port a) Vee Ii = 3.) 1. Vee is +5 .4 - - V V V V 0.0 - Vee V V IL -0. 2.2 mA IOL = 10mA IOH Port A Output "High" Voltage Test Condition Symbol Item 20 VIH - VTH+0. Figure 1 Bus Timing Test Loads • LATOR OPTIONS for recommendations about these inputs. Ta =0"" +70°C unless otherwise noted.5 VIH Port A Input Leak Current min = -10~A IOH = -100~A IOH = -200~A IOH = -1 mA IOH = -100flA IOL = 1.8V Vin = 2V Vin = 0. • Vee and Vss Power is supplied to the MCU using these two pins.4kfl 24 kfl 1.0 V 2.4V"'" Vee Vin IlL Input "Low" Voltage max - - PortB.C.4 V - 1.8 V -500 - - ~A -300 - - ~A - - 20 ~A =0.4 V 0. Refer to TIMER for additional information about the timer circuitry.3 - 0. • NUM This pin is not for user application and should be connected to ground. 8xV ee V - as digital Input ** Port 0 as analog input TTL Equiv.i! probe and the jig etc. • XTAL and EXTAL These pins provide control input for the on-chip clock circuit.4 - - Port A. INT This pin provides the capability for applying an external interrupt to the MCU Refer to INTERRUPTS for additional information.HD8806U1-------------------------------------------------------• PORT ELECTRICAL CHARACTERISTICS (Vee = 5. Unit 2.2 - V VIL - VTH-0. Refer to RESETS for additional information.25V ± 0.5 - - - 2. 4 MHz maximum) or a resistor can be connected to these pins to provide the internal oscillator with varying degrees of stability.. Port 0** (Do"" 0 6 ) Port 0** (Do"'" 0 6 ) Port 0**(0. and 0 Input "High" Voltage typ 3. .. and 0* a. All diodes are 1S20748 or equivalent.4 V 2. V ss is the ground connection.. Test Point 40 pF (NOTE) Ii = 1.

Input/Output Lines (Ao .. then the high order four bits (PCH) are stacked.\ ROM (128 Bytes) $OF $1 255 256 Not Used Port A 1 Port B $001 2 Port C $002 3 Port D (digital) $003" 4 Port A DDR $004" 5 Port B DDR $005" 6 Port C DDR 7 2047 2048 $7F sa $000 0 $006" $007"" Port D (analog) 8 Timer Data Reg. A subroutine call will cause only the program counter (pCH.. Refer to IN· PUTS/OUTPUTS for additional information._______________________________________________________ HD6806U1 • MEMORY The MCU memory is configured as shown in Figure 2. B7 . Carry/Borrow Figure 3 Interrupt Stacking Order Zero Negative Interrupt Mask Half Carry Figure 4 Programming Model 151 .. the contents of the MCU regi· sters are pushed onto the stack in the order shown in Figure 3. by reading $003 address. by read· ing $007 address. Co .. The other function of them is 7 Voltage comparators. Since the stack pointer decrements during pushes. • • Input Lines (Do"" D7 ) These are 8~it input lines.. During the processing of an interrupt. All lines are programmable as either inputs or outputs under software control of the data direction registers. o $000 000 1/0 Ports Timer RAM (128 Bytes) $07 127 128 1. $008 9 Timer CTRL Reg. Firstly. the low order byte (PCL) of the program counter is stacked first. $009 $OOA 0 Not Used (22 Bytes) 1 ROM ~ (1920 Bytes) Sttek 12 3967 3968 4087 4088 $F7 F $F 80 $FF 7 $FF 8 Self-Test Interrupt Vectors $07F * Write only registers * * Read only register $FF 4095 $01F $020 RAM (96 Bytes) Figure 2 MCU Memory Configuration 6 n-4 1 5 1 4 3 2 Condition 11 Code Register Accumulator n-3 0 0 Pull I A n+1 x n+2 11 n-2 n-1 n Index Register 1 1 1 1 1 PCl* PCH* n+3 n+4 Accumulator 0 I I I Index Register 0 PC 11 Program Counter 0 SP Stack Pointer n+5 Condition Code Register Push * For subroutine calls. Band C). This ensures that the program counter is loaded correctly as the stack pointer in· crements when it pulls data from the stack. which has two functions..... Please refer to INPUT PORT for more detail. C7 ) These 24 lines are arranged into three 8·bit ports (A. these become TTL compatible inputs. Bo . only PCH and PCl are stacked. PCL) contents to be pushed onto the stack. A7 .

• Condition Code Register (CC) The condition code register is a 5·bit register in which each bit is used to indicate or flag the r~sults of the instruction just executed. • Index Register (X) The index register is an 8-bit register used for the indexed addressing mode. the stack point· er is set to location $07F and is decremented as data is being pushed onto the stack and incremented as data is being pulled from the stack... During an MeU reset or the reset stack pointer (RSP) instruction..HD8806U1-------------------------------------------------------• indicate that a carry occurred between bits 3 and 4. Each jndi. and rotates. This bit is also affected during bit test and branch instructions. The interrupt bit (I bit) in the condition code register will also prevent a timer interrupt from being processed. They are shown in Figure 4 and are explained in the following paragraphs. the index register can be used as a temporary storage area. vidual condition code register bit is explained in the following paragraphs. The source of the clock input is one of the options that has to be specified before manufacture of the MeU. It contains an 8·bit address that may be added to an offset value to create an effective address. REGISTERS The MeU has five registers available to the programmer. • TIMER The MeU timer circuitry is shown in Figure 5.. These bits can be individually tested by a program and specific action taken as a result of their state.-. • Negative (N) Used to indicate that the result of the last arithmetic. • Accumulator (A) The accumulator is a general purpose 8·bit register used to hold operands and results of arithmetic calculations or data manipulations. The MeU responds to this interrupt by saving the present Meu state in the stack.... The clock input to the timer can be from an external source applied to the TIMER input pin or it can be the internal ~2 signal. shifts. Time Out 7 Timer t---::~--t1-6-~ Interrupt Req.-----. The 8·bit counter is loaded under program control and counts down to· ward zero as soon as the clock input is applied.. fetching the timer interrupt vector from locations $FF8 and $FF9 and executing the interrupt routine.Interrupt Mask N o Write Read T U Timer Control Register S E o o Figure 5 Timer Block Diagram 152 . When not required by a code sequence being executed. The timer interrupt can be masked by setting the timer interrupt mask bit (bit 6) in the time control register. • Zero (Z) Used to indicate that the result of the last arithmetic. • Half Carry (H) Used during arithmetic operations (ADD and ADC) to • Interrupt (I) Trus bit is set to mask the timer and external interrupt (INT). Note that when the ~2 signal is used as the source it can be gated by an input applied to the TIMER input pin allowing the user to easily perform pulse·width measurements. The index register can also be used for limited calculations and data manipulations when using read/modify/write instructions. • • I I I I L I _____ .II Manufacturing Mask Options .. Timer t---fo'I. Subroutines and interrupts may be nested down to location $061 which allows the programmer to use up to 15 levels of subroutine calls. • Program Counter (PC) The program counter is a 12·bit register that contains the address of the next instruction to be executed. Initially. the stack pointer is set to location $07F. When the timer reaches zero the timer interrupt request bit (bit 7) in the timer control register is set.~. logical or data manipulation was negative (bit 7 in result equal to a logical one). If an interrupt occurs while this bit is set it is latched and will be processed as soon as the interrupt bit is reset. The six most significant bits of the stack pointer are permanently set to 0000011.. • Carry/Borrow (C) Used to indicate that a carry or borrow out of the arithmetic logic unit (ALU) occurred during the last arithmetic operation. A prescaler option can be applied to the clock input that extends the timing interval up to a maximum of 128 counts before being applied to cf>2 (Internal) Timer Input Pin . • Stack Pointer (SP) The stack pointer is a 12·bit register that contains the address of the next free location on the stack. logical or data manipulation was zero.

The Timer Data Register is 8-bit Read/Write Register with address $008 on Memory-Map. 14 C 5 15 c. The bit 6 of Timer Control Register is writable by program.~ B.~F A.. l~~v v 10kn ~~. ~A 30 ~ ~12 C 3 vv v 1 E- Bs 30 9 r. (mask option) see Figure 7. Connecting a capacitor to the RES input as shown in Figure 8 will provide sufficient delay.--------------------------------------------------------HD8806U1 the counter.-v 1°~~ vv = Pin4 Vss '" Pin 1 0 ~ B.~ ° 1 1 C. Connect the MCU as shown in Figure 6 and monitor the output of port C bit 3 for an oscillation of approximately three hertz. 8 B. The timer continues to count past zero and its present count can be monitored at any time by monitoring the timer data register. 3l0n ~ I::i\ 10 C. 39 T2. Upon power up. • RESETS The MCV can be reset three ways: by initial powerup. 31 B.E- C A. by the external reset input (m) and by an internal low voltage detect circuit. A'-I\. 7 NUM P 10kn AI\. 40 A. Both of those bits can be read by MPU. This Timer Data Register and the prescaler are initialize with all logical ones at Reset time. and is cleared by program or by hardware reset. 3 INT 2 REs As 38 XTAL A3 36 '-- A. The Timer Interrupt Request bit (bit 7 of Timer Control Register) is set to one by hardware when timer count reaches zero. 25 13 C. This time allows the internal crystal oscillator to stabilize. • Re f er to Fi gure 9 about crystal option V cc Figure 6 Self Check Connections Vec OV--------------J RES Pin --------r Internal Reset Figure 7 Power Up and RES Timing 153 . 29 C. 16 C. This pre scaling option must also be specified before manufacturing begins.::::i A." 33an . 26 B. All the I/O port are initialized to Input mode (DDR's are cleared) during RESET. '17 8. HD6805U1. 34 EXTAL +9V + V cc 130n TIMER (Register option) B. a minimum of 100 milliseconds is needed before allowing the reset input to go "High" . • SELF CHECK The self check capability of the MCU provides an internal check to determine if the part is functional. 35 A. This allows a program to determine the length of time since a timer interrupt has occured and not disturb the counting process.

\ C II> ~ AT Co = f=4 Rs = g Cut Parallel Resonance Crystal 7 pF max. XTAl~~EXTAl 5 ~~ \ 4 N ::I: ~ • > (. A manufacturing mask option is available to provide better matching between the external components and the internal oscillator. MHz 60n max.... Vee Part of HD6805U1 MCU Figure 8 Power Up ~eset Delay Circuit 6 EXTAl 6 EXTAl M HZ 4 ma x c:J 5 XTAl HD6805U1 MCU HD6805U1 MCU 5 XTAl 22P F±20%T Approximately 25% Accuracy External: Jumper . The different connection methods are shown in Figure 9. A resistor selection graph is given in Figure 11.HD8806U1-------------------------------------------------------• INTERNAL OSCILLATOR OPTIONS The internal oscillator circuit has been designed to require a minimum of external components. u: 2 "- ". Crystal specifications are given in Figure 10.) 3 I \.r__6. EXT A l 6 EXTAl External Clock Input R 5 XTAl HD6805U1 MCU 5 XTAl HD6805U1 MCU No Connection External Clock Approximately 15% Accuracy External Resistor CRYSTAL OPTIONS RESISTOR OPTIONS Figure 9 Internal Oscillator Options 5 ~ C. 4 MHz max) or a resistor is sufficient to drive the internal oscillator with varying degrees of stability..~ Figure 10 Crystal Parameters o 5 10 15 20 25 30 Resistance /kn) "- 35 ~~ 40 Figure 11 Typical Resistor Selection Graph 154 J Vee = 5. The use of a crystal (AT cut...25V T A = 25°C - 45 50 ..

. FF9 Fetch Instruction Y SWI Execute Instruction Figure 12 Interrupt Processing Flowchart Output Data Bit 1/0 Pin Data Direction Register Bit Figure 13 Typical Port I/O Circuitry 155 Output Data Bit Output State Input to MCU 1 1 0 0 0 0 x 3·State Pin .X...A. I 7F .... Timer 7F .. TCR TIMER Load PC From Reset: FFE.. DDR's Stack PC... SP o ....________________________________________________________ HD8806U1 1 ....CC CLR INT Logic FF .. FFF Load PC From SWI: FFC. FFB TIMER: FF8.. FFD TNT: FFA. Prescaler 7F ...

(pin 17) is the input pin ofVTH (reference level). and Figure 15(d) shows 3 levels inputs. ROM or I/O allows the user to have individual flags in RAM or to handle single I/O bits as control lines. A capacitive touch panel interface and a diode isolated keyboard interface are the examples. The example in Figure 16 illustrates the usefulness of the bit manipulation and test INPUT/OUTPUT There are 24 input/output pins. BCLR). if the input levels are higher or lower respectively when $007 address is read. the internal timer interrupt request t and a software interrupt instruction (SWI). the interrupt bit (I) in the condition code register is set. All input/output lines are TTL compatible as both inputs and outputs. ·· ·••• Port B Programmed as output/s) driving Darlington base directly.CMOS Inverter Port C Programmed as output(s) driving CMOS using external pull-up resistors. (a) (b) +V +V A Port B ·•·•• ·· - Port C 10 mA max Port B Programmed as output(s) driving LED(s) directly. All pins are programmable as either inputs or outputs under software control of the data direction registers. the input data can be read by MPU at $003 address. When any interrupt occurs.. the address of the interrupt routine is obtained from the appropriate interrupt vector address.. and the vector address that contain the starting address of the appropriate interrupt routine. Figure 15(c) shows the application of Port D to A/D converter. and the program branches as a result of its state. which has two functions.. A flowchart of the interrupt processing sequence is given in Fig. Any bit in the page zero read only memory can be tested. D. "1" or "0" signals appear at internal data bus. (d) (c) Figure 14 Typical Port Connections 156 . Port A lines are CMOS compatible as outputs while port Band C lines are CMOS compatible as inputs. (b». 12.HD8806U1--------------------------------------~-------------• programmed for outputs. and the other seven input pins (Do '" D6 ) are analog level inputs. In the latter case. When programmed as outputs. ·•• ·· t . Table 1 provides a listing of the interrupts. This function is effective in such case that unusual logic level inputs are used. the present MCU state is pushed onto the stack... The interrupt service routines normally end with a return from interrupt (RTI) instruction which allows the MCU to resume processing of the program prior to the interrupt.-. 13). INTERRUPTS The MCU can be interrupted three different ways: through the external interrupt (INT) input pin. One of them is usual digital signal input port and the other is voltage compare type input port. Figure 14 provides some examples of port connections.. When port B is Bo Ao •• ··• Port A Port B · Port A Programmed as output(s) driving CMOS and TTL Load directly. SWI 2 $FFC and $FFD TNT 3 $FFA and $FFB • BIT MANIPULATION TIMER 4 $FFS and $FF9 The MCU has the ability to set or clear any single random access memory or input/output bit (except the data direction registers) with a single instruction (BSET. which are compared with VTH (see Figure 15(a). This capability to work with any bit in RAM. processing is suspended. their priority. and the interrupt routine is executed. using the BRSET and BRCLR instructions. • Table 1 Interrupt Priorities Interrupt Priority Vector Address 1 $FFE and $FFF RES • INPUT Port D is 8-bit input port. it is capable of sinking 10 millamperes on each pin (VOL = IV max). In the former case. all I/O pins read latched output data regardless of the logic level at the output pin due to output loading (see Fig.

7V . Reference Level 06 Port Analog Input S ) 0 Do 0.3V 1 1 0 3. The timer could also be incorporated to provide turnon at some later time which would permit pulse-width modulation of the controlled power. pro- vides turn-on of the TRIAC within 14 microseconds of the zero crossing.SV 0 0 2. Port o 06 t----Analog Input S Do t-----Analog Input 0 Analog Input 0 (b) Seven analog inputs and a reference level input of Port 0 (c) Application to AID convertor 0. which uses only seven ROM locations. $003 Read Internal Bus (BitO .3.Vee 1 3 Levels Input 0 (d) Application to 3 levels input Figure 15 Configuration and Application of Port 0 157 .---------------------------------------------------------HD8806U1 instructions. VTH (= 3. This program.0V .BitS) + $003 Read Input Port (07) Internal Bus (Bit 7) (a) The logic configuration of Port 0 Port ~- C 0.5V) 06 3 Levels Input S Port 0 \ Do Input Voltage ($003) ($007) OV -O. Assume that bit 0 of port A is connected to a zero crossing detector circuit and that bit 1 of port A is connected to the trigger of a TRIAC which power the controlled hardware.

bit manipulation. Extended addressing instructions are three bytes long. They can be divided into five different types: register/memory. These instructions are two bytes long. Extended addressing is used to reference any location in memory space. Refer to Figure 22. This mode of addressing accesses the lowest 256 bytes of memory. • Extended Refer to Figure 19. In this mode the contents of the byte following the opcode is added to the program counter when the branch is taken. This mode of addressing applies to instructions which can test any bit in the first 256 locations ($OO-$FF) and branch to any location relative to the PC. branch. Refer to Table 3.HD6806U1--------------------------------------------------------- SELF 1 ··• ·· • Bit Set/Clear Refer to Figure 24. The byte to be tested is addressed by the byte following the opcode. control instructions such as SWI. the address of the operand is contained in the second byte of the instruction. This addressing mode calculates the EA by adding the contents of the two bytes following the opcode to the index register. • Control Instructions • • Alphabetical Listing Indexed (l6-bit Offset) Refer to Figure 23. • Relative Refer to Figure 20. EA=(pC)+2+Rel. 158 The control instructions control the MCV operations during program execution. The value of the bit tested is written to the carry bit in the condition code register. Refer to Table 5. The third byte is the relative address to be added to the program counter if the branch condition is met. Refer to Table 6. • Opcode Map Table 8 is an opcode map for the instructions used on the MCV. The effective address (EA) is the PC and the operand is fetched from the byte following the opcode. The lower three bits in the opcode specify the bit to be set or cleared while the byte following the opcode specifies the address in page zero. In this mode. Direct operations on the accumulator and the index register are included in this mode of addressing. The MCV has a set of 59 basic instructions. The following paragraphs briefly explain each type. The immediate addressing mode accesses constants which do not change during program execution. The test for negative or zero (TST) instruction is an exception to the read/modify/write instructions since it does not perform the write. the entire memory space may be accessed. . The EA is calculated by adding the contents of the byte following the opcode to the contents of the index register. Direct addressing allows the user to directly address the lowest 256 bytes in mem"ry. Refer to Table 4. They are explained and illustrated briefly in the following paragraphs. The implied mode of addreSSing has no EA. The jump unconditional (JMP) and jump to subroutine (JSR) instructions have no register operand. BRClR 0. Thus. These instructions are one byte long and their EA is the contents of the index register. These instructions are three bytes long. • Register/Memory Instructions Most of these instructions use two operands. Such instructions are two bytes long. The complete instruction set is given in alphabetical order in Table 7. and write the modified value back to memory or to the register. The EA is the contents of the two bytes following the opcode. The other operand is obtained from memory using one of the addressing modes. This mode of addressing applies to instructions which can set or clear any bit on page zero. All implied addressing instructions are one byte long. SELF 1 BSET 1. • Indexed (8-bit Offset) Refer to Figure 26. In addition. • Read/Modity/Write Instructions These instructions read a memory location or a register. All the instructions within a given type are presented in individual tables. If the branch is not taken Rel=O. modify or test its contents. ReI is the contents of the location following the instruction opcode with bit 7 being the sign bit. PORT A BClR 1. when a branch takes place. The individual bit within that byte to be tested is addressed by the lower three bits of the opcode. I/O registers and 128 bytes of ROM are located in page zero to take advantage of this efficient memory addressing mode. Instructions which use this addressing mode are three bytes long. and control. One group either sets or clears. PORT A • Bit Test and Branch The MCU has ten addressing modes available for use by the programmer. All the information necessary to execute an instruction is contained in the opcode. Refer to Figure 25. The other group performs the bit test and branch operations. the program goes to somewhere within the range of + 129 bytes to -127 of the present instruction. All RAM space. One operand is either the accumulator or the index register. These instructions occupy two bytes. • Branch Instructions The branch instructions cause a branch from the program when a certain condition is met. • Indexed (No Offset) Refer to Figure 21. RTI belong to this group. Refer to Table 2. In direct addressing. 511 low memory locations are accessable. • Bit Manipulation Instructions These instructions are used on any bit in the first 256 bytes of the memory. PORT A. • Direct Refer to Figure 18. The relative addressing mode applies only to the branch instructions. • • Implied • INSTRUCTION SET ·•• · Figure 16 Bit Manipulation Example • ADDRESSING MODES Immediate Refer to Figure 17. read/modify/ write.

... Figure 18 Direct Addressing Example 159 20 -1 Index Reg I 0520 I A _I I I I Prog Count 052F CC I .------------------------------------------------------HD8806U1 Memory I I I I I ~ I A Stack Point I I PROG LOA #$F8 05BE 05BF ..------4 A6 Prog Count F8 05CO CC ~ I I I I Figure 17 Immediate Addressing Example i lEA Memory I I I I I I I I I I I I CAT FCB 32 LOA CAT I 004B 1 / Adder '" oo~oo 20 OO4B I PROG I -I B6 052E 4B I Stack Point I I ~ I I I I I I I : .

.. . .HD880&U1----------------------------------------------------- Memory 0000 A 40 PROG LOA CAT Index Reg Stack Point Prog Count CAT FCB 64 06E5 .-----.j 40 040C CC Figure 19 Extended Addressing Example EA 04C1 Memory i I ~ A Index Reg Stack Point I I PROG BEQ PROG2 04A7 04A8 27 0000 1-------1 18 ~ I I Figure 20 Relative Addressing Example 160 .

• CF I Index Reg I 03 I Stack Point TABL.--------------------------------------------------------HD8806U1 EA OOB8 Memory TABL FCC I LlI 00B8 4C 4C 49 Index Reg B8 Stack Point PROG LOA X Prog Count 05F5 CC Figure 21 Indexed (No Offset) Addressing Example lEA Melory TABL •t i I t FCB #BF 0089 BF FCB #86 OOSA 86 FCB #OB oo8B DB FCB #CF 008C CF I LOA J 008C I L' 1 Adder I I t t PROG I '" A -. X 075B E6 075C 89 I I I § I I Prog Count t Figure 22 Indexed (8-Bit Offset) Addressing Example 161 075E CC I .

X 0692 0693 0694 I 02 ~6 07 Stack Point ~______.I Figure 24 Bit Set/Clear Addressing Example 162 .HD8806U1------------------------------------------------------ Memory i I § A DB Index Reg I PROG LOA TABL.J 7E Prog Count 0695 I TABL CC I FCB #BF 077E BF FCB #86 077F 86 FCB #OB 0780 DB FCB #CF 0781 CF Figure 23 Indexed (16-Bit Offset) Addressing Example Memory PORT B EQU BF 0001 A 0000 Index Reg 10 0590 Stack Point 01 Prog Count 0591 I I CC § I I .

. PROG 2 0574 0575 0576 05 Prog Count 02 0594 . -----.. PORT C..f 1--------1 10 CC C Figure 25 Bit Test and Branch Addressing Example Memory i I I I I ~ A E5 Index Reg I ES I PROG TAX 05BA~ Prog Count 05B8 CC I I I I § Figure 26 Implied Addressing Example 163 . .-------------------------------------------------------HD8806U1 PORT C Eau 0002 2 FO A Index Reg 0000 Stack Point PROG BRCLR 2. .

HD8806U1------------------------------------------------------Table 2 Register/Memory Instructions Addressing Modes Function Mnemonic Immediate Indexed (No Offset) Extended Direct Op Op Op # # # # Code Bytes Cycles Code Bytes Cycles Code Op # # Bytes Cycles Code Indexed (8-Bit Offset) Op # # Bytes Cycles Code Indexed 06-Bit Offset) Op # # Bytes Cycles Code # # Bytes Cycles Load A from Memory LOA A6 2 2 B6 2 4 C6 3 5 F6 1 4 E6 2 5 06 3 6 Load X from Memory LOX AE 2 2 BE 2 4 CE 3 5 FE 1 4 EE 2 5 DE 3 6 Store A in Memory STA - B7 2 5 C7 3 6 F7 1 5 E7 2 6 07 3 7 STX - '- Store X in Memory - - BF 2 5 CF 3 6 FF 1 5 EF 2 6 OF 3 7 Add Memory to A ADD AB 2 2 BB 2 4 CB 3 5 FB 1 4 EB 2 5 DB 3 6 Add Memory and Carry to A AOC A9 2 2 B9 2 4 C9 3 5 F9 1 4 E9 2 5 09 3 6 Subtract Memory SUB AO 2 2 BO 2 4 CO 3 5 FO 1 4 EO 2 5 DO 3 6 Subtract Memory from A with Borrow sec A2 2 2 B2 2 4 C2 3 5 F2 1 4 E2 2 5 02 3 6 AND Memory to A AND A4 2 2 B4 2 4 C4 3 5 F4 1 4 E4 2 5 04 3 6 OR Memory with A ORA AA 2 2 BA 2 4 CA 3 5 FA 1 4 EA 2 5 OA 3 6 Exclusive OR Memory with A EOR A8 2 2 B8 2 4 C8 3 5 F8 1 4 E8 2 5 08 3 6 Arithmetic Compare A with Memory CMP A1 2 2 B1 2 4 C1 3 5 F1 1 4 E1 2 5 01 3 6 Arithmetic Compare X with Memory CPX A3 2 2 B3 2 4 C3 3 5 F3 1 4 E3 2 5 03 3 6 Bit Test Memory with A (Logical Compare) BIT A5 2 2 B5 2 4 C5 3 5 F5 1 4 E5 2 5 05 3 6 Jump Unconditional JMP - 2 3 CC 3 4 FC 1 3 EC 2 4 DC 3 5 JSR - BC Jump to Subroutine - BO 2 7 CD 3 8 FO 1 7 ED 2 8 DO 3 9 - Table 3 Read/Modify/Write Instructions Addressing Modes Function Implied (A) Mnemonic Op Code Implied (X) Op # # Bytes Cycles Code # Indexed (No Offset) Direct # Op Bytes Cycles Code Op # # Bytes Cycles Code Indexed (8-Bit Offset) Op # # Bytes Cycles Code # # Bytes Cycles Increment INC 4C 1 4 5C 1 4 3C 2 6 7C 1 6 6C 2 Decrement DEC 4A 1 4 5A 1 4 3A 2 6 7A 1 6 6A 2 7 Clear CLR 4F 1 4 5F 1 4 3F 2 6 7F 1 6 6F 2 7 Complement COM 43 1 4 53 1 4 33 2 6 73 1 6 63 2 7 Negate (2's Complement) NEG 40 1 4 50 1 4 30 2 6 70 1 6 60 2 7 Rotate Left Thru Carry ROL 49 1 4 59 1 4 39 2 6 79 1 6 69 2 7 Rotate Right Thru Carry ROR 46 1 4 56 1 4 36 2 6 76 1 6 66 2 7 Logical Shift Left LSL 48 1 4 58 1 4 38 2 6 78 1 6 68 2 7 7 7 Logical Shift Right LSR 44 1 4 54 1 4 34 2 6 74 1 6 64 2 Arithmetic Shift Right ASR 47 1 4 57 1 4 37 2 6 77 1 6 67 2 7 Arithmetic Shift Left ASL 48 1 4 58 1 4 38 2 6 78 1 6 68 2 7 Test for Negative or Zero TST 40 1 4 50 1 4 3D 2 6 70 1 6 60 2 7 164 .

---------------------------------------------------------HD8806U1 Table 4 Branch Instructions Relative Addressing Mode Mnemonic Function Op Code # # Bytes Cycles Branch Always BRA 20 2 4 Branch Never BRN 21 2 4 Branch IF Higher BHI 22 2 4 Branch I F lower or Same BlS 23 2 4 Branch I F Carry Clear BCC 24 2 4 (Branch I F Higher or Same) (BHS) 24 2 4 Branch I F Carry Set BCS 25 2 4 (Branch IF lower) (BlO) 25 2 4 Branch I F Not Equal BNE 26 2 4 4 Branch I F Equal BEQ 27 2 Branch I F Half Carry Clear BHCC 28 2 4 Branch I F Half Carry Set BHCS 29 2 4 Branch I F Plus BPl 2A 2 4 Branch IF Minus BMI 2B 2 4 Branch IF Interrupt Mask Bit is Clear BMC 2C 2 4 Branch I F Interrupt Mask Bit is Set BMS 20 2 4 Branch I F Interrupt Line is low Bil 2E 2 4 Branch IF Interrupt Line is High BIH 2F 2 4 Branch to Subroutine BSR AO 2 8 Table 5 Bit Manipulation Instructions Addressing Modes Function Mnemonic Bit Set/Clear Branch I F Bit n is set BRSET n (n=O . 7) 10+2·n 2 7 Clear bit n BClR n (n=O .. 7) 11+2·n 2 7 - Table 6 Control Instructions Implied Function Mnemonic Op Code # # Bytes Cycles 2 Transfer A to X TAX 97 1 Transfer X to A TXA 9F 1 2 Set Carry Bit SEC 99 1 2 Clear Carry Bit ClC 98 1 2 Set Interrupt Mask Bit SEI 9B 1 2 Clear Interrupt Mask Bit CLI 9A 1 2 Software Interrupt SWI 83 1 11 Return from Subroutine RTS 81 1 6 Return from Interrupt RTI 80 1 9 Reset Stack Pointer RSP 9C 1 2 No-Operation NOP 90 1 2 165 ....... 7) Bit Test and Branch # # Bytes Cycles - - Op Code Op Code # # Bytes Cycles - 2·n 3 10 - 01+2·n 3 10 - - - Set Bit n BSET n (n=O . 7) Branch I F Bit n is clear BRClR n (n=O ..........

x x Bit Set/ Clear BHCC x BHI x BHS x BIH x BIL x x BIT x x x BLS x BMC x BMI x BMS x BNE x x x x BPL BRA BRN COM x x x x x x EOR x x x x x CPX DEC x x x x x x x x x x x x x x x x x x x JSR x x x x x x x x x x x x LOA x LOX x Condition Code Symbols: H Half carry (From Bit 3) I I nterrupt Mask N Negative (Sign Bit) Z Zero x x 1\ 1\ 1\ 1\ 1\ • • • • • x x x x x JMP INC 1\ 1\ • • x x 1\ 1\ x x CMP 1\ x x x 1\ 1\ • • • • BSET x 1\ x x x CLR • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 0 • • • • • • • • • • • x BRCLR CLI 1\ x BRSET BSR C x x BLO Z 1\ x x x BHCS N x x BEQ I x BCLR BCS H x x x BCC CLC Bit Test & Branch x x x x x • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 1\ • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 1\ 1\ • • • • • • • • • • • • • • • • • • • • • • • • • 1\ • 1\ • • • • • 0 • • 1 • 0 1\ 1\ 1\ 1\ 1\ 1\ 1\ 1\ 1\ 1\ 1\ 1 • • 1\ 1\ • • • • • • • 1\ 1\ • 1\ 1\ • 1\ (to be continued) C 1\ • Carry Borrow Test and Set if True.HD8806U1-------------------------------------------------------Table 7 Instruction Set Addressing Modes Mnemonic Implied Immediate Direct Extended ADC x x x ADD x x x x x AND x ASL x x ASR x x Relative Condition Code Indexed Indexed Indexed (No (8 Bits) (16 Bits) Offset) x . Cleared Otherwise Not Affected 166 .

---------------------------------------------------------HD8806U1 Table 7 Instruction Set Addressing Modes Mnemonic LSL LSR NEG NOP ORA ROL ROR RSP RTI RTS SBC SEC SEI STA STX SUB SWI TAX TST TXA Implied Immediate x x x Direct Extended Relative x x x Condition Code Indexed Indexed Indexed (No (8 Bits) (16 Bits) Offset) x x x x x x Bit Set! Clear x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Condition Code Symbols: H Half Carry (From Bit 3) I I nterrupt Mask N Negative (Sign Bit) Z Zero x C /\ • ? x Carry IBorrow Test and Set if True. Cleared Otherwise Not Affected Load CC Register From Stack 167 Bit Test & H Branch I N Z C • • • • • • • • • /\ /\ /\ • 0 /\ /\ • /\ /\ /\ • • • • • /\ /\ • • /\ /\ /\ • /\ /\ /\ • • • • ? ? • • • • • • • 1 • • • • • • • 1 • • • • • ? ? ? • • • /\ /\ /\ • • 1 • • • /\ /\ • /\ /\ • /\ /\ /\ • • • • • • /\ /\ • • • ·1· .

Xl 6 I 2 BRSETI BSET1 BHI - SWI· ~ 1 1 OIR 1 B Register/Memory EXT 1 C I )(2 J )(1 1 I E 0 SUB I . The number at the bottom of each column denote the number of bytes and the number of cycles required (Bytes/Cycles).. 2. ( indicate that the number in parenthesis must be added to the cycle count for that instruction.. require a different number of cycles as follows: ATI 9 RTS 6 SWill BSA 8 3.XO 1F +. 168 I 1/4 .HD8806U1-----------------------------------------------------Table 8 Bit Manipulation Control Read/Modify /Write Branch Test & Branch Set/ Clear Rei OIR 0 BRSETO 1 3 BSETO 2 BRA 1 BRCLRO BCLRO 0 Opcode Map I I I I .XO IMP IMP IMM 7 8 9 A NEG RTI· - BRN - RTS· - I A 4 I X 5 I .. Mnemonics followed by a . Undefined opcodes are marked with "-"..HIGH 0 CMP 1 - SBC 2 - CPX 3 L AND 4 o 3 BRCLAI BCLRI BLS COM 4 BASET2 BSET2 BCC LSR 6 BACLA2 BCLR2 BCS - - - BIT 5 W 6 7 BRSET3 BSET3 BNE ROA - - LOA BACLR3 BCLR3 BEQ ASR TAX 6 7 8 BRSET4 9 BACLR4 BSET4 BHCC LSL/ASL BCLR4 BHCS ROL - - A BASET5 BSET5 BPL DEC B BRCLR5 BCLR5 BMI - C BRSET6 BSET6 BMC INC 0 BRCLR6 BCLA6 BMS TST E BRSET7 BSET7 BIL - F BRCLR7 BCLA7 BIH CLR 3/10 (NOTE) 2/7 2/4 2)6 I 1/4 I 1/4 I 2/7 - I 1/6 1/· - 1 STA(+I) CLC EOR SEC AOC CLI ORA ADD SEI RSP NOP 8 9 A B I JMP(-ll C BSR·I JSR(-3) 0 LOX E STX(+l1 - TXA - [ 1/2 2/2 I 2/4 I 3/5 I 3/6 l F 2/5 1.

HD6805V1 MCU (Microcomputer Unit) The HD6805VI is the 8-bit Microcomputer Unit (MCU) which contains a CPU. A. 8. A O'f 1'109 1'109 C_ 5 RegIster CC 5 SlICk POinter 8 Pr09r. Port ° ROM 0. I/O and timer. A. .External and Timer • 24 I/O Ports + 8 Input Port (8 Lines LED Compatible. B. C.. RAM and I/O Compatible Instruction Set with MC6805P2 • BLOCK DIAGRAM (DP·40) • PIN ARRANGEMENT A.. C. A. D. Accumulator A CPU ContrOl Index RegISter A. C. lin" B.. 8. on-chip clock.8 8 1/0 8. ROM 0.. C. The following are some of the hardware and software highlights of the MCU. D. Program Counte. A.. HD6805V1P • • • • • • • HARDWARE FEATURES 8-Bit Architecture 96 Bytes of RAM Memory Mapped I/O 3848 Bytes of User ROM Internal 8-Bit Timer with 7-Bit Prescaler Vectored Interrupts . AI A. C. B.. A. 7 Voltage Comparator Inputs) • On-Chip Clock Circuit • Self-Check Mode· • Master Reset • Low Voltage Inhibit • Complete Development System Support by Evaluation Kit • 5 Vdc Single Supply • • • • • • • • • • • • • • SOFTWARE FEATURES Similar to HD6800 Byte Efficient Instruction Set Easy to Program True Bit Manipulation Bit Test and Branch Instructions Versatile Interrupt Handing Powerful Indexed Addressing for Tables Full Set of Conditional Branches Memory Usable as Registers/Flags Single Instruction Memory Examine/Change 10 Powerful Addressing Modes All Addressing Modes Apply to ROM. ALU C. PCH Port CPU Sp 4 8. 8. 0. Input OJ Lin. A. A. A. Condition Port D. C. 0. TIMER c.. H . C. c. C. C. Port C 1/0 Lines 0. c. SelfctM:ck O. D. A. ROM. 0. D. D. C. . A...m Counter "Low" PCL 3848. Pott A I/O Lines A. It is designed for the user who needs an economical microcomputer with the proven capabilities of the HD6800based instruction set. B. (Top View) C. RAM. A.

6 0.F .+7.0 - - V mW 4.3 - 0.3 -+12:0 V °c °c Operating Temperature Top' o -+70 Storage Temperature Tstg . VSS-GND.0 V Selt-Check Mode -0.+150 * With respect to Vss (SYSTEM GND) (NOTE) Permanent LSI damage may occur if maximum ratings are exceeded.2p.A • AC CHARACTERISTICS (Vcc=5.A 0 p.55 . 2 - - ns Oscillation Start-up Time (Crystal Mode) tose - - 100 ms - ms Delay Time Reset Input Capacitance tRHL I I EXTAL All Other Cin 170 R ep=15.25V ± O..8 V - 0.3.F Vin=OV 100 - 25 6 35- pF 10 p.5V.H 2.0 MHz t'WL t2~ - - ns RES Pu Ise Width tRWL tc c+ 2 0 5 - - ns TIMER Pulse Width tTWL t .HD8805V1-------------------------------------------------------• ABSOLUTE MAXIMUM RATINGS Value Symbol Item Supply Voltage Vee Input Voltage (EXCEPT TIMER) V ln Input Voltage (TIMER) * * Unit -0. Ta=G-+70°C.25V ± O.L -0.8 V - 0.0 - Vee 11.0 INT V .3-+7.4 Cycle Time tCYC 1.s 2. • ELECTRICAL CHARACTERISTICS • DC CHARACTERISTICS (Vcc-5.7 - 4.) Item Input "High" Voltage Symbol INT 3.0 MHz 10 p.8 V V V .0 Oscillation Frequency (External Resister Mode) fexT INT Pulse Width typ - max Unit 4. Normal operation should be under recommended operating conditions.0kn±1% C L=22pF±20%. VSS=GND.75 V - V 20 loLA 50 p.0 V -0.0 max Unit Vee V Timer Mode 2.3 XTAL(Crystal Mode) All Other -0.5V. Rs=60n max. unless otherwise noted. it could affect reliability of LSI. unless otherwise noted.0 All Other Input "High" Voltage Timer Test Condition RES IlL V in =0.3 -0.) Item Symbol Test Condition min Clock Frequency fcl 0. = 2.3 Power Dissipation Po - Low Voltage Recover LVR - Low Voltage Inhibit LVI - -20 TIMER INT I nput Leak Current - - RES Input "Low" Voltage min typ 4. External Cap. Ta=O .+70°C.0 V -0.4V-Vee XT AL(Crystal Mode) -50 -1200 - Vee V Vee V 400 700 4.0 9. If these conditions are exceeded.

8xV ee V Vin Vin IlL Vin =0. Vss is the ground connection. Vss = GNO. Port B.6 mA 2. C. Refer to RESETS for additional information. Refer to INTERNAL OSCIL- 171 • TIMER This pin allows an external input to be used to decrement the internal timer circuitry. Vee is +5. A crystal (AT cut.4 1. 4 MHz maximum) or a resistor can be connected to these pins to provide the internal oscillator with varying degrees of stability. Load capacitance includes the floating capacitance of 2.4V '" Vee 2.4 typ max - - - - - - - - - 0.2 mA VOL Port B IOL = 10 mA Input "High" Voltage VIH Port A.4 1.A Port A IOH =-100JJ. • XT AL and EXTAL These pins provide control input for the on-chip clock circuit.2 mA . • Vee and Vss Power is supplied to the MCU using these two pins. B.A - - JJ.A VOH Port B IOH = -1 mA Port C IOH = -100'JJ.5V.25V ±O.25V ± 0..4 0. (Port A and TTL Equiv.. and 0 Port 0** (Do'" 0 6 ) Port 0** (Do'" 0 6 ) Port 0**(0. Refer to TIMER for additional information about the timer circuitry. Test Point 40pF (NOTE) C) Ii Test Point 30 pF 12 kn 1.20 - 20 JJ.A Output "High" Voltage IOH = -200JJ.6 mA Output "Low" Voltage IOL =3. = 1.) = 0'" +70°C unless otherwise noted. • INT This pin provides the capability for applying an external interrupt to the MCU Refer to INTERRUPTS for additional information.A VIH - VTH+0.2 - V VIL - VTwO.0 -0. Figure 1 Bus Timing Test Loads • LATOR OPTIONS for recommendations about these inputs. ..3 -500 -300 - * Port 0 as digital Input ** Port 0 as analog input TTL Equiv. • NUM This pin is not for user application and should be connected to ground. Ta Item Symbol Test Condition IOH = -10JJ. • RES This pin allows resetting of the MCU at times other than the automatic resetting capability already in the MCU.0 - - - Vee 0. All diodes are 1520746 or equivalent .) min 3.4kn 24 kn the probe and the jig etc. SIGNAL DESCRIPTION The input and output signals for the MCU shown in PIN ARRANGEMENT are described in the following paragraphs. C.8V =2V =O. and 0* Input "Low" Voltage VIL I Port A Input Leak Current Input "High" Voltage Input "Low" Voltage Threshold Voltage .5 2.A .8 Unit V V V V V V V V - - V V JJ.2 - V VTH 0 - 0.5 2.5V.A Port A and C IOL = 1.---------------------------------------------------------HD6806V1 • PORT ELECTRICAL CHARACTERISTICS (Vee = 5.4 2. (Port B) Vee Ii = 3.

.. $008 9 Timer CTR l Reg.) These are 8-bit input lines.. the low order byte (PCL) of the program counter is stacked first.. Co . Since the stack pointer decrements during pushes. C. these become TTL compatible inputs.. Carry IBorrow Figure 3 Interrupt Stacking Order Zero Negative Interrupt Mask Half Carry Figure 4 Programming Model 172 . Input/Output Lines (Ao .. only PCH and PCl are stacked..HD6806V1--------------------------------------------------------• • MEMORY The MCU memory is configured as shown in Figure 2.. the contents of the MCU registers are pushed onto the stack in the order shown in Figure 3. The other function of them is 7 Voltage comparators. 3 2 Condition Code Register o 7 0 Pull ' -_ _ _ _A_ _ _ _. by reading $003 address... Program Counter LI_ _ _ _ _ _ _ 11 5 4 0 n'+5 Condition Code Register Push * For subroutine calls.. by reading $007 address. During the processing of an interrupt.. o 7 000 $000 1/0 Ports Timer RAM (128 Bytes) 127 1-_ _ _ _ _ _ _ _ _-'. PCL) contents to be pushed onto the stack.. • Input Lines (Do . Band C). which has two functions.. 128 6 5 4 3 0 2 0 Port A 1 Port B $001 2 Port C $002 $000 3 Port 0 (digitel) $003** 4 Port A DDR $004* $005· 5 Port BOOR 6 Port C DDR $006* 7 Port 0 (analog) $007** 8 Timer Deta Reg...I1 Accumulator n+1 n-3 Accumulator n+2 n-2 Index Register n+3 o 7 "-_ _ _ _X_ _ _ _~llndex Register 0 11 n-1 n 1 1 1 11 PCl * PCH* n+4 I P_C _ _ _ _ _ _. A subroutine call will cause only the program counter (pCH.. Bo . B.... then the high order four bits (PCH) are stacked.) These 24 lines are arranged into three 8-bit ports (A. 0. Refer to INPUTS/OUTPUTS for additional information. This ensures that the program counter is loaded correctly as the stack pointer increments when it pulls data from the stack. Firstly.. All lines are programmable as either inputs or outputs under software control of the data direction registers. A. Please refer to INPUT PORT for more detail. $009 ROM (3840 Bytes) 3967 3968 0 $OOA Not Used (22 Bytes) Self-test 4087 4088 31 3 ~ Interrupt Vectors (8 Bytes) St~k 12 $07F * Write only registers ** Read only register $FFF 4095 $01F $020 RAM (96 Bytes) Figure 2 MCU Memory Configuration 6 n-4 1 5 1 4 1-.

the index register can be used as a temporary storage area. logical or data manipulation was zero. These bits can be individually tested by a program and specific action taken as a result of their state. Time Out 7 Timer t--~~--If-6-~ Interrupt Req.---------------------------------------------------------HD6805V1 • indicate that a carry occurred between bits 3 and 4. During an MeU reset or the reset stack pointer (RSP) instruction.. logical or data manipulation was negative (bit 7 in result equal to a logical one). the stack pointer is set to location $07F and is decremented as data is being pushed onto the stack and incremented as data is being pulled from the stack. . This bit is also affected during bit test and branch instructions. • Carry/Borrow (C) • Program Counter (PC) Used to indicate that a carry or borrow out of the arithmetic logic unit (ALU) occurred during the last arithmetic operation.. and rotates. . • Accumulator (A) The accumulator is a general purpose 8-bit register used to hold operands and results of arithmetic calculations or data manipulations. shifts.:-. The program counter is a 12-bit register that contains the address of the next instruction to be executed. fetching the timer interrupt vector from locations $FF8 and $FF9 and executing the interrupt routine. The index register can also be used for limited calculations and data manipulations when using read/modify/write instructions. Note that when the 4>2 signal is used as the source it can be gated by an input applied to the TIMER input pin allowing the user to easily perform pulse-width measurements. REGISTERS The MeU has five registers available to the programmer.. The 8-bit counter is loaded under program control and counts down toward zero as soon as the clock input is applied. • TIMER • Stack Pointer (SP) The stack pointer is a 12-bit register that contains the address of the next free location on the stack.. • Interrupt (I) • Negative (N) This bit is set to mask the timer and external interrupt (00). • Half Carry (H) Used during arithmetic operations (ADD and ADC) to The MCU timer circuitry is shown in Figure 5. • Condition Code Register (CC) The condition code register is a 5-bit register in which each bit is used to indicate or flag the r~sults of the instruction just executed. It contains an 8-bit address that may be added to an offset value to create an effective address... The clock input to the timer can be from an external source applied to the TIMER input pin or it can be the internal 4>2 Signal. Initially. Used to indicate that the result of the last arithmetic. The MCU responds to this interrupt by saving the present MeU state in the stack.. The six most significant bits of the stack pointer are permanently set to 0000011.. The timer interrupt can be masked by setting the timer interrupt mask bit (bit 6) in the time control register. • I ndex Register (X) The index register is an 8-bit register used for the indexed addressing mode.. When the timer reaches zero the timer interrupt request bit (bit 7) in the timer control register is set.1 L I I . A prescaler option can be applied to the clock input that extends the timing interval up to a maximum of 128 counts before being applied to 1/>2 (Internal) Timer Input Pin r-----. Each individual condition code register bit is explained in the following paragraphs. The interrupt bit (I bit) in the condition code register will also prevent a timer interrupt from being processed. . If an interrupt occurs while this bit is set it is latched and will be processed as soon as the interrupt bit is reset. the stack pointer is set to location $07F.. The source of the clock input is one of the options that has to be specified before manufacture of the MeU. • Zero (Z) Used to indicate that the result of the last arithmetic. Timer I-~.Interrupt Mask Manufactu ring Mask Options N o Write Read T U Timer Control Register 5 E D o Figure 5 Timer Block Diagram 173 . When not required by a code sequence being executed.. I I I I I I _____ . Subroutines and interrupts may be nested down to location $061 which allows the programmer to use up to 15 levels of subroutine calls. They are shown in Figure 4 and are explained in the following paragraphs.

The Timer Interrupt Request bit (bit 7 of Timer Control Register) is set to one by hardware when timer count reaches zero. B. 8 TIMER (Register option) B. 31 Bs 30 Vee B. The Timer Data Register is 8-bit Read/Write Register with address $008 on Memory-Map. Both of those bits can be read by MPU. Upon power up. 16 C. 11 C.HD8806V1-----------------------------------------------------the counter. This allows a program to determine the length of time since a timer interrupt has occured and not disturb the counting process. Connecting a capacitor to the RES input as shown in Figure 8 will provide sufficient delay.2#F 5 XTAL A) 38 A. The timer continues to count past zero and its present count can be monitored at any time by monitoring the timer data register. The bit 6 of Timer Control Register is writable by program. (mask option) see Figure 7. a rrrlnimum of 100 milliseconds is needed before allowing the reset input to go "High" . 32 7 NUM B. 15 C. 13 C 4 10kO 10kn 1o. 39 T As 38 A. All the I/O port are initialized to Input mode (DDR's are cleared) during RESET. • Refer to Figure 9 about crystal option Vee=Pin4 Vss = Pin 1 Figure 6 Self Check Connections Vee OV--------------J REs Pin ----------------~ InterOll' Reset Figure 7 Power Up and RES Timing 174 . 40 A.kn 14 C. 35 A. 29 Co B) 28 10 C. A. 37 2 . This prescaling option must also be specified before manufacturing begins. by the external reset input (imS) and by an internal low voltage detect circuit. 33 HD6806V1. B. 34 6 EXTAL +9V A. This Timer Data Register and the prescaler are initialize with all logical ones at Reset time. This time allows the internal crystal oscillator to stabilize. • RESETS The MCU can be reset three ways: by initial powerup. and is cleared by program or by hardware reset. 27 12 C. 25 9 B. Connect the MCU as shown in Figure 6 and monitor the output of port C bit 3 for an osciIlation of approximately three hertz. 3 iNT 2 REs • SELF CHECK The self check capability of the MCU provides an internal check to determine if the part is functional.

Crystal specifications are given in Figure 10. The different connection methods are shown in Figure 9. A resistor selection graph is given in Figure 11. A manufacturing mask option is available to provide better matching between the external components and the internal oscillator. 1\ XTAL~~EXTAL 5 L---f~ II I C. 4 MHz max) or a resistor is sufficient to drive the internal oscillator with varying degrees of stability. MHz 60n max. Vee Part of HD6805V1 MCU Figure 8 Power Up Reset Delay Circuit 6 EXTAL 6 EXTAL 4 MHz max c::J HD6805V1 MCU 5 XTAL HD6805V1 MCU 5 XTAL 22PF:t20%T Approximately 25% Accuracy External: Jumper 6 EXTAL 6 EXTAL R External Clock Input 5 XTAL HD6805V1 MCU HD6805V1 MCU XTAL 5 No Connection External Clock Approximately 15% Accuracy External Resistor CRYST AL OPTIONS RESISTOR OPTIONS Figure 9 Internal Oscillator Options 5 . 4 ~ N :I: ~ 6 ~ 3 Vee = 5.25V TA = 25°C - ~ \ c: Q) ::l AT Co = f=4 Rs = cr Cut Parallel Resonance Crystal 7 pF max.---------------------------------------------------------HD6805V1 • INTERNAL OSCILLATOR OPTIONS The internal oscillator circuit has been designed to require a minimum of external components. ~ LL 2 ~ ~ ~~ ~~ Figure 10 Crystal Parameters o 5 10 15 20 25 30 Resistance (knl 35 40 Figure 11 Typical Resistor Selection Graph 175 45 50 . The use of a crystal (AT cut.

..CC CLR INT Logic FF . DDR·s Stack PC..A.. Prescaler 7F ... 1 7F . Timer 7F .. FFD TNT: FFA...... SP o ..... TCR Y TIMER Load PC From Reset: FFE. FF9 Fetch Instruction SWI Y Execute Instruction Figure 12 Interrupt Processing Flowchart Output Data Bit I/O Pin Data Direction Register Bit 1 1 0 Figure 13 Typical Port 1/0 Circuitry 176 Output Data Bit Output State Input to MCU 0 0 0 x 3-State Pin .X.. FFB TIMER: FF8........ FFF Load PC From SWI: FFC.HD6805V1--------------------------------------------------------- 1 .

. all I/O pins read latched output data regardless of the logic level at the output pin due to output loading (see Fig. the input data can be read by MPU at $003 address.. Figure 14 provides some examples of port connections.-.. All pins are programmable as either inputs or outputs under software control of the data direction registers. and the other seven input pins (Do"'" 0 6 ) are analog level inputs. D7 (pin 17) is the input pin of V1H (reference level). The example in Figure 16 illustrates the usefulness of the bit manipulation and test • INPUT/OUTPUT There are 24 input/output pins. BCLR).CMOS Inverter C.. • INPUT Port D is 8-bit input port. (b». Ie) Figure 14 Typical Port Connections 177 . All input/output lines are TTL compatible as both inputs and outputs. Figure IS( c) shows the application of Port D to A/D converter. the address of the interrupt routine is obtained from the appropriate interrupt vector address. In the former case. When any interrupt occurs. if the input levels are higher or lower respectively when $001 address is read. and the program branches as a result of its state. the interrupt bit (I) in the condition code register is set. 13). 12. and the interrupt routine is executed. • INTERRUPTS The MeU can be interrupted three different ways: through the external interrupt (INT) input pin. "I" or "0" signals appear at internal data bus. One of them is usual digital signal input port and the other is voltage compare type input port. (a) Ib) +V +V R Bo Port B ••• •• • • · - Port C 10mA max B. their priority. The interrupt service routines normally end with a return from interrupt (RTI) instruction which allows the MeU to resume processing of the program prior to the interrupt. A capacitive touch panel interface and a diode isolated keyboard interface are the examples.---------------------------------------------------------HD6805V1 programmed for outputs. Port C Programmed as output Is) driving CMOS using external pull-up resistors. ROM or I/O allows the user to have individual flags in RAM or to handle single I/O bits as control lines. When port B is Bo Ao ••• • •• • · Port A Port B · ·•• ·• Ie" hFE' 18 B. using the BRSET and BRCLR instructions.. which has two functions. which are compared with VTH (see Figure 15(a). In the latter case. it is capable of sinking 10 millamperes on each pin (VOL = 1V max).. processing is suspended. Port A lines are CMOS compatible as outputs while port Band C lines are CMOS compatible as inputs. Id) Port B Programmed as output(s) driving LED Is) directly. Port B Programmed as outputls) driving Darlington base directly.. When programmed as outputs. This capability to work with any bit in RAM. Any bit in the page zero read only memory can be tested. and the vector address that contain the starting address of the appropriate interrupt routine. the internal timer interrupt request. the present MeU state is pushed onto the stack. Table 1 Interrupt Priorities Priority Vector Address $FFE and $FFF SWI 1 2 TNT 3 $FFA and $FFB TIMER 4 $FF8 and $FF9 Interrupt RES" $FFC and $FFD • BIT MANIPULATION The MCU has the ability to set or clear any single random access memory or input/output bit (except the data direction registers) with a single instruction (BSET. A flowchart of the interrupt processing sequence is given in Fig. and Figure IS(d) shows 3 levels inputs. ··• ·· 1 . This function is effective in such case that unusual logic level inputs are used. Port A Programmed as output(s) driving CMOS and TTL Load directly. Table 1 provides a listing of the interrupts. and a software interrupt instruction (SWI).

5V) 0.0V .Bit6) + $003 Read Input Port (07) Internal Bus (Bit 7) (a) The logic configuration of Port 0 Port ~- C 07 Reference Level 0. The timer could also be incorporated to provide tumon at some later time which would permit pulse-width modillation of the controlled power. Port 3 Levels Input 6 ~ 0 Do (c) Application to AID convertor Input Voltage ($003) ($007) OV-0. instructions. Port o 0. This program. Assume that bit 0 of port A is connected to a zero crossing detector circuit and that bit 1 of port A is connected to the trigger of a TRIAC which power the controlled hardware.0 6) Internal Bus (BitO .7V.3.3V 1 1 0 3. which uses only seven ROM locations. pro- $003 Read Input Port (00. Port Analog Input 6 ) 0 Do 0.V CC 1 3 Levels Input 0 (d) Application to 3 levels input Figure 15 Configuration and Application of Port 0 178 .HD6805V1--------------------------------------------------------vides tum-on of the TRIAC within 14 microseconds of the zero crossing. r-"----Analog Input 6 Do r----Analog Input 0 Analog Input 0 (b) Seven analog inputs and a reference level input of Port 0 r 10 1 VTH (= 3.8V 0 0 2.

and control. control instructions such as SWI. In this mode. In direct addressing. POAT A. These instructions are three bytes long. Refer to Figure 22. Direct operations on the accumulator and the index register are included in this mode of addressing. modify or test its contents. ReI is the contents of the location following the instruction opcode with bit 7 being the sign bit. The third byte is the relative address to be added to the program counter if the branch condi~ tion is met. Thus. All the information necessary to execute an instruction is contained in the opcode. 179 The control instructions control the MCV operations during program execution. • Bit Manipulation Instructions These instructions are used on any bit in the first 256 bytes of the memory. One operand is either the accumulator or the index register. The effective address (EA) is the PC and the operand is fetched from the byte following the opcode. • Read/Modity/Write Instructions These instructions read a memory location or a register. • Relative Refer to Figure 20. If the branch is not taken Rel=O. The immediate addressing mode accellses constants which do not change during program execution. All RAM space. Instructions which use this addressing mode are three bytes long. when a branch takes place. Direct addressing allows the user to directly address the lowest 256 bytes in memory. The implied mode of addressing has no EA. Refer to Table 2. The byte to be tested is addressed by the byte following the opcode. • Register/Memory Instructions Most of these instructions use two operands. This mode of addressing applies to instructions which can test any bit in the first 256 locations ($OO-$FF) and branch to any location relative to the PC. RTI belong to this group. The EA is the contents of the two bytes following the opcode. These instructions are two bytes long. These instructions occupy two bytes. One group either sets or clears. Refer to Table 3. Refer to Table 4. • INSTRUCTION SET The MCV has a set of 59 basic instructions. Such instructions are two bytes long. The EA is calculated by adding the contents of the byte following the opcode to the contents of the index register. They are explained and illustrated briefly in the following paragraphs. I/O registers and 128 bytes of ROM are located in page zero to take advantage of this efficient memory addressing mode. The value of the bit tested is written to the carry bit in the condition code register. POAT A • Bit Test and Branch The MCV has ten addressing modes available for use by the programmer. The jump unconditional (JMP) and jump to subroutine (JSR) instructions have no register operand. In this mode the contents of the byte following the opcode is added to the program counter when the branch is taken. SELF 1 B5ET 1. the program goes to somewhere within the range of + 129 bytes to -127 of the present instruction. The individual bit within that byte to be tested is addressed by the lower three bits of the opcode. The lower three bits in the opcode specify the bit to be set or cleared while the byte following the opcode specifies the address in page zero. • Opcode Map Table 8 is an opcode map for the instructions used on the MCV. . and write the modified value back to memory or to the register. Rejer to Figure 25. The test for negative or zero (TST) instruction is an exception to the read/modify/write instructions since it does not perform the write. • Indexed (No Offset) Refer to Figure 21. • • ·· · Figure 16 Bit Manipulation Example • ADDRESSING MODES Immediate Refer to Figure 17. The relative addressing mode applies only to the branch instructions. 511 low memory locations are accessable. The complete instruction set is given in alphabetical order in Table 7. This addressing mode calculates the EA by adding the contents of the two bytes following the opcode to the index register. The other group performs the bit test and branch operations. The other operand is obtained from memory using one of the addressing modes. Refer to Table 5.----------------------------------------------------------HD6805V1 SELF 1 ·· ·· • Bit Set/Clear Refer to Figure 24. The following paragraphs briefly explain each type. • Direct Refer to Figure 18. read/modify / write. • Control Instructions • • Alphabetical Listing Indexed (16-bit Offset) Refer to Figure 23. This mode of addressing applies to instructions which can set or clear any bit on page zero. These instructions are one byte long and their EA is the contents of the index register. POAT A BClA 1. In addition. bit manipulation. BAClA 0. the address of the operand is contained in the second byte of the instruction. This mode of addressing accesses the lowest 256 bytes of memory. Refer to Table 6. branch. • Branch Instructions The branch instructions cause a branch from the program when a certain condition is met. All the instructions within a given type are presented in individual tables. They can be divided into five different types: register/memory. EA=(pC)+2+Rel. • Extended Refer to Figure 19. All implied addressing instructions are one byte long. Extended addressing instructions are three bytes long. • Indexed (8-bit Offset) Implied Refer to Figure 26. Extended addressing is used to reference any location in memory space. the entire memory space may be accessed.

HD8805V1--------------------------------------------------------EA Memory i I I I I 8 A Stack Point I PROG LOA #$F8 OSBE OSBF I I A6 Prog Count 1-------1 OSCO F8 CC I I § I I I I Fipure 17 Immediate Addressing Example ~ lEA Memory I i I I I I I I I I FCB 32 LOA CAT / Adder 1 I '" A Joo 20 OO4B I L 0520 B6 052E 4B I Stack Point I I Prog Count 052 F CC ~ I I I I Figure 18 Direct Addressing Example 180 20 I Index Reg I I PROG 004B I I CAT I I I .

I .--------------------------------------------------------HD6806V1 Memory i I I I I ~ I PROG LOA CAT -~J O4OA 06 040B E5 64 40 Index Reg Stack Point I I I FCB A I I CAT 0000 Prog Count 40 06E5 040C CC Figure 19 Extended Addressing Example EA Memory 04C1 i I @ A Index Reg Stack Point I PROG BEQ PROG2 04A 7 0000 27 t--------1 O4A8 18 04C1 ~ I . Figure 20 Relative Addressing Example 181 .

X 0758 E6 075C 89 I I Prog Count I 075E CC I § .I Figure 22 Indexed (8-Bit Offset) Addressing Example 182 .HD6805V1--------------------------------------------------------- Memory A TABL FCC / LI /00B8 4C 4C 49 Index Reg B8 I PROG LOA X I Stack Point 05F4~ Prog Count 05F5 CC § Figure 21 Indexed (No Offset) Addressing Example Memory TABL FCB #BF 0089 BF FCB #86 OOBA 86 FCB #OB 008B DB CF FCB #CF 008C CF Index Reg 03 Stack Point PROG LOA TABL.

X 0692 0693 02 I ~6 Stack Point 07 0694 ~---~ 7E Prog Count 0695 . PORT B 058F ' -_ _ _ 1D _ _--I 0590 Stack Point 01 Prog Count 0591 I I t@ I I I I Figure 24 Bit Set/Clear Addressing Example CC ..---------------------------------------------------------HD6806V1 Memory I I § A DB Index Reg I PROG lDA TABl. I TABl FCB #BF 077E FCB #86 077F FCB #DB 0780 FCB #CF 0781 CC I BF 86 I-__~D~B_ __t--------------~ CF Figure 23 Indexed (16-Bit Offset) Addressing Example Memory PORTB EaU BF 0001 A 0000 Index Reg PROG BClR 6..

HD8806V1------------------------------------------------------ PORT C EQU 2 FO 0002 A Index Reg 0000 Stack Point PROG BRCLR 2. Figure 25 Bit Test and Branch Addressing Example Memory I I I I I ~ A E5 Index Reg I I PROG TAX E5 I I O~AR Prog Count I I I I I 0588 CC I § Figure 26 Implied Addressing Example 184 . PORT C. PROG 2 0574 05 Prog Count 1------1 0575 02 0576 10 I 0000 0594 CC I ~ I L -______________________________________ ~ .

---------------------------------------------------------HD6806V1 Table 2 Register/Memory Instructions Addressing Modes Function Mnemonic Immediate Indexed (No Offset) Extended Direct Op Op Op # # # # Code Bytes Cycles Code Bytes Cycles Code Op # # Bytes Cycles Code Indexed (8-Bit Offset) Op # # Bytes Cycles Code Indexed (16-BitOffset) Op # # Bytes Cycles Code # # Bytes Cycles Load A from Memory LOA A6 2 2 B6 2 4 C6 3 5 F6 1 4 E6 2 5 06 3 6 Load X from LOX AE 2 2 BE 2 4 CE 3 5 FE 1 4 EE 2 5 DE 3 6 Store A in Memory STA - - B7 2 5 C7 3 6 F7 1 5 E7 2 6 07 3 7 Store X in Memory STX - - - BF 2 5 CF 3 6 FF 1 5 EF 2 6 OF 3 7 Add Memory to A ADD AB 2 2 BB 2 4 CB 3 5 FB 1 4 EB 2 5 DB 3 6 Add Memory and Carry to A AOC A9 2 2 B9 2 4 C9 3 5 F9 1 4 E9 2 5 09 3 6 Subtract Memory SUB AO 2 2 BO 2 4 CO 3 5 FO 1 4 EO 2 5 DO 3 6 Subtract Memory from A with Borrow sac A2 2 2 B2 2 4 C2 3 5 F2 1 4 E2 2 5 02 3 6 6 Memory AND Memory to A AND A4 2 2 B4 2 4 C4 3 5 F4 1 4 E4 2 5 04 3 OR Memory with A ORA AA 2 2 BA 2 4 CA 3 5 FA 1 4 EA 2 5 DA 3 6 Exclusive OR Memory with A EOR AS 2 2 B8 2 4 C8 3 5 F8 1 4 E8 2 5 08 3 6 Arithmetic Compare A with Memory CMP A1 2 2 B1 2 4 C1 3 5 Fl 1 4 El 2 5 01 3 6 Arithmetic C:ompare X with Memory CPX A3 2 2 B3 2 4 C3 3 5 F3 1 4 E3 2 5 03 3 6 Bit Test Memory with A (Logical Compare) BIT A5 2 2 B5 2 4 C5 3 5 F5 1 4 E5 2 5 05 3 6 Jump Unconditional JMP - 2 3 CC 3 4 FC 1 3 EC 2 4 DC 3 5 JSR - - BC Jump to Subroutine - BO 2 7 CD 3 8 FO 1 7 ED 2 8 DO 3 9 Table 3 Read/Modify/Write Instructions Addressing Modes Function Implied (X) Implied (A) Mnemonic Op Code Op # # Bytes Cycles Code Indexed (No Offset) Direct Op # # Bytes Cycles Code Op # # Bytes Cycles Code Indexed (8-Bit Offset) Op # # Bytes Cycles Code # # Bytes Cycles Increment INC 4C 1 4 5C 1 4 3C 2 6 7C 1 6 6C 2 7 Decrement DEC 4A 1 4 5A 1 4 3A 2 6 7A 1 6 6A 2 7 Clear CLR 4F 1 4 5F 1 4 3F 2 6 7F 1 6 6F 2 7 Complement COM 43 1 4 53 1 4 33 2 6 73 1 6 63 2 7 Negate (2's Complement) NEG 40 1 4 50 1 4 30 2 6 70 1 6 60 2 7 Rotate Left Thru Clrry ROL 49 1 4 59 1 4 39 2 6 79 1 6 69 2 7 Rotate Right Thru Clrry ROR 46 1 4 56 1 4 36 2 6 76 1 6 66 2 7 Logical Shift Left LSL 48 1 4 58 1 4 38 2 6 78 1 6 68 2 7 Logical Shift Right LSR 44 1 4 54 1 4 34 2 6 74 1 6 64 2 7 Arithmetic Shift Right ASR 47 1 4 57 1 4 37 2 6 77 1 6 67 2 7 Arithmetic Shift -Left ASL 48 1 4 58 1 4 38 2 6 78 1 6 68 2 7 Test for Negative or Zero TST 40 1 4 50 1 4 3D 2 6 70 1 6 60 2 7- 185 .

.... 7) - - # # Cycles Op Code Bytes Cycles - 2-n 3 10 01+2-n 3 10 - - Set Bit n BSET n (n=O . 7) 11+2-n 2 7 - - Table 6 Control Instructions Implied Function Mnemonic Op Code # # Bytes Cycles Tiansfer A to X TAX 97 1 2 Transfer X to A TXA 9F 1 2 2 Set Carry Bit SEC 99 1 Clear Carry Bit ClC 98 1 2 Set Interrupt Mask Bit SEI 9B 1 2 Clear Interrupt Mask Bit CLI 9A 1 2 Software Interrupt SWI 83 1 11 Return from Subroutine RTS 81 1 6 Return from Interrupt RTI 80 1 9 Reset Stack Pointer RSP 9C 1 2 No-Operation NOP 90 1 2 186 ........... 7) - Branch I F Bit n is clear BRClR n (n=O .HD6805V1-------------------------------------------------------Table 4 Branch Instructions Relative Addressing Mode Function Mnemonic Op Code # # Bytes Cycles 4 Branch Always BRA 20 2 Branch Never BRN 21 2 4 Branch IF Higher BHI 22 2 4 Branch I F lower or Same BlS 23 2 4 Branch I F Carry Clear BCC 24 2 4 (Branch IF Higher or Same) (BHS) 24 2 4 Branch I F Carry Set BCS 26 2 4 (Branch IF lower) (BlO) 26 2 4 Branch I F Not Equal BNE 26 2 4 4 Branch I F Equal BEQ 27 2 Branch I F Half Carry Clear BHCC 28 2 4 Branch I F Half Carry Set BHCS 29 2 4 Branch I F Plus BPl 2A 2 4 Branch I F Minus BMI 2B 2 4 Branch I F Interrupt Mask Bit is Clear BMC 2C 2 4 Branch I F Interrupt Mask Bit is Set BMS 20 2 4 Branch I F Interrupt Line is low Bil 2E 2 4 Branch IF Interrupt Line is High BIH 2F 2 4 Branch to Subroutine BSR AD 2 8 Table 5 Bit Manipulation Instructions Addressing Modes Function Mnemonic Bit Set/Clear Op Code Bit Test and Branch # # Bytes Branch IF Bit n is set BRSET n (n=O . 7) 10+2-n 2 7 - Clear bit n BClR n (n=O ...

Cleared Otherwise Not Affected Z_E!ro 187 .• • • • • • 0 1\ 1\ 1\ 1\ 1\ 1 1\ 1\ 1\ 1\ 1\ /\ • 1\ 1\ • • • • • • • • • • • • • • • • • • • • 1\ 1\ • • 0 • • 1\ 1 1\ • • • • • 1\ • • • • • • • • • • 1\ 1\ • • /\ 1\ • (to be continued) C 1\ • Carry Borrow Test and Set if True.-----------------------------------------------------------HD6805V1 Table 7 Instruction Set Addressing Modes Mnemonic Implied Immediate Direct Extended Relative ADC x x x ADD x x x x x x x AND ASL x x ASij x x Condition Code Indexed Indexed Indexed (No (8 Bits) (16 Bits) Offset) x x x Bit Set/ Clear x x BHCC x BHCS x BHI x BHS x BIH x x BIL x BIT x x x BLS BMC x x BMI x BMS x BNE x BPL x BRA x BRN x x COM x x CMP x • • • • • • • x x DEC x x x x x x x x x x x x x x x JMP x x x x x x x x x x x LOA x x x x x x x LOX x x x x x x JSR Condition Code Symbols: H Half Carry (From Bit 3) I Interrupt Mask N Negative (Sign Bit) 1\ 1\ 1\ 1\ • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 1\ 1\ • • • • • • x x x x INC x x x x EOR x x x x CPX x 1\ 1\ x x CLR 1\ 1\ 1\ 1\ 1\ • • • • • • • • x x 1\ x BSET x • • • • • • • • • • • x x x CLI 1\ x BRSET CLC C x BRCLR BSR Z x x BLO N 1\ x BCS I x BCLR BEQ H x x BCC Z Bit Test & Branch x • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 0 • • • • • -.

Cleared Otherwise Not Affected Load CC Register From Stack 188 • • • • • • • • • • • I N Z • • • • • • • • ? • • • 1 • • 1\ 0 1\ 1\ 1\ 1\ 1\ 1\ 1\ • C • • • 1\ 1\ • 1\ 1\ 1\ 1\ 1\ 1\ • • • ? ? 7 • • • 1\ 1\ 1\ • • 1 • • • 1\ 1\ • 1\ 1\ • 1\ 1\ 1\ • • • • • • • • 1\ 1\ • • • • • 1 .HD6806V1--------------------------------------------------------Table 7 Instruction Set Addressing Modes Mnemonic LSL LSR NEG NOP ORA ROL ROR RSP RTI RTS SBC SEC SEI STA STX SUB SWI TAX TST TXA Implied Immediate x x x x Direct Extended Relative x x x x x x x x x x x x x Condition Code Indexed Indexed Indexed (No (8 Bits) (16 Bits) Offset) x x x x x x x x x x x x Bit Setl Clear x Bit Test & H Branch • • • • • • • • ? x x x x x x x x \ x x x x x Condition Code Symbols: H Half Carry (From Bit 3) I I nterrupt Mask N Negative (Sign Bit) Z Zero x x x x x x X x x x x C 1\ • ? x x x x x x x Carry/Borrow Test and Set if True.

189 o AND BIT A I 1/6 SBC CPX ADD - HIGH 0 1 SEI ClR I 2/7 +- - Bil I 1/4 F ADC BIH I 1/4 . Undefined opcodes are marked with "-". The' number at the bottom of each column denote the number of bytes and the number of cycles required (Bytes/Cycles)... require a different number of cycles as follows: RTI 9 RTS 6 SWI 11 BSR 8 3. Mnemonics followed by a ..XO IMP IMP IMM 7 8 9 A Rei DIR 1 2 3 BSETO BRA NEG RTI· - - I A 4 I X 5 I 6 I 1 BRClRO BClRO BRN BRSET1 BSET1 BHI - RTS· 2 3 BRClR1 BClR1 BlS COM SWI· 4 BRSET2 BSET2 BCC lSR 5 BRClR2 BClR2 BCS - - I DIR I EXT I B I C BRSET3 BSET3 BNE ROR - - 7 BRClR3 BClR3 BEQ ASR TAX 8 BRSET4 9 BRClR4 BSET4 BHCC lSl/ASl BClR4 BHCS ROl BRSET5 BSET5 BPl DEC - B BRClR5 BClR5 BMI - C BRSET6 BSET6 BMC INC D BRClR6 BClR6 BMS TST - I 2 3 l 4 5 W lDA 6 STA(+1) 7 EOR B RSP NOP I JMPH) C BSR·I JSR(-3) D - TXA - I 1/· 1/2 2/2 I - 2/4 I 3/5 lDX E STX(+1) F I 3/6 I 2/5 1. ( indicate that the number in parenthesis must be added to the cycle count for that instruction. 2..XO ORA BSET7 2/6 I CLI BClR7 2/4 E SEC F BRClR7 2/7 I 8 9 ClC E BRSET7 3/10 D CMP - (NOTE) I X2 I Xli I SUB - 6 A RegisterIMemory Control Read/ModifyJWrite Branch I 1/4 .X1 I .---------------------------------------------------------HD8806V1 Table 8 Bit Manipulation Test & Branch Clear 0 0 BRSETO Setl Opcode Map I I I .

Vee XTAl EXTAl NUM TIMER Co C. A~ A. B2 B. standby RAM. 10~ AN~/03 AN3/0. 4-channel Internal A/D Converter • Internal Clock Circuit • Self·Check Mode • Master Reset • Low Voltage Inhibit • Complete Development System Support by Evaluation Kit • 5 Vdc Single Supply • • • • • • • • • • • • • • -PRELIMINARY - HD6805WOP (DP-40) • PIN ARRANGEMENT A. B. This MCU is a memo ber of the HD680S family but compared with HD680SS. A. IC/C s DC/C 6 10 0 INT~ ANo/O. it is a single·chip microcomputer with strengthened internal functions of standby RAM. B6 Bs B. Vss A6 RAME/RES INT. on·chip clock. Bo AVee AVss VRH/O s Vee Standby C~ C3 C.2 External and 4 Timers • 23 TTL/CMOS compatible I/O Lines. RAM. timers and I/O. I/O and two timers. (Top View) 190 . 8 Lines LED Direct Drive • 8-Bit.HD6805WO------------MCU (Microcomputer Unit) The HD680SWO is an 8-bit microcomputer unit (MCU) which contains a CPU. ROM. RAM and I/O Compatible with MC6805P2. The following are some of the hardware and software high· lights of the MCU. HD6805S1 and HD6805V1 As A. AN. Ao B. AID Converter. • HARDWARE FEATURES • 8-Bit Architecture • 96 Bytes of RAM (8 bytes are standby RAM functions) • Memory Mapped 1/0 • 3834 Bytes of User ROM • Internal 8-Bit Timer (Timer 1) with 7-Bit Prescaler • Internal 8-Bit Programmable Timer (Timer 2) • Interrupts . A/D Converter. SOFTWARE FEATURES Similar to HD6800 Byte Efficient Instruction Set Easy to Program True Bit Manipulation Bit Test and Branch Instructions Versatile Interrupt Handing Powerful Indexed Addressing for Tables Full Set of Conditional Branches Memory Usable as Registers/Flags Single Instruction Memory Examine/Change 10 Powerful Addressing Modes All Addressing Modes Apply to ROM.

.: "o~ f!os.2 Port 0 Input Lines . CPU Port C I/O Lines Stack Point Output Compare (OC) 8 Register Input Capture (IC) 8 Register 6 Port A I/O Lines Ao AI A2 A3 A... ~.. Do IINT 2 ) 0 1 (AND) O2 (ANd 03 (AN 2 ) D... c: Co CI C2 C3 C... As A6 A. Bo BI B2 B3 B. SP c: Program Counter "High" 4 PCH Timer Control 8 Register 2 "Low" ~ 0 '.. ... (AN 3 ) 05 (VRH) g Ia Q) oa: (RAME) Vee Standby ADC Lines .... . 0 0. ..~ Program Counter 8 0 ----. Cs II C) C6 (OC) . B5 B6 B..AVSS _~--~--~~----(VRH) (ANo) (ANI) (AN 2 ) (AN 3 ) A/D Control Status Register 8 AID Result Register 8 (NOTE) 191 The contents of ( ) items can be changed by software.. u Q) AlU '0 PCl Q) a: c5! () oa: 0.---------------------------------------------------------HD6805WO • BLOCK DIAGRAM TIMER 7 8 Port B I/O Lines TIMER-2 c: Accumulator A 8 7 Prescaler 2 Prescaler Control 8 Register 2 Timer Data 8 Register 2 CPU Control Timer 8 Status Register 2 '0 o~ al co·~ 10~ X Condition Code Register CC 5 '£ .AVee .~ ~ Index Register 8 ~ 0 oa: Q) a: .. ~ '0 Q) a: « 1:: 0 0....--..:.

8 V V 0.75 5.F 100 - - ms - 25 30 pF - 6 10 pF I nput Capacitance I J EXTAL All Others Cln 192 Rep =15.25V ±0.8 V 0.4 - 4. = 2.3 Power Dissipation Po - Low Voltage Recover LVR Low Voltage Inhibit LVI - TIMER Input Leak Current -20 INT IlL V ln =O·4V-V ee XTAL(Crystal Mode) Standby Voltage Standby Current -50 Vee V Vee 15.A -1200 - 0 JJ.0 - 5. unless otherwise noted. Vss = GND.0 - Vee V INT 3. Ta = 0 -+70°C.+7. Ta =0 -+70°C.0 RES -0. Vss = GND.0 This device has an input protection circuit for high quiescent voltage and field.0 o -+70 Storage Temperature Tstg -55 . unless otherwise notedJ min typ max Unit RES 4.+15.0 Self-Check Mode Input "Low" Voltage 9.0V - 3 V mA • AC CHARACTERISTICS (Vee = 5.A Nonoperation Time V SBB 4. To insure normal operation.A Symbol Item Input "High" Voltage Test Condition V IH All Others 2. be careful not to impress a high input voltage than the insulation maximum value to the high input impedance circuit.HD6805VVO---------------------------------------------------------• ABSOLUTE MAXIMUM RATINGS Symbol Item Supply Voltage Value Vee Input Voltage (EXCEPT TIMER) V in Input Voltage (TIMER) V -0.3 All Others (except XTAL) V IL -0.0kO±1% Vin=OV 2. - - 100 ms Delay Time Reset tRHL External Cap.8 V 850 mW JJ.5V.0 Timer Mode Input "High" Voltage Timer 2.75 V 4.0 JJ.3 INT -0.0 - V 20·· 50 JJ.2 JJ.0 MHz 1.s MHz - ns Time VSBB=4.75 Nonope~ation ISBB - min typ max Unit 0. however.7 .75 Operation Time V SB 4.3 .0 V V °c °c Operating Temperature T oDr -0.5V.0 - Vee V - 4.3 -+7.25V ±O.+150 (NOTE) Unit -0.) Item Symbol Clock Frequency Test Condition fel Cycle Time tcyc Oscillation Frequency (External Resister Mode) fexT INT Pulse Width tlwL t cvc+ 250 - RES Pulse Width tRwL t cvc + 250 - - ns TIMER Pulse Width tTWL c+ tc"5 2 0 - - ns Oscillation Start-up Time (Crystal Mode) tose CL =22pF±20% Rs=600 max.0 10 4.3 .0 V 0. the following are recommended for Vln and V out : Vss ~ (Vln or Vout ) ~ Vee • ELECTRICAL CHARACTERISTICS • DC CHARACTERISTICS (Vee = 5.

AVec = 5.1 0 - V - - 7.25 V Reference Voltage AVss -0. Ta=25°C.0V. AVec = 5.8V Vin = 2V V in = O. VRL Ta = 25°C =OV. VRH =5.25 V AV in VRH 0 - 5. B. otherwise noted.0V - - ±1/2 LSB Absolute Accuracy Ta = 25°C.5 - 2.3 - Vee 0.5V.) -300 -20 V V V V V V - ~A 20 JlA =AVss = GND.--------------------------------------------------------HD6806VVO • PORT ELECTRICAL CHARACTERISTICS (Vee =5.5 pF 2. AVec =4. Vss . Vss = GND. VRH = 5. C and 0 • A/D CONVERTER ELECTRICAL CHARACTERISTICS (Vee =5.0 V V IH 2.4 V - - 1.0 5.0V - - 1.4 - IOH = -1 mA Port C IOH Ports A and C IOL VOL Port B = -100 ~A IOL = 10 mA Ports A. On-channel AV1n =5V 193 .5V.75V.0V.75 5. AVec = 5.0V.4 - IOH = -200~A 2.5 kfl - 8 76 4 - Bit - Channel Item Analog Power Supply Voltage Symbol Analog Input Voltage Test Condition Analog Multiplexer Input Capacitance Ladder Resistance VRH = 5. unless otherwise noted.4 = 3.0V. VRH = 5.4V-V ee IlL Ports B.25V.6 mA - - 0.5 - 12.0 - V IL -0.0V.0V - - ±1/2 LSB Offset Error Ta = 25°C.4 - - IOL = 1.0V - ±1/4 ±3/8 LSB Quantum Error Ta = 25°C. AVec = 5. Ta = 0-+70°C. AVec = 5. Ta =0 - Item Symbol Port A Output "High" Voltage Output "Low" Voltage Input "High" Voltage Input "Low" Voltage I nput Leak Current Test Condition min typ max Unit IOH =-10~A 3. AVec =4.2 mA - 0.0V. VRH = 5. unless min typ max Unit AVec 4. ±0. Ta=25°C.8 V -500 - - ~A V OH Port B +70°C. On-channel AV1n=OV AVln =OV. C and 0 Port A V in = 0.25V ±0.75V.0 LSB - 10 100 nA -100 -10 - nA Off-channel Leak Current Off-channel Leak Current AV1n =5.0V.5 - - V 1.0 V Reference Voltage - 5 AVec +0.0V - ±1/4 ±3/8 LSB Full-scale Error Ta = 25°C. Resolution Power Conversion Time at 4MHz I nput Channels ~s Non-Linearity Error Ta = 25°C.) IOH = -100 ~A 2. VRH =5.

A crystal (AT cut. $003 address is read and they become Port D function. Refer to the section on INPUTS/ OUTPUTS for details." U .. Figure 1 Bus Timing Test Loads • SIGNAL DESCRIPTION The input and output signals for the MCU shown in PIN ARRANGEMENT are described in the following paragraphs.4k!l 24 k!l 1. (1) Software • Write "0" into the RAM enable bit (RAME). Load capacitance includes the floating capaci. • Maintain Vee standby voltage above VSBB (main). 4MHz maximum) or a resistor can be connected to these pins to provide the internal oscillator with varying degrees of stability. RAME is set to "0" and Vee is set off.6 mA Test Point Test Point 30 pF 12 k!l 2. Refer to INTERRUPTS for additional information. (Ports A. • XTAL and EXTAL These pins provide control input for the on-chip clock circuit. • Vee Standby When source voltage Vee is down. • I/O Lines (Ao ~ A 7 . • INT 1 /INT 2 This pin provides the capability for applying an external interrupt to the MCU. (Port B) TTL Equiv.SV. • TIMER This pin allows an external input to be used to count for the internal timer circuitry. The content of the low order 8 bytes are maintained when source voltage is off (3 rnA max. Vee is S. RAME is bit 6 of the RAM control register location SOIF.).). Since this operation disables the RAM standby part.2 mA 40pF (NOTE) Ii = 1. . source voltage SV ±S% is impressed to this pin to maintain standby RAM. Refer to INTERNAL OSCILLATOR OPTIONS for recommendations about these inputs. Refer to TIMER for additional inform~ion about the timer circuitry. 2. • RES This pin allows resetting of the MCU at times other than the automatic resetting capability already in the MCU. contents are 'present with power source off. • Vee andVss Voltage is supplied to the MCU using these two pins. All diodes are 1S2074(8) or equivalent. 8 0 ~ 8 7 . • Input Lines (Do '" Os) Since the input for these 6 lines is TTL compatible. the RAM contents are maintained.. standby is connected to Vee· Vee Stoodby T P". When standby RAM is not needed.HD6805WO-------------------------------------------------------TTL Equiv. Co'" C6 ) There 23 lines are arranged as three ports (A. is for the external control of standby RAM. the following hardware and software procedures are necessary. All lines are programmable as I/O under software control of the data direction registers. To maintain the RAM contents when source voltage is off. • NUM This pin is not for user application and should be connected to ground. The same type of function as this can be realized by software by setting the RAM control register ($OIF) RAME (bit 6) to "0".2SV ±O. like RES. After power up. Refer to RESETS for additional information. B and C). (2) Hardware • Set RAME pin to "0" before setting Vee to off. Since RAM is disabled.tance of the probe and the jig etc. The circuit in Figure 2 is an example of a circuit for maintaining Vee standby voltage when source voltage is off. C and D) Vee Ii = 3. • Maintain Vee standby voltage above VSBB (min. 194 Figure 2 Battery Backup for Vee Standby • RAME This pin. Vss is the ground connection.

Port A SOOO Port B $001 Port C $002 Timer $OlF $020 031 032 RAM 196 BI 127 128 $07F $080 Port 0 S003' . the low order byte (PCL) of the program counter is stacked first. the contents of the MCV registers are pushed onto the stack in the order shown in Figure 4. 1 $009 Miscellaneous Reg. Specification of the positive or negative edge is set by bit 1 of the timer control register 2 ($018). The specification is for 000 $000 1/0 Ports positive edge when bit 1 is "1" and for the negative edge when bit 1 is set to "0". PCL) contents to be pushed onto the stack. 2 S019 Timer Status Reg. DC pin output is "0". • ANo .5V Connect to Vee for all other cases. 4095 ·-Read Reg $FFF •• ·Standby RAM uses f. 2 SOlC Output Compare Reg. AVss is fixed at OV. SooA SooB SOOC SooO AID eTA L Status Reg AID Result Reg SooE SooF" SOlO SO 11 S012 S013 $014 SOlS S016 S017 S018 3961 $F78 3962 SF79 Prescaler eTA L Reg. • VRH and AVss The input terminal reference voltage for the AID converter is "High" (VRH) or "Low" (AVss).----------------------------------------------------------HD6805VVO • AVec This pin is used for the power supply of the AID converter.AN3 This pin is used for AID converter analog input. These signals are switched by the internal multiplexer and the analog input selection uses bit 0 through bit 1 of the AID control status register (ADCSR: $OOE). the DDR of port C5 is set to "0". When high accuracy is requested. During the interrupt processing. • Input Capture (lC) The timer data register ($01 C) contents are managed by input capture register ($OIE) due to the positive or negative edge of this pin.timer data register 2 ($01C) contents are the same. This ensures that the program counter is loaded correctly as the stack pointer increments when it pulls data from the stack.1 $008 $007 ROM 13834 BI Timer eTA L Reg. In this case. a different power source than Vcc is impressed as AVec =5. this pin is used for data output. SOlD Input Capture Reg SOlE" RAM Control Reg SOlF Standby RAM 18 BI'" $020 S S027 Self·te . When bit 0 is "1". Since the stack pointer decrements during pushes.. A subroutine call will cause only the program counter (pCH. 2 SOlA" Timer eTR L Reg. Port A DDR $004' Port BOOR S005' Port C ODR S006' Timer Data Aeg. Data desired for output is specified by bit 0 of timer control register 2 ($018).25 ±O. then the high order three bits (PCH) are stacked. ROM 1120BI 4081 SFFl 4082 SFF2 -----------------RAM 196 BI Interrupt Vectors sr S028 ~ S07F ·WriteReg. • MEMORY The MCV memory is configured as shown in Figure 3. DC pin output is "1" and when bit 0 is "0". In this case. 2 SOlB Timer Data Reg. • Output Compare (OC) When the output compare register ($OID) and . An analog signal is used for input during measure.rst 8 bytes of RAM Figure 3 MCU Memory Structure 195 . DDR of port C6 is set to "1".

Carry/Borrow (C) Carry/borrow is used to indicate that a carry or borrow out of the arithmetic logic unit (ALV) occurred during the last arithmetic operation. Figure 4 Interrupt Stacking Order • Stack Pointer (SP) The stack pointer is a 12-bit register that contains the address of the next free location on the stack. n+1 n-3 n-1 • Pull REGISTERS The MeV has five registers available to the programmer. shifts and rotates. fetching the timer 1 interrupt vector from locations $FF8 and $FF9 and executing the interrupt routine. When the timer data register 1 (TORI) reaches zero. The timer 1 continues to count past zero and its present count can be monitored at any time by monitoring the timer data register 1 This allows a program to determine the length of time since a . Each individual condition code register bit is explained below. The index register can also be used for limited calculations or data manipulations when using read/modify/write instructions. The MCV responds to this interrupt by saving the present MCV s. Initially. Program Counter 0 SP Interrupt (I) This bit is set to mask everything. • Program Counter (PC) The program counter is a 12-bit register that contains the address of the next instruction to be executed. the stack pointer is set to location $07F and is decremented as data is being pushed onto the stack and incremented while data is being pulled from the stack. Negative Interrupt Mask Half Carry • Figure 5 Programming Model • Accumulator (A) The accumulator is a general purpose 8-bit register used to hold operands and results of arithmetic calculations or data manipulations. 0 PC Half Carry (H) The half carry bit is used during arithmetic operations (ADD or ADC) to indicate that a carry occurred between bits 3 and 4. If an interrupt occurs while this bit is set. the timer interrupt request bit (bit 7) in the timer control register 1 is set. Note that when tP2 is used as the source. The six most significant bits of the stack pointer are permanently set to 000001. logical or data manipulation was negative (bit 7 in a result equal to a logical one). Subroutines and interrupts may be nested down to location $041 which allows the programmer to use up to 31 levels of subroutine calls. The interrupt bit (I bit) in the condition code register will also prevent a timer 1 interrupt from being processed. The timer 1 interrupt can be masked by setting the timer interrup-t mask bit (bit 6) in the timer control register 1. 196 TIMER 1 The MCV timer circuitry is shown in Figure 6. 7 0 I A 11 I I I 11 6 5 1010101010111 Index Register • Negative (N) The negative bit is used to indicate that the result of the last arithmetic. as shown in Figure 5 and explained below.HD6806VVO-------------------------------------------------------6 n-4 1 5 1 4 3 2 0 Condition 11 Code Register Accumulator n+2 n-2 Index Register n+3 1 1 1 1 11 PCH* PCl* n n+4 n+5 Push * For subroutine calls. it is latched and will be processed as soon as the interrupt bit is reset. During an MCV reset or reset stack pointer (RSP) instruction. This bit is also affected during bit test and branch instructions. The 8-bit counter is loaded under program control and counts down toward zero as soon as the clock input is applied. When not required by a code sequence being executed. • Index Register (X) The index register is an 8-bit register used for the indexed addressing mode and contains an 8-bit address that may be added to an offset value to create an effective address.tate in the stack. only PCH and PCl are stacked • Condition Code Register (CC) The condition code register is a 5-bit register in which each bit is used to indicate or flag the results of the instruction just executed. logical or data manipulation was zero. These bits can be individually tested by a program and specific action taken as a result of their state. the index register can be used as a temporary storage area. • Accumulator 0 X • Stack Pointer • Condition Code Register Carry/Borrow • Zero Zero (Z) Zero is used to indicate that the result of the last arithmetic. the stack pointer is set to location $07F. The clock input to the timer 1 can be from an external source applied to the TIMER input pin or it can be the internal tP2 signal. it can be gated by an input applied to the TIMER input pin allowing the user to easily perform pulse-width measurements.

(Internal Clock) 4>2---1--1 3 Multiplexer Timer Data Register 1 (TDR1: $008) Time Out Write Read Figure 6 Timer Clock • Timer Control Register 1 (TCR1: $009) Clock input source selection. 197 0 1 1 1 1 TCR1 Bit 1 0 0 1 1 0 0 1 1 Bit 0 0 1 0 1 0 1 0 1 Prescaler Frequency Comparator +1 +2 +4 +8 +16 +32 +64 + 128 . prescaler frequency compare selection and timer interrupt control are controlled by software written into timer control register I (TCRI : $009). the prescaler and counter are initialized with all logical ones. As shown in Table 2.? Timer Pin Control q.. prescaler frequency compare is selected by timer control register 1 (TCRI) three bits. Table 1 Clock Input Source Selection TCR1 Bit 5 Bit 4 0 0 0 1 1 0 1 1 Timer Control Register 1 (TCR 1: $009) 6 5 4 I TIF ITIMI'S1 I ISO 3 k}s++sol ~ ..2 - Event Input From Timer Pin Table 2 Prescaler Frequency Comparator Selection P'''QI" F"quo. internal clock q. ISO or lSI (bits 4 and 5) of timer control register 1 (TCRl). q..------------------------------------------------------------HD6805VVO timer interrupt has occurred and not disturb the counting process.... MSO through MS2 (bit 0 through bit 2). a 2 L Clock Inpu~ Source Internal Clock... "0" is written into TIF by software. After reset. At power up or reset.T i m e r Interrupt Request Flag As shown in Table 1.? (bit 4 = 1 and bit 5 =0) timer control is selected. ." Comparator Clock I nput Source Bit 2 0 0 0 Timer Interrupt Mask L ... To erase the timer I interrupt bit. clock input source selection is made by the three inputs. .. the timer I interrupt request bit (bit 7) is cleared and the timer 1 interrupt request mask bit (bit 6) is set.

The timer 2 hardware consists of • an 8-bit control register 2 an 8-bit status register 2 • an 8-bit timer data register 2 • an 8-bit output compare register • an 8-bit input capture register • as-bit prescaler control register 2 • a 7-bit prescaler 2 A block diagram of the timer 2 is shown in Figure 7. • Output Compare Register (SCnD) The output compare register is an 8-bit read/write register which is used to control an output waveform.HD6805WO---------------------------------------------------------• TIMER 2 The HD680SWO contains an on-chip programmable timer (timer 2) which may be used to perform measurements on an input waveform while independently generating an output waveform. The output compare register is set to SFF by reset. the output level register value will appear on the pin for port C. a flag is set (OCF) in the timer status register 2 (TSR2) and the current value of the output level bit (OLVL) in TSR2 is clocked to port C bit 6. The counter value may be read by the CPU software at any time. The input transition change required to trigger the counter transfer is controlled by the input edge bit (IEDG) in the TCR2... Pulse widths for both input and output signals may vary from a few microseconds to many seconds. Read/Write Input Capture Register IICR: $01E) 8 bit Register Reed Timer Control Register 2 (TeR2: $01 B) ICI OCI TOI Internal Interrupts Request Signal Figure 7 Timer 2 Block Diagram • Timer Data Register 2 (S01C) The key element in timer 2 is an 8-bit timer data register 2 free running counter which is driven to increasing values by the internal clock <P2 or by timer input. • 198 Input Capture Register ($01E) The input capture register is an 8-bit read-only register used to store the current value of the timer data register 2 when the proper transition of an external input signal occurs. The contents of this register are constantly compared with the current value of timer data register 2. bit 6 contains a "1 " (output). This counter can also read and write. Providing the data direction register for port C. bit 6. The data direction register bit for port C bit 5 should· be clear (zero) in ... Output Compare Register (OCR: $010) 8 bit Register 8 ~-----. When a match is found. The values in the output compare register and output level bit may then be changed to control the output level on the next compare value. The timer data register 2 is cleared by reset.

When IEDG = I. Each bit is discussed below. Bit 6 OCF Output Compare Flag This read-only bit is set when a match is found between the output compare register and the free running counter.ed in three different ways by bits 4 and 5 of prescaler control register 2 (PCR2). When IEDG = 0. ·With port C bit 5 confIgUred as an output and set to "I ". In all cases. the external input will still be seen by the edge detect unit. Bit 4 ICIM Input Capture Interrupt Mask When this bit is cleared. After reset. +8. Table 3 Clock Input Source Selection PCR2 Bit 5 Bit4 0 0 0 1 0 1 1 1 Clock Input Source ---I nternal Clock ifJ2 Timer Pin Control ifJ2 Timer Pin Input . simultaneous cyclic pulse control with a short width is easy. the positive edge triggers ("Low" to "High" transition). +2. internal interrupt (TOI) is enabled by TOF interrupt but when it is set. Prescaler Control Register 2 (PCR2: $019) 6 7 5 4 3 o 2 1/VI. When writing into prescaler control register 2. internal clock ifJ2 (bit 4 = 1 and bit 5 = 0) is selected by timer pin control. +64 and +128). internal interrupt (lCI) by ICF interrupt occurs. it is necessary to clear DDR beforehand. When this function is used. This read-only bit is set by a change in IEDG specification detected by the edge detection circuit and cleared by a read of the TSR2 followed by a CPU read of the input capture register ($OlE). internal interrupt (OCI) by OCF interrupt occurs. prescaler is initialized to $FF. it is necessary to make the input pulse width at least 2 enable cycles in order to mantain the input capture. output compare register ($OID). or when writing into time counter 2. If the I bit in the condition code register is cleared. • Prescaler Control Register 2 (PCR2: $019) The selections of clock input source and prescaler frequency compare are performed by prescaler control register 2 (PCR2: $019). +32.M IOCIM ITOIM I EDG IOLVL I Bit 0 OLVL Output Level When this value is compared with the counter value and output compare register value. +1 (bit 0 = bit 1 = bit 2 = 0) is set. Timer Status Register 2 (TSR2: $OlA) 76 5432 0 ICF OCF TOF IZI/VL212j 199 Selection of clock input source is perfonr. It is cleared by a read of the TSR2. it is moved to bit 6 of Port C. followed by a read of timer/ counter 2 ($01 B). This read-only bit is set when the counter contains $00. +4. as shown in Table 3. If DDR is set to "1" according to bit 6 of Port C. priority vectors are generated in response to clearing these flags. + 16. The frequency compare can be selected in seven ways (+1. Accordingly. this value is output from the line of bit 6 of Port C. • Timer Status Register 2 (TSR2: $01A) The timer status register is a 3-bit read-only register· which indicates that: (1) A proper transition has taken place on the input pin with a subsequent transfer of the current counter value to the input capture register (lCF). the negative edge triggers ("High" to "Low" transition). Prescaler Frequency Comparator L--_ _ _ _ _ _ _ Clock I nput Source Bit 3 OCIM Output Compare Interrupt Mask When this bit is cleared. (3) When $00 is in the counter (TOF) Each of the flags in the TSR2 has interrupt and inhibit bits. output compare output can be written into C6 port by software. Bit 1 IEDG Input Edge This bit determines the trigger to change either polarity of input line bit 5 of Port C for data transmission to input capture register from timer/counter 2. as shown in Table 4. Bit 7 ICF Input Capture Flag Timer Control Register 2 (TCR2: $OlB) 7654321 Bit 5 TOF Timer Overflow Flag 0 1/V121 IC. after C6 port has been written into by software. interrupt is inhibited. The prescaler frequency compare is selected by three bits in the prescaler control register 2 (bits 0 through 2). interrupt is inhibited. by which the interrupt output request is controlled. interrupt is inhibited.S1 ISO 1/1 MS2 MS1 MSO Bit 2 TOIM Timer Overflow Interrupt Mask When this bit is cleared. Although TCR2 and TSR2 are as described above.--------------------------------------------------------HD6805VVO order to gate in the external input signal to the edge detect unit in the timer. After reset. When this bit is set. It is cleared by a read of the TSR2 followed by a CPU write to the. (2) A match has been found between the value in the counter and the output compare register (OCF). When this bit is set. • Timer Control Register 2 (TCR2: $01B) The timer control register 2 consists of an 5-bit register of which aIlS bits are readable and writeable. according to Port C bit 5.

The reset conditions are the same as all of the input ports of the MCU (the contents of DDR are cleared). 34 Ao 33 +9V 8 TIMER HD6805WO * (Register option) B7 32 7 NUM B. if the LSI is normal. 31 Vee Bs 30 B. 3 INT 2 RES A. 39 7fT As 38 A.HD6805VYO-------------------------------------------------------Table 4 Prescaler Frequency Comparator Selection Bit 2 0 0 0 0 1 1 1 1 PCR2 Bit 1 BitO 0 0 1 1 0 0 1 0 1 1 1 • The self check capability of the MCU provides an internal check to determine if the part is functional. Upon power up. Connect the MCU as shown in Figure 8 and monitor the output of port C bit 3 for and oscillation of approximately three hertz. 37 2. 40 A.2}JF 5 XTAL A3 36 A2 35 6 EXTAL A. 8 2 27 11 C 2 B. a sufficient delay occurs by connecting a capacitor to the RES input. reset input requires a minimum of 100 milliseconds to stabilize the internal oscillator. 26 12 C 3 Bo 25 Vee = Pin 3 Vss = Pin 1 * Refer to Figure 9 about crystal option Figure 8 Self Check Connections Vee RES Pin --------------~ Part of HD6805WO MCU Internal Reset Figure 10 Power Up Reset Delay Circuit Figure 9 Power Up and Reset Timing 200 . Prescaler Frequency Comparator +1 +2 +4 +8 +16 +32 +64 + 128 0 1 0 1 0 SELF CHECK • RESETS The MCU can be reset by the external reset input (RES) as shown in Figure 9. As shown in Figure 10. 29 9 B3 28 Co 10 C. then it is necessary to go "Low".

Furthermore. Four different connection methods are shown in Figure 11. The use of a crystal (AT cut.Cut Parallel Resonance Crystal Co = 7 pF max. Crystal specifications are given in Figure 12. 5 XTAL~~EXTAL ~~ I I 4 C..----------------------------------------------------------HD6805VVO • INTERNAL OSCILLATOR OPTIONS option manufactured separately from the LSI is available to provide better matching between the external components and the internal oscillator. 5 HD6805WO MCU No Connection ~ 4 I 6 \ N ~ ~ 3 Vee = 5. The internal oscillator circuit has been designed to require a minimum of external components. \ c: Q> :l ~ AT . =22pF±20%l Rs = 60 U max. 4 MHz max) or a resistor is sufficient to drive the internal oscillator with varying degrees of stability. f = 4 MHz (C. a mask 6 EXTAL 6 EXTAL 4 MHz c:::::J max HD6805WO MCU 5 XTAL 5 XTAL HD6805WO MCU 22P F±20%=ifi= Approximately 25% Accuracy External: Jumper 6 EXTAL 6 EXTAL External Clock Input 5 XTAL R HD6805WO MCU 5 XTAL External Clock Approximately 15% Accuracy External Resistor CRYSTAL OPTIONS RESISTOR OPTIONS Figure 11 Internal Oscillator Options .25V Ta = 25°C - I\. u. A resistor selection graph is shown in Figure 13. 2 ~ ~ ~~ Figure 12 Crystal Parameters o 5 10 15 20 25 30 Resistance (kUl 35 ~ 40 Figure 13 Typical Resistor Selection Graph '){\1 ~ 45 50 .

CC. FF5 OFI: FF2. Priority Vector Address RES 1 $FFE. The priority interrupts are shown in Table 5 with the vector address that contains the starting address of the appropriate interrupt routine. the external interrupt routine is executed. : FFA. OCI and OFI) or on command (SWI). After that.HD6805VVO-------------------------------------------------------• Table 5 Interrupt Priorities INTERRUPTS The CPU can be interrupted in seven different ways: through external interrupt (I NT 1 and INT 1)' internal timer interrupt request (Timer 1. ICI. $FF7 OCI OFI S 7 $FF4. FF7 OCI: FF4. FF9 INT2 : FF8. FFD INT. A Execute Instruction Load PC From SWI: FFC. FF9 ICI: FF6. The interrupt sequence is shown as a flowchart in Figure 14. processing of the program is suspended. When interrupt occurs. $FFB Timer/INT 1 4 $FFS. X. FFB TIMER 1: FF8. Y INT2 Clear y TIMER 1 1~1 y ICI Y OCI 7F~SP O~DDR's CLR TNT Logic Fetch Instruction FF~TDR1 OO~TDR2 7F ~Prescaler 1 7F ~Prescaler 2 50~TCR1 1C~TCR2 10~PCR2 y OO~TSR2 FF~OCR OO~ICR Stack PC. Moreover. The interrupt service routines normally end with a return from interrupt (RTI) instruction which allows the CPU to resume processing of the program prior to the interrupt. the present CPU state is pushed onto the stack.$FFD INTi 3 $FFA. $FF9 ICI 5 $FFS. the interrupt mask bit (I) of condition code register is set and the external routine priority address is achieved from the special external vector address. $FF5 Interrupt $FF2. INT1 and Timer 1 are generated by the same vector address. FF3 Figure 14 Interrupt Flowchart 202 . Among these. $FF3 y INT.$FFF SWI 2 $FFC.

. When Port B is output by program. At this time the data input uses port C ($002). For that reason. Furthermore. Ports Band Care CMOS compatible at input. The details of these instructions are shown in Table 8. When output is programmed. Bit 7 is reset by software (BCLR instruction). port C bit 5 is reset to "0" (input) and timer control register 2 (TCR2: $01 B) bit 4 (lCIM) is reset to "0". the value in TCR2 bit 1 (IEDG) is input to input capture register as timer data register 2 value. __ Miscellaneous register (MR) bit 7 is the INT 2 interrupt request flag. the control register for INT 2 is the miscellaneous register (MR: $OOA).. Cs and C6 are timer 2 and are selected by software... Accordingly. When the output compare match is written with software. port C. DDR ($006) bit 6 is set to "I " (output). All of the pins are controlled by the data direction register and both input and output are programmable. When port C is used for output. bit 7 is set at "1". interrupt request should not be written in with software.. output matched output is written at C6 and caution must be taken. interrupt inhibit is the same as the (I) bit for other condition co~e register (CC). even if the output load of output level changes. if INT 2 interrupt occurs.. miscellaneous register set/reset should not be used for read-modify-write instructions (COM. Bit 7 is checked by software in the vector address ($FF8. ROR. INT 2 interrupt request can be received. Since IRF can read/write. the interrupt vector address of external interrupt vector INT 2 is the same as Timer 1 interrupt vector address. When all of port C is used for input. IRF is written with software and "1" should not be written in. all of port C DDR ($006) should be "0". the current from each pin is capable is sinking 10 rnA (VOL max. In this case..I N T 2 Interrupt Request Flag The interrupt of INT 2 is caused by the negative edge to enable latch. the latched logical level data is read as shown in Figure 15.. = IV). While read-modify-write instruction is processing IRF... When timer 2 output compare (OC) is used. When bit 6 is "1" INT 2 interrupt is inhibited... Several examples of the Port distributions are shown in Figure 16. all of port C DDR should be "1". • INPUT/OUTPUT There are 23 input/output pins.INT2 Interrupt Mask ' . For either edge. when C6 is output-only. data can also be written to C6 by software. the software write has priority and the output compare write is ignored. Bit 6 is the interrupt mask bit for INT 2. LSR and ASL). Accordingly. Moreover. LSL.. timer data register 2 matches the content of output compare register and the value of bit 0 of timer control register 2 is output to C6 • In this case. $FF9) interrupt routine and indicated by interrupt of INT 2. When port C is used as timer 2 input capture (IC).----------------------------------------------------------HD6805VVO • Miscellaneous Register (MR: SOOA) As shown in Table 5.. ROL. for example. port A pin is CMOS compatible at output.. Miscellaneous Register (MR: SOOA) 6 IRF 1M 5 4 3 2 0 VVVlZ121/1 ' . When interrupt occurs. On port C. Moreover. the I/O port is read.. OutPut Data Bit 1/0 Pin Data Direction Register Bit Output Data Bit Output State Input to o o o 3·State Pin MCU 1 o Figure 15 Typical Port I/O Circuitry 203 ..

Port B Programmed as outputls) driving Darlington base directly.. 4 AVss . A. refer to the section on A/D converters. When $003 is read in the input is 6 pin TTL compatible. result register and control/status register (ADCSR).HD6805WO-------------------------------------------------------- ··• ·· Ao Port A ••• • • · · Port B B. ·•• ·• CMOS Inverter C3 Port B Programmed as outputls) driving LED(s) directly... CONVERTER The HD6805WO has an internal 8 bit A/D converter... The AID converter is shown in Figure 18 and has 4 pins for analog input (ANo through AN 3 ). Port C Programmed as output(s) driving CMOS using external pull-up resistors._ _ _ _ _ Port 0 Do to 0.. (a) (b) +V +V A Bo Port B ·••• ·• · • - Port C 10 mA max B. $003 Aead Internal Bus OIA 1-. For use as an AID converter... The conceptual structure of port D is shown in Figure 17. Figllre 17 Port D AVec 0 0 . Select MUX AN. Port A Programmed as output(s) driving CMOS and TTL Load directly.' ANo AN._ 5V AID Control StatuI Aegister (ADCSA: $OOE I AID Aesult Aegister (ADAA: SOOFI Figure 18 AID Converter Block Diagram 204 .. AN.. (d) (c) Figure 16 Typical Port Connections • • AID INPUT Port D has 6 TTL compare compatible pins and 4<hannel input AID converter can be used....

~ 6 Bit 0 Not Used Bit 1 Not Used Bit 2 Not Used Bit 3 Not Used Bit 4 Not Used Bit 5 Not Used • • 7 STBY PWR \ Reg. RAME 5 4 3 2 X X X X o IIIIIII X X Bit 6 RAM Enable The RAM enable control bit allows the user to disable the standby RAM. A "0" in the RAM enable bit (RAME) will disable the standby RAM. A/D conversion begins when data is writen into bits 0 through 1 of control status register. (logic "0") the RAM address is ineffective. After this. Moreover. • STANDBY RAM The 8 bit RAMs S020 through $027 are used for standby RAM. When the ADCSR CEND flag is set. and the data in the standby RAM is valid. During A/D conversion execution. To end the A/D conversion.L. Bit 7 is reset after the AID result register is read. Standby RAM control is performed by RAM control register or RAME signal. without software. standby RAM is disabled. AN2 AN3 AID Control Status Register (ADCSR: $OOE) Control status register ($OOE) is used to select analog input or AID conversion termination. Consequently. ($01FI / I 1 RA--M-E------~\ jv------ :\""----------'f: I RAM (96BI 1 • I Standby RAM Enable I Standby RAM Disable . then Vee is set to off. This bit is a read/write status flag that the user can read which indicates that the standby RAM voltage has been applied. Accordingly. as shown in Figure 20.L. Analog conversion is selected by bits 0 through of control status register (ADCSR) analog input. When AID conversion ends. A/D result register is set to the most recent value. When the RAM is disabled. When in a hardware standby mode. ADCSR CEND flag is reset. Moreover. there is a small savings in power supply but the standby RAM data is maintained. RAME signal is used externally to control the RAM. RAME rises to "1" after Vee on and RCR RAME bit is "1". This bit can be written to "1" or "0" under program control. In this way. The bit which resets the CPU is set to "I" and standby RAM is enabled. RAME as "0" causes the signal to fall and RCR RAME bit is reset at "0". the result is set in the A/D conversion result register (SOOF)... • RAME Signal The RAME signal can control the RAME bit in the RAM control register to be "0" (RAME is disabled). When used as standby RAM.L.S at 1 MHz.--------------------------------------------------------HD6805VVO • Analog Input (AN o through AN 3) Analog pins AN o through AN3 accept analog voltages of OV through 5V. AID Result Register (ADRR: $OOF) When A/D conversion ends. converted result is obtained from A/D result register. thereby protecting it at power down in Vee standby is held greater than VSBB volts as explained previously in the Signal description for Vee standby. data is written into the new A/D control status register which selects the input channel and A/D conversion execution at that time is suspended. Vee standby is impressed after Vee OFF.. Since the CPU is unnecessary for conversion. Vee RAM CTRL ~===~-5jj. The analog input signal is selected from among ANo through AN 3. Bit 7 Standby bit The standby bit is cleared when the standby voltage is removed. Furthermore. • RAM Control Register (RCR: $01F) This register. Analog input selection is as shown in Table 6 and is selected by bits 0 through 1 of bit 2. Standby RAM is then enabled. bit 7 (CEND flag) is set. Table 6 Analog Input Selection RAM Control Register ADCSR Bit 1 0 0 1 1 Bit 0 0 1 0 1 Analog Input Signal $01F ANo AN. Vee standby remains on and the RAME signal falls.. when bit 7 is set A/D conversion execution continues. CEND flag is set and new A/D conversion begins. gives status information about the standby RAM. which is addressed at $01 F. power supply is connected only to standby RAM and other parts are not connected with power supply. With Vee on. The resolution power is 8 bit (256 divisions) with a conversion time of 76 #J.1 1 1--_ _ _-t$07F Figure 19 Standby RAM Figure 20 RAM Control Signal (RAME) 205 . other user programs can be executed. Vee becomes off and RAME is maintained by the Vee standby power source.

and the program branches as a result of its state. In addition. All RAM space.be tested is written to the carry bit in the condition code register. Thus. In this mode. . the entire memory space may be accessed. Refer to Figure 29. 'The byte to be tested is addreSsed 'by the byte following the opcode. • Direct Refer to Figure 23. which uses only seven bytes of ROM provides tum-on of the TRIAC within 14 microseconds of the zero crossing. SELF 1 BSET 1. In direct addressing. The effective address (EA) is the PC and the operand is fetched from the byte following the opcode. These instructions occupy two bytes. I/O registers and 128 bytes of ROM are located in page zero to take advantage of this efficient memory addressing mode. Assume that bit 0 of port A is connected to a zero crossing detector circuit and that bit 1 of port A is connected to the trigger of a TRIAC which powers the controlled hardware. This addressing mode calculates the EA by adding the contents of the two bytes following the opcode to the index register. • Indexed (No Offset) Refer to Figure 26. the program goes to somewhere within the range of +129 bytes to -127 bytes of the present instruction. the address of the operand is contained in the secondbyte of the instruction. • Extended Refer to Figure 24. This mode of addressing accesses the lowest 256 bytes of memory. This mode of addressing applies to instructions which can test any bit in the fll'St 256 locations (SOO through SFF) and branch to any location relative to the PC. 511 low memory locations are accessable.HD6805VVO-------------------------------------------------------• BIT MANIPULATION • The MeU has the ability to set or clear any single RAM or input/output port (except the data direction registers) with a single instruction (BSET and BCLR). ROM or I/O allows the user to have individual flags in RAM or to handle single I/O bits as control lines. This capability to work with any bit in RAM. Such instructions are two bytes long. PORTA Relative Refer to Figure 25. The implied mode of addreSSing has no EA. The example in Figure 21 shows the usefulness of the bit manipulation and test instructions. The third byte is the relative address to be added to the program counter if the branch condition is met. The immediate addressing mode accesses constants which do not change during program execution. • Indexed U6-bit Offset) Refer to Figure 28. Extended addressing instructions are three bytes long. PORTA. All implied addressing instructions are one byte long. Instructions which use this addressing mode are three bytes long. Bit Manipulation Example • Bit Set/Clear The MCU has ten addressing modes available for use by the programmer. All of the information necessary to exe9ute an instruction is contained in the opcode. EA =(PC) +2 + ReI. These instructions are three bytes long. PORTA BClR 1. The relative addressing mode applies only to the branch instructions. In this mode the contents of the byte following the opcode is added to the program counter when the branch is taken. These modes are explained and illustrated briefly in the following paragraphs. when a branch takes place. Extended addressing is used to reference any location in memory space. 206 Refer to Figure 30. These instructions are one byte long and their EA is the contents of the index register. • Indexed (8-bit Offset) Refer to Figure 27. control instructions such as SWI and RTI belong to this group. The EA is the contents of the two bytes following the opcode. The value of the bit to. The timer is also incorporated to provide tum-on at some later time which permits pulse-width modulation of the controlled power. This mode of addressing applies to instructions which can set or clear any bit on page zero. Direct addressing allows the user to directly address the lowest 256 bytes in memory. If the branch is not taken. This program. These instructions are two bytes long. The lower three bits in the opcode specify the bit to be set or cleared while the byte following the opcode specifies the address in page zero. Any bit in the page zero read only memory can be tested by using the BRSET and BRCLR instructions. • Implied Refer to Figure 31. • • Bit Test and Branch • ADDRESSING MODES Immediate Refer to Figure 22. SELF 1 Figure 21 ··• ·· ·•• ·· BRClRO. ReI is the contents of the location following the instruction opcode with bit 7 being the sign bit. Direct operations on the accumulator and the -index register are included in this mode of addressing. The EA is calculated by adding the contents of the byte following the opcode to the contents of the index register. ReI = 0. The individual bit within that byte to be tested is addressed by the lower three bits of the opcode.

Figure 22 I mmediate Addressing Example t lEA Memory I I I I I I I I I I I I CAT FCB 32 l 004B / Adder 1 ~ A ooto 20 004B I I I 20 I Index Reg I I I PROG LOA CAT 0520 B6 052E 4B Stack Point I I Prog Count I 052F CC ~ I I I I I I 1 I Figure 23 Direct Addressing Example 207 I I I .--------------------------------------------------------HD6805VVO Memory I I I I I ~ I A F8 Index I ea Stack Point I I PROG LOA #$F8 05BE 05BF A6 Prog Count t-------I OSCO F8 CC I 1 § I I I I.

.HD6806VVO-------------------------------------------------------- Memory i i I i i 8 I PROG LDA CAT 06 040B E5 64 06E5 40 Index Reg J Stack Point I I FCB A I ~O9~ 040A I I CAT 0000 Prog Count 40 040C CC Figure 24 Extended Addressing Example EA 04C1 Memory i I ~ A Index Reg Stack Point I I PROG BEQ PROG2 04A7 27 04A8 18 I I I i 0000 ~ . Figure 25 Relative Addressing Example 208 .

MeJory I I TA8L . X 075B E6 075C 89 I I I 075E CC I I Prog Count I § Figure 27 Indexed (S-Bit Offset) Addressing Example 209 I .--------------------------------------------------------HD6805VVO EA 00B8 Memory A TABL FCC t Lit 00B8 4C ~C 49 Index Reg 88 I PROG LOA X I Stack Point 05F4~ Prog Count 05F5 CC § Figure 26 Indexed (No Offset) Addressing Example lEA .I I FCB #BF 0089 BF FCB # 86 008A B6 FCB "" DB 0088 DB FCB #CF 008C CF I 008C /' Adder t I ~ I I I I I A I I CF I Index Reg I 03 I Stack Point PROG LOA TAB L.

HD6805WO-------------------------------------------------------- Memory i I I ~ I PROG LOA A DB Index Reg 02 I TABLX069'~ 0693 07 0694 7E Stack Point Prog Count 0695 . I TABL CC I BF FCB #BF 077E FCB #86 077F 86 FCB #DB 0780 DB FCB #CF 0781 CF Figure 28 Indexed (16-Bit Offset) Addressing Example Memory PORT B EQU 0001 BF A 0000 Index Reg 10 0590 Stack Point 01 Prog Count 0591 .. I Figure 29 Bit Set/Clear Addressing Example 210 .. I CC §@ ..

PROG 2 0574 05 Prog Count t--------4 0575 0576 0000 02 0594 I------i 10 CC C Figure 30 Bit Test and Branch Addressing Example EA Memory i I I I ~ A E5 Index Reg I I PROG TAX 05BA 8 @ E5 I I Prog Count 05BB CC I I I I Figure 31 Implied Addressing Example 211 .----------------------------------------------------------HD6805VVO PORT C EQU 2 0002 A FO Index Reg 0000 Stack Point PROG BRCLR 2. PORT C.

The other group performs the bit test and branch operations. The jump unconditional (JMP) and jump to subroutine (JSR) instructions have no register operand. register/memory. The other operand is obtained from memory by using one of the addressing modes. Alphabetical Listing The complete instruction set is given in alphabetical order in Table 12. Refer to Table 10. Bit Manipulation Instructions These instructions are used on any bit in the first 256 bytes of the memory. • • Branch Instructions The branch instructional cause a branch from a program when a certain condition is met. Refer to Table 11. read/modify/write. One group either sets or clears. Refer to Table 8. 212 . • Register/Memory Instructions Most of these instructions use two operands.HD6805VYO---------------------------------------------------------• INSTRUCTION SET The MeU has a set of 59 basic instructions. Each instruction is breifly explained below. The TST instruction for test of negative or zero is an exception to the read/modify/write instructions since it does not perform the write. Refer to Table 7. One operand is either the accumulator or the index register. Refer to Table 9. These instructions can be divided into five different types. modify or test its contents and write the modified value back to the memory or register. bit manipulation and control. • • • Control Instructions The control instructions control the MeV operations during program execution. branch. • Opcode Map Table 13 is an opcode map for the instructions used on the MeV. Read/ModifylWrite Instructions These instructions read a memory location or a register. All of the instructions within a given type are presented in individual tables.

- ::J: C G) CO o 01 :eo ...Table 7 Register/Memory Instructions Addressing Modes Function Mnemonic Indexed (No Offset) Extended Direct Immediate Op Op Op # # # # Code Bytes Cycles Code Bytes Cycles Code # ' Op # Bytes Cycles Code Indexed (8-Bit Offset) Op # # Bytes Cycles Code Indexed 06-Bit Offset) Op # # Bytes Cycles Code # # Bytes Cycles Load A from Memory LDA A6 2 2 B6 2 4 C6 3 5 F6 1 4 E6 2 5 D6 3 Load X from Memory LDX AE 2 2 BE 2 4 CE 3 5 FE 1 4 EE 2 5 DE 3 6 Store A in Memory STA - - - B7 2 5 C7 3 6 F7 1 5 E7 2 6 D7 3 7 Store X in Memory STX - - - BF 2 5 CF 3 6 FF 1 5 EF 2 6 DF 3 7 6 Add Memory to A ADD AB 2 2 BB 2 4 CB 3 5 FB 1 4 EB 2 5 DB 3 6 Add Memory and Carry to A ADC A9 2 2 B9 2 4 C9 3 5 F9 1 4 E9 2 5 D9 3 6 N Subtract Memory SUB AO 2 2 BO 2 4 CO 3 5 FO 1 4 EO 2 5 DO 3 6 """'" Subtract Memory from A with Borrow SBC A2 2 2 B2 2 4 C2 3 5 F2 1 4 E2 2 5 D2 3 6 AND Memory to A AND A4 2 2 B4 2 4 C4 3 5 F4 1 4 E4 2 5 D4 3 6 FA 1 4 EA 2 5 DA 3 6 (.) OR Memory with A ORA AA 2 2 BA 2 4 CA 3 5 Exclusive OR Memory with A EOR A8 2 2 B8 2 4 C8 3 5 F8 1 4 E8 2 5 D8 3 6 Arithmetic Compare A with Memory CMP Al 2 2 B1 2 4 C1 3 5 F1 1 4 E1 2 5 D1 3 6 Arithmetic Compare X with Memory CPX A3 2 2 B3 2 4 C3 3 5 F3 1 4 E3 2 5 D3 3 6 Bit Test Memory with A (Logical Compare) BIT A5 2 2 B5 2 4 C5 3 5 F5 1 4 E5 2 5 D5 3 6 Jump Unconditional JMP - - - BC 2 3 CC 3 4 FC 1 3 EC 2 4 DC 3 5 Jump to Subroutine JSR - - - BD 2 7 CD 3 8 FD 1 7 ED 2 8 DD 3 9 Symbols: Op: Operation Abbreviation # : Instruction Statement - -I.

.- Symbols: Op: Operation Abbreviation # : Instruction Statement 4 36 .....% C G) 00 oCJI ~ o Table 8 Read/Modify/Write Instructions Addressing Modes Function Implied (A) Mnemonic Op Code N . ~ Op # # Bytes Cycles Code Indexed (No Offset) Direct Implied (X) Op # # Bytes Cycles Code Op # # Bytes Cycles Code Indexed (8-Bit Offset) Op # # Bytes Cycles Code # # Bytes Cycles Increment INC 4C 1 4 5C 1 4 3C 2 6 7C 1 6 6C 2 7 Decrement DEC 4A 1 4 5A 1 4 3A 2 6 7A 1 6 6A 2 7 Clear CLR 4F 1 4 5F 1 4 3F 2 6 7F 1 6 6F 2 7 Complement COM 43 1 4 53 1 4 33 2 6 73 1 6 63 2 7 Negate (2's Complement) NEG 40- 1 4 50 1 4 30 2 6 70 1 6 60 2 7 Rotate Left Thru Carry ROL 49 1 4 59 1 4 39 2 6 79 1 6 69 2 7 2 6 76 1 6 66 2 7 Rotate Right Thru Carry ROR 46 1 4 56 1 Logical Shift Left Logical Shift Right LSL 48 1 4 58 1 4 38 2 6 78 1 6 68 2 7 LSR 44 1 4 54 1 4 34 2 6 74 1 6 64 2 7 Arithmetic Shift Right ASR 47 1 4 57 1 4 37 2 6 77 1 6 67 2 7 Arithmetic Shift Left ASL 48 1 4 58 1 4 38 2 6 78 1 6 68 2 7 Test for Negative or Zero TST 40 1 4 50 1 4 3D 2 6 70 1 6 60 2 7 -----~---.

Operation Abbreviation #... 7) - - # # Cycles Op Code Bytes Cycles - 2·n 3 10 01+2·n 3 10 - - - Set Bit n BSET n (n=O ... Instruction Statement Table 11 Control Instructions Implied Function Mnemonic Op Code # # Bytes Cycles 2 Transfer A to X TAX 97 1 Transfer X to A TXA 9F 1 2 Set Carry Bit SEC 99 1 2 Clear Carry Bit ClC 98 1 2 Set Interrupt Mask Bit SEI 9B 1 2 Clear Interrupt Mask Bit CLI 9A 1 2 Software Interrupt SWI 83 1 11 Return from Subroutine RTS 81 1 6 Return from Interrupt RTI 80 1 9 Reset Stack Pointer RSP 9C 1 2 No-Operation NOP 90 1 2 Symbols.... Instruction Statement Table 10 Bit Manipulation Instructions Addressing Modes Mnemonic Function Bit Set/Clear Op Code Bit Test and Branch # # Bytes Branch I F Bit n is set BRSETn (n=O . Operation Abbreviation #... Op. Op. Instruction Statement .. Operation Abbreviation #... 7) 10+2·n 2 7 Clear bit n BClR n (n=O .-----------------------------------------------------------HD6806VVO Table 9 Branch Instructions Relative Addressing Mode Function Mnemonic Op Code # # Bytes Cycles 4 Branch Always BRA 20 2 Branch Never BRN 21 2 4 Branch IF Higher BHI 22 2 4 Branch I F lower or Same BlS 23 2 4 Branch I F Carry Clear BCC 24 2 4 (Branch IF Higher or Same) (BHS) 24 2 4 Branch I F Carry Set BCS 25 2 4 (Branch I Flower) (BlO) 25 2 4 Branch I F Not Equal BNE 26 2 4 4 Branch I F Equal BEQ 27 2 Branch IF Half Carry Clear BHCC 28 2 4 Branch I F Half Carry Set BHCS 29 2 4 Branch I F Plus BPl 2A 2 4 Branch I F Minus BMI 2B 2 4 Branch IF Interrupt Mask Bit is Clear BMC 2C 2 4 Branch IF Interrupt Mask Bit is Set BMS 20 2 4 Branch I F I nterrupt Line is low Bil 2E 2 4 Branch IF Interrupt Line is High BIH 2F 2 4 BSR AO 2 8 Branch to Subroutine Symbols. 7) 11+2·n 2 7 Symbols. 7) - - Branch I F Bit n is clear BRClR n (n=O ... Op...

Cleared Otherwise Not Affected 216 I N Z C 1\ • 1\ 1\ 1\ /\ 1\ 1\ 1\ 1\ 1\ • 1\ 1\ 1\ • • • • • • • • • • 1\ • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 1\ x x H • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 0 • • • • • • • • • • • 1\ • • • • • • • • • • 1\ • • • • • • • • • • • • • • • 1\ 1\ 1\ • • 0 • • 0 1 1\ 1\ 1\ 1\ 1 1\ 1\ 1\ 1\ • • /\ /\ • • • • • • • 1\ /\ • /\ /\ • 1\ 1\ /\ 1\ (to be continued) .HD6805\NO---------------------------------------------------------Table 12 Instruction Set Mnemonic ADC ADD AND ASl ASR BCC BClR BCS BEQ BHCC BHCS BHI BHS BIH Bil BIT BlO BlS BMC BMI BMS BNE BPl BRA BRN BRClR BRSET BSET BSR ClC Cli ClR CMP COM CPX DEC EOR INC JMP JSR lOA lOX Implied Immediate x x x x x ExDirect tended x x x x x Relative x x Addressing Modes Indexed Indexed Indexed (No (8 Bits) (16 Bits) Offset) x x x x x x x x x x x x x Condition Code Bit Set/ Clear Bit Test & Branch x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Condition Code Symbols: H Half Carry (From Bit 3) I Interrupt Mask N Negative (Sign Bit) Z Zero x x x x x x x x x x x x x x x x x x x x x x x x x x x x x C 1\ • x x x x x x x x x x x x x x x x x x Carry Borrow Test and Set if True.

Undefined opcodes are marked with "-". The number at the bottom of each column denote the number of bytes and the number of cycles required (Bytes/Cycles).Xl 6 I I . Mnemonics followed by a ". ( ) indicate that the number in parenthesis must be added to the cycle count for that instruction. Cleared Otherwise Not Affected Load CC Register From Stack ? Table 13 Opcode Map Bit Manipulation Setl Test & Branch Clear 0 0 Brnch Control Aead/Modify/Write Ael DIA 1 2 3 BASETO BSETO BAA 1 BAClAO BClAO BAN - 2 BASET1 BSETl BHI - I I A 4 I X I 5 I I .X2 I 0 SUB 1 I E 1 F -H IGH 0 CMP 1 - SBC 2 3 BAClAl BClAl BlS COM - CPx 3 4 BASET2 BSET2 BCC lSA - - AND 4 5 BAClA2 BClA2 BCS - - BIT 5 W TAX SWI' 6 BASET3 BSET3 BNE AOA - 7 BAClA3 BClA3 BEQ ASA - 8 BASET4 9 BAClA4 BSET4 BHCC lSL/ASl - BClA4 BHCS AOl - LOA 6 STA(+ll 7 ClC EOA SEC AOC 8 9 A - I BASET5 BSET5 BPl DEC - CLI OAA B BACLA5 ~ClA5 BMI - SEI ADD B C BASET6 BSET6 BMC INC JMP(-l) C D BAClA6 BClA6 BMS TST - JSA(-3) D E BASET7 BSET7 Bil - - LOX E F BAClA7 BClA7 BIH ClA - TXA - I 1/" 1/2 212 I A 3/10 [NOTE] 2/7 2/4 2/6 I 1/4 I 1/4 I 2/7 j 1/6 ASP NOP - I BSA'I STX(+l) 2/4 I 3/5 I 3/6 I 2/5 1. 217 F I 1/4 o . 2.----------------------------------------------------------HD6805VVO Table 12 Instruction Set Addressing Modes Implied Mnemonic Immediate Direct Condition Code Indexed Indexed (No (8 Bits) Offset) Relative Extended LSL x x x x LSR x x x x NEQ x x x x NOP x x x x x x x x ROR x x x x RSP x x x ORA ROL Bit Set/ Clear Indexed (16 Bits) Bit Test & Branch I H Z N C • • /\ /\ /\ • • 0 /\ /\ • • /\ /\ /\ • • • • • • • /\ /\ • • • /\ /\ /\ • • /\ /\ /\ • • • • • x RTI x ? RTS x • • • • • • • /\ /\ /\ • • • • 1 • 1 • • • • • /\ /\ • • • /\ /\ • x SBC SEC x SEI x x x x x x STA x x x x x x x x STX x x x x x x x x x SUB x TAX x x TST TXA x Condition Code Symbols: H Half Carry (From Bit 3) I Interrupt Mask N Negative (Sign Bit) Z Zero C /\ • ? ? ? • • /\ /\ /\ • 1 • • • • • • • • • • /\ /\ • • • • • • x x SWI ? Carry/Borrow Test and Set if True.x l.xo .XC IMP IMP IMM 7 8 9 - A NEQ ATI' ATS' - I DIA l I I B Aegister IMemory EXT C l 1." require a different number of cycles as follows: "ATI 9 ATS 6 SWI 11 BSA 8 3.

ROM. C.(DATA.) E. B3 B2 B.) G7(DATA 7 ) F. Os C./Rx C6 /Tx CsICK 2 0. 0. Co 00 (Top View) 218 F.) Eo (ADRo) . (ADR. (ADA'2) F 3 (ADR II ) F2 (ADR. Timer. D 6 /1NT. (ADA.HD6805XQ-------------MCU (Microcomputer Unit) -ADVANCE INFORMATION- The HD6805XO is the 8-bit single chip Microcomputer Unit (MCU) which contains a CPU.2 External. I/O and timer. (E) F6 (AtW) Fs (ADR 13 ) • SOFTWARE FEATURES • • • • • • • • • • • • • • INT.) E. HD6805XO Ao B. HD6805XOP • HARDWARE FEATURES • • • • • • • • • • • • • • 8-Bit Architecture 96 Bytes of RAM Memory Mapped I/O 4096 Bytes of ROM Internal 8-Bit Timer with 7-Bit Prescaler Vectored Interrupts . (ADR.) E. O.(ADR. H06805U1 vee XTAL EXTAL NUM TIMEA A. RAM and I/O Compatible with MC6805P2 Compatible with H06805V1. The HD6805XO is a member of HD6805 family and has more I/O ports and seriail/O than HD6805VI.) Gs(DATAs) G 6 (DATA. Bo C.) E2 (ADR. 0. on-chip clock. Soft and Serial I/O 56 I/O Lines (16 Lines LEO Compatible) On-Chip Serial I/O (Usable as Timer) On-Chip Clock Circuit Self-Check Mode Master Reset Low Voltage Inhibit Complete OevelopmentSystem Support by Evaluation Kit 5 Vdc Single Supply (OP-64) • PIN ARRANGEMENT Go (DATAo ) G. (DATA.o) F. (ADR.) Es (ADRs) E. D. C2 C.) 47 E6 (ADR.) Fo (ADR. Similar to H06800 Byte Efficient Instruction Set Easy to Program True Bit Manipulation Bit Test and Branch Instruction Versatile I nterrupt Handing Powerful I ndexed Addressing for Tables Full Set of Conditional Branches Memory Usable as Registers/Flags Single Instruction Memory Examine/Change 10 Powerful Addressing Mode All Addressing Modes Apply to ROM.) G. (DATA. RAM.) G 3 (DATA 3 ) G.

Port G2 G G. 05 06 (JNT 2 ) 0. Lines D. C s (CK) C 6 (Tx) c. E Output E4 Lines Es E6 E.------------------------------------------------------HD6805XO • BLOCK DIAGRAM XTAL Eo E. A2 A. F Output F 4 Lines Fs F6 F. Port F2 F. 5 Port F Reg 8 Port G Reg SP Program Counter "High" 6 PCH ALU Program Counter "Low" Data oir Reg Port 8 Reg 80 8. EXTAL Timer/ Counter TIMER NUM Accumulator 8 Port E Reg A CPU Control Index Register Port A Reg X 8 5 Data oir Reg Ao A. 219 . Port o 0 2 Input 0. 8 8. Lines C. E2 Port E. (Rx) Serial I/O Reg Do D. Port A A4 I/O As Lines A6 A. Data Dir Reg Data Dir Reg Port C Reg Co Port C. C C2 I/O C. Condition Code Register CC CPU Stack Pointer Fo F. I/O 8 Lines 5 86 8. 8 2 Port 8. Gs G6 G. Go G. I/O Lines G.

• • • • • HD6301VOP... 2 t . t-----P'5 t------P. H06301 VO has Sleep Mode and Stand-By Mode. Object Code compatible with the H06801. Op-Code Trap Up to 65k Words Address Space Wide Operation Range Vcc=3 to 6V (f=O...l to 1.5MHz)..... provided with some additional functions such as an improved execution time of key instruction plus several new instructions of operation to increase system throughput.5MHz (Vcc=5V ±10%). t------.. 128 Bytes RAM..5 MHz H063B01VO 2 MHz .. 128 bytes RAM. The HD6301 VO can be expanded up to 65k words...Ls (f=2MHz) • • • • Bit Manipulation.HD6301VO. 4kB ROM... HD63A01VO.vee (Top View) • t-----PIO .. f=O.P l l TYPE OF PRODUCTS Type No.. Like the HMCS6800 family.. low power consumption is realized. HD63A01VOP. Bit Test Instruction Protection from System Burst: Address Trap.-HD63B01VO CMOS MCU (Microcomputer Unit) -PRELIMINARY The HD6301 VO is an 8-bit CMOS single-chip microcomputer unit..0MHz (V cc =5V ±5%) • BLOCK DIAGRAM (DP-40) • PIN ARRANGEMENT ________. 2 Lines of Data Strobe. Serial Communication Interface Low Power Consumption Mode: Sleep Mode. f=O. And as lower power dissipation mode.Ls (f=1.0V single power supply..... l6-bit Timer..67J. HD63B01VOP FEATURES Object Code Upward Compatible with H06801 Family Abundant On-Chip Functions Compatible with HD6801VO.. 4kB ROM.P I7 220 Bus Timing H06301VO 1 MHz HD63A01VO 1.5J.5MHz). . By using the H~tachi's 3~m CMOS process._ P . O. So flexible low power consumption application is possible..1 to 2. Serial Communication Interface (SCI)....P I3 t . O. parallel I/O terminals as well as three functions of timer on chip are incorporated in the H06301VO. Standby Mode Minimum Instruction Cycle Time lJ.29 Parallel I/O Lines. I/O level is TTL compatible with +5.Ls (f=lMHz). It is bus compatible with HMCS6800..P .

IS3 IITS11 V in = 0.0 2.3 V Input "Low" Voltage All Inputs V 1L -0.A 6.P24 .7 - V - - 0.OV.1 V - - 1. V out : VSS ~ (Vin or V out ) ~ Vee.8V ** Current Dissipation of the operating or sleeping condition is proportional to the operating frequency.0 - - * V 1H min: Vee-1.0V±10% •.3 - 0.1 V - - 1.-------------------------------------HD6301VO.0 V Input Voltage Vin -0.3 .0 IJ.0MHz.0V±5% .) Item Symbol = 5.4 - - V IOH = -lOJ.A Vee. RES.5 - Vee xO .55 V - - 12.6mA Vin=OV.3 0.HD63B01VO • ABSOLUTE MAXIMUM RATINGS Item Symbol Value Unit Supply Voltage Vee -0.A Three State (off-state) Leakage Current PlO. Vss = OV.P17.8 V Input Leakage Current NMI. Test Condition RES.0 - max Unit Vee +0.+70 DC -55 .0 IJ. A 2.+7.+150 This product has protection circuits in input terminal from high static electricity voltage and high electric field. So the typo or max.4-5. STBY Input "High" Voltage EXTAL V 1H Other Inputs min typ Vee-0.7 - 2.. value (f : 1 MHz) x x (both the sleeping and operating) 221 mA V . P20 . Vee D Ta = O-+70 C.A Output "High" Voltage All Outputs V OH Output "Low" Voltage All Outputs VOL IOL = 1. value (f: x MHz) : max. P30 -P 37 .5MHz. unless otherwise noted. f = 2.0 15.4-5.0 2.J. we recommend V in . values about Current Dissipations of the when of f : x MHz operation are decided according to the following formula.J.0. P40 -P47 . f = 1. f=l.3 - Operating Temperature Topr V DC Storage Temperature T stg (NOTE) Vee+0. To assure the normal operation. VIL max: O.. • ELECTRICAL CHARACTERISTICS • DC CHARACTERISTICS (Vee = 5.0 J. HD63A01VO.5 pF 2. But be careful not to apply overvoltage more than maximum ratings to these high input impedance protection 'circuits. typo value (f: X MHz) : typo value (f: 1 MHz) x x max. D Ta = 25 C - Operating (f=l MHz**) - Sleeping (f=lMHz**) - 1. STBY lI in I V in = 0.OMHz..0-1.0 10.0 Input Capacitance All Inputs Cin Standby Current Non Operation lee Cu rrent Dissipation * lee RAM Stand-By Voltage V RAM IOH = -2001J. IRQI.

5 - 2* 3 4 t pwo ' .0V±10% --. 4 Delay Time.f = 1.3.f = 2.2. 3 200 - Peripheral Data Hoid Time Port 1.0MHz.HD6301VO.4 tpDH Fig. Port 1. Vee = 5.666 - 35 35 Enable Pulse Width "Low" Level PW EL 450 - Address Strobe to Enable Delay Time t ASEO 60 - - Address Delay Time t A0 1 t A02 Fig. Enable Positive Transition to OS3 Positive Transition tos02 Fig.4 tposu Fig. 5 - - Delay Time.HD63B01VO------------------------------------• AC CHARACTERISTICS (Vee =5.3. 6 0 - 150 tiS - * Except P21 222 0 ns . Vss =OV. Enable Positive Transition to OS3 Negative Transition tOS01 Fig. 11 250 - Symbol Test Condition HD6301VO HD63A01VO min typ typ - TBD - - 250 - TBD Oscillator stabilization Time Multiplexed Bus (tACCM) Unit 1 - Address Delay Time for Latch max ns PERIPHERAL PORT TIMING Item Peripheral Data Set·up Time Port 1. 6 200 - - 200 tlH Fig. = D-+70°C. T.-.) BUS TIMING Item Symbol Test Con· dition HD6301VO HD63A01VO HD63B01VO typ typ max min typ 10 0.0V±5% .0""1. Enable Nega-. 1 tAOL Fig.5 - min Cycle Time tcyC Address Strobe Pulse Width "High" PW ASH Address Strobe Rise Time tASr - Address Strobe Fall Time tASf - Address Strobe Delay Time tAso 40 Enable Rise Time tEr - Enable Fall Time - Enable Pulse Width "High" Level tEf PW EH 450 max min - 200 - - 135 - - 120 - 35 - - 35 - 35 - 35 - TBD - - ns 10 0. tive Transition to Peripheral Data Valid Input Strobe Pulse Width Input Data Hold Time Input Data Setup Time I I Port 3 Port 3 max min HD63B01VO max min typ max Unit - 200 - - 200 - - ns - 200 - - 200 - - ns 300 - - 300 - - 300 ns - 300 - - 300 - - 300 ns - - 300 - - 300 - - 300 ns - - 200 ns 150 - - - 0 - - ns I tPWIS Fig.5MHz. 3 200 - Delay Time. 6 150 Fig. 2 Write Data Set-up Time Data Hold Time 350 230 Read tOSR 80 Read tHR Write 0 tHW 20 Address Set-up Time for Latch tASL 60 Address Hold Time for Latch tAHL 20 Address Hold Time tAH 20 Ao '" A. HD63A01VO.2. Fig. Set-up Time Before E tASM Peripheral Read Access Time ~ - - tosw Non-Multiplexed (tACCN) Bus 250 ! - - - 35 - - 35 - TBD TBD TBD - - TBD - TBD - 220 TBD - TBD - 0 20 - - TBD - - 200 - - - (635) - (635) - 20 TBD TBD ns ns - ns 35 ns 35 ns - ns - - ns - - TBD TBD ns ns - TBD - 35 35 ns - - - - ps TBD - - 10 TBD TBD 0 20 TBD TBD 20 - TBD - 140 ns - ns - ns ns - - ns ns ns ns ns ns - TBD - - TBD - - TBD - - - 20 - TBD 20 - ms 250 - - 250 - - ns - - tRC Fig_ 10 20 Processor Control Set-up Time tpcs Fig. unless otherwise noted.

(SC1l (Port4) }~2.4 v) typ HD63B01VO HD63A01VO HD6301VO I+-tHR .t t-fN . 2..As--Ar. HD63A01VO.4 Test Symbol Condition min 3 - 2 - 150 - Fig..4V ) Data Valid O.-0" A.--tASM } \ 2.6 tCYC 2. \ ~r -.HD63B01VO TIMER.1 -tAH . SCI TIMING Item Symbol Timer Input Pulse Width Test Condition HD63A01VO HD6301VO tpWT max min typ - TBD - - - - 400 - - TBD - - /lS 0.4V I \'06V I ) ) t05W- f.- 0 ••\ . ~ J -+ R/W . Address Valid 2. Data Valid O. - -tEr -tAO- MPU Read 0. ~ I I-¥ -'OOR~J }~2. Valid O.4 -- 0.0 SCI Input Clock Pulse Width tpWSCK 0.6V .6 0.-A. (Port 3) typ -'k- I- -PWASH- Enable lEI max min tcyc Address Strobe (AS) 2.5 - - - 400 - - TBD 0.8V Figure 1 Expanded Multiplexed Bus Timing 223 - I+-. Enable Positive Transition to Timer Out HD63B01VO max min min - TBD - - 400 tCYC ns MODE PROGRAMMING Item RES "low" Pulse Width PW RSTL Mode Programming Set-up Time tMPs Mode Programming Hold Time tHMP Fig.6V r- \.6 0.oJ \..8V V 'J - 2 150 - - . 8 ..0V -. ~ .------------------------------------HD6301VO..V' -tASf ASED -if- pW EL \ PW EH .. 7 max Unit typ typ Delay Time..4 tToo SCI Input Clock Cycle tscyC 2. (Port 3) - 3 max ~ -tASr tASO MPU Write Do-D"A.6V -tAOl- -tEf - ~ tASLI \..4V Address Valid O. (tACCM) ~ .4V ~rAddress I\.{ Unit tcyC tcyc ns . ~l I+tAHL I{ }'f-2.-A.4V typ max min - - - 3 2 150 O..

(Port 41 R/W (Se2) ~ (SCt) 2.HD6301VO. - ~f-eo -tet -tEr - . - All Data Port Outputs P)7 _ _ _ _ _ _ _. (Port3) O. HD63A01VO.P" Inputs p.6V'r-tosw- MPUWrit e 2.4V.8V\----J! PIO - Pl7 P 20 P" - I-tpwo p •• ..4V -'k- fPWEL O.. a read.-0.-0.4V '~O.'{.6V A.. Address Valid .1 ~:~~ Data Valid Inputs- Note) Port 2: Except P2 .4V J"'"" 0. OSS = 1. Figure 4 Port Data Delay Times (MPU Write) ·Port 3 Non-Latched Operation Figure 3 Port Data Set-up and Hold Times (MPU Read) r- MPU access of Port 3' Address Bus p.....8V ~ PWEH /' Enable (EI 1\-.--tAD1-+ A... ·Access ma"tches Output Strobe Select (OSS = 0.-A. - P" Inputs 053-----. O.. tcyc 2.tAH ~ A.:J'fi--toSR- . (Port 1) j -'" 2.6V\- - Data Valid· (tACcNI ~tt-MI ~~ .-A" (Port 4 I Address Valid -Jl Figure 2 Expanded Non-Multiplexed Bus Timing rMPURead r MPUWrite O.0V ~ MPU Read 0. a write) Figure 6 Port 3 Latch Timing (Single Chip Mode) Figure 5 Port 3 Output Strobe Timing (Single Chip Mode) 224 .HD63B01VO-----------------------------------I. I -.8V'r- i". 2. Data Valod tAD2 ~ O...-A."'"" -II\. (Port 3) I--tAH I--tHR ~K.....

P40 .......~~~....~"..-"~........-----------~> Vee RES IPCS j \ ~~~~~:~ BUS\S\\\SSS\\~ ~..2kn 14...-_____~I Internal Write \~-----------Figure 10 Interrupt Sequence \\\\\\\\\\\~~~~ J /~ ~ tPCS( ~.--------------------------------------HD6301VO.".' ' .1 1'------""'1 P" Output Figure 8 Mode Programming Timing Figure 7 Timer Output Timing Vce Test Point m RL =2.. SC! = 30 pF for PIO -PI" P JO -Pu = 40 pF for E R = 12 kn for Pl0-. O .~_-J~_....."-~~..-""""''"''""'''"'''=-''"~.........SC •.....___"-__ -J"-_-'.-"'.n".. NMI. Internal DataBus _ _-"'_.~_-''--_J~~~·~~J~~~''-~~~ Internal Read ...... P)7......... E.':-:--~"-_-"....-J'=". P41...I ' . P I'7' P20. Po.o. se l Figure 9 Bus Timing Test Loads (TTL Load) Interrupt Test Internal Address Bus _ _J'--+.-_ __ I~~~~.ernal I IRC J VCC..J1.IRQ. Pp.O .... HD63A01VO._~....n-_-"~_"-_--I·'- __-'..sv tsS\\S\\\S\\S\Ssd FFFF FFFF New PC \\S\\\S\\SQ ~\S\\\\\S\\\S\S\\ H ~.."...I~~~:: 1-------<........-''( Instruction Figure 11 Reset Timing 225 FFFF FFFF FFFF .P ...."'-~~"-~-"~..........P14' P30 ...0kn for EI 152074 ® or EQuiv C R C =90pF forP....HD63B01VO RES Timer Counter _ _ _ _.ernal ss\S\\\\~ }SSSS\SSS\\\SSS\ :$ I = S\S\SS\S\\\: ~\\SSS\S\ssS\\\y 1\ ~~~~n:~s \S\SSSSSSs!-\ '%MSS\SS\\\Q f R '~ W FFFF ~ FFFF FFFF FFFF tt=x=x=:lJt=x=x=:l- . sc •....I s-----Ji O~F-...=""..._ _ _.......

. • Non maskable Interrupt (NMI) When the input signal of this pin is recognized to fall. Independently of the Mask Bit condition. TRAP interrupt is invoked. With the internal oscillator in use. and locates the contents in Program Counter to branch to an interrupt service routine. Ove. NMI sequence starts. From the third cycle on. SV ±S% (HD63B01VO) or 3 to 6V other than for high speed operation (SOOkHz). vectoring address $FFFC and FFFD will occur to load the contents to the program counter and branch to a non maskable interrupt service routine. the MPU generates 16 bit vectoring addresses indicating memory addresses $FFF8 and $FFF9... (1) I/O Port 2 bits 2. write "0" into RAM enable bit (RAME)... CJ e L1 = C L2 -10-22pF ± 20% (3.e Interrupt (SWI) FFFB FFF9 IRQ.. Interrupt Mask Bit in the condition code register. • XTAL. the MPU will start an interrupt sequence. Vss These two pins are used for power supply and GND. .2-BMHz) EXT A L 1 . it must be held "Low" at least 3 system clock cycles. In order to have the MPU recognize the maskable int~rrupts IRQI and IRQ2. the internal condi tion is reset with inactive oscillation and fixed in ternal clock. Table 1 Interrupt Vectoring memory map Vector Figure 12 Crysta I interface Highest Priority • STSY This pin is used to place the MCU in the Stand-by mode. will keep the both interrupts off. MPU does the following. EXTAL accepts an external clock input of duty SO% (±1 0%) to drive. if the interrupt mask bit in Condition Code Register is not set. this supplies system clock for the rest of the system. $FFFE. all address buses become "High" with RES at "Low" level. It will drive two LS TTL load and 40pF. The following pins are available only for Port 3 in single chip mode. in order to obtain the system clock 1MHz. Accumulators. • Reset (RES) This input is used to reset the MCU and start it from a power off condition..1. the former' precede the latter. (2) The contents of the two Start Addresses. In response to NMI interrupt. otherwise.. PCO of program control register. In order to retain information in RAM during stand-by. For instance.flowl SCI (RORF + ORFE + TORE) At the end of the cycle. Interrupt mask bit in Condition Code Register has no effect on NMI. At that time. TTL compatible and 1/4 the crystal oscillation frequency. so the contents of RAM is guaranteed. from which program starts (see Table 1). After the execution of instructions. An example of connection circuit is shown in Fig.0 are latched into bits PC2. On completion of this sequence. Condition Code Register are stored on the stack.. Output is a single-phase. This disables the RAM.. then internal clock is a quarter the frequency of an external clock.HD6301VO. The Internal Interrut will generate signal (IRQ2) which is quite the same as IRQI except that it will use the vector address $FFFO to $FFF7. $FFFF are brought to the program counter. Index Register. External driving frequency will be less than 4 times as maximum internal clock. Then the MPU sets the interrupt bit so that no further mask able interrupts may occur. if being set. start the interrupt routine in synchronization with E.FFEF. no XTAL should be connected. AT cut. a 4MHz resonant fundamental crystal is useful because the devide by 4 circuitry is included.n max XTAL 1 . the information of Program Counter. RAME is bit 6 of the RAM Control Register at address $0014.-. HD63A01VO. The MPU will wait receiving the request until it completes the current instruction that being executed before it recognizes the request. For external driving. the information of Program Counter. interrupt request is neglected. RES must be held "Low'. Index Register.... Detecting "High" level.. see the ST AND-BY section. AT Cut Parallel Resonance Crystal • Co = 7 pF max Rs = 60.. Once the sequence has started. Interrupt Request (lRQI) This level sensitive input requests that an interrupt sequence be generated within the machine. and NMI are hardware interrupt lines sampled by internal clock. PC1. EXTAL These two pins are connected with parallel resonant fundamental crystal. On occurrence of following Address Error or Op-code error.HD63B01VO------------------------------------• • Enable (E) FUNCTIONAL PIN DESCRIPTION • Vee. This interrupt has priority next to RES. 226 lowest Priority Interrupt MSB LSB FFFE FFFF 1m FFEE FFEF TRAP FFFC FFFO NMI FFFA FFFB Softw. To reset the MCU during system operation. For details of the stand-by mode. MPU begins interrupt sequence. (3) The interrupt mask bit is set. HD63AOIVO). (0' IS31 FFF6 FFF7 ICF (TirM' Input FFF4 FFF5 FFF2 FFF3 FFFO FFF1 C~tu'el OCF (firM' Output Comp"e TOF (Tim. Setting to "Low" level. Accumulator.. When IRQI and IRQ2 are generated at the same time. Recommended power supply voltage is SV ± 10% (HD6301VO. The vector for this interrupt will be FFEE. 12. Inputs IRQI . The current instruction may be continued to the last if NMI signal is detected as well as the following IRQI interrupt. clear it beforehand. and Condition Code Register are stored on the stack.. for at least 20ms when power is on..-__.

HD63A01VO.. Port 3 as a data bus is bi-directional. It is used to' latch the lower 8 bits addresses multiplexed with data at Port 3 and to control the 8-bit latch by address sfrobe as shown in Figure 18. Its output will drive one TTL load and 90pF. The timing chart is shown in Figure 2. an input strobe (IS3) and an output strobe (OS3). • PORTS There are four I/O ports on HD6301 V MCU (three 8-bit ports and one 5-bit port). (2) OS3 can be generated by MPU read or write to Port 3's data register. 5 and 6. regular TTL level must be supplied. Port 3.. The normal stand-by state is Read ("High").: Port 1. 8 of the chip) are used to program the mode of operation during reset.* When the bit of associated Data Direction Register is "1".0V for a logic" 1" and less than 0. all I/O lines are configured as inputs in all modes except mode 1. • Address Strobe (AS) (SCI) In the expanded multiplexed mode.. Additional 3 characteristics of Port 3 are summarized as follows: (1) Port 3 input data can be latched using IS3 (SCd as a control signal.0V for logic "I" and less than 0. These pins on Port 2 (pins 10. 6 and 5). a data bus. I/0Pon 1 1I0Pon2 1I0Pon3 1I0Pon" $0002 s0003 $0006 $0007 be read accurately. After the MCU has been reset. SOOOO $0001 $0004 I/O Port 3 Control/Status Register $0005 • 1/0 Port 1 This is an 8-bit port. The follOwing pins are available for Expanded Modes. In mode 1. The timing chart of this signal is shown in Figure 1. Bit 1 Not used. the flag of Port 3 Control Status Register is set. Its function depends on hardware operation mode programmed by the user using 3 bits of Port 2 during Reset. or in Write ("Low"). I/O Port 3 can become data bus during E pulse. • Output Strobe (0S3) (SC 2 ) This signal is used to strobe to an external device. In all modes. In the expanded Modes.. This allows external access up to 256 addresses from $0100 to $OIFF in memory. This TTL compatible three-state buffer can drive one TTL load and 90pF. The timing chart for Output Strobe are shown in figure 5. I/O lines are configured as inputs. However. The 5-bit output buffers have three-state capability. There are two control lines associated with this port in this mode. . then programmed for an input. Direction Register Add . In all modes other than expanded non multiplexed mode. note that bit 1 (P 2I ) is the only pin restricted to data input or Timer output. For respective bits of Port 3 Control Status Register. that is greater than 2. 2 control pins are connected to one of the 8-bit port.8V for logic "0". For an input from peripherals. (3) IRQI interrupt can be generated by an IS3 negative edge. I/O pin is programmed for output. Oat. After the MCU has been reset. It cannot be used as an output port. lOS decodes internally A9 to A Is as zero's and As as a one. Addresses of each port and associated Data Direction Register are shown in Table 2. if "0". Port 2. The 8-bit output buffers have three-state capability. data direction register will be inhibited after Reset and data flow will be dependent on the state of the R/W line. Thereby. or an address bus multiplexed with data bus. When detected the signal fall. which is expanded in the MODE SELECTION section. the voltage on the input lines must be more than 2.0V for logic "1" and less than 0.HD63B01VO • Input Strobe (lS3) (SCI) This signal controls IS3 interrupt and the latch of Port 3. In order to be read accurately.8V for logic "0". Table 2 Port and Data Direction Register Addresses Pons PonAddr. Port 3 in each mode assumes the following characteristics. address strobe appears at this pin. Port 1 will be output line for lower order address lines (Ao to A7)' I/O Port 2 This port has five lines. Each port has an independent write-only data direction register to program individual I/O pins for input or output. mode 1. see the I/O PORT 3 CONTROL STATUS REGISTER section. each bit being defined individually as input or outputs by associated Data Direction Register. There are four ports. These are TTL compatible. 9. They are controlled by I/O Port 3 Control/Status Register.8V for a logic "0". the voltage on the input lines must be more than 2. The values of these three pins during reset are latched into the upper 3 bits (bit 7. indicating effective data is on the I/O pins. Single Chip Mode" (Mode 7): Parallel Inputs/Outputs as programmed by its corresponding Data Direction Register. respectively. both being used for handshaking. Port 3 strobe and latch timing is shown in Figs. • • I/O Port 3 This is an 8-bit port which can be configured as I/O lines. In order to 227 Bit 0 Not used. * Only one exception is bit 1 of Port 2 which becomes either a data input or a timer output. maintaining in high impedance state when they are used for input. Port 2 can be configured as I/O lines.--------------------------------------HD6301VO. and Port 4.. • I/O Strobe (lOS) (SCI) In expanded non multiplexed mode 5 of operation. going high impedance state when used as inputs. This port also provides access to the Serial I/O and the Timer. Port 1 is always parallel I/O. whose I/O direction depends on its data direction register. • Read/Write (R/W) (SC 2 ) This TTL compatible output signal indicates peripheral and memory devices whether MCU is in Read ("High").

SC2 pins are configured for control lines of Port 3 and can be used as input strobe (IS3) and output strobe (OS3) for handshaking data .. When all of the eight bits are not required as addresses. It is cleared by a read of the Control/Status Register followed by a read/write of I/O Port 3. To use these pins as addresses. The relation between each mode and I/O Port 1 to 4 is summarized in Table 3. Port 4 becomes output for upper order address lines (As to Au) regardless of the value of data direction register.HD63B01VO-----------------------------------Bit 2 Not used. The bit is cleared by a reset. PC2 in I/O Port 2 register when reset goes "High".bus. The latch is cleared by the MCV read to Port 3. Expanded Non Multiplexed Mode (Mode 5): In this mode. • Expanded Multiplexed Mode In this mode. HD63A01VO. 13.0V for a logic" 1". Port 1 is configured for 8 parallel I/O. Port 4 becomes the lower address lines (Ao to A7) by writing "1 "s on the data direction register. Port 2 is configured for 5 parallel I/O or Serial I/O. 17)./0 31. Port 4 becomes Ao to A7 address bus or partial address bus and I/O (inputs only). Port 4 assumes following characteristics. Port 2 DATA REGISTER Bit 3 is used to control the input latch of Port 3. I/O 1. For outputs. 6) Port 3 becomes both the 'data bus (0 0 . These three pins are lower order bits. 228 . Expanded Non Multiplexed Mode (Mode 1): In this mode. address bits must be latched outside the board. Timer or any combination thereof. Bit 4 is cleared by a reset. the remaining lines can be used as I/O lines (Inputs only) starting with the MSB. In this mode.. the voltage at the input lines must be greater than 2. The data bus and the lower order address bus are multiplexed in Port 3 and can be seperated by an output called Address Strobe. The H06301 VO operates in three basic modes: (1) Single Chip Mode. Port 3 becomes a data bus and Port 1 becomes Ao to A. (3) Expanded Non Multiplexed Mode (compatible with HMCS6800 peripheral family) 1/0 Port 4 This is an 8-bit port that becomes either I/O or address outputs depending on the operation mode selected. Serial I/O. H06301 VO is expandable to 65k words (See Fig. In each mode. and less than 0. it can now be latched again. I/O Port 2 Register is shown below. Bit 7 is a read-only bit which is set by the falling edge of IS3 (SC t ). 4): In this mode. In the application system enough with fewer addresses. address . Clearing the flag causes the interrupt to be disabled. Bit 3 is cleared by a reset. they should be programmed as outputs. The mode selection of the H06301VO is shown in Table 4. the HDI4053B is available to seperate the peripheral device from the MCV. 6 • Lower Order Address Bus Latch Because the data bus is multiplexed with the lower order address bus in Port 3 in the expanded multiplexed mode. When the bit is not cleared. the H06301 VO can directly address HMCS680Q peripherals with no external logic.. This is shown in figure 15. 9. In this mode. PC 1. In this mode. In this mode. SCI. all ports will become I/O. the H06301VO is expandable to 65k words with no external logic . Bit 3 LATCH ENABLE.0 7) and lower bits of the address bus (Ao . or any combination thereof. In mode 5. Port 4 is configured for I/O (inputs only) or address lines. A7)' An address strobe output is true when the address is on the port. • • 4 3 0 I 1. Port 3 becomes data bus. • MODE SELECTION The operation mode after the rest must be determined by the user wiring the 10. The bit is cleared by reset. an interrupt is enabled. the strobe will be generated by a read operation to Port 3. be changed through software because the bits 5 6 and 7 of Port 2 are for read only.8V for a logic "0". Port 3 becomes a data bus. In mode 1. Bit 6 IS3 ENABLE. In order to be read accurately. It requires the 74LS373 Transparent octal Ootype to latch the LSD. If the IS3 flag (bit 7) is set with bit 6 set. and 8 externally. (00 to 0 7) Expanded Multiplexed Mode (mode 0. Latch connection of the HD6301 VO is shown in Figure 18. Bit 7 IS3 FLAG./0 1. 16). I/O 0. Ouring reset.. 7 $00031 PC21 Bit 4 OSS (Output Strobe Select) This bit identifies the cause of output strobe generation: a write operation or read operation to I/O Port 3. They are latched into the programmed control bits PeO. idle pins of Port 4 can be used as I/O lines (inputs only)(See Fig.. Single Chip Mode (Mode 7): Parallel Inputs/Outputs as programmed by its associated data direction register. Bit 5 Not used. I/O 2 of Port 2./0 21. (2) Expanded Multiplexed Mode (compatible with the HMCS6800 peripheral family). H0630lVO is expandable to 256 locations. and Port 4 becomes As to At 5 address bus. or Timer. Expanded Multiplexed Mode (Mode 0.5) In this mode. the input data on Port 3 is latched by the falling edge of IS3. No mode can. If the bit is set at "I".HD6301VO. Port 4 becomes output for upper order address lines (All to AlS). this port becomes inputs. each line is TTL compatible and can drive one TTL load and 90pF. • Expanded Non Multiplexed Mode In this mode. It is necessary where the data conflict can occur between peripheral device and Mode generation circuit. Port 2 is configured for a parallel I/O. After reset. 4. PC1 5 An example of external hardware used for Mode Selection is shown in Fig. When the bit is cleared. Expanded non multiplexed mode (mode 1.0 PCO 4 1 0 ) Single Chip Mode In the Single Chip Mode. Port 1 is configured as a parallel I/O only. the strobe will be generated by a write operation./0 1..

X. C I ??? ~ Mode Control Sw'tch 8 9 10 Z Inh P. . Zo Yo X. Y.- Y. Y P. 0 Z.. R. Z. R. Zo Y. Z. Xo Z. X z. 0 Z. Yo X. Y. P" (PC2) HD14053B Note 1) Figure of Mode 7 2) RC""Reset Constant J... 0 1 Z. x.. . . . f--. P" Z.HD63B01VO Vee ~ R > ~ > ~ R. . Z C B A HD14053B 0 0 On Switch Select . P" Y.-------------------------------------HD6301VO. Yo X. - X X X Figure 14 HD140538 Multiplexers/De-Multiplexers Vee Enable Port' 81/0 lines Port 3 81/0 Lines Port 4 8110 Lines Port 2 5110 Lines 8 Lines Multiplexed Data/Address Port 1 81/0 Lines Port 2 51/0 Lines SCI Timer SCI Timer Vss Port 4 To 8 Address Lines or TO 7 I/O Lines (Inputs Onlv) Figure 16 HD6301VO MCU Expanded Multiplexed Mode Figure 15 HD6301 VO MCU Single-Chip Mode 229 . X. 6 I I I A B RES ~ HD6301VO X.. 3) RI =10kn Figure 13 Recommended Circuit for Mode Selection Truth Table Control Input Inh Inhibit A B C Xo XI Yo Yla Zo ZI X Y 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 . Yo X. HD63A01VO.). (PCO) P" (PC. Y. X.

HD63A01VO. Z 0 .-A. Table 3 Feature of each mode and lines PORT 1 Eight Lines PORT 2 Five Lines PORT 3 Eight lines PORT 4 Eight lines SCI SC2 SINGLE CHIP I/O I/O I/O I/O IS3 (I) OS3(0) EXPANDED MUX I/O I/O ADDRESS BUS (Ao-A7) DATA BUS (Do-D7) ADDRESS BUS· (A8-AIs) AS(O) R/W(O) MODE EXPANDED Mode 5 I/O I/O DATA BUS (Do-D7) ADDRESS BUS· (Ao-A7) 10S(0) R/W(O) NON-MUX Mode 1 ADDRESS BUS (Ao-A7) I/O DATA BUS (Do-D7) ADDRESS BUS (A8-AIs) Not Used R/WiO) *These lines can be substituted for 1/0 (Input Only) starting with the MSB (except Mode 0. 0. 1 Enable Output 0 H L O. Port 3 Address/Data l 0.-0.. I o R/Vii Input Output ReadlWrite IS3 OS3 lOS Input Strobe Output Strobe 1/0 Select SC AS 230 = Strobe Control = Address Strobe .HD63B01VO------------------------------------Vee Vee Port 1 8 Parailel 1/0 Port 2 5 Parallel 1/0 SCI Timer Port 3 8 Data Lines Port 1 To 8 Address Lines Port 3 8 Data Lines Port 4 To 8 Address Lines or To 7110 Lines (Inputs Onlyl Port 2 5 Parailel I/O SCI Timer Port 4 To 8 Addresl Lines Vss (a) Mode 5 (b) Mode 1 Figure 17 HD6301 VO MCU Expanded Non Multiplexed Mode GND AS I I G OC 0. Function Table ) A"'~A. 0. 4l.HD6301VO. 74LS373 [ Output Control G 0 L L H H H L L H L X X X 0.. Figure 18 Latch Connection • Mode and Port Summary MCU Signal Description This section gives a description of the MCV signals for the various modes. SC 1 and SC 2 are signals which vary with the mode that the chip is in.

Logic "1" • MemoryMap The MCU can provide up to 6Sk byte address space depending on the operating mode. Fig. Table 5 Port Port Port Port Internal Register Area Register 1 Data Direction Register···· 2 Data Direction Register···· 1 Data Register 2 Data Register Port 3 Port 4 Port 3 Port 4 Data Data Data Data Direction Register···· Direction Register •••• Register Register Address 00' 01 02' 03 04" 05'" 06" 07'" Timer Control and Status Register Countar (High Byte) Counter (Low Byte) Output Compare Register (High Byte) 08 09 OA OB Output Compare Register (Low Byte) Input Capture Register (High Byte) Input Capture Register (Low Byte) Pon 3 Control and Status Register 00 OE OF" Rate and Mode Control Register Transmit/Receive Control and Status Register Receive Data Register Transmit Data Register 10 11 12 13 oc 14 1S-1F RAM Control Register Reserved * External address in Mode 1 External address in modes 0. as shown in Table S. 0 = Input 231 Operating Mode Single Chip Multiplexed/Partial Decode Non-Multiplexed/Partial Decode Multiplexed/RAM Not Used Not Used Non-Multiplexed Multiplexed Test .External MUX .HD63B01VO Table 4 Mode Selection Summary Mode 7 6 5 4 3 2 1 0 Pu (PC2) P 21 (PClI P 20 (PCO) ROM RAM H H H H H H I L I I I I I MUX(4) L H I I I NMUX(4) H L E(2) E MUX L L H L H H L L H L L L L E(2) I Interrupt Vectors I 1(1) - - - I I I 1(3) Bus Mode NMUX MUX (NOTES) 1) Internal RAM is addressed at $0080. 2) Internal ROM is disabled.Internal E .--------------------------------------HD6301VO.4 1 = Output.Multiplexed NMUX . 1. The first 32 locations of each map are for the MCU's internal register only. 1.Non-Multiplexed L . LEGEND: I . 19 shows a memory map for each operating mode.4. 3) Reset vector is external for 3 or 4 cycles after RES goes "high". 4) Idle lines of Port 4 address outputs can be assigned to I nput Port.6 . cannot be accessed in Mode 5 External address in Modes 0. HD63A01VO.Logic "0" H .

_ _ _ _ J [NOTE) Excludes the following addresses which may be used externally. there must be no overlapping of internal and external memory spaces to avoid driving the data bus with more than one device.. HD63A01VO. $06.. $02. $04. $FFFF . 4) This mode is the only mode which is used for testing..HD63B01VO------------------------------------- HD6301VOO Mode HD6301VO Mode 1 Non-Multiplexed/Partial Decode Multiplexed Test mode $0000(1) $0000 Internal Registers Internal Registers $001F $001F External Memory Space External Memory Space $0080 $0080 Internal RAM Internal RAM $OOFF $OOFF External Memory Space External Memory Space $FOOO Internal ROM $FFFF(2) Internal Interrupt Vectors(2 [NOTES) 1) Excludes the following addresses which may be used externally: $04. $07 and $OF. $05. 2) Addresses $FFFE and $FFFF are considered external if accessed within 3 or 4 cycles after a positive edge of RES and internal at all other times. 3) After 3 or 4 MPU cycles.. $06.HD6301VO. $07 and $OF. $05. (to be continued) Figure 19 HD6301VO Memory Maps 232 . $00.

.y Space $FOOO Internal ROM $FFFF _ _ _ _ _ .HD63B01VO HD6301V04 Mode Multiplexed/RAM Non·Multiplexed/Partial Decode $0000 $OOlF $0080 1 HD6301V5 Mode Internal Registers } External Memory Space I Internal RAM $0000 } _ _ Internal Registers $OOlF ""~~"'+"~~ Unusable $0080 } Internal RAM $OOFF $0100 } External Memory Space $OlFF . External Memoc. (to be continued) Figure 19 HD6301VO Memory Maps ... $04. [NOTE) Internal Interrupt Vectors Excludes $04. $05.-T""""-.. $OF. $OF. $07. $06. These address cannot be used externally. $FFFF [NOTE) Excludes the following address which may be used externally... HD63A01VO.-------------------------------------HD6301VO. $06.

$OF. $06. Figure 19 HD6301VO Memory Maps 234 Interrupt Vectors .HD63B01VO-------------------------------------- HD6301V06 Mode HD6301V07 Mode Single Chip Multiplexed/Partial Decode $0000 Internal Registers $OOOO~} External Memory Space $001F '""~'f""~'" Unusable $0080 $001F $0080 Internal RAM Internal Registers } Internal RAM $OOFF $OOFF External Memory Space $FOOO $FFFF $FOOO Internal ROM Internal ROM Internal Interrupt Vectors Int~rnal $FFFF [NOTE] Excludes the following address which may be used externally: $04.HD6301VO. HD63A01VO.

. In addition independently it can generate an output waveform by itself. the value of Output Compare Register and Output level bit should be changed to control an output level again on the next compare values. the value will appear on the output pin of Port 2 bit 1. a flag (OCF) in the timer control/status register (TCSR) is set and the current value of an output level Bit (OLVL) in the TCSR is transferred to Port 2 bit 1. Timer Control I Status Register 6543210 ICF I OCF I TOF I EICI I EOCI I ETOIIIEDG (5AF3 written to the counter! Figure 21 Counter Write Timing * To write to the counter can disturb serial operations. this bit is transferred to the Port 2 bit 1.HD63B01VO • PROGRAMMABLE TIMER The HD6301 VO contains 16-bit programmable timer and used to make measurement of input waveform. Output Input Lt¥el EdtII B~ 1 B. This is because for one thing.. To allow the external input signal to gate in the edge detect unit. or. 2 Figure 20 Programmable Timer Block Diagram • Free Running Counter ($0009: OooA) The key element in the programmable timer is a 16-bit free running counter. When the MPU writes arbitrary data to the MSB of $09. When bit 1 of the Port 2 data direction register is "1" (output). the OLVL value will appear on the bit 1 of Port 2. 2-byte transfer instruction such as STX is available. the width of an input pulse requires at kiast 2 Enable cycles. and for another. To insure input capture in all cases.. Then. the pulse width may vary from a few microseconds to many seconds. a writing of the Counter to the upper bytes. HD63A01VO. the counter is set to FFF8 in the cycle following writing to "High" of the counter. When the contents match with the value of the free running counter. the data preceedingly written in "High" byte is set to "High".-------------------------------------HD6301VO. the bit of the Data Direction Register corresponding to bit o of Port 2 must have been cleared (to zero). and • a 16-bit input capture register A block diagram of the timr is shown in Figure 20. A description of each bit is as follows. (2) A match has been found between the value in the free running counter and the output compare register (OCF). When the MPU writes arbitrary data to the LSB ($OA). the data is set to the "Low". If the DDR corresponding to Port 2 bit 1 is set" 1". All 8 bits are readable and the lower 5 bits may be written. The input transition change required to trigger the counter transfer is controlled by the input Edge bit (IEDG). . $OA) indepently of the write data value. Each flag may contains an individual enable bit in TCSR where controls whether or not an interrupt request may be output to internal interrupt signal (IRQ2). (1) A proper transition has taken place on the input pin with a subsequent transfer of the current counter value to the input capture register (lCF). When a match is found in the value between the counter and the output compare register. on the other hand. Bit 1 Port 2 DOR I I _____ : For the data writing on Compare Register. • Timer Control/Status Register (TCSR) ($0008) This is an 8-bit register. (3) When counting up to $0000 (TO F). The contents of this register are constantly being compared with current value of the free running counter. Reset will clear the counter. The counter value will be read out by the MPU software at any time desired with no effects on the counter. If the I-bit in Condition Code Register has been cleared. The upper 3 bits are read-only. 0 "". the operation makes sure to set the values of 16 bits in the register before comparing. indicating the timer status information below. For both input and output waveform. The output compare register is set to $FFFF during reset.. The timer hardware consists of • an 8-bit control and status register • a 16-bit free running counter • a 16-bit output compare register. a priority vectored address occurs corresponding to each flag being set. so it should be inhibited during using the SCI. * * • Input Capture Register ($0000: $OooE) The input capture register is a 16-bit read-only register used to hold the current value of free running counter obtained when the proper transition of an external input signal occurs..2 . The counter value written to the counter using the double store instruction is shown in Figure 21.. HD6301 VO Internal Bus • Output Compare Register ($OOOB:$OOOC) This is a 16-bit read/write register which is used to control an output waveform. The compare function is inhibited for one cycle immediately after writing of the output compare register to the upper bytes. 235 I OLVLI sooos Bit 0 OLVL (Output Level). then value of $FFF8 is being pre set to the counte ($09. that is driven by an E (Enable) clock to increment its values.

• Wake-Up Feature In typical multiprocessor applications the software protocol will usually have the designated address at the initial byte of the message. interrupt is masked. internal clock enabled or disabled to Port 2 bit 2 • Port 2 (bits 3. this bit enables OCF interrupt to generate the interrupt request (IRQ2). With this hardware feature. When set. Serial I/O utilizes Port 2 bit 3 (input) and bit 4 (output). When IEDG = 0. Bit 7 ICF (Input Capture Flag). • Transmit/Receive Control Status Register (TRCSR) TRCS Register consists of 8 bits which all may be read while only bits 0 to 4 may be written. When clear. Enabled or disabled • Interrupt requests. The read-only bit is set by a proper transition on the input. Both of transmitter and receiver communicate with the MPU via the data bus and with the outside world. through Port 2 bit 2. This read-only bit is set when the counter value is $0000. • Programmable Option The HD6301 VO has the following optional features provided for its Serial I{O. it is set by hardware. When this bit is set with bit 7 (RDRF) or a bit 6 (ORFE) set. When IEDG = 1. software. Bit 4 EICI (Enable Input Capture Interrupt). Reset will clear each bit of Timer Control and Status Register. this bit enables ICF interrupt to generate the interrupt request (IRQ2) but when clear. Bit 2 TIE (Transmit Interrupt Enable). When clear. It should be noted that RE flag has already set in advance of WU flag's set. standard mark/space (NRZ) • Clock Source . the interrupt is inhibited. it will permit an IRQ. When clear. Bit 5 TOF (Timer Over Flow Flag).HD63B01VO------------------------------------Bit 1 IEDG (Input Edge). enabled or masked individually for transmitter and receive data registers • Clock Output. The register is initialized to $20 on RES. Set by software and clear by hardware on receipt of ten consecutive "1 "s. the non-selected MPU be re-enabled (or "wakes-up") for the appearing next message. When this bit is set with TDRE (bit 5) set. status register and followed by writing the next new data into the Transmit Data Register. The purpose of Wake-Up feature is to have the non-selected MPU neglect the remainder of the message. The bit is cleared by reading the. SCI may select the several kinds of the data rate and comprises a transmitter and a receiver which operate independently on each other but with the same data format at the same data rate. Set to produce preample of ten consecutive "I"s and to enable the data of transmitter to output subsequently to the Port 2 bit 4 independently of its corresponding DDR value. TDRE interrupt is masked. They are all programmable. It is cleared by a read of TCSR (with OCF set) following an MCU write to the output compare register ($OOOB or $OOOC). register is as follows. When the data transfer is made from the Transmit Data Register to Output Shift Register. and is cleared by a read of TCSR (with ICF set) followed by an MPU read of Input Capture Register ($OOOD). Bit 2 ETOI (Enable Timer Overflow Interrupt). Description of hardware. When set. dedicated or not dedicated to serial I/O individually for receiver and transmitter • Serial Communication Hardware The serial communications hardware is controlled by 4 registers as shown in Figure 22. . Bit 4 RIE (Receive Interrupt Enable). the interrupt is inhibited. Transmit I Receiver Control Status Register 7654 J 210 Bit 0 WU (Wake Up).HD6301VO. Bit 6 ORFE (Over Run Framing Error). the interrupt is inhibited. it will permit an IRQ. Bit 5 TORE (Transmit Data Register Empty). Bit 3 EOCI (Enable Output Compare Interrupt). When clear. When set. E clock frequency or 1/8 of external clock • wake-up feature . Bit 6 OCF (Output Compare Flag). gates Port 2 bit 3 to input of receiver regardless of DDR value for this bit. HD63A01VO. When overrun or . • SERIAL COMMUNICATION INTERFACE The HD6301 VO contains a full-duplex asynchronous Serial Communication Interface (SCI). The DDR corresponding to Port 2 bit 0 must be clear in advance of using this function. TDRE is initialized to 1 by RES. Bit 3 RE (Receive Enable). 4). Therefore software protocol needs an idle period between the messages. The bits of the TRCS register are defined as follows. Thus the non-selected MPU can inhibit the all further interrupt process until the next message begins. 3 and 4. interrupt. trigger takes place on a leading edge ("Low" -to"High" transition).. Wake-Up feature is triggered by a ten consecutive "I "s which indicates an idle transmit line. one of 4 rates per given MPU. when clear. external or internal • baud rate . The registers include: • an 8-bit control/status register • a 4-bit rate/mode control register (write-only) · an 8-bit read-only receive data register • an 8-bit write-only transmit data register Besides these 4 registers. trigger takes place on a negative edge ("High" -to-"Low" transition). IRQ. Port 2 bit 2 can be used when an option is selected for the internal-clock-out or the externalclock-in. When set. It is cleared by MPU read of TCSR (with TOF set) following an MPU read of the counter ($0009). Bit 1 TE (Transmit Enable). 236 • data format . This bit control which transition of an input of Port 2 bit 0 will trigger the data transfer from the counter to the input capture register. This read-only bit is set when a match is found in the value between the output compare register and the counter. the serial I/O affects nothing on Port 2 bit 3. this bit enables TOF interrupt to generate the interrupt request (lRQ2) but when clear. serial If0 affects nothing on Port 2 bit 4.

Over Run Error occurs if the attempt is made to transfer the new byte to the receive data register with the RDRF set.. Rate and Mode Control Reg.600Baud 300Baud Table 7 SCI Format and Clock Source Control CC1.ft Reg .t 0 CCllccoISS1ISS0\510 Transm.400 Baud 16 0 1 E+ 128 2081ls/4.500 Baud 104.1 Baud 3.. It is set by hardware when the data transfer is made from the receive shift register to the receive data register.4 kHz 1. It is cleared by reading the status reSister and followed by reading the receive data register. 237 - - - .0 MHz 4. . 00 - - 01 NRZ Internal Not Used 10 NRZ Internal Output· 11 NRZ External Input * Clock output is available regardless of values for bits RE and TE. e Control and Status Reg . or by RES. Bit 7 RDRF (Receive Data Register Full)..HD63B01VO framing error occurs (receive only)...2.t/Rece .9152MHz 1..0 MHz E 614.6 Baud 833.200B8ud 1 1 E+4096 6. Bit 4 is used for serial output if TE = "1" in TRCS.us/ 9..096ms/244.4576 MHz 4. Framing Error occurs when the bit counters are not synchronized with the boundary of the byte in the bit stream.ster I I B.67ms/150 Baud 4.800Baud 0 0 E+ 16 26 115/38.3.u 51 1.-------------------------------------HD6301VO.ve Sh. ter Clock B. it is set by hardware.u s/16... CCO Format Clock Source Port 2 Bit 2 Port 2 Bit 3 Port 2Bit 4 - .333ms/ 115/62.2288MHz 13 . The bit is cleared by reading the status register and B.800 Baud 128 11511812.t 2 10 E Transmit Shift Register Tx Bit 12 4 513 Transmit Data Register Figure 22 Serial I/O Register X 6 5 4 3 2 X X X CC1 cco 0 sso SS1 ADDR : $0010 Transfer Rate I Mode Control Register Table 6 SCI Bit Times and Transfer Rates SSl : SSO XTAl 2. HD63A01VO. ter IRORFIORFEITOREI RIE I I TIE RE I TE I wu 1511 512 POrt 2 (Not Addressable) Rece..5 Baud 1 0 E + 1024 1.. or by RES. ** Bit 3 is used for serial input if RE = "1" in TRCS.024ms/976..t 7 followed by reading the receive data register.67ms/600 Baud 1..

receive data register. (2) If the data has been loaded into the Transmit Data Register (TDRE =0). the hardware sets the TDRE flag bit: If the MCU fails to respond to the flag within the proper time. ceo must be set to "10" . Bit 2 CCO } Bit 3 CCI Clock Control/Format Select • They control the data format and the clock select logic. it should be noted that the setting of TE. Then either of the following states exists. • The maximum external clock frequency is the same as E clock. If the tenth bit is "1". RE bit cleared during SCI operation. field in the Rate and Mode Control Register must be set to "11" (See Table 7). • GENERAL DESCRIPTION OF INSTRUCTION SET The HD6301VO has an upward object code compatible with the HD6801 to utilize all instruction sets of the HMCS6800. Following the preamble.------------------------------------consecutive" 1"s are transmitted indicating an idle lines. "I" is set in the RAM Enable bit thus enabling the standby RAM. Next the 8-bit data (beggining at bitO) and the stop bit. the 0 start bit is first transferred. still RDRF is preserved set. If this bit is preserved set. During the data transfer.output irrespectively of corresponding DDR value. In addition. RDRF or ORFE will be cleared. With the program control. This bit is a read/write status flag that user can read. the system assumes a framing error and the ORFE is set. the sleep instruction are added. • Internally Generated Clock If the user wish to employ externaly a internal clock for the serial I/O. TDRE is preserved set and then a 1 will be sent (instead of a 0 at start bit time) and more 1s will be set successively until the data is supplied to the data register. with the interrupt flag set. 1':. • Writing the desired operation control bits to the TRCS register. During 10-bit time. • The external clock must be set to 8 times the desired baud rate. the received bit stream is synchronized by the first "0" (space). RE bits may be preserved set. the change instruction of the index and the accumulator. the following requirements should be noted. • The CCl. (1) If the transmit data register is empty (TDRE = 1). • The clock is once the bit rate. The execution time of the key instruction is reduced to increase the system through-put. cleared by RES. gates the output of the serial transmit shift register to Port 2 bit 4 which is unconditionally configured as an . internal synchronization is established and the transmitter section is ready to operate. and subsequently set again.HD63B01VO. Bit 0 SSO } Speed Select Bit 1 SS 1 These bits select the Baud rate for the internal clock. The 4 bits are considered as a pair of 2-bit fields. Table 7 defines the bit field. the RAM address becomes external address and the MPU may read the data from the outside memory. it is transferred to the output shift register and data transmission begins. Bit 1 Not used. then ORFE is set indicating that an overrun error has occurred. Bit 6 RAM Enable. RAM Control Register ~"I ':':. Bit 4 Not used. This section describes: . If the tenth bit is not "1" (stop bit). the 238 Receive Operation The receive operation is enabled by the RE bit. gating the serial input through Port 2 bit 3. TE. The lower 2 bits control the bit rate of internal clock while the upper 2 bits control the format and the clock select logic. it is capable of writing "I" or "0". When set. • Externally Generated Clock If the user wish to supply an external clock for the Serial I/O. When TE. • Serial Operations The serial I/O hardware must be initialized by the HD6301 VO software prior to operation. Table 6 lists the available Band Rates. • Transfer rate/Mode Control Register (RMCR) The register controls the following serial I/O variables: • Bauds rate • data format • clock source • Port 2 bit 2 feature It is 4-bit write-only register. the approximate center is strobed. When the MPU is reset. the user can disable the RAM.1: 1: 1: 1 1 I : I X X Bit 0 Not used. If using Port 2 bit 3. no "0" will be sent. While the TDRE remains a "1". When the transmit data register has been empty. however. Bit 5 Not used. the bit operation instruction. Using this control bit. • Writing the desired operation control bits to the Rate and Mode Control Register. The sequence will be normally as follows. Bit 7 Standby Bit This bit is cleared when the Vee voltage is removed. • CC 1. With the disabled RAM (logic "0"). RE must refrain for at least one bit time of the current baud rate. the following requirements should be noted . If set within one bit time. 4 for serial I/O exclusively. the data is transferred to the. In the normal non-biphase mode.HD6301VO. If the tenth bit of the next data is received. After the MCU read of the status register as a response to RDRF flag or ORFE flag. • Transmit Operation Data transmission is enabled by the TE bit in the TRCS register. • The values of RE and TE have no effect. HD63A01VO. The rates selectable are function of E clock frequency within the MPU. • RAM CONTROL REGISTER The register assigned to the address $0014 gives a status information about standby RAM. CCO. Setting the TE bit during this procedure causes a transmission of ten-bit preamble of "I "s. following the MCU read of the receive data register. Following RES the user should configure both the RMC register and the TR(:S register for desired operation. indicating that Vee voltage is applied and the data in the RAM is valid. Bit 3 Not used. The receive section operation is conditioned by the contents of the TRCS and RMC register. there mav be the case where the initializing of internal functi~n for tran~mit and receive does not take place. Bit 2 Not used. • The maximum clock rat~ will be E/16.

Direct addressing allows the user to directly address the lowest 256 Bytes in the machine ie. These are two or three-byte instructions. Because the modified address is held in the Temporary Address Register. The double accumulator is physically the same as the accumulator A concatenated with the accumulator B. it is recommended that these locations should be RAM and be utilized preferably for user's data realm. For each of AIM. . EJM"TIM have three. 23) • Addressing modes • Accumulator and memory manipulation instructions (See Table 8) • New instructions • Index register and stack manipulation instructions (See Table 9) • Jump and branch instructions (See Table 10) • Condition code register manipulation instructions (See Table 11) ·Op-code map (See Table 12) memory. ISP) 1'5 PC 0 1 Proi. This is an absolute address in 239 In this mode. so that the contents of A and B is changed with executing operation of an accumulator D. Direct Addressing In this mode. These are two-byte instructions.5 X 0 1 1. Accumu"'o" A and 8 ~ Or 16-811 O?uble Accumulator 0 Indl'JtRegistt'f IX) 1. Accumulator (ACCX) Addressing Only the accumulator (A or B) is addressed. the second byte of instruction indicates the address where the operand is stored. ElM and TIM each have three. the contents of the second byte is added to the lower 8 bits in the program counter.-------------------------------------HD6301VO. Relative Addressing In this mode. - °U A - - - - - - 0 7 - ~ 8 - - - - - - - 8·8. Immediate Addressing In this mode. OIM. the contents of the second byte is added to the lower 8 bits in the Index Register. t. the second byte indicates the upper 8 bit addresses where the operand is stored. OIM. In addition.lf <Any (From alt 31 Figure 23 MCU Programming Model • MCU Addressing Modes The HD630 1VO has seven address modes which depend on both of the instruction type and the code.HD63B01VO • MCV programming model (See Fig.. Enhanced execution times are achieved by storing data in these locations. index register. . When the clock frequency is 4 MHz. the machine cycle will be microseconds. The address mode for every instruction is shown along with execution time given in terms of machine cycles (Table 8 to 12). ElM and TIM instructions.5 SP 0 1 StKk POinte. the instruction itself gives the address. this carry is added to the upper 8 bits in the Index Register. These are two-byte instructions except the AIM. locations zero through 255. HD63A01VO. This helps the user to address the data within a range of -126 to + 129 bytes of the current execution instruction.rrv/Borrow from MSB Overflow Zero Ne9f tlYe Interrupt H. The result is used for addressing memory. etc are stored in the second and the third byte.m Counter (PC) 7 1 0 ~ H I N Z V C Condition Code Register teeRI c. These are I-byte instructions. there is no change to the Index Register. stack pointer. Implied Addressing • MCU Programming Model The programming model for the HD630 1VO is shown in Figure 23.. the operand is stored in the second byte of the instruction except that the operand in LDS and LDX. OIM. Extended Addressing In this mode. while the third byte indicates the lower 8 bits. The resulting carry or borrow is added to the upper 8 bits. etc. the contents of the third byte are added to the lower 8 bits in the Index Register. For system configuration.. I ndexed Addressing In this mode. These are three-byte instructions. These are two-byte instructions but AIM. Either accumulator A or B is specified by one-byte instructions.

Memory Manipulation Instructions Condition Code Addressing Modes Operations Mnemonic IMMED OP - DIRECT # OP - # OP - Register EXTEND INDEX # OP - # Boolean/ Arithmetic Operation IMPLIED OP - H # BB 2 2 9B 3 2 AB 4 2 BB 4 3 A + M-+ A ADDB CB 2 2 DB 3 2 EB 4 2 FB 4 3 B+M-+B Add Doable ADDD C3 3 3 03 4 2 E3 5 2 F3 5 3 Add Accumulators ABA Add With Carry AOCA B9 2 2 99 3 2 A9 4 2 B9 4 3 A+M+C-+A AOCB C9 2 2 09 3 2 E9 4 2 F9 4 3 B+M+C-+B AND ANOA B4 2 2 94 3 2 A4 4 2 84 4 3 A'M-+A ANDB C4 2 2 04 3 2 E4 4 2 F4 4 3 8·M -+ B Bit Test BITA 85 2 2 95 3 2 A5 4 2 B5 4 3 A·M BIT B C5 2 2 05 3 2 E5 4 2 F5 4 3 6F 5 2 7F 5 3 Clear Compare A:B+M:M+l-+A:B lB CLR 1 1 B'M 00-+ M CLRA 4F 1 1 00 -+ A CLRB 5F 1 1 00 -+ B CMPA 81 2 2 91 3 2 Al 4 2 Bl 4 3 A-M CMPB Cl 2 2 01 3 . SP . Inclusive ORAA 8A ORAB CA 2 3D 2 3 2 AA 4 2 BA 4 3 OA 3 2 EA 4 2 FA 4 3 2 9A 2 7 1 AKB-+A:B A+M-+A B + M-+ B PSHA 36 4 1 A -+ MsP.. M -+ A Multiply Unsigned MUL OR. MsP -+ B 49 1 PULB Rotate Left ROL 69 6 2 79 6 ROLB Rotat. M+l-+M A+l-+A INCA 4C 1 INCB 5C 1 1 B + 1.2 El 4 2 Fl 4 3 B-M 63 6 2 73 6 3 Compere Accumulators CeA Complement. : : @ • I R : : : R : : R R ® I Push Olta 2 ·· ·• ·· ·· .' <I> . . • · · •· ·· ·· · · • ··· • • • ·• ·•• ··• ··. • ·· ·· . SP . ·• ··• • ItJ · • · . A DAA 19 1 1 Decrement DEC Exclusive OR Increment Load Accumulator 6 2 6 3 A-l-+A OECA 4A 1 1 OECB 5A 1 1 B-l-+B EORA 88 2 2 98 3 2 AS 4 2 B8 4 3 A@M-+A EORB C8 2 2 3 2 E8 4 2 F8 4 3 B @ M-+ B 6C 6 2 7C 6 3 INC . · ·· ·• ·. ··· ···• ·· ·· · .1 -+ SP PSHB 37 4 1 B -+ MsP. • • •· ·· •• . t t t R R R R ·· ·· R S R R R S R R R S R R I I I I I I I I I I I I I I R S R S I I t I I I I I I I t @ • : : : : R S <D~ (j) (V CD® : @ I @ • t t @ • I I I R t R t @• t I @. MsP-+ A 3 SP + 1 -+ SP. @ . l's COM 11 43 COMB 53 70 1 1 A-B M-+M COMA 60 1 1 1 A -+A 1 B -+ B OO-M-+M Complement.. Right ROR 59 66 6 2 76 6 .HD63B01VO------------------------------------Table 8 Accumulator.B LOAA 86 2 2 96 3 2 A6 4 2 B6 4 3 M-+A LOAB C6 2 2 06 3 2 E6 4 2 F6 4 3 M-+B Load Double Accumulator LOO CC 3 3 DC 4 2 EC 5 2 FC 5 3 M + 1 -+ B.HD6301VO. 3 AOlA 1 1 1 3 RORA 46 1 1 RORB 56 1 Note) Condition Code Register will be expla:ned in Note of Table 11. 240 1 :} C9=1! ! ! ! ! ! B b7 :}~) I I I I t t I I I I I I 1 0 I I I I I I I I : : I I I I I I I I .1 -+ SP Pull Data PULA 32 33 3 1 SP + 1-+ SP. HD63A01VO.2's NEG (Negate) NEGA NEGB 40 1 1 OO-A-+A 50 1 1 OO-B-+B Decimal Adjust. Converts binary add of BCD characters into BCD format M-l-+M 6A 6 2 7A 6 3 08 I A+B-+A 3 I N Z V C ·· · ·· ·· ··· ··· ·· ·· ·· ··• ·· · •· ·· ·· ·• ·• ·· ·· I I ADDA Add 4 5 iiO I I I II !~ bO R : @ I I I @ I I I <I> I I <1>. (to be continued) .

.g M) 3 LSRA =J C?Ib7 8 4 Store Accumulator bO 3 ASRA ASRB Shift Right Logical - - Booleanl Arithmetic Operation M+IMM-M M®IMM-M M·IMM 5 4 H I N Z V ··· ··· ·· ·· ·· ·· ·· ·· ·· ·· ·· ·· ·• · ·· ··· ·· ·· ·• ·· ··· ··• ·• ·• •• •• •• 3 2 1 0 C t t @t t t @H t t KIDt t t ~t t t & t t t 6 t t t 6 t R t 6 t R t @t R t @t R t @t t t t t R t t R R ··· t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t R t R t R R t R R t R R t R t t t t t t ·· R R R • • • • Note) Condition Code Register will be explained in Note of Table 11 . see the "sleep mode" section... EIM. TIM----(M) • (IMM) Evaluates the AND of the immediate data and the memory. places the result in memory.. changes the flag of associated condition code register Each instruction has three bytes. B 93 4 2 A3 5 2 B3 5 3 2 90 1 1 A . M STAB 07 3 2 E7 4 2 F7 4 3 B .. Memory Manipulation Instructions Condition Code Register Addressing Modes Operations Mnemonic IMMED OP Shift Left Arithmetic Double Shift Left.. M B . the HD630l VO has the following new instructions: AIM----(M) • (IMM) -+ (M) Evaluates the AND of the immediate data and the memory. B B . OIM---.. the fIrst is op-code.B ...ltors 1-0 80 111111J. 241 ....-The MPU is brought to the sleep mode... places the result in the memory. A 82 2 2 92 3 2 A2 4 2 B2 4 3 A-M-C .. the third is address modifier.--------------------------------------HD6301VO.. A:B 10 SBCA Transfer Accumul. For sleep mode. M Store Double Accumulator STD DO 4 2 FO 5 3 A .(M) + (IMM) -+ (M) Evaluates the OR of the immediate data and the memory.. HD63A01VO. A M -00 4 2 70 4 3 TSTA 40 1 1 TSTB 50 1 1 B . A SBCB C2 2 2 02 3 2 E2 4 2 F2 4 3 B-M-C .. Arithmetic Shift Right Arithmetic - DIRECT # OP - INDEX # ASL EXTEND # op - IMPLIED OP - # OP 68 2 7B 6 3 6 Double Shift Right Logical # M} __ 9"111111111-0 48 58 1 1 ASLB 1 1 ASLD 05 1 1 ~ 47 57 1 1 1 1 44 1 1 AS LA 67 ASR 6 2 77 6 64 LSR 6 2 74 6 A 8 b7 A7 A~e!l.... XGDX--(ACCD) # (IX) Exchanges the contents of accumulator and the index register... SLP. A DO 3 2 EO 4 2 FO 4 3 B -M ... places the result in the memory.... • New Instructions In addition to the HD680l Instruction Set. HD63B01VO Table 8 Accumulator..-(M) (±) (IMM) -+ (M) Evaluates the EOR of the immediate data and the contents of memory.. M+ 1 Subtract SUBA 80 2 SUBB CO 83 2 2 3 3 Double Subtract SUBO Subtract Accumulators SBA Subtract With Carry 2 ED 5 3 2 AO 4 2 BO 4 3 A-M .... the second is immediate data... ~ee I --- AO 87 _ AO-olIIIIIIII"'"9 8 b7 bO LSRB 54 1 1 LSRD 04 1 1 o-oj A7 -- ACCAOAJ 8~CC 8 STAA 97 3 2 A7 2 B7 4 3 A .00 And Immediate AIM OR Immediate DIM EDR Immediate ElM Test Immediate TIM 61 7 3 3 62 7 3 75 6 3 65 7 3 7B 4 3 68 5 3 71 6 72 6 A -00 M·IMM-M 3 80~ A:B-M:M+1 ... B TAB TBA Test Zero or Minus TST 16 17 60 1 1 1 1 A ....

. Table 10 Jump..t -LOS ~- f--..M...' . Zero BlE 2F 3 2 Z+ (N 0 Branch If lower Or Same BlS 23 3 2 C+Z-l Branch If < Zero VI . XL .SP H . _---INX Increment Index Reg ..1 BlT 20 3 2 N0 V-I Branch If Minus BMI 2B 3 2 N -I Branch If Not Equal Zero BNE 26 3 2 Z-O Branch If Overflow Clear BVe 28 3 2 v-o Branch if Overfiow Set BVS 29 3 2 V-I Branch If Plus BPl 2A 3 2 N-O 80 5 2 Branch To Subroutine BSR Jump JMP Jump To Subroutine JSR No Operation NaP 01 Return From Interrupti RTI 3B 10 1 Return From Subroutine RTS 39 5 1 Software Interrupt SWI 3F 12 1 Wait for InterruptSleep WAI 3E 9 1 SLP lA 4 1 6E 90 5 2 3 AD 5 2 7E 3 II See Special Operations 3 2 BO 6 3 1 1 Advances Prog.SP 4 2 EE 5 2 FE 5 3 M-XH. SP -1..Mop.SP..Stack Pntr TXS ~X .. HD63A01VO.. Zero BGE 2e 3 2 N0 > Zero BGT 2E 3 2 Z + (N 0 VI ... Data Bus goes to the three state level. Branch Instruction Condition Code Register Addressing Modes Operations Mnemonic RELATIVE OP Branch Alwavs BRA 20 3 # DIRECT OP 2 - # INDEX OP - # EXTEND IMPLIED OP OP - # - Branch Test # None None Branch Never BRN 21 3 2 Branch If Carrv Clear Bee 24 3 2 C=O Branch If Carry Set BCS 25 3 2 Branch If = Zero BEQ 27 3 2 C.(M + 11 SPH .XL • CZ) l R l l • (j) l R • (j) • (j) R R •••••• ACCD-IX Note) Condition Code Register will be explained in Note of Table 11. SP . ------------ 35 1 30 1 1 SP+l-X 3A 1 1 B XL ..SP X-I-X 1 1 31 1 1 sP + 1 ..M IP .. SP L .1 . Mop . (M+lI-SP L 3 1 X H ..SP XH. Increment Stack Pntr INS load Index Reg lOX -- CE --t8E -.Index Reg "X-M:M+l 3 3 3 5 4 3 2 1 0 H # 3 Store Index Reg --------..0 Branch If v-o Branch If Higher BHI 22 3 2 C+Z=O Branch If ..M..t---.1 Z -I Branch If ......-Pntr ..-Stack ...SP SP + 1 . Cntr.- - Boolean/ Arithmetic Operation X SP + 1'" SP.. _--_ . 242 5 H S .(M+ll-XL 4 2 AE 5 2 BE 5 3 M.1 . Address Bus goes to FFFF.(M+ 1) X-l-SP OF 4 2 EF 5 2 FF 5 STS 9F 4 2 AF 5 2 BF 5 3 Index Reg .r- 1 1 34 1 1 SP .. IMMED DIRECT OP - # OP 8C 3 3 9C 4 INOEX EXTEND IMPLIED OP OP # OP - 2 AC 5 2 BC 5 3 # - # 1---- DES Decrement Stack Pntr . Stack Manipulation Instructions Condition Code Register Addressing Modes Pointer Operations Mnemonic Compare Index Reg CPX Decrement Index R~_ DEX 1---.. MIP .. -Load ._..f--- ABX Add ----.. Onlv 4 3 2 1 0 I N Z V C ·· ·· ·· ·· ·· ·· ··· ··· ··· ··· ··· ··· ··· ··· ··· ··· ··• ··· ·· ·· ·· ·· ·· ·· ··· ··· ··· ··· ··· ··· ·· ·· ·· ·· ·· ·· ·· ·· ·· ·• ·· ·· ·· ·· ·· ·· ·· ·· · · · ·--· · ·· · ·· ·· ·· ·· ·• ev·• • ·• ·• ·• --@ See Special Operations Note) *WAI puts R/W high.HD6301VO..... X H Push Data PSHX 3C 5 1 Pull Data PUlX 38 4 1 Exchange XGDX 18 2 1 +X~ V C t l t l ·· ·• · · · ·· ·· ·· • ·· ·· ·· · · · · ·· ·· ··• ·· • · · · • • · · ·· • · ··· • · ·• · · · · • ·· ··· l X+l-X 08 OE STX I N Z l 09 9E Store Stack Pntr Stack Pntr . HD63B01VO-----------------------------------Table 9 Index Register... Condition Register will be explained in Note of Table 11.

In this mode. STBY. HD63B01VO Table 11 Condition Code Register Manipulation Instructions ~ddressin9Modet Operltions Mnemonic Clear Carry Cleer Interrupt Misk Cleer Overflow Set Carry Set Interrupt Milk SetO\lllrflow Accumulltor A .. the next instruction of ..--------------------------------------HD6301VO. Set when interrupt occurs. ElM. Result of Multiplication Bit 7=1? (ACCB) (Bit C) Table 12 OP-Code Map OP CODE ~ lO 0000 0 1000 0001 o~ 1 NOP 0010 0011 0100 3 2 4 0101 0110 5 0111 1000 1001 1010 7 lOll 0001 I SBA CBA . sleep and standby mode • SleepMode On execution of SLP instruction.CCR CCR ./ ~ . the MCU is brought to the sleep mode. So the operations such as transmit and receive of 243 the SCI data and counter may keep on functioning. In the sleep mode. then the MPU is brought to the operation mode and vectors to the interrupt routine. RES. the sleep mode escapes. OIM.CCR CCR-A S S --- ®--- Condition Code CD (Bit V) @ (Bit C) @ (Bit C) @ (Bit V) @ (Bit V) @ (Bit N) CD (Bit N) @ (All) ® (Bit I) Register Notes: (Bit set if test is true and cleared otherwise) Test: Result = 1000oo00? Test: Result" OOOOOOOO? Test: BCD Character of high-order byte greater than 10? (Not cleared if previously set) Test: Operand = 10000000 prior to execution? Test: Operand = 01111111 prior to execution? Test: Set equal to NEIlC=l after the execution of instructions Test: Result less than zero? (Bit 15=1) Load Condition Code Register from Stack. the power consumption is reduced to about 1/10 the value of a normal operation. When interrupt is requested to the MPU and accepted. In this mode.. a Non-Maskable Interrupt is required to exist the wait state. The escape from this mode can be done by interrupt.-'--- SBC COM lSR ~~ SWI ~ C C STD 0 E LOX STX I o I E F I F UNDEFINED OP CODE ~ • Only each instructions of AIM. If previously set. but the contents of the register in the MPU is secured.c-- 8 .Accumulltor A [NOTE] Condition Code Register Boolean Operation IMPLIED # OP 1 1 OC OE 1 1 1 OA 1 1 00 1 1 OF 1 1 OB 1 1 06 1 1 1 07 - ClC Cli ClV SEC SEI SEV TAP TPA 5 4 3 2 H I N Z 1 V 0 C R ·· · ·· ·· ·· · ·· ·· ·· ·· · · ·· · ·· ·· · ·· ······ O-C 0-1 R o-v R S 1. the MPU sleeps (the MPU clock becomes inactive).I-- ADC INC TST ~ STS 9 I A I B 3 5 LOA ~l 0 I 2 . HD63A01VO.C 1-1 1-V A./' ~ lSRD ASlD ~ 0010 2 BRA BRN BHI BlS BCC ~ BCS 0011 3 TSX INS DES TXS TAB TBA BNE BEQ 9 A INX DEX ClV BVC BVS BPL B SEV XGDX DAA SlP ABA PSHB PUlX RTS ABX BMI RTI 1100 C 1101 0 ClC ~ BGE PSHX 8 1110 E 1111 F SEC Cli SEI 0 ~ BLT ~ BGT ~ BlE I 2 0100 4 0101 0110 5 6 IND B ------ PSHA MUl WAI ACC ------- PULA PUlB TAP TPA 6 ACC A --- 3 4 5 DIR 0111 7 ACCA or SP ACCB or X I DIR liND I EXT 1000 1 1001 1 1010 1 lOll IMM 8 I 9 I A I IMM 1100 B C I J J SUB NEG AIM DIR liND 1101 0 -Tex:r- I 1110 I 1E I 1111 F CMP OIM SUBD -- ADDD AND BIT ElM ROR ASR 4 6 ~I STA STA EOR ASL ROl DEC 9 A QRA ADD TIM B CPX BSR I ~i ClR 7 8 I LDD ~I JSR LOS JMP 6 7 . When the MPU has masked the interrupt. The RES resets the MCU and the STBY brings it into the standby mode (This will be mentioned later). TIM • LOW POWER CONSUMPTION MODE The HD6301 YO has two low power consumption modes.. the peripherals of MPU will remain operational. (All Bit) Set according to the contents of Accumulator A. after releasing from the sleep mode.

First. that has a second highest priority (RES is the highest). • 0 I 4 5 6 7 $0000 $0000 $0000 $0000 $ocioo $0000 I I I I I I Address $ooiF $ooiF $ooiF $007F $ooiF $007F $0200 $0100 I I $EFFF $EFFF Address Error When an instruction is fetched from other than a resident ROM. standby mode and reset are shown in Fig. the sleep mode cannot be released due to the absence of the interrupt request to the MPU. The addresses which cause address error in particular mode are as shown in Table 13. the MPU becomes reset with all clocks of the HD6301VO inactive and goes into the standby mode. RAM. the H06301 VO is continuously supplied with power so the contents of RAM is retained.~ : I I I ~ ~ Oscil. In caSe where the instruction is fetched from external memory area of non-resident memory.. The standby mode should escape by the reset start.HD8301VO. Transitions among the active mode. and then goes into the standby mode. in such a case that the timer interrupt is inhibited on the timer side.iming relation for each line in this application is shown in Figure 24. it means that the power supply and the contents of RAM is normally guaranteed. NMI routine stacks the MeU's internal information and the contents of SP in RAM. HD83B01VO-----------------------------------sleep ~tarts to execute. sleep mode . 25. 27. Vee il NMl1 I I NMI <D In the standby mode.28 and 29 shows a system configuration. This feature is applicable only to the instruction fetch.lator I starting time ~ restart o Stack o RAM control register set Figure 24 Standby Mode Timing • ERROR PROCESSING When the H06301 VO fetches an undefined instruction or fetches an instruction from nonresident memory area. that may protect the system from system burst due to noise or a program error. or an external memory area. The t. However. Figures 26. This sleep mode is available to reduce an average power consumption in the applications of the H06301 VO which may not always drive. the MPU starts the same interrupt as op-code error. the HD6301VO will stack the MPU register as in the case of a normal interrupt and vector to the TRAP ($FFEE. it generates the most precedent internal interrupt. it cannot function. This mode remarkably reduces the power consumptions of the HD6301VO. not to normal read/write of data accessing. If the STBY bit keeps set on reset start. 244 . sets the STBY bit. HD83A01VO. disables RAME bit of RAM control register. The system recovery may be possible by returning SP and bringing into the condition before the standby mode has started. $FFEF). The following is the typical application of this mode. I HD6301VO STBY ® RES I I I I I I LI_ _ _ _ _ _ I r:- I ~. • Table 13 Address Error Mode Op-Code Error Fetching an undefined op-code. • Standby Mode Bringing STBY "Low".

and Reset Vee Vee Enable Enable IRQ. Standby Mode Sleep Mode.-------------------------------------HD6301VO. Port 3 8 Transfer Lines Port 1 Port 1 81/0 81/0 Lines Lines Port 2 5110 Lines Port 4 8110 Lines SCI 16 Bit Timer Vss Port 4 81/0 Lines Port 2 5110 Lines SCI Vss Figure 26 HD6301VO MCU Single-Chip Dual Processor Configuration 245 . iRQ. HD63A01VO.HD63B01VO Figure 25 Transitions among Active Mode.

HD63B01VO------------------------------------ HD6301VO MCU 8 Address Bus 8 Data Bus Address Bus Figure 27 HD6301VO MCU Expanded Non-Multiplexed Mode (Mode 5) Data Bus Figure 28 HD6301VO MCU Expanded Multiplexed Mode HD6301VO MCU 16 Address Bus Figure 29 8 Data Bus HD6301VO MCU Expanded Non-Multiplexed Mode (Mode 1) 246 . HD63A01VO.HD6301VO.

i-r--P'o t4-r---P2I A" t4-~-P22 t4-!--+-'''---P23 p" All (Top View) As A.s./A. 16-bit Timer. ~:~ ~:~ Au -- A. Bit Test Instruction Error Detecting Function. Op Code Trap • Up to 65k Words Address Space • BLOCK DIAGRAM • • (DP-40) PIN ARRANGEMENT • AS R/Vii D. 13 Parallel 1/0 Lines (includ- • • ing Timer.P" P..H 063 B03 CMOS MPU (Micro Processing Unit) -ADVANCE INFORMATIONThe HD6303 is an 8-bit CMOS micro processing unit which has the completely compatible instruction set with the H06301VO. HD6303P HD63A03P HD63B03P • • FEATURES Object Code Upward Compatible with the HD6800./A. D.PI' 1------. parallel I/O terminals as well as three functions of timer on-chip are incorporated in the HD6303./A. It is bus compatible with HMCS6800 and can be expanded up to 65k words. D. O.0 MHz HD63A03 1. A. HD6802.Ls (f=2./A.671lS (f=1. ~ HD6303 nV'l rrm D.) • Abundant On-Chip Functions Compatible with the HD6301 VO. power dissipation is extremely low.H 063A03. I/O level is TTL compatible with +5. 128 bytes RAM. Bus Timing HD6303 1. ~~ D. 247 TYPE OF PRODUCTS Type No./Ao-A. And also Sleep Mode and Stand-By Mode which the H06303 has for low power dissipation make lower power application possible. 128 Bytes RAM. -P.' Address Buffers r=====:~:~ • 1------. D. Serial Communication I nterface (SCI) Low Power Consumption Mode. Address Trap.H 06303.Serial Communication Interface (SCI).-____ 1------./A. Stand-By Mode Minimum Instruction Cycle Time 11lS (f=1MHzl. SCI I/O Terminals).P..5J. Sleep Mode.5 MHz HD63B03 2.o I---~P. HD6801 • Multiplexed Bus (Do-D.0MHz) Bit Manipulation. O.5MHz). ~ 1 .0V single power supply. m xx «~~ n". Like the HMCS6800 family.0 MHz ./A. As the HD6303 is CMOS MPU.

$05. $06. 248 .HD6303. $OF are external address. HD63A03. $07. HD63B03----------------------------------------~ • MEMORY MAP } Internal Registers (Note) } External Memory Space } Internal RAM ~~~~~~~~~~~LL~~~ ~~~~~~~~~~~~~~~ ~~~~LL~~~~~~~~~~ External Memory Space $FFFF~ ________________________ ~ (Note) $04.

... I/O.HD63L05--------------CMOS MCU (Microcomputer Unit) . SEG IO SEG II SEG" SEG"/CH.oOOOwww muuuuuuu".. 8 bits A/D... ./CH. and LCD (6 x 7 segments) drivers./CH... Having CPU functions similar to those of the HMCS6800 family... SEG. SEG.. SEG.PRELIMINARY- The HD63LOS is a CMOS single-chip microcomputer suitable for low-voltage and low-current operation. the HD63LOS is equipped with a 4k bytes ROM. HD63L05 VCM i rJ. 96 bytes RAM.. • • • • • • • • • • • HARDWARE FEATURES 3V Power Supply 8-Bit Architecture Built-in 4k Bytes ROM (Mask ROM) Built-in 96 Bytes RAM 20 Parallel I/O Ports Built-in 6 x 7 Segments LCD Driver Capability Built-in 8-Bit Timer Built-in 8-Bit A/D Converter Program Halt Function for Low Power Dissipation Stand-by Input Terminal for Data Holding • • SOFTWARE FEATURES An Instruction Set Similar to That of The HMCS6800 Family (Compatible with The HD6805S) HMCS6800 Family Software Development System Is Applicable • HD63L05 (FP-60A) • PIN ARRANGEMENT ~i~t5tE<E ~ . all on one chip. timer.. r3 IS > > u u (Top View) 249 .

co GIl\! ~c Accumulator 8 0 () A II) t: ~ c: 0 () Index Register Ao AI A2 A3 A4 As A6 A.. SEGlo II) E CI LCD5 II) (/) 7 LCD6 SEG 13 SEG I4 7 SEG 15 7 LCD7 7 LCD8 SEG I6 SEG 17 RES NUM TIMER 7 Prescaler SEG II ' SEG I2 c: 8 0 . o'~ !!!([ 10$ t: .g . SEG s SEG.~! o'~ !!!([ ce :...I I\! C Bo BI B2 B3 B4 Bs B6 B...([ .... .!!! J'.HD63L05--------------------------------------------------• BLOCK DIAGRAM Common Driver Output COMI COM 2 COM 3 Data Latch LCD1 SEG I SEG2 LCD2 SEG 3 SEG4 8 8 . 5 I\! a :. c: .(g Condition Code Reg.~ 0'61 GI I\! C 250 ~ 's.. UGI ALU !1.::::J S::::J LCD3 0 7 XIN ~ XOUT '': LCD4 C 7 E SEG s SEG 6 SEG. X 0 «S ~'i Q. Co CI C2 C3 .( () CCR CPU --CHI CH2 CH3 CH4 CHs CH6 (CH. Reg.. c: 8 System Cont.::.) (CH s ) Stack Pointer C 5 SP 4 Program Counter "High" PCH 8 Program Counter "Low" PCL c: 0 '. '.. ~! ()$ !!!([ Q.. .

J.2 - V 2.J.) min typ max Unit Operating Clock Frequency fel - 400 - kHz Cycle Time teye - 10 - f.3 .J.A Others Test Condition V IH Timer Mode Self-check Mode RES Input "Low" Voltage INT V IL Others Current Dissipation lee At Stand-By During AID Operation I nput leakage Current • TIMER IlL INT V in = OV -Vee 0.4 - V 2.2 - V 1.3 .+75 V °c -55-+125 °c If LSI's are used at rating exceeding the absolute maximum rating.0V ±O.0 - s Reset Delay Time tRHL Ext.6 - V 0.J.J.A 0.A At Halt - 40 - f. • ELECTRICAL CHARACTERISTICS • DC CHARACTERISTICS (Vee = 3.s Oscillation Start Time (Crystal Option) toscf C L = 10 pF ±20% - 100 - ms Oscillation Start Time (32kHz) toscl CG = 10 pF ±20%' - 1.----------------------------------------------------------HD63L05 • ABSOLUTE MAXIMUM RATINGS Item Symbol Supply Voltage Input Voltage Output Voltage Operating Temperature V out Topr Storage Temperature Tstg (NOTE) Value Vee Vin Unit -0.s tlWL - teyc +1 - f. Capacitance = 2. they can be permanently destroyed.Vee +0.SV.5 V -0. typ means typical value at 3V unless otherwise noted.4 - V INT - 2.1 - f.A - 2 - f.SV.0V ±O. Ta= -20-+75°C.2 f.J.A 300 - f.1 - f. typ means typical value at 3V unless otherwise noted. Vss =OV.8 V AC CHARACTERISTICS (Vee = 3.5 - V 0.s Item Symbol INT Pulse Width Test Conditions RES Pulse Width tRWL - teyc +1 TIMER Pulse Width tTWL - teyc +1 - f.J.J.3 V -0. Ta= -20-+75°C.A 0.s - f.J.3 -20 .+5.3 . Vss =OV.6 - V During System Operation - 100 - f.Vee +0.F - 400 - ms Oscillation Frequency (Resistor Option) f EXT - 400 - kHz - 10 - pF 10 pF - 5 - R = 90 kQ ±1% EXTAL I nput Capacitance XOUT Cin Others 251 pF .J.) Item Input "High" Voltage Symbol min typ max Unit RES - 2.J.

2 V V OL3 IOL =SJ.2 V Symbol Segment IOH VOH 1 and VOL3 characteristics apply to the .LA 2. B. C V IH Input "Low" Voltage Port A.LA 2.7 - V 0. B.LA - - 2. IOL = JOlLA).3 - V V 0.LA - - 0.8 - V V OL1 IOL = 1 J.) Item Accuracy Reference Voltage min typ max Resolution Symbol Test Condition - 8 - Unit Bit Non-Linear Error - ±1. C· VOL Input "High" Voltage Port A. Vss =OV.8 - V V OH2 IOH = -SJ.2 V = 3.LA 1.2 V OL3 - 0.2 - V - 2. Vss noted. C IlL V in = OV Input Leakage Current (Resistor Option) Port A.VAL Input Voltage Range V IN Conversion Time tCNV 252 .LA - - - 1.HD63L05--------------------------------------------~------------ • PORT CHARACTERISTICS (Vee = 3.8 - 0.8 - V V OH2 IOH = -1 J. unless otherwise noted.2 - V "Low" Side VAL t!. Vss =OV.LA 2.5 - LSB "High" Side V AH - 2.LA 0.8V.0V ±0.8 - V V OL1 IOL=SJ. C IIH V in = 3.0 - V VAL 2 - V AH V - 4 ms V AH .) Item • =OV. B.LA IOL = 100 J. typ means typical value at 3V unless otherwise Symbol Test Condition =-100 J.LA 20 - J.2 V V OL2 IOL = 1 J. Ta = -20°C-+75°C.0V.output obtained when segment terminals are used as output ports (lOH = -JOlLA.LA - 1.) Test Condition min typ max Unit V OH1 IOH = -1 J. Ta = -20-+75°C. V AEF - 0.LA V IOL = 1 J.8 - - V V OH3 IOH =-SJ.LA Output "High" Voltage Port A. B.1 - J. -________________~V·OH1 __________~------~~~~VOH2 ________________~~~--~VOH3 • AID CONVERTER CHARACTERISTICS (Vee = 3. ______. Ta = -20 -+75°C. C V IL I nput Leakage Current Port A. C V OH Output "Low" Voltage Port A. B.1 - J.LA 2.8 - V V OH3 IOH = -1 J. B.0V.LA 0.0V I nput Leakage Current Port A.LA 1. typ means typical value at 3V unless otherwise noted.2 V V OH1 IOH = -SJ. C liLA V in = OV LCD DRIVER OUTPUT CHARACTERISTICS (Vee Item Output "High" Voltage Output "Low" Voltage Output "High" Voltage Output "Low" Voltage (NOTE) Segment Common Common min typ max Unit - 2.LA 0. C = 300 pF. B.2 V V OL2 IOL =SJ.

see "Reset".- S016 S017 LC05 Dati Reg. Then the upper 4 bits (PCH) are stacked. These may also be used as level check inputs under program control. V2 and Vee· • MEMORY The memory map of the MCV is shown in Figure 1. Input/Output Terminals (Ao '" A" Bo '" B" Co'" C3 ) Each of these 20 terminals consists of two 8 bits ports and one 4 bits ports. 1 • STANDBY An external input terminal used halt all MCV operations and hold data. • XTAL.- SOlA SOlS SYS CTRL Reg. $FF4 ------------STACK S060 • S07F Interrupt Vectors ROM • Writ. • VI. SEG I '" SEG I . "AID Converter".' LCOB OltlReg. Vee is a positive power input port and Vss is grounded. Connect it to Vee. $OOB Timer CTR L Reg. AID Input Terminals (CH I 1 1 '" I Port C $002 Not Used $003 Port A ODR' $004 Port B DOR' $005 Not Used CHs) Input terminals for analog voltages needed for A/D conversion. Vss Power is applied to the MCV at these two terminals. • TIMER An external input terminal at which the internal timer is counted down. For the method of using the input terminals.----------------------------------------------------------HD63L06 • SIGNALS The input and output signals of the MCV are described in the following: • Vcc. the contents of the MCV registers are saved into the stack in the order shown in Figure 2. driving segments.768kHz crystal. During processing of an interruption.) These are 6 x 7 segments LCD terminals. while SEG I '" SEG I. • VCH Output Terminal from Internal Voltage Regulator (A capacitor is connected between VeH and Vcd. PCL) are saved into the stack. For details. $000 SOOE $OOF SOlO Not Used • VRH. CC 2 Connected to CC I and CC 2 are A/D converter offset compensating capacitors. the stack pointer is decremented and the lower byte (PCL) of the program counter is the first to be stacked. • E System Clock Output (Cycle clock). 0 Port A SOOO $001 Port B • RES Vsed to reset the MCV. • XIN. For details. "Interruptions" . For details.' S019 LC07 OataRlg. COM I '" COM 3 are for driving common electrodes.- S015 LC03 Data Aeg.. 1--------. For details. EXTAL These are control input ports to the built-in clock circuit. For details.. Capacitors are connected between VI. S013 Main ROM 13632 Bytes) • CC I . see the information. • INT This terminal is used to envoke an external interruption to the MCV.. Reg.a Reg. • 1 I Port C DOR' Not Used $006 $007 Timer Data Reg. the contents of only the program counters (PCH. SF30 D8te Reg. For pulling. see "A/D Converter". "Internal Oscillator Option". For details. A clock operation is possible by using a 32. AID CTR L Reg. the saved contents are pulled in order while the stack pointer is being incremented. ''Timer''. A crystal or resistor is connected to each of them depending on the degree of stability of the internal oscillation.- SOlS LC06 O.. • NUM This is not intended for user applications. V2 These are terminals for LCD driver.. see "Internal Oscillator Option". During saving. see "Internal Oscillator Option".. Only Register 112 Bytes) • '--_ _ _ _ _ _-' SFFF Figure 1 MCU Memory Map 253 . are for SF2F LCOl LC02 S01C SOlO Not Used S01F S020 RAM 196 Sytes! $FF3 1--------. For details. see the information. It may be used as an input or output under program control of the data direction register. see the information given under the title. For details. For details.VRL Reference voltages for A/D conversion are applied to these two terminals. For details.. In the case of a subroutine call. see "A/D Converter". see "Input/Output" . They can be used as outputs only under program control.- LC04 OataReg. Self Check ROM 1196 Bytes) • Liquid Crystal Driver Terminals (COM! '" COM 3 . see the information. XOUT Connected to these terminals are crystals for the oscillator on the time base. $009 SOOA Not Used AID Data Reg. see "LCD Circuit".' S014 Oat.

the Interruption Request Flag is not acknowledged. the stack pointer is set to address $07F. Carry/Borrow (C) Indicates the carry/borrow that occurred in the most recent arithmetic operation.e . this index register is used for index addressing mode. At the beginning. It is decremented each time data is saved. Its configuration is shown in Figure 4. • • • Program Counter (PC) The program counter. During MCU resetting or a reset stack pointer (RSP) instruction. 254 . Zero (Z) Condition Code Register Carry/Borrow Zero Negative I nterrupt Mask Used to indicate that the result of the most recent arithmetic operation. Since a subroutine or interruption can use addresses up to $061 for saving. This bit is affected by the Bit Test and Branch instruction. o 0 Figure 4 System Control Register Configuration )1 Reset Time Base Interruption Request Flag (TB INT) Stores an' interruption request flag from the time base which is selected by the TB select bit. external (I NT) . A/D masked. the held. logical operation or data processing is a zero. They are shown in Figure 3. Time Base Interruption Mask (TB MASK) If this bit is set. each bit showing the result of an instruction having just been executed. Program Counter Negative (N) 0 I Accumulator A 0 I X 11 timer. any interrupt request from the time base is not acknowledged. Intl!rrupt (I) 7 Index Register When this bit is set. Half Carry • Figure 3 Programming Model • Accumulator (A) SYSTEM CONTROL REGISTER Apart from the registers for program operation explained above. there is a register that controls system operation. This accumulator is an ordinary 8 bits register.HD63L05-----------------------------------------------------------o 7 1 1 11 n-4 Condition Code Reg. it is possible to call subroutines up to level 15. If the TB mask or I (Interrupt Mask Bit in the CCR) is set. the stack pointer is set at address $07F.· When the register is not referenced to by the instruction being executed. It is used to accumulate operands and the results of arithmetic operations or data processing. The upper 7 bits of the stack pointer are fixed to 0000011. • SYS CTRl Register o Index Register (X) Being an 8 bits register. logical operation or data processing is negative (i. The index register X may also be used for processing a limited range of data at a Read/Modify/Write instruction. and incremented each time data is reset. a 12 bits register. The five bits of the condition code register are used as follows: Half Carry (H) • REGISTER The CPU has five registers that can be operated by the programmer. contains the address of the next instruction to be executed. Pull n+1 n-3 Accumulator n+2 n-2 Index Register n+3 1 1 1 1 n-1 I PCH* PCl* n+4 n+5 Push • • * Only the PCH and PCl are stacked in the case of a subroutine call. If an interruption interruption information is after the interruption mask 0 PC 11 5 4 10 I 0 10 10 1 0 11 11 1 0 SP I Stack Pointer Used to indicate that the result of the most recent arithmetic operation.. all of the and time base interf'lptions are occurs with this bit (I) set. The address contained in the register is composed of 8 bits. An execution address can be obtained by adding the 8 bits to an offset value. All bits can be tested by conditional Branch instructions. Shift instruction and Rotate instructions. Used to indicate that a carry occurred between bits 3 and 4 during an arithmetic operation (ADD. ADC). bit 7 being at logical" I "). Figure 2 Interruption Stack Sequence Stack Pointer (SP) The stack pointer is a 12 bits register that indicates the address the next save space on the stack. It is processed immediately bi t (I) is reset. Condition Code Register (CC) The condition code register is a 5 bits register. it can be used as a temporary storage area.

an interruption from the I-second cycle time base is acknowledged. The LCD drive signal is based on 1/3 bias .. there are two types of internal clock signals within the MCU to allow timer operation when the CPU is halted. Then it fetches a timer interruption vector and executes an interruption routine. At the time of resetting. Clock inputs to the timer may be the input signal that is applied from an external source to the timer input terminal. When this bit is set.. A combined use of the Halt and Time Base Interruption functions permits the CPU to operate intermittently.. when this bit is set. Then the timer interruption request bit is cleared and the timer interruption request mask bit is set. or the clock signal within the MCU.. there are switching circuits built in for expanded LCD capabilities and output only ports. These clock signals are under program control. the timer continues counting. ____ JI Program Control Write Read Figure 5 Timer Block Diagram TIMER CTR L Register 1 1 ~ Indicates Frequency Bit Count Interruption Request at "1" Mask at "1" .' ~----------Timer at "1" Counter at "0" '----------------tP2 at"1" (100kHz) tP32k at "0" (32kHz) Figure 6 Timer Control Register Configuration 255 . the CPU halts and is wait-for-interrupt state. In logical "1".. without disturbing the contents of the counter. It starts countingdown immediately after clock inputs are applied.and the counter are all initialized to logical" I". If the count comes to below zero. it resets the frequency divider and after that.. So. Normally.. When the timer count comes to zero. the pre scaler . the count below zero can be monitored anytime by reading the timer data register... Then. After all registers have been saved. the timer interruption request bit (bit 7) in the timer control register is set. The interruption mask bit (I) within the condition code register also inhibits a timer interruption. Time Base Select Bit (TB SELECT) This bit selects the time base. If the bit is reset by an external interruption or time base interruption. Timer Input Terminal ~ _ _ _ _ _ _ _ _ _ _ _ Timer Output r----' I 1 . 1/ I6-second cycle time base is acknowledged.. • Time Base Reset Bit (TB RESET) This bit resets the frequency divider behind the 32kHz oscillator. If the internal clock signal is used as the source. In response to the interruption request. For details. this permits easy measurement of its pulse width. the registers are saved into the stack in the same sequence as in interruption processing. one shot reset pulse is generated by the hardware.(Timer I nterrup· tion Request) I I I I. However. • EXT • Duty Select Bit (DUTY) Used to switch the hardware configuration for expanded LCD capabilities. Any timer interruption can be masked by setting the timer mask bit (bit 6) within the timer control register. the CPU restarts operating..1/3 duty. it is need to pay an attention when "TB RESET" is used. see the infor- • TIMER Figure 5 shows a block diagram of the MCU timer. Also.. it indicates logical "0" to the CPU. As this bit has not a register. • Halt (HALT) Used to halt the CPU. This 8 bits counters is loaded under program control. it is reset.----------------------------------------------------------HD63L06 • mation given in "LCD Circuit" . The number of bits of the prescaler can be program controlled by the lower 3 bits within the timer control register. In logical "0". The frequency divider provides the system clocks to the A/D converter and LCD driver. A 7 bits prescaler is provided to increase the timer's timing interval. the clock input is gated by the input applied to the timer input terminal.. the MCU saves its contents into the stack. the frequency divider restarts.

HD63L06---------------------------------------------------------•

RESET

The MCV can be reset either by an external reset input
(RES) or by applying power. In the latter case, the reset input
must be "Low" for a sufficient length of time to have the
internal oscillator stabilized. A sufficient time of delay is generated by connecting a capacitor to the RES input as shown.

VCCT:~":,----n/
GND-----',

-t

V1

An T"m''''

,

"

Built-in Reset

~VIL
1_

1

V1H

'

HD63L05
MCU

-----

~--------~I~

Figure 8 Input Reset Delay Circuit

Figure 7 Application of Power and Reset Timing

INTERNAL OSCILLATOR OPTION

• Oscillator 1 (XTAL, EXTAL)

The MeV incorporates two oscillators: oscillator 1 for system clock supply and oscillator 2 for time base interruption,
LCD driving and clock supply.

The internal oscillator circuit can be driven by an external
crystal or resistor depending on the stability. Which to select,
crystals or resistors, is determined by the mask option at the
time of LSI production. The oscillator 1 can stop when power
is applied in either Halt or Standby status. Figure 9 shows
the connection.

EXTAL
XTAL
Vee

HD63L05
MCU

HD63L05
MCU

6
Crystal Oscillator

Vee
Ext. Clock
Input

Vee

EXTAL
XTAL

RC Oscillator

.....-'''''~----4

EXTA,L

Ext. Clock
Input

MCU

HD63L05
MCU

Ext. Clock

Ext. Clock

Crystal Option

Resistor Option

Figure 9 Mask Option for Oscillator 1

256

------------------------------------------------------------HD63L05
• Oscillator 2 (XIN, XOUT)
Clocks for time base interruption and LCD driving can be
supplied by connecting a 32.768kHz crystal. In Halt status,
oscillator 2 operates and this permits low power dissipation,

as well as steady LCD driving and clock operation. In Standby
status, this oscillator stops when power is applied. Figure 10
shows the connection; the relation between oscillators 1 and
2 is shown in Figures 11 and 12.

XOUT

CJ

HD63L05
MCU

XIN

CPU Clock

Veer
HALT---~

Crystal Oscillator

,--______. . . .1I _

STANDBY

Freq. Divider

Time base
Interrupt

XOUT

Vee
XIN

Vee

HD63L05
MCU

Figure 11

Relation between Oscillators 1 and 2

Not Used

Figure 10 Connection of Oscillator 2

When OSC 1 is RC

When OSC1 is X-TAL
Mask Option
State
~

OSC2
Not Available
OSC1

OSC2
Available

CPU Peripheral OSC1

OSC2
Available

OSC2
Not Available

CPU Peripheral OSC1

CPU Peripheral OSC1

CPU Peripheral

During System
Operation

0

0

0

0

0

0

0

0

0

0

0

0

At Halt
At Standby

0
X

X
X

0
X

0
X

X
X

0
X

0
X

X
X

0
X

X
X

X
X

0
X

(NOTE)

0 ..... run

x ..... stop
Figure 12 Oscillator 2 Mask Option and System Operation

NOTE IN OSCILLATOR SELECTION

When OSC2 is not available, the clocks for the AID converter and
LCD drivers are provided by the OSCI through the frequency divider.
When OSCI is crystal, OSCI is not allowend to stop at HALT. Because
the response of the oscillator is not so fast. The accuracy of the time
base is kept when OSC2 is 32.768 kHz crystal oscillator.

INTERRUPTION
There are six different interruptions to the MCV: external
interruption (INT), interruption envoked via an input terminal,
internal timer interruption, interruption by termination of
AID conversion, time base interruption (2 types), and interruption by an instruction (SWI).

When an interruption is envoked, the job in progress is
suspended and the state of the MeV is saved into the stack.
Also, the interruption mask bit (I) of the condition code register
is set and the start address of the interruption routine is obtained from the specified vector address. Then, the routine is
executed. The RTI instruction is used where control is returned
to the program to which the interruption was envoked, after
the interruption service routine has been completed.
Table 1 shows the relation between interruptions, priority
and vector addresses. Figure 13 shows the system operation
flow, in which the portion surrounded with dot-dash lines
contains the interruption execution sequence.

257

HD63L06-------------------------------------------------------Table 1 Interruption Priority
Priority

Vector Address

RES

1

SWI
INT

2

3

$FFFE,$FFFF
$FFFC,$FFFD
$FFFA,$FFFB

TIMER

4

$FfiF8, $FFF9

AID
TIME BASE

5
6

$FFF6,$FFF7

Interruption

$FFF4,$FFF5

Standby
Operation
Sequence

Figure 13 System Operation Flowchart

Acknowledging an INT in HALT Status

In HALT status, the CPU is not operating but the peripherals
are operating. When an interruption is acknowledged, the CPU
is activated and executes interruption service matching the
interruption condition by means of vectoring.

Acknowledging an INT in Standby Status

In Standby status, the system is not operating with power
supplied to it, therefore, any interruption request (including
m) is not acknowledged.

258

---------------------------------------------------------HD83L06

INPUT/OUTPUT

There are 20 input/output terminals, which are program
controlled by data direction registers for use as either input or
output. If an I/O port has been programmed as an output and
is read, then the latched logical level data is read even though

the output level changes due to the output load.
If a port is to be used as an input terminal, the user must
specify whether or not it will be equipped with a pull-up PMOS.
Figure 14 shows the port I/O circuit.

Output
Data Bit

1/0 Pin

Bits of
Data
Direction
Register

Figure 14 Port I/O Circuit

Configuration of Port

Figure 15 shows the configuration of I/O ports. As the
output is on/off controlled by a data direction register, an I/O
port may directly be applied as an input terminal. No problem

Bit of Output Data

Output
State

Input to
MCU

0

0

0

x

3-State

Pin

1
0

is involved with the input if both "High" and "Low" levels
are applied. For only one level, the user must specify the use
of a pull-up PMOS for "Open/Low" input application.

Pull-up PMOS available

Pull-up PMOS not available

rVss~

,.--,
I

,--

..
I

I

:
---' __ L..... __

r

~

VSS

Vss

Vss

Figure 15 Selection of Input Configuration for I/O Port

259

HD63L06---------------------------------------------------------• AID CONVERTER
The MCU incorporates an 8 bits AID converter based on the
resistor ladder system. Figure 16 shows its block diagram.
Offset Camp. Capacitor

r1
r-l- -,
CC1

CC I

CHI
Multiplexer

I
I

I

~~:

} MASK OPTION

CH.

S

'--_ _.....I.----(CH. )

I

Multiplexer

I

L __ ~.£ontr:2!J

MPX

_ _ _---'''-_ _ _ _ _ _ _ _.x...._ _ _ _ _

Data Bus

Channel

000

CHI

001

CH 1

010

CH 3

011

CH 4

100

CH.

101

CH 6

110

(CH 7 )

111

(CH.)

Figure 16 8 Bits AID Converter Block Diagram

The "High" signal of reference voltage is applied V RH, while
the "Low" signal is applied to V RL. The reference vol tage is
divided by resistors into voltages matching each bit, which then
is compared with analog input voltage for AID conversion.

~_~

_ _- L_ _

o

~~_~_~

o

o

_______

o

o

~

AID CTRL
Register

0

Figure 17 AID Control Register Configuration

the AID conversion ends.
In AID conversion, supply voltage is applied to the comparator only when CNY ="1". The digital data obtained by the
AID conversion is held in the AID data register. This data is
reset when the CNY is set to "1" again.
• AutolProgram
Used to select either auto-run 8 bits AID conversion or 8
bits programmed comparator operation (Auto 8 bits AID
conversion at "0").

This voltage comparison system achieves high input impedance. Offset are compensated for by external capacitors.
Figure 17 shows the configuration of the AID control register.

• COMP OUT

• AID INT
Used to request an interruption after completion of AID
conversion (Request at "1").

• MPX

• AID MASK
Used to mask interruptions after completion of AID conversion (Masking at "I").

CNV

To start AID conversion, set this bit to "I". During conversion, "1" is held. Tlie bit is automatically reset to "0" when

The result of comparator operation under program control
can be read from this bit (At "1", input> reference voltage).
Used to select 8-channel analog inputs. The multiplexer is
an analog switch based on CMOS.
LCD CIRCUIT

The system configuration of the LCD circuits is shown in
Figure 18. Segment data for display are stored in data registers
LCDI to LCD8. Since the circuits are connected to the output
terminals via a pin location block, the user may specify a combination of data to be multiplexed to the segment output
terminals.

260

----------------------------------------------------------HD63L05
SEG.
SEG,
SEG,
SEG.
SEG.
SEG.
SEG,
SEG.
SEG.
SEG ••
SEG ..
SEG ..
SEG ..
SEG ••
SEG ..
SEG ..

Pin Location
Block

SEG .. -SEG"
Mask Option

System
Cont.
Duty

Contents of
SEG 1 -SEG 17

00

OUTPUT PORT

01

---

SEG"

10

---

11

1/3 Bias
1/3 Duty LCD

Data Reg.
COM.
COM,
COM,

4>.4>,4>,

o

I

System Cont. Reg.

Duty

I

Figure 18 LCD Circuit System Configuration

• LlaUID CRYSTAL DRIVER WAVEFORMS
The LCD circuit is based on 1/3 bias - 1/3 duty driving.
Figure 19 shows the common electrode output signal waveforms
(COM I , COM2, COM3), segment signal waveforms (SEG 1
through SEG 1,), and LCD bias waveforms (COM-SEGMENT).
The segment output terminal may be used as an output-

only terminal if the duty of the system control register is so
specified. Assignment of segment terminals to the bits of the
LCD data register, including the case where they are used as
output-only terminals, is to be specified by the user when he
orders masks.

COMMON 1

COMMON 2

COMMON 3

SEGMENT

(1.2.3)

COM, ·SEGMENT

COMo·SEGMENT

COM,·SEGMENT

Vee

Fb:
"1"

GND

Output level.
"0" matching Data in

Regilte,

Figure 19 LCD Waveforms

261

HD63L05-------------------------------------------------------•

BIT PROCESSING
This MCV can use one instruction (BSET, BCLR) to set
or clear one bit of the RAM or I/O port (except for the data
direction register). All bits of I/O or memory on page 0 are
tested by the BRSET and BRCLR instructions. Depending
on the result of the test, the program can be branched. Since
the bits within the RAM, ROM or I/O can be processed by the
MCV, the user can easily use a bit in the RAM as a flag or
utilize a single I/O bit as an independent control terminal.

ADDRESSING MODE
There are 10 addressing modes available to the MCV for
programming. Familiarize yourself with these modes by reading
the information and referring to the diagrams that follow.

Immediate
See Figure 20. In immediate addressing mode, constants
that will not change during execution of a program are accessed.
The instruction used for that purpose has a length of 2 bytes.
The effective address (EA) is PC. The operand is fetched from
the byte that follows the OP code.
• Direct
See Figure 21. In direct addressing mode, the address of the
operand is contained in the second byte of the instruction.
The user can gain direct access to the LSB 256 of memory. All
RAM bytes, I/O registers, and 128 bytes of ROM are located
on page 0 in order to utilize this useful addressing mode.

Extended
See Figure 22. The extended addressing mode is used for
referencing to all addresses of memory. The EA consists of
the contents of the two bytes that follow the OP code. The
instruction used for extended addressing has a length of 3
bytes.

Relative
See Figure 23. Only Branch instructions are used in relative
addressing mode. When a branching takes place, the contents
of the byte next to the OP code are added to the program
counter. EA =(PC) + 2 + ReI., where ReI. indicates signed 8 bits
data at the address following the OP code. When no branching
takes place, ReI. = O. When a branching occurs, the program
jumps to any byte of +129 to -127 of the current instruction.
The length of the Branch instruction is 2 bytes.

Indexed (without Offset)
See Figure 24. In this addressing mode, the lower 256 bytes
of memory are accessed. The length of the instruction used
for this mode is one byte. The EA consists of the contents of
the index register.

Indexed (8 Bits Offset)
See Figure, 25. The EA consists of the contents of the byte
following the OP code, and the contents of the index register.
In this mode, the lower addresses of memory up to 5 II can be
accessed. Two bytes are required for the instruction.

Indexed (16 Bitl Offset)
See Figure 26. The EA consists of the contents of the two
bytes folloWing the OP code, and the contents of the index
register. In this mode, the whole of the memory can be accessed. The instruction using this addressing mode has a length of
3 bytes.

Bit Set/Clear
See Figure 27. This addressing mode can be applied to any
instruction that permits any bit on page 0 to be set or cleared.
The byte following the OP code indicates an address within
page O.

• Bit Test, Branch
See Figure 28. This addressing mode can be applied to instructions that test bits at the first 256 addresses ($00 to $FF)
and are branched by relative qualification. The byte to be tested
is addressed by the contents of the address next to the OP code.
The individual bits of the byte to be tested are designated by
the lower 3 bits of the OP code. The third byte indicates a
relative value that is to be added to the program counter when
a branch condition is satisfied. The instruction has a length
of 3 bytes. The value of the bit that has been tested is written
at the carry bit of the condition code register.

Implied
See Figure 29. There is no EA for this mode. All information
needed for execution of instructions is contained in the OP
code. Operations that are carried out directly on the accumulator and index register are included in the implied addressing
mode. In addition, the SWI and RTI instructions are also included in the group of this operation. The instruction using
this addressing has a length of one byte.

262

--------------------------------------------------------HD83L06

Memory

,i
I

I

I

8
I

PROG LOA # $F8 05BE

05BF

A

Fa
Ind,J,Q.:QD"'-_ _ _...

Steck Point
I

I

A6
1-------1
F8

Prog Count
06CO
CC

~
I
I
I,

Figure 20 Example of Immediate Addressing

t

Memory

•I

lEA

,
,,
i

,
I

I
I

I
I

I

/

t
Adder

'"
~

A

r

0000

20

CAT FCB 32 0048

I

004B

-.

I

I

I

PROG LOA CAT 0520

86

052E

48

Steck Point

I
I

~

I

I
I

,,

Figure 21

Example of Direct Addressing

263

20

1

Index Reg.

I
Prog Count
062F
CC

I
I
I

HD63 L06-------------------------------------------------------

Memory
i
i
I

§
I

PROG

LOA CAT

0000

0409~6
06

040A
040B

A

I

E5

40

J

Index Reg

-------..

Stack Point
I
I

Prog Count

40

CAT FCB 64 06E5

040C

1-------1

CC

Figure 22 Example of Extended Addressing

Memory

ii

§

A

Index Reg

Stack Point

I

I

PROG BEQ PROG2 04A7

27

04A8

18

I

§

0000

I
i
i

Figure 23 Example of Relative Addressing

264

------------------------------------------------------------HD63L05

Memory

A

TABL FCC/LI/ 00B8

4C
I-----~
49

4C
Index Reg
B8

I

PROG LOA X

I

Stack Point

05F4~

Prog Count
05F5
CC

§
Figure 24 Example of Indexed (without Offset) Addressing

lEA
I

Melory

I

I

008C

I

BF

/

Adder

FCB # 86 008A

86

FCB # DB 008B

DB

FCB # CF 008C

CF
I
I

PROG LOA TABL.X 075B

E6

075C

89

~

I
I
I

I

t

I

I
TABL FCB # BF 0089

I

'"

A

r
~

r

CF

I

Index Reg
03

1

Stack Point

I

I

I

Prog Count

I

075E
CC

I

I

§
Figure 25 Example of Indexed (8 Bits Offset) Addressing

I

HD63L06----------------------------------------------------------

Memory

i
I

§

A

DB
Index Reg

I

I

02

~6

PROG LOA TABL.X 0692
0693

07

0694

7E

Stack Point
1-------'

Prog Count

0695
I

CC

I

TABL FCB # BF 077E

BF

FCB # 86 077F

86

FCB # DB 0780

DB

FCB # CF 0781

CF

Figure 26 Example of Indexed (16 Bits Offset) Addressing

Memory

PORT B EQU 1 0001

BF

A

0000
Index Reg

PROG BCLR 6. PORT B 058F
0590

10
I-----~
01

L
I

I

I

I

Stack Point

I
Prog Count

0591

I

CC

~

I

I

I

Figure 27 Example of Bit Set/Clear Addressing

266

--------------------------------------------------------HD63L06

PORT C EaU 2 0002

A

FO

Index Reg

0000

Stack Point

PROG SRCLR 2. PORT C. PROG 2 0574 ' -_ _ _0..;.,5_ _-f
0575

02
~------1
0576
10
~------1

Prog Count

0000

0594

CC

C

Figure 28 Example of Bit Test and Branch Addressing

Memory

I
I

I

I
I

~

8
§
I

PROG TAX OSBA

E5
Index Reg

I

E5

I
I

Prog Count
OSSB

CC

I

I

I

I

Figure 29 Example of Implied Addressing

HD63L06---------------------------------------------------------•

INSTRUCTION SET
There are 59 instructions available to the MCV. They can
be divided into five groups: Register/Memory, Read/Modify/
Write, Branch, Bit Processing, and Control. All of these instructions are explained below according to the groups, and are
summarized in individual tables.

Register/Memory
Most of these instructions use two operands. One operand
is either the accumulator or index register, while the other is
acquired from memory using one of the addressing modes.
No operand of register is available in the unconditional Jump
(JMP) and Subroutine Jump (JSR) instructions. See Table 2.

Read/Modify/Write
These instructions read a memory address or register, modify
or test its contents, and writes a new value into the memory or
register. Negative or Zero instructions (TST) do not provide
writing, and are exceptions for the Read/Modify/Write. See
Table 3.

• Branch
A Branch instruction will branch from the program sequence
in progress if the specific branch condition is satisfied. See
Table 4.
• Bit Processing
This instruction can be used for any bit of the first 256
bytes of memory. One group is used for setting or clearing,
while the other is used for bit testing and branching. See Table 5.
• Control
The Control instruction controls the operation of the MCV
for which a program is being executed. See Table 6.
• A List of Instructions Arranged in Alphabetical Order
All instructio~s are listed in Table 7 in the alphabetical
order.
• OP Code Map
Table 8 shows an OP code map of the instructions used
with the MCV.

268

----------------------------------------------------------HD63L05
Table 2

Register/Memory Instructions
Addressing Mode

Immediate
Operation

Mnemonic

Op
Code

Direct

#
Op
#
Bytes Cycles Code

Op
#
#
Bytes Cycles Code

Indexed
(8-BitOffset)

Indexed
(No Offset)

Extended

Op
#
#
Bytes Cycles Code

Op
#
#
Bytes Cycles Code

Indexed
(16-8it Offset)

Op
#
#
Bytes Cycles Code

---#

#

Bytes Cycles

Load A from Memory

LDA

A6

2

2

B6

2

3

C6

3

4

F6

1

2

E6

2

4

D6

3

Load X from Memory

LDX

AE

2

2

BE

2

3

CE

3

4

FE

1

2

EE

2

4

DE

3

5

Store A in Memory

STA

-

-

-

B7

2

4

C7

3

5

F7

1

3

E7

2

5

D7

3

6

Store X in Memory

STX

-

-

-

BF

2

4

CF

3

5

FF

1

3

EF

2

5

DF

3

6

Add Memory to A

ADD

AB

2

2

BB

2

3

CB

3

4

FB

1

2

EB

2

4

DB

3

5

Add Memory and
Carry to A

ADC

A9

2

2

B9

2

3

C9

3

4

F9

1

2

E9

2

4

D9

3

5

Subtract Memory

SUB

AO

2

2

BO

2

3

CO

3

4

FO

1

2

EO

2

4

DO

3

5

Subtract Memory from
A with Borrow

SBC

A2

2

2

B2

2

3

C2

3

4

F2

1

2

E2

2

4

D2

3

5

AND Memory to A

AND

A4

2

2

B4

2

3

C4

3

4

F4

1

2

E4

2

4

D4

3

5

OR Memory with A

ORA

AA

2

2

BA

2

3

CA

3

4

FA

1

2

EA

2

4

OA

3

5

Exclusive OR Memory
with A

EOR

A8

2

2

B8

2

3

C8

3

4

F8

1

2

E8

2

4

D8

3

5

Arithmetic Compare A
with Memory

CMP

Al

2

2

Bl

2

3

Cl

3

4

Fl

1

2

El

2

4

Dl

3

5

Arithmetic Compare X
with Memory

2

2

B3

2

3

C3

3

4

F3

1

2

E3

2

4

D3

3

5
5

--

5

CPX

A3

Bit Test Memory with
A (Logical Compare)

BIT

A5

2

2

B5

2

3

C5

3

4

F5

1

2

E5

2

4

D5

3

Jump Unconditional

JMP

-

-

BC

2

2

CC

3

3

FC

1

2

EC

2

3

DC

3

4

Jump to Subroutine

JSR

-

-

-

BD

2

4

CD

3

5

FD

1

3

ED

2

4

DD

3

5

Symbols: Op = Operation

# = Instruction

Table 3 Read/ModifylWrite Instructions
Addressing Mode

---Implied (A)
Operation

Mnemonic

Implied (X)

Op
Code

#

#

Bytes

Cycles

Op
Code

Indexed
(No Offset)

Direct

I T ,Cycles
#
Bytes

Op
Code

#

#

Bytes

Cycles

Indexed
(8-Bit Offset)

Op
Code

#

#

#

Cycles

Op
Code

#

Bytes

Bytes

Cycles
5

Increment

INC

4C

1

1

5C

1

1

3C

2

4

7C

1

3

6C

2

Decrement

DEC

4A

1

1

5A

1

1

3A

2

4

7A

1

3

6A

2

5

Clear

CLR

4F

1

1

5F

1

1

3F

2

4

7F

1

3

6F

2

5

Complement

COM

43

1

1

Negate
(2's Complement)

NEG

40

1

1

- - r----

----

f--

53

1

1

33

2

4

73

1

3

63

2

5

50

1

1

30

2

4

70

1

3

60

2

5
5

Rotate Left Thru Carry

ROL

49

1

1

59

1

1

39

2

4

79

1

3

69

2

Rotate Right Thru Carry

ROR

46

1

1

56

1

1

36

2

4

76

1

3

66

2

5

Logical Shift Left

LSL

48

1

1

58

1

1

38

2

4

78

1

3

68

2

5

Logical Shift Right

LSR

44

1

1

54

1

1

34

2

4

74

1

3

64

2

5

Arithmetic Shift Right

ASR

47

1

1

57

1

1

37

2

4

77

1

3

67

2

5

Arithmetic Shift Left

ASL

48

1

1

2

4

78

1

3

68

2

5

Test for Negative or
Zero

TST

4D

1

1

5D

1

1

3D

2

4

7D

1

3

6D

2

5

Symbols: Op = Operation

# = Instruction

- - - - I - - - - f--------1
58
38
1
- ---

HD63L06--------------------------------------------------------Table 4 Branch Instructions
Relative Addressing Mode
Mnemonic

Op
Code

#

#

Bytes

Cycles

Branch Always

BRA

20

2

Branch Never

BRN

21

2

2 or 3 *

Branch IF Higher

BHI

22

2

2 or 3 *

Branch I F lower or Same

BlS

23

2

2 or 3 *

24

2

2 or 3 *

(Branch IF Higher·or Same)

BCC
(BHS)

24

2

2 or 3 *

Branch I F Carry Set

·BCS

25

2

2 or 3 *

(Branch IF lower)

(BlO)

25

2

2 or 3 *

BNE

26

2

2 or 3 *

Branch I F Equal

BEQ

27

2

2 or 3 *

Branch I F Half Carry Clear

BHCC

2B

2

2 or 3 *

Branch I F Half Carry Set

BHCS

29

2

2 or 3 *

Branch I F Plus

BPl

2A

2

2 or 3 *

Branch IF Minus

BMI

2B

2

2 or 3 *

Branch IF Interrupt Mask Bit is Clear

BMC

2C

2

2 or 3 *

Branch IF Interrupt Mask Bit is Set

BMS

20

2

2 or 3 *

Branch I F Interrupt Line is low

Bil

2E

2

2 or 3 *

Branch IF Interrupt Line is High

BIH

2F

2

Branch to Subroutine

BSR

AD

2

2 or 3 *
4

Operation

Branch I F Carry Clear

Branch I F Not Equal

3

Symbol: Op - Operation
# • Instruction
• If branchad. each instruction will be a 3-cycle instruction.

Table 5 Bit Processing Instructions
Addressing Mode
Bit Set/Clear
Operations

Mnemonic

Branch IF Bit n is Set

BRSET n (n = 0 ..... 7)

Branch IF Bit n is Clear

BRClR n (n = 0 ..... 7)

Bit Test and Branch

Op
Code

#

#

Bytes

Cycles

-

-

-

-

Op
Code
2-n

3

4 or 5 *

3

4 or 5 *

-

BSET n (n = 0 ..... 7)

10+ 2 - n

2

4

-

Clear Bit n

BClR n (n = 0 ...•• 7)

11+2-n

2

4

-

270

#
Cycles

01 + 2 - n

Set Bit n

Symbol: Op" Operation
# - Instruction
• If Branched. each instruction will be a 5-cycle instruction.

#
Bytes

-

Cleared Otherwise Not Affected 271 .---------------------------------------------------------HD63L06 Table 6 Control Instructions Implied Operation Mnemonic Op Code # # Bytes Cycles Transfer A to X TAX 97 1 Transfer X to A TXA 9F 1 1 Set Carry Bit SEC 99 1 1 Clear Carry Bit ClC 98 1 1 Set Interrupt Mask Bit SEI 9B 1 1 1 Clear Interrupt Mask Bit CLI 9A 1 1 Software Interrupt SWI 83 1 9 Return from Subroutine RTS 81 1 4 Return from Interrupt RTI 80 1 7 Reset Stack Pointer RSP 9C 1 No-Operation NOP 90 1 1 1 Symbol: Op = Operation # = Instruction Table 7 Instruction Set Addressing Modes Mnemonic Implied Immediate ADC x ADD x AND x ASl x ASR x Direct x x x x x Extended Relative x x x x x x BCC BClR x BCS x x x x x x x x x x x Bit Set/ Clear BHCC BHCS BHI BHS BIH Bil x BlO x x x x x x x x x x BMI BMS BNE BPl BRA Symbols for condition code: H Half Carry (From Bit 3) I Interrupt Mask N Negative (Sign Bit) Z Zero • • • • • • • • x BlS H 1\ x x x BMC Bit Test & Branch 1\ x BEQ BIT Condition Code Indexed Indexed Indexed (No (8 Bits) (16 Bits) Offset) x x x x x x • • • • • • • • • • • • • • Z C • 1\ 1\ • 1\ 1\ • 1\ 1\ • 1\ 1\ • 1\ 1\ • • • • • • • • • • • • • • • • • • • • • e • • • • • • • • • 1\ 1\ • • • • • • • • • • • • • • • • • • • • • • • • 1\ I N 1\ • 1\ 1\ • • • • • • • • • • • • • • • • • • • (Continued) C 1\ • Carry/Borrow Test and Set if True.

~D63L06---------------------------------------------------------Table 7 Instruction Set (Continued) Addressing Modes Mnemonic Implied Immediate Direct Extended Relative Condition Code Indexed Indexed Indexed (No (8 Bits) (16 Bits) Offset) Bit Setl Clear Bit Test & Branch H I • • • • • • • • • • • • • • • • • • • • • • • N Z • • • • • • • C • RSP x • RTI x • • • • • • • 0 • • 0 • A • A • A • A • A • A • • • • • AA • • A • 0 • A • • • A • A • A • • ? ? ? ? RTS x • • • • • • • • • • • • • • • A A • • • 1 • • • A A • A A • A A 1 • • • • • • A A • • • • x BRN x x BRCLR BRSET x BSET BSR x CLC x CLI x CLR x 1< X x x x x x EOR INC X x CPX DEC x x CMP COM x x x x JMP JSR x x LOA LOX LSL x LSR x NEG x x NOP ROL x ROR x x SBC SEC SEI x x x X X X x x x x "x·· x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x • x x x x x x x x x x STA STX SUB )( SWI x TAX x TST x x TXA x x x x ORA x x x Symbols for condition code: Half Carry (From Bit 3) H I Interrupt Masl< N Negative (Sign Bit) Z Zero )( x x x x x x x x x x x x C A • ? x x x Carry/Borrow Test and Set if True. Cleared Otherwise Not Affected Load CC Register From Stack 272 • • • • • • ? 1 A A A A A A A A • • 0 • • A 1 A • • • • • • • A A A • • A A A A A • • A • A A A A • • A 1 • • • A • • • • .

The number of cycles for the asterisked (*) mnemonics is a follows: RTI 7 RTS 4 SWI 9 BSR 4 3.XO IMP IMP 7 8 9 ATI* RTS* - SWI* IMMj DIR AI B - EXT I C . 273 HIGH 0 6 A - Branch Test & Branch I 1/2 .X2 I I D E .X1 .I I 2/2 STX(+1) 2/3 I 3/4 I 3/5 0 E F I 2/4 1.X1 6 J I .----------------------------------------------------------HD63L06 Table 8 OP Code Map Bit Manipulation Control Read/Modify /Write I Register /Memory 1 l J 1 Set/ Clear Rei DIR 0 1 2 3 0 BRSETO BSETO BRA 1 BACLRO BCLRO BRN - 2 BRSET1 BSET1 BHI - 3 BRCLR1 BCLR1 BLS COM - CPX 3 L 4 BRSET2 BSET2 BCC LSR - - AND 4 o 5 W I I A 4 I 1 X 5 NEG I . "-" is an undefined operation code. If the instruction is branched. 2.xo I F SUB +- CMP 1 SBC 2 5 BRCLR2 BCLR2 BCS - - - BIT BRSET3 BSET3 BNE ROR - - LOA 6 7 BRCLR3 BCLR3 BEQ ASR - TAX STA (+1) 7 8 BRSET4 9 BRCLR4 BSET4 BHCC LSL/ASL EOR BHCS ROL - CLC BCLR4 SEC AOC 8 9 CLI SEI ORA A BRSET5 BSET5 BPL DEC B BRCLR5 BCLR5 BMI - C BRSET6 BSET6 BMC INC 0 BRCLR6 E BRSET7 BCLR6 BMS BSET7 SIL BRCLR7 BCLR7 3/4 or 5 2/4 f--- F (NOTES) NOP - - - - TXA 1/* 1/1 CLR BIH 2/20r 3 TST - 2/4 I 1/1 I 1/1 I 2/5 ! 1/3 RSP - - BSR* I I I JSR(+1) ADD B JMP(-1) C I JSR IJSR(+1 LOX . The figure in the lowest row of each column gives the number of bytes and the cycles needed for the instruction. The parenthesized figure must be added to the cycle count of the associated instruction. the cycle count is the larger figure. 4.

0 I 2 3 4 5 6 ¢WAITE (NOTE) U Mark a selected Multiplexed Timing and Segment Output Terminal with a circle (OJ. ~ ~ ~ LC01 LC02 Multiplexed Timing C 0 M 1 C 0 M 2 c 0 M 3 Segment Output Terminal sis ~I~ 1 2 s s s s s E G E G E G E G E G 3 4 5 6 7 s E G 8 s E G 9 s E G 10 s E G 11 s s s E G E G E G 12 13 14 15 16 17 0 1 2 3 4 5 6 7 0 1 2 3 4 7 0 1 2 3 4 5 6 LC05 0 1 2 3 4 5 6 0 1 2 3 4 5 6 LC06 LC07 LeOS 0 1 2 3 4 5 6 0 1 2 3 4 5 6 .HD63L05--------------------------------------------------------• HD63L05 LCD PIN LOCATION COMPOSITION TABLE ~ ~. In the case of Output or Static LCD driver. It is generated when LCD1 is rewritten by the CPU. 274 s E G 6 LC04 s E G 5 LC03 s E G . Multiplexed Timing is fixed at COM 1 • 4> WR ITE is a write clock for the external option (EXT = "'''J.

----------------------------------------------------------HD63L06 • HD63L05 1/0 COMPOSITION TABLE 110 Option Pin Name Remarks I/O A B C 0 I/O I/O I/O I/O I/O I/O I/O I/O !LO !LO I/O I/O Ao A1 A2 A3 A4 A5 As A7 Bo B1 B2 B3 B4 B5 Bs B7 Co C1 C2 C::I /LO I/O I/O I/O I/O I/O I/O I/O I INT 110 Option Pin Name SEG1 SEG2 SEG3 SE.1 0..1 0. Output Port H.1 0.1 0. A / 1\ I \ I \ I I II I I l~ /"'-.1 0. CMOS Output D.1 1\ II I J .1 0.~ 1 \ L 11 I I 1 I 1 1 V 1\ /\ / ~ / \ / \ 1f \I \. No pull up MOS B. Open Drain Output E. LCD Power Supply 275 .G4 SEG5 SEGs SEG7 SEGa SEGs SEG10 SEGll SEG12 SEG13/CHs SEG14/CH5 SEG15/CH4 SEG16/CH3 SEG 17/CH 2 V1/CH7 V2/CHa (NOTE) I/O Remarks F E G H J) °° °° °° °° ° ° ° 0. Mark a selected composition with a circle (0). Segment Output G. A. AID Input F. With pull up MOS C.

O All 0 0. 0 Vee '0 Vee 0 Vee 0 A.. 00. P. P. l l 40A. 0 A.. p. The H068POl can function as a monolithic microcomputer or can be expanded to a 65k byte address space. p •• ' OVSS Pit 1 'II' PO' 276 P.HD68P01V07 MCU (Microcomputer Unit) The H068POI is an 8-bit single chip microcomputer unit (MCU) which significantly enhances the capabilities of the HMCS6800 family of parts.. REi vee p .. parallel I/O and a three function Programmable Timer on chip. vee Standby PO' Vss I Type No. HN482764 128 Bytes of RAM (64 bytes Retainable on Powerdown) 29 Parallel I/O and Two Handshake Control Line Internal Clock Generator with Divide-by·Four Output Full TTL Compatibility Full Interrupt Capability Single-Chip or Expandable to 65k Bytes Address Space Bus compatible with HMCS6800 Family • TYPE OF PRODUCTS -PRELIMINARY- HD68POISO. P" P.. 0 0. OA. P" OA. 00. vee StandbY PO' P. EXTAL P» NMi P" iRCi... 4096 bytes or 8192 bytes of EPROM on package. and 2048 bytes. OA.. P. p. Sc. 0 A. OA. OA. P.. It includes an upgrade H06800 microprocessing unit (MPU) while retaining upward source and object code -compatibility.. HD68POIV05. OA. 0 0.. p . P" Pu Pu 1 11 ONe OA.HD68P01 SO. A summary of H068POl features includes: • • • • • • • • • • • • • • FEATURES Expanded HMCS6800 Instruction Set 8 x 8 Multiply Instruction Serial Communications Interface (SCI) Upward Source and Object Code Compatible with HD6800 16-bit Three·function Programmable Timer Applicable to All Type of EPROM 2048 bytes. P.. P. Execution times of key instructions have been improved and several new instructions have been added including an unsigned 8 by 8 multiply with 16-bit result. P" P. OA.0 P" P" P" p . 0 All 0 VssO A.. Serial Communications Interface (SCI). HD68P01V07 Sc... p . 0 0.. It can be used in production systems to allow for easy firmware changes with minimum delay or it can be used to emulate the H06801 for software development. OA..0 0. 0 0. It includes 128 bytes of RAM. PH 1 P. Vee 0 Vee 0 VccO A. It is TTL compatible and requires one +5 volt power supply.. OA. Bus Timing EPROM Type No. o Vee ONe OA. OA. l P II 14 OA. sc..... 0 0. P" P~ p . P. HD68P01S0 1 MHz HN462716 HD68P01V05 1 MHz HN462532 HD68P01V07 1 MHz HN462732 o Vee ONe OA. 00. 0 0. Vee Standby . PO' p . HD68POIV07 • PIN ARRANGEMENT (Top View) HD68P01V05 HD68P01S0 Vss 1 Vss 1 xrAL EXTAl NMi o Vee iiiO. Pn 1 OA. 1 .. sc. OVss p .. P" p . P" p . 0 Vee 0 0"£0 A. 0 sc.. P" P. P. 0 O. P14 t OA. p . 1 00.. P.. 'u " OA. ill P" vee P" p . 0 Vee 0 VssO AIO 0 CEO 0... p.0 0. o A. HN462732 or HN462532 8192 bytes.0 0. p... sc.0 0. P" p . OA. OVss l Vee 0 Vee 0 Vee 0 A. Pu 1 OA... PilI 00.. 0 A. OA. P" Pn 1 PO' p •• p . P.. HD68P01 V05.'1 00. 00. HN462716 4096 bytes. OA. p . OA. P" P" p .. 00.00. 0 O.O C"E0 0.

---------------------------------HD68P01S0.-----+PI6 tt-----+PI7 On Package r-..j I I I I I I I I I EPROM HN462716] [ HN462732 HN462532 Ao I Al A2 A3 A4 -As A6 A7 As A9 AIO Address Output Au l Ct:-___ AI21 ~ I I 00 I 01 I 02 I 03 I O.----+PI2 1+------+PI3 M-----+P 14 k-----+PIs .-----..JI ')77 . I Data Input 05 : 06 I 07 I IL _ _ _ _ _ _ _ _ _ _ ..-. HD68P01V05... HD68P01V07 • BLOCK DIAGRAM ~-~-+"'P20 I++-r-~>-t-+ I++-+-~~'" 1++-+-+--1~-+ P21 P22 P23 I++-+-+-tl-r+ P24 M----+PIO M-----+Pu .

0 4.0 mA 1200 mW 12.5 - - - Vin = 0 . SCl Cin f = 1.25 V SB 4.P47 SCl EXTAL Ilinl Input Leakage Current NMI.75 - 5.0 Extarnal Clock 4fo 2. SC z .0 2. - Other Outputs Output "Low" Voltage Test Condition Po - P47 .5 V 10.2.5.25V V in = 0.P 30 -P 37 Pzo .3 -+7.0 V SBB 4.A V 0. E. V 0.4V V in = 0.0 V in = 0 .0 MHz - Vee 0. Ta = 0.P47 .8 0.5V 1.A I LOAD = 1.5 10. Vss =OV.4 2.5 IJ.0 pF V mA MHz . Normal operation should be under recommended operating conditions.6 mA - -IOH V out = 1.0 - 5.P37 P40 . RES Ilinl Three State (Offset) Leakage Current PlO -P l7 .0V Unit 4.+70°C.145 IJ. P40 Other Inputs typ -0. Ta = 25°C.0V±5%.8 Powerdown V SBB = 4. SC l .0 V -0.4 VOL I LOAD = -100 IJ.0 Crystal fXTAL 3. HD68P01V05. it could affect reliability of LSI. HD68P01V07-------------------------------• ABSOLUTE MAXIMUM RATINGS Symbol Item Supply Voltage * Input Voltage Vee V in Operating Temperature Topr Storage Temperature T stg * * Value Unit -0.HD68P01S0. • ELECTRICAL CHARACTERISTICS • DC CHARACTERISTICS (Vee =5.4 2. A 2.unless otherwise noted.3 -+7.A 10 100 IJ.0 V in = OV.25 Powerdown ISBB - - 8.) Item Input "High" Voltage Symbol RES V1H Other Inputs* Input "Low" Voltage Allinputs* Input Load Current P40 .P37 .2.8 2. IRQl.+150 With respect to VSS (SYSTEM GND) [NOTE] Permanent LSI damage may occur if maximum ratings are exceeded.579 - 278 V mA Operating * Except Mode Programming Levels: See Figure 8.0 V °c 0 -+ 70 °c -55 .3 VIL All Outputs Darlington Drive Current PlO Power Dissipation min 4. Output "High" Voltage Input Capacitance Vee Standby Standby Current Frequency of Operation - max - Vee 0.A ILOAD=.4V ilTSd V OH I LOAD = -2051J.Vee Pl7 P30 .5 . If these conditions are exceeded.PZ4 P30 .

.. Ta = 0"'" +70°C. 2. unless otherwise noted..4 t pwo Fig. 2*.OV±S%.. Vss = OV.HD68P01 SO.... 2 Fig.rt3 Port 3 ** 10kn pull up register requ ired for Port 2 ns .) Symbol Test Condition min typ max Unit Peripheral Data Setup Time Port 1.3.4 tpOH Fig.OV ±S%..) Item Symbol Cycle Time Test Condition typ max Unit 1 - 10 200 - Ils ns 50 ns 50 ns min Address Strobe Pulse Width "High" tCYC PWASH Address Strobe Rise Time tASr 5 - tASf 5 - Address Strobe Fall Time Address Strobe Delay Time tAS O 60 - - ns Enable Rise Time tEr 5 50 ns Enable Fall Time 5 50 ns Enable Pulse Width "High" Time tEf PW EH - 450 - ns Enable Pulse Width "Low" Time PW EL 450 - - ns Address Strobe to Enable Delay Time Address Delay Time tASEO tAD Address Delay Time for Latch (f=1..4 - - 2.. 4 tCMOS Fig. 3 200 - ns Peripheral Data Hold Time Port 1. 12 - 100 - 200 - - ns 260 ns 270 ns - ns - ns (610) (600) - ns ns ns ns ns ms ns PERIPHERAL PORT TIMING (Vee = S. HD68P01 V07 • AC CHARACTERISTICS BUS TIMING (Vee = S. 6 50 - - ns tiS Fig. Enable Negative Transition to Peripheral Data Valid Port 1..3. 5 - - 350 ns Delay Time. 11 Fig. Enable Positive Transition to OS3 Negative Transition tOS01 Fig..4 tposu Fig.3. 5 - - 350 ns Delay Time.. Enable Negative Transition to Peripheral CMOS Data Valid * Port 2**. 3 200 - - Delay Time. 6 20 - - ns Item Input Strobe Pulse Width Input Data Hold Time Input Data Set-up Time *Except P21 -K..2.0 Ils tPWIS Fig.. 6 200 - - ns tlH Fig.. Enable Positive Transition to OS3 Positive Transition toso2 Fig. Ta = 0"'" +70°C. unless otherwise noted. 1 Fig. Vss = OV..0MHz) tAOL Data Set-up Write Time tosw Data Set-up Read Time tOSR 225 80 tHR 10 tHW 20 tAS L tAHL 60 20 Data Hold Time I Read I Write Address Set-up Time for Latch Address Hold Time for Latch Address Hold Time Peripheral Read Access Time l Non-Multiplexed Bus I Multiplexed Bus Oscillator stabilization Time - 20 tAH (tAC CN ) - (tACCM) tRC tpcs Processor Control Set-up Time 60 Fig.4 - - 400 ns Delay Time. HD68P01V05.

Enable Positive Transition to Timer Out tToD max - - ns -- -- 600 ns min Fig.Jl2.. unless otherwise noted..{ -- V -. Ta =0 -.) Symbol Item Mode Programming Input "Low" Voltage V MPL Mode Programming Input "High" Voltage V MPH Test Condition min typ max Unit - 1. Vss =OV.0V ±5%.7 V Fig.¥- O.2V Address Valid ) ) l'-+1 I I j-tAHl tosw-~2.2 .l\. PW EH J \ MPU Write Do-D."-PWASH- Address Strobe (ASt / -.Ar-A.6V j ~ -tADL- Data Valid }'f. SCI TIMING (Vee =5.-A.0V ±5%.6V -tOSR- \ -tAH .+70°C.8V Data Valid ItACCMt Figure 1 Expanded Multiplexed Bus Timing 280 - .0 150 - PW RSTL RES "Low" Pulse Width Mode Programming Set-up Time tMPs Mode Programming Hold Time tMPH . HD68P01V05.d. (Port 3t \. r- J -tAD- R/W .-A.) Item Symbol Timer Input Pulse Width tpWT Delay Time..+70o C.2V -lr Address \ Valid I O...4 V~ Enable (Et -- ~r ---.0V )~ !.0 3.-0" A.6V tASl-J MPU Read 0. ~ -tt-NV ~ l O.4 - 0." (SC~ (port4t Unit - ~tHR .-.. (Port 3t . .r. HD68P01V07--------------------------------TIMER. teye . Ta = 0 -.8 4..2V.HD68P01S0.6 tScyc = 5.ess ~~ Valid r. Vss = OV. / -tASf -tASr tASD ASEC 0'\ PW El -- ~ -- -tEr -tEf - }~2.-- O.2V 2.6V ..0 2.I{ \ ..0 .A.. O. 7 SCI Input Clock Cycle tSCYC SCI Input Clock Pulse Width tPWSCK MODE PROGRAMMING (Vee typ 2tcyc+ 2OO Test Condition 1 - -- tCYC 0. tcyc - tcyc -- ns . unless otherwise noted.6V-t- 2.

..SV Figure 2 Expanded Non-Multiplexed Bus Timing r- r-MPU Read MPU Write E E CMOS t P IO -P I7 P 20 .-0. -Access matches Output Strobe Select (OSS = 0. a read.2V r- 0.'f- Enable IE) PWEL 0. -tOSR- (tACCN) MPU Read 0.. ~ 2. r+--tosw--+ MPUWrite 2..0V Data Valid --------------------------------------~ O.. 27v'Jr- -. (Port 3) -tt-fill .. Port 4 cannot be pulled above Vee Figure 4 Port Data Delay Timing (MPU Write) E Address Bus OS3 ... 10 kn Pullup resistor required for Port 2 to reach 0.~ O.-.)l. HD68P01V05. O ..6V\" J ~~ Data Valid .7VCC 2. -tHR 2. OSS = 1...p. a write) Figure 5 Port 3 Output Strobe Timing (Single Chip Mode) Figure 6 281 Port 3 Latch Timing (Single Chip Mode) .. (Port 3) O.. .6V Data Valid p)O - (NOTE) -Port 3 Non-Latched Operation (LATCH ENABLE = 0) Figure 3 Data Set-up and Hold Times (MPU Read) 1. Not applicable to P11 3.5V-~ Rjlil iOS (SC2) (SCI) :"~ PW EH ~{ --\ J r-----tAO- AO"""'AJ(Port4 ) - tcyc - -- -tEr _tEf .-0.2V r- j -tAH Address Valid ..---------------------------------HD68P01S0..2V O.7 Vee 2.. 7 --+} -tPWD_ All Data Port Outputs Inputs P)7 Inputs" _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _J " ----0.6V\.. HD68P01V07 ...PH p..

:~~~... 7' p. R = 12 kn for p... E..I 1'---.. -p"... The Microprocessor Unit (MPU) is an enhanced HD6800 MPU with additional capabilities and greater throughput. HD68P01V05...-4. = 30 pF for p.. and type of external bus..~ ... = 24 kn for p. p •• -P.- ..p:: )-----. available on-chip resources. SC...- _oUO ?... SC.130PF Test Point 0-..- ~ .. it is controlled by its Data Direction Register and the programmer has direct access to its pins using the port's Data Register.. Each port consists of at least a Data Register and a write-only Data Direction Register. Software developed using the HD68POI can then be masked into the HD6801 ROM. R C =90 pF for P.~oo 21 8·Bit Accumulators A and B Or 16-Bit Double Accumulator 0 115 X 01 Index Register (X) 115 SP 01 Stack Pointer (SP) P5 PC 01 Program Counter (PC) Condition Code Register (CCR) Carry/Borrow from MSB Overflow Zero Negative Interrupt Half Carry (From Bit 3) Figure 10 282 HD68P01 Programming Model . It is upward source and object code compatible with the HD6800. p •• -P.. p. A list of new operations added to the HMCS6800 instruction set are shown in Table 8.____ ___ (. 1S2074 Or ® Equ... Twenty-nine pins are organized as three 8-bit ports and one S-bit port. HD68P01V07-------------------------------E Timer Counter _ _ _ _.. The configuration of the remaining 22 pins is not dependent on the operating mode. Port pins are labled as Pij where i identifies one of four ports and j indicates the particular bit. The basic difference between the HD6801 and the HD68POI is that the HD6801 has an on-chip ROM while the HD68POI has an on-package EPROM. SC. allowing easy software development using the onpackage EPROM. The Data Direction Register is used to define whether corresponding bits in the Data Register are configured as an input (clear) or output (set). refers to all of its associated hardware.. The facility which provides this extraordinary flexibility is its ability to be hardware programmed into eight different operating modes.-----r-.HD68P01S0. by itself. C (a) CMOS Load (b) TTL Load Figure 9 Bus Timing Test Loads • INTRODUCTION The HD68POI is an 8-bit monolithic microcomputer which can be configured to function in a wide variety of applications... location (internal or external) of interrupt vectors. ~175. The term "port". When the port is used as a "data port" or "I/O port"..... The operating mode controls the configuration of 18 of the MCU's 40 pins. E.I~... -P.~ . The HD68POI is pin and code compatible with the HD6801 and can be used to emulate the HD6801.'"<1 r------------J1 P2I Output Figure 7 Timer Output Timing Figure 8 Mode Programming Timing Vee Test Point O.. SC. memory map. -p".. -P". The programming model is depicted in Figure 10 where Accumulator D is a concatenation of Accumulators A and B.-p .v. -P..

V.nal RtW I l r\...':'..-C-C-A-' ' ..... The I-bit is L..... Index Register.... The Interrupt flowchart is depicted in Figure 13 and is common to every MCV interrupt excluding Reset... The Program Counter.. ' -_ _ _ _ _ ' _ _ _ mMO'IAa:-----~\"_~ ..ess Bus-"_....v-e-cl-o-.-tP-cs-----------_ _ XSS\\\\\\\\\\SSSSSS\\\\\\Ssy 6.I_..... \\\\\\\\\\\\\§\\\\\\'{ nn.-IPCS .J'-----... Interrupt and RES timing is illustrated in Figure 11 and 12. "0-'-o..J ' ' __ _' _ __ ______________________________________________________________ -II--'pcs Inle'n. 1..----.......lod Figure 12 Reset Timing 283 pc:::x:::::x:: .r---. ...r----..----------------------------------HD68P01S0. B Accumulator..ns I U .n.75V { }\\\\\\\\\\\\\\\\\ Interrupt Sequence LrLf4 . The vector is transferred to the Program Counter and instruction execution is resumed... 0 I #" I Internal Add. The I-bit controls all maskable interrupts..-rs-tl-nsJt.~_. A Non-Maskable Interrupt (NMI) is always recognized and acted upon at the completion of the current instruction.." InstruCl..' . . A Accumulator. External devices (and IS3) use IRQl.._ ....' .r-----..'S\\\S\\\\\\\\\\\S\\\\\\\\\SS\~ '--_ . J '---oI"-O-P-C-od-e' ~O-P-Cod-"...I'~--J"-_"'-_01'-_''-:~ Instruction ~NOIV.~~~~~~~~~~~~:...'" #12 I _ _.."F .. The MCV supports two types of interrupt requests: maskable and non-maskable..J'---...X-S---X'-5' '-A-C-C-A......-~f-~~~~~~~~~~_'_AC-------_----~s ~1e-4 RES __ Inl.~! %\\\\\\\\\\\\\\\\\\'{ ...l "-v-ec-to-...._ . and Condition Code Register are pushed to the stack..1 A!W * IRQ2.I '-A-C-C-B.e-Ie••-nl.... ' .."""_.... .. " _ _ .---""'\.I .. HD68P01V05.-. The Programmable Timer and Serial Communications Interface use an internal IRQ2 interrupt line.----"\.c 4.---...a MSS LSB Inlerrupl Routone Inle..X-O---X7-' . interrupts use hardware prioritized vectors. Of the maskable interrupts.. there are two types: IRQl and IRQ2 .. All MCV interrupt vector locations are shown in Table 1..... ~PC-O-_p-CoI7 "'p-CS---PC-"S ... Bus ~_ _ _. ~o.---"'---.__..-. as shown in BLOCK DIAGRAM.on ---I Table 1 MCU I nterrupt Vector Locations MSB LSB Interrupt FFFE FFFF RES FFFC FFFO NMI FFFA FFFB Software Interrupt (SWI) FFF8 FFF9 IRQ l (or IS3) FFF6 FFF7 ICF (Input Capture) OCF (Output Compare) FFF4 FFF5 FFF2 FFF3 TOF (Timer Overflow) FFFO FFF1 SCI (RORF + OR FE + TORE) Cvcle I #7 #1 #. J " _ _ _..." " ' i 1 .---..25V Vc. ' -_ _ _ _ _ ' _ _ _ ' . An IRQl interrupt is serviced before IRQ2 if both are pending...----.. The single SCI interrupt and three timer interrupts are serviced in a prioritized order where each is vectored to a separate location.. Maskable interrupts are controlled by the Condition Code Register's I-bit and by individual enable bits. HD68P01V07 • INTERRUPTS set to inhibit maskable interrupts and a vector is fetched corresponding to the current highest priority interrupt.r---~- oal. Internal Interrupt \~------------------------------~I Figure 11 E ~~\\~\\\\~ --5. All 'I'RQ.---__"\..

...... / Vector NMI SWI IRQ! ICF OCF TOF SCI Figure 13 Interrupt Flowchart PC FFOC:FFFO FFFA:FFFB FFF8:FFF9 FFF6:FFF7 FFF4:FFF5 FFF2:FFF3 FFFO:FFF1 Non-MaskablEl Interrupt Software Interrupt Maskable Interrupt Request 1 Input CapturE! Interrupt Output Compare Interrupt Timer Overfle.. ..........% C 0') co -u - 0 en 0 % C 0') CO -u 0 < 0 UI % C 0') CO -U 0 ../ .. ~n("l...w Interrupt SCI Interrupt (TORE + RORF + ORFEI ~ ...a < 0 I\:) (X) ~ ..

RAME is set (enabled) during Reset provided standby ~er is available on the positive edge of RES. This bit is a Read/Write status bit which is cleared whenever Vee Standby decreases below VSBB (min). must be cleared before the MPV can recognize maskable interrupts. XTAL and EXTAL These two input pins interface either a crystal or TTL com- 285 NMI (Non-Maskable Interrupt) An NMI negative edge request an MCV interrupt sequence. The power supply should provide +5 volts (±5%) to Vee. It is intended that RAME be cleared and STBY PWR be set as part of a powerdown procedure. When a "High" level is detected. In the powerup state. Vee Standby must remain above VSBB (min) to sustain the standby RAM and STBY PWR bit. the standby current will not exceed ISBB. Finally. 3 x 2 Ix This is an output clock used primarily for bus synchronization. During powerdown. IRQ1 has no internal pullup resistor.3 k!2 (nominal) resistor to Vee for wire-OR application. It can be set ~ by software and is not . Vee Standby T Figure 14 • Pow. If the interrupt mask bit (I-bit) in the Condition Code Register is clear. The MPV will complete the current instruction before it responds to the request.5 Not Used Bit 6 RAME Bit 7 STBY PWR • 4 Ix • RES This input is used to reset the MCU's internal state and provide an orderly startup procedure. If RAME is clear. The internal oscillator is designed to interface with an AT-cut quartz crystal resonator or a ceramic resonator operated in parallel resonance mode in the frequency range specified for fXT AL. A 22 pF capacitor is required from each crystal pin to ground to ensure reliable startup and operation. NMI must be held low for at least one E-cycle to be recognized under all conditions. The crystal should be mounted as close as possible to the input pins to minimize output distortion and startup stabilization time. and 0 are latched into programmed control bits PC2. and instruction execution is resumed. Battery Backup for Vee Standby RAM Control Register ($14) RAM Control Register 6 5 Bit 0. the MCV does the following: 1) All the higher order address lines will be forced "High". During powerup. Vee Standby should be tied to either ground or Vee in Mode 3. 7 patible clock to the MCU's internal clock generator. NMI typically requires a 3.8 volts: (1) at least tRe after Vee reaches 4. Finally. • E (Enable) The RAM Control Register includes two bits which can be used to control RAM accesses and determine the adequacy of the standby power source during powerdown operation. PCI and peo. will not exceed PD milliwatts.. HD68P01V05. and (2) until Vee Standby reaches 4. RES must be held low at least three E-cycles if asserted during powerup operation. I.75 volts in order to provide sufficient time for the clock generator to stabilize. 4) The interrupt mask bit is set. Standby Power.. 2. any access to a RAM address is external.0 volts. the power supply should provide +5 volts (±5%) and must reach VSB volts before RES reaches 4. While in powerdown operation. • o RAM Enable. . affected by RES. It is TTL compatible and is the slightly skewed divide-byfour result of the MCV input frequency. the RAM is included in the internal map. $FFFF) locations in memory will be used to load the program addressed by the program counter. The MCU is compatible with most commercially available crystals and ceramic resonators and nominal crystal parameters are shown in Figure 15. Alternatively. and all data given in cycles is referenced to this clock unless otherwise noted. It will drive one Schottky TTL load and 90 pF. Total power dissipation (including Vee Standby). EXTAL may be driven with an external TTL compatible clock of 4fo with a duty cycle of 50% (±1O%) with XTAL connected to ground. Voltage requirements depend on whether the MCU is in a powerup or powerdown state. a vector is fetched from $FFF8 and $FFF9. If RAME is set and not in Mode 3. • Vee Standby Vee Standby provides power to the standby portion ($80 through $BF) of the RAM and the STBY PWR and RAME bits of the RAM Control Register. the MCU will begin an interrupt sequence. transferred to the Program Counter and instruction execution resumes.75 volts. A diode must be used between them to prevent supplying power to Vee during powerdown operation. U".3 k!2 (nominal) resistor to Vee. but the current instruction will be completed before it responds to the request. The MCV will then begin an interrupt sequence. 3) The last two ($FFFE. It is typical to power both Vee and Vee Standby from the same source during normal operation.58 MHz Color Burst TV crystals.---------------------------------HD68P01S0. Divide-byfour circuitry is included which allows use of the inexpensive 3. transferred to the Program Counter. RES must be held below 0. and V ss should be tied to ground. IRQ1 typically requires an external 3. HD68P01V07 • FUNCTIONAL PIN DESCRIPTIONS • Vee and Vss Vee and VSS provide power to a large portion of the MCU. There is no internal NMI pullup resistor. a vector is fetched from $FFFC and $FFFD. This Read/Write bit can be used to remove the entire RAM from the internal memory map. (Maskable Interrupt Request 1) IRQ1 is a level-sensitive input which can be used to request an interrupt sequence. 2) I/O Port 2 bits. • IRQ.

75V -----------------' E RES . A latch controlled by Address Strobe captures address on the negative edge. and SC 2 depends on the operating mode. An MPU read is enabled when Read/Write and E are high. and both function as Port 3 controllines.. respectively. SCI is configured as an output in all modes except single chip mode.------.. HD68P01V05. SC1 and SC2 in Expanded Multiplexed Mode In the Expanded Multiplexed Modes. SCI and SC2 are configured as an input and output. SC. Three options associated with IS3 are controlled by Port 3's Controi and Status Register and are discussed in Port 3's description. The strobe is generated by a read (OSS= 0) or write (OSS = I) to Port 3's Data Register. ------------------~------------~ .. tAC (b) Oscillator Stabilization Time hRC' Figure 15 Oscillator Characteristics 286 . OS3 timing is shown in Figure S. In the Expanded Non-Multiplexed Mode. functions as Input/Output Select (lOS) and is asserted only when $0100 through $OIFF is sensed on the internal address bus. SC 2 is configured as Read/Write and is used to control the direction of data bus transfers.. AT Cut Parallel Resonance Crystal Co'" 7 pF max Rs '" 60 n max XTAL 2------------~IDI~-------------3 r---4I.---tRC---'~ Oscillator Stabilization Time. SC 2 is configured as Read/Write and is used to control the direction of data bus transfers..2 ± 20% -4 MHz) 2 3 EXT A L t-----tl-.rJ~'-----------------------------4. HD68P01V07-------------------------------• SC1 and SC2 (Strobe Control 1 and 2) SC1 and SC2 in Expanded Non-Multiplexed Mode The function of SC.. SC 2 is configured as OS3 and can be used to strobe output data or acknowledge input data.. It is controlled by Output Strobe Select (OSS) in Port 3's Control and Status Register. whereas SC 2 is always an output... as shown in Figure 20. Co Equivalent Circuit (a) Nominal Recommended Crystal Parameters Vcc / ~~~--------_~. both SCI and SC 2 are configured as outputs. An MPU read is enabled when Read/Write and E are high. functions as Address Strobe and can be used to demultiplex the eight least significant addresses and the data bus. If unused. SC...HD68P01S0. SCI and SC2 can drive one Schottky load and 90 pF. both SCI and SC 2 are configured as outputs. IS3 can remain unconnected. Cll '" C l 2 '" 22pF (3. SCI functions as IS3 and can be used to indicate that Port 3 input data is ready or output data has been accepted. SC1 and SC2 in Single Chip Mode In Single Chip Modes.

During RES. Bit 1. Bit 4 Bit 5 Bit 6 • P20-P24 (Port 2) Port 2 is a mode independent 5-bit I/O port where each line is configured by its Data Direction Register. is dedicated to the timer's Output Compare function and cannot be used to provide output from Port 2 Data Register. $0003 • P30-P37 (Port 3) Port 3 can be configured as an I/O port. Port 4 can drive one Schottky TTL load and 90 pF and is the only port with internal pullup resistors. Port 3 latch timing is shown in Figure 6. Unused lines can remain unconnected. When clear. If lines P23 and P24 are unused. This read-only status bit is set by an IS3 negative edge. Port 3 is held in a high impedance state between valid address and data to prevent potential bus conflicts. It is cleared by a read of the Port 3 Control and Status Register (with IS3 FLAG set) followed by a read or write to Port 3's Data Register or by RES. This bit determines whether OS3 will be generated by a read or write of Port 3's Data Register. This bit controls the input latch for Port 3.---------------------------------HD68P01S0. There are four ports: Port 1. Port 4 functions as an 8-bit I/O port where each line is configured by its Data Direction Register. Unused lines can remain unconnected. A "0" in the corresponding Data Direction Register bit will cause the I/O line to be an input. which can be used to control Port 3 data transfers. When set. P21. This bit is cleared by RES. 287 . the interrupt is inhibited. and P 22 provide the operating mode which is latched into the Program Control Register on the positive edge of RES. Port 2 Data Register I 7 6 PC21 PC1 543 2 1 0 P22 P21 P20 I I I I I I PCO P24 P23 Not used. (2) OS3 can be generated by either an MPU read or write to Port 3's Data Register. P21 and P22 must always be connected to provide the operating mode. Bit 7 Port 3 in Expanded Non-Multiplexed Mode Port 3 is configured as a bidirectional data bus (Do . The direction of data transfers is controlled by Read/Write (SC 2 ) and clocked by E (Enable). ass is cleared by RES. all lines are configured as inputs. when clear. • P40-P47 (Port 4) Port 4 is configured as an 8-bit I/O port. IS3 and OS3. an IRQl interrupt will be enabled whenever IS3 FLAG is set. they can remain unconnected. Darlington transistors. A "1" in the corresponding Data Direction Register bit will cause that I/O line to be an output. or CMOS devices using external pullup resistors. The latch is transparent after a read of Port 3's Data Register. Unused lines can remain unconnected. Port 2 also provides an interface for the Serial Communications Interface and Timer.A7) and data bus (Do'" 0 7 ) in Expanded Multiplexed Mode where Address Strobe (AS) can be used to demultiplex the two buses. LATCH ENABLE. IS3 IRQl ENABLE. if configured as an output. Each port has an associated write only Data Direction Register which allows each I/O line to be programmed to act as an input or an output. P20 . LATCH ENABLE is cleared by RES. Port 3 in Single-Chip Mode Port 3 is an 8-bit I/O port in Single-Chip Mode where each line is configured by its Data Direction Register. two lines. The mode may be read from Port 2 Data Register as shown where PC2 is latched from pin 10. If set. Their addresses and the addresses of their Data Direction registers are given in Table 2. HD68P01V07 • PORTS There are· four I/O ports on the MCU. input data is latched by an IS3 negative edge. The TTL compatible three-state output buffers can drive one Schottky TTL load and 30 pF. Three Port 3 options are controlled by the Port 3 Control and Status Register and available only in Single-Chip Mode: (1) Port 3 input data can be latched using IS3 as a control signal. There are two control lines associated with one of the 8-bit ports. ass (Output Strobe Select). Not used. Port 3 Control and Status Register Table 2 Port and Data Direction Register Addresses Ports I/O I/O I/O I/O Port 1 Port 2 Port 3 Port 4 Port Address Data Direction Register Address $0002 $0003 $0006 $0007 $0000 $0001 $0004 $0005 $OOOF Bit 0-2 Bit 3 • P10-P17 (Port 1) Port 1 is a mode independent 8-bit I/O port where each line is an input or output as defined by its Data Direction Register. the strobe is generated by a read. a bidirectional 8-bit data bus. The TTL compatible three-state output buffers can drive one Schottky TTL load and 90 pF. Port 3 in Expanded Multiplexed Mode Port 3 is configured as a time multiplexed address (Ao . three 8-bit ports and one 5-bit port. or a multiplexed address/data bus depending on the operating mode. it is generated by a write.0 7) in the Expanded Non-Multiplexed Mode. address outputs. when set. Port 2. It is configured as a data input port by RES. or data inputs depending on the operating mode. HD68P01V05. The TTL compatible three-state output buffers can drive one Schottky TTL load and 30 pF or CMOS devices using external pullup resistors. P20. and (3) an IRQl interrupt can be enabled by an IS3 negative edge. and Port 4. There are also Port 4 in Single Chip Mode In Single Chip Mode. Port 3. IS3 FLAG.

Internal pull- 288 Expanded.6) In the Expanded·Multiplexed Modes. Table 3 Summary of HD6800 Operating Modes Common to all Modes: Reserved Register Area Port 1 Port 2 Programmable Timer $erial Communication Interface Single Chip Mode 7 128 bytes of RAM. Expanded Multiplexed Modes 1.2. In Mode 6. Ao to A. as shown in Figure 16.& to AI5 .HD68P01S0. Port 4 functions as half of the address bus a!!!Erovides As to A lS • In Mode 6. I. • OPERATING MODES The MCU provides eight different operating modes which are selectable by hardware programming and referred to as Mode 0 through Mode 7.Multi~ed Mode Port 4 is configured from RES as an 8·bit input port where its Data Direction Register can be written to provide any or all of address lines. Internal pullup resistors are intended to pull Port 4's lines high until software configures the port. Port 4. The MCU functions as a monolithic microcomputer in these two modes without external address or data buses. or 6. Expanded Non-Multiplexed. execution will begin at $XXFE: XXFF. as shown in Figure 17. In ad· dition to other peripherals. Table 3 summarizes the characteristics of the operating modes.. • Fundamental Modes up resistors are intended to pull Port 4's lines high until it is configured. another MCU can be interfaced to Port 3 in a loosely coupled dual processor configuration. As to A is . no ROM (Mode 2) (3) Internal RAM and ROM (Mode 1) (4) Internal RAM. HD68P01V07------------------------------Internal pullup resistors allow the port to directly interface with CMOS at 5 volt levels. 2. the Reset vector is external for the first two E· cycles after the positive edge of RES and internal thereafter. Single chip modes include 4 and 7. In Mode 0. may be provided while retaining the remainder as input data lines. Any combination of the eight least-significant address lines may be obtained by writing to Port 4's Data Direction Register. 2. This allows Port 3 to function as a Data Bus when E is high. cannot be used. Figure 19 depicts a typical conflgUration for the Expanded· Multiplexed Modes. 1.3.Multiplexed Modes (0. the MCU has the ability to access a 65k bytes memory space.3. and the physical location of interrupt vectors. Stated alternatively. Internal pullup resistors are intend· ed to pull the lines high until its Data Direction Register is configured. In . SC 2 . 2048 bytes of ROM Port 3 is a parallel I/O port with two control lines Port 4 is a parallel I/O port SCI is Input Strobe 3 (~) S~ is Output Strobe 3 (0S3) Expanded Non·Multiplexed Mode 5 128 bytes of RAM. configuration of Port 3. A maximum of 29 I/O lines and two Port 3 control lines are provided. Port 3 functions as an 8-bit bidirectional data bus and Port 4 is configured as an input data port. This mode is used primarily to test Ports 3 and 4 in the Single-Chip and Non·Multiplexed Modes. Expanded Non-Multiplexed is Mode 5 and the remaining five are Expanded Multiplexed modes. however. Mode 5 can be irreversibly entered from Mode 4 without going through Reset by setting bit 5 of Port 2's Data Register. the port is configured from RES as an 8·bit parallel in· put port where its Data Direction Register can be written to provide any or all of address lines. Port 4 provides address line!. Port 3 functions as a time multiplexed address/data bus with address valid on the negative edge of Address Strobe (AS) and the data bus valid while E is high. The operating mode controls the memory map. lOS provides an address decode of external memory ($1oo-$IFF) and can be used similarly to an address or chip select line. The MCU interfaces directly with HMCS6800 family parts and can access 256 bytes of external address space at $100 through $1 FF. HD68P01V05. Figure 18 illustrates a typical system configuration in the Expanded Non-Multiplexed Mode. ROM with partial address bus (Mode 6) Port 3 is a multiplexed address/data bus Port 4 is an address bus (inputs/address in Mode 6) SCI is Address Strobe (AS) SC2 is ReadlWrite (RJW) Single Chip Modes (4. Internal pullup resistors are intended to pull the lines high until its Data Direc· tion Register is configured where bit 0 controls As . Port 4 is configured during RES as data port inputs and the Data Direction Register can be changed to provide any combination of address lines. Port 4 in Expanded Non.6 Four memory space options (65k address space): (1) No internal RAM or ROM (Mode 3) (2) Internal RAM. 7) Test Modes 0 and 4 Expanded Multiplexed Test Mode 0 May be used to test RAM and ROM Single Chip and Non·Multiplexed Test Mode 4 (1) May be changed to Mode 5 without going through Reset (2) May be used to test Ports 3 and 4 as I/O ports In Single-Chip Mode. 2048 bytes of ROM 256 bytes of external memory space Port 3 is an 8·bit data bus Port 4 is an input port/address bus SCI is Input/Output Select (lOS) SC2 is read/write (RJW) The MCU's eight modes can be grouped into three funda· mental modes which refer to the type of bus it supports: Single Chip. any combination of Ao to A. As to Ais • Stated alternatively. however. A test program must first be loaded into the RAM using modes 0. the RAM responds to $XX80 through $XXFF and the ROM is removed from the internal ad· dress map. Port 4 in Expanded Multiplexed Mode In all Expanded Multiplexed modes except Mode 6. In Single-Chip Test Mode (4). Expanded Non·Multiplexed Mode (5) A modest amount of external memory space is provided in the Expanded Non-Multiplexed Mode while retaining significant on·chip resources. any subset of As to Ais can be provided while retaining the remainder as input data lines. SCI. External pullup resistors to more than 5 volts. the MCU's four ports are configured as parallel input/output data ports. Address Strobe can be used to-control a transparent D-type latch to capture addresses Ao to A" as shown in Figure 20. If the MCU is Reset and then programmed into Mode 4. In Modes 0 to 3. and Expanded Multiplexed.

. -. 5) ---'-+---(A o . Mode 0 is used primarily to verify the ROM pattern Vee Vee Vee XTAL XTAL c::::J EXTAL Port 1 Port 3 81/0 Lines 8110 Lines NMI IRQ. "--IO'S' -_i-+-+--_ R/W ~-~~r+~--_. addition. UUI ' A.... 8 110 Lines Lines Port 4 Port 2 8110 Lines 5110 Lines Serial 1/0 16·Bit Timer Vss Port 2 Port 4 5110 Lines 81/0 SCI 16·Bit Timer Lines Vss Figure 16 NMI Vss Lines 16·Bit Timer Single Chip Mode Figure 17 Vee Single Chip Dual Processor Configuration Vee ._r~r+---. . HD68P01V07 and monitor the internal data bus with the automated test equipment.E Port 3 8 Data Lines Port 1 81/0 Lines Port 1 81/0 Port 2 Port 2 5110 5110 Lines Serial 110 16·Bit Timer SCI Timer Vss Vss Figure 18 Expanded Non-Multiplexed Configuration Vee Vee XTAL R/iN Port 3 Port 1 16 81/0 Lines Port 2 Port 4 8 Lines Address Bus 16·Bit Timer Port 2 5S~~ • • •~ Timer '----.---------------------------------HD68P01S0..----' Vss Vss Figure 19 Expanded Multiplexed Configuration 289 --_1-+---.~ 4I• •1t1 5110 Lines Serial 1/0 Add...IA o-A1) . Port 1 8 I/O Lines Port 1 81/0 Port 3. the internal and external data buses are connected and there must be no memory map overlap to avoid potential bus conflicts.100 -01) .JlIW ·E ~o~.. HD68P01V05.~~_r--_. IRQ..

If configured as outputs. PC1 . and PCO of the program control register on the positive edge of RES. 2. . otherwise.6) 5 H L H I I I NMUX(5. The operating mode may be read from Port 2 Data Register as shown below. O.Multiplexed 'UX . the circuit shown in Figure 21 may be used.0.Internal ~ .." .HD68P01S0. . 1. address output is optional by writing to Port 4 Data Direction Register 290 .. PC1. and 3 (5) Addresses associated with Port 3 are considered external in Modes 5 and 6 (6) Port 4 default is user data input. ~ Figure 20 Typical Latch Arrangement • Programming The Mode The operating mode is programmed by the levels asserted on P22 .." G 0 H H L X H L X X L 00 Z ) Do. PC2 . Enable -.. pco . P231 P221 P21 I 0 P20 I $0003 Table 4 Mode Selection Summary Mode PH (PC2) (PC1) P20 (PCO) ROM RAM Interrupt Vectors 7 H H H I I I I 6 H H L I I I MUXI5. HD68P01V05. three-state buffers can be used to provide isolation while programming the mode.6) 4 H L L 1(2) 111 ) I I 3 L H H H L 1 L L H I I E E E MUX(4) L E E E 2 0 L L L I I 1(3) P21 \egend: I . 4 3 2 1 P24 . P21 ../Dota .External \JX .. 01 1 74LS373 (Typical) _ T T I TI I I I Function Table Add. HD68P01V07-------------------------------GND AS I G OC 01 r Port 3 Add". and programming levels and timing must be met as shown in Figure 8. and P20 which are latched into PC2.A.Non·Multiplexed logic "0" ogic "1" I Bus Mode Operating Mode Single Chip Multiplexed/Partial Decode Non·Multiplexed/Partial Decode Single Chip Test Multiplexed /No RAM or ROM MUX(4) Multiplexed /RAM MUX(4) Multiplexed/RAM & ROM MUX(4) Multiplexed Test NotlS: (1) Internal RAM is addressed at $XX80 (2) Internal ROM is disabled (3) RES vector is external for 2 cycles after RES goes high (4) Addresses associated with Ports 3 and 4 are considered external in Modes 0. OR DR - ~ IIIIII L L H . Circuitry to provide the programming levels is dependent primarily on the normal system usage of the three pins. A brief outline of the operating modes is shown in Table 4. Port 2 Data Register 7 6 5 .

:>!+-+++_---l X Yoo-------------------4<~++_--. YIo---------------------~H-+_---l Y Zoo-------------------K>H---..> RI RI RI 6 I BI IC A HD68P01 Xo Yo x f .--------------------------------HD68P01S0.. HD68P01V07 Vee Q . HD68P01V05. Zlcr--------------~~~ Figure 22 Select Z 0 0 0 Zo Yo Xo 0 0 0 1 Zo Yo XI 0 0 1 0 Zo YI Xo 0 0 1 1 Zo YI Xl 0 1 0 0 ZI Yo Xo 0 1 0 1 ZI Yo XI 0 1 1 0 Zl YI Xo 0 1 1 1 ZI YI XI 1 X X X HD14053B Multiplexers/Demultiplexers 291 HD14053B 0 - . ~ R .Zo Y Xl Z RES 8 9 10 P20 (PCO) P21 (PC1) P22 (PC2) YI ZI ( C~ 1 ( ( ??? ~ Mode Control Switch Figure 21 Inh HD14053B [NOTES) Jr 1) Mode 7 as shown 2) RC ~ Reset time constant 3) RI = 10kfl Recommended Circuit for Mode Selection Truth Table Control Input On Switch Inh A B C Inhibit Binary to 1-of-2 Decoder with Inhibit C B A xocr-----------------4~~~~+-~ Xl o--------------------!c.

as shown in Table S. HD68P01V07--------------------------------• MEMORY MAPS Table 5 Internal Register Area The MCV can provide up to 6Sk byte address space depending on the operating mode..5. EPROM of the HD68P01S0 must be located at $F800-$FFFF. The HD68PO 1 provides 8k byte address space for EPROM. Register Address Port 1 Port 2 Port 1 Port 2 Data Data Data Data Direction Register* * * Direction Register*** Register Register 00 01 02 03 Port 3 Port 4 Port 3 Port 4 Data Data Data Data Direction Register*** 0 irection R egister* * * Register Register 04* 05** 06* 07** Counter (High Byte) Counter (Low Byte) Output Compare Register (High Byte) 08 09 OA OB Output Compare Register (Low Byte) Input Capture Register (High Byte) Input Capture Register (Low Byte) Port 3 control and Status Register OC 00 OE OF* Rate and Mode Control Register Transmit/Receive Control and Status Register Receive Data Register Transmit Data Register 10 11 12 13 Tim@r C-OntrQI and Statu! Register RAM Control Register Reserved 14 15-1F * External address in Modes 0.6. 1) HN462716 (a 2k byte ROM) In order to support the HD6801S0. Output. 1. 1. A memory map for each operating mode is shown in Figure 23. but the maps differ in EPROM types as follows. In this case. 0 = Input 292 .3 *** 1 . HD68P01V05. with exceptions as indicated. The first 32 locations of each map are reserved for the MCU's internal register area. cannot be accessed in Mode 5 (No lOS) ** External addresses in Modes 0. 3) HN482764 (a 8k byte ROM) The HD68PO 1 can provide up to 8k byte address space using HN482764 instead of HN462732.2. is located at $EOOO-$FFFF.HD68P01S0. 2) HN462532.3.2. EPROM of the HD68POI . HN462732 (a 4k byte ROM) In order to support the HD6801VO EPROM of the HD68PO 1VOS and the HD68PO 1V07 must be located at $FOOO-$FFFF.

2) EPROM addresses $FFFO to $FFFF are not usable. Figure 23 External Interrupt Vectors $FFFF " . HD68P01V07 HD68POl Mode o HD68POl Mode 1 Multiplexed/RAM & EPROM Multiplexed Test mode $0000(1) $0000(1) Internal Registers I nternal Registers $001F $001F External Memory Space External Memory Space $0080 $0080 Internal RAM Internal RAM $OOFF $OOFF External Memory Space External Memory Space $EOOO $EOOO EPROM $FFEF EPROM $FFFO $FFFF(2) Internal Interrupt Vectors(2 (NOTES) 1) Excludes the following addresses which may be used externally: $04. $07 and $OF.----------------------------------HD68P01S0. $06.-. there must be no overlapping of internal and external memory spaces to avoid driving the data bus with more than one device. $06. $05. $05. HD68POl Memory Maps 293 . [NOTES] 1) Excludes the following addresses which may be used externally: $04. 3) After 2 MPU cycles.. HD68P01V05.. 4) This mode is the only mode which may be used to examine the interrupt vectors in EPROM using an external Reset vector.. $07 and $OF. 2) Addresses $FFFE and $FFFF are considered external if accessed within 2 cycles alter a positive edge of RES and internal at all other times..

Figure 23 External Interrupt Vectors [NOTE] 1) Excludes the following addresses which may be used externally: $04.. $07. } [NOTE] 1) Excludes the following addresses which may be used externally: $04... $FFFF 1. HD68POl Memory Maps (Continued) 294 . $FFFO . $05.-_ _ _. $06. $05. HD68P01V05.HD68P01S0... $07 and $OF. $06. and $OF.. HD68P01V07-------------------------------- HD68POl Mode 2 HD68POl Mode Multiplexed/RAM 3 Multiplexed/No RAM or EPROM $0000(1) $0000(1) } Internal Registers Internal Registers $001F $001F External Memory Space $0080 Internal RAM $OOFF External Memory Space External Memory Space ----I.1 } External Interrupt Vectors $FFFO 1----11· $FFFF _ _ _ _.

.. HD68P01V07 HD68POl Mode 4 HD68POl Mode Single Chip Test 5 Non-Multiplexed/Partial Decode $0000 } Internal Registers $OOlF $0080 } I nternal RAM $OOFF $0100 $01 FF ' .. Figure 23 $FFFF HD68POl Memory Maps (Continued) 295 ....... [NOTES] 1) The internal ROM is disabled.H D 6 8 P 0 1 S Q ........ HD68P01V05._. and $OF. 4) Internal RAM will appear at $XX80 to $XXFF... 2) Mode 4 may be changed to Mode 5 without having to assert RESET by writing a "1" into the PCO bit of Port 2 Data Register. 3) Addresses As to AI s are treated as "don't cares" to decode internal RAM. (No lOS) 2) This mode may be entered without going through RESET by using Mode 4 and subsequently writing a "1" into the PCO bit of Port 2 Data Register. These address lines will assert "l's" until made outputs by writing the Data Direction Register..... 3) Address lines Ao -A..... } External Memory Space $EOOO EPROM $XX80 $XXFF Internal RAM Internal Interrupt Vectors Internal Interrupt Vectors [NOTES] 1) Excludes the following addresses which may not be used externally·: $04. $06._ . will not contain addresses until the Data Direction Register for Port 4 has been written with "l's" in the appropriate bits.

These address lines will assert ""s" until made outputs by writing the Data Direction Register.HD68P01S0. HD68P01V07--------------------------------- HD68P01 Mode 6 HD68P01 Mode 7 Single Chip Multiplexed/Partial Decode $0000(1) Internal Registers $OO'F Internal Registers External Memory Space $0080 $0080 Internal RAM $OOFF $OOFF External Memory Space $EOOO $FFFF $EOOO EPROM EPROM Internal Interrupt Vectors Internal Interrupt Vectors $FFFF [NOTES) . HD68P01V05.) Excludes the following address which may be used externally: $04. Figure 23 HD68P01 Memory Maps (Continued) 296 . $OF. $06. 2) Address lines As -A IS will not contain addresses until the Data Direction Register for Port 4 has been written with ""s" in the appropriate bits.

----------------------------------HD68P01S0, HD68P01V05, HD68P01V07
• PROGRAMMABLE TIME
The Programmable Timer can be used to perform input waveform measurements while independently generating an output
waveform. Pulse widths can vary from several microseconds to
many seconds. A block diagram of the Timer is shown in Figure

The Output Compare Register is set to $FFFF by RES.

Input Capture Register ($00: OE)
The Input Capture Register is a 16-bit read-only register used
to store the free-running counter when a "proper" input transition occurs as defined by IEDG. Port 2, bit 0 should be configured as an input, but the edge detect circuit always senses P 20
even when configured as an output. An input capture can occur
independently of ICF: the register always contains the most current value. Counter transfer is inhibited, however, between accesses of a double byte MPU read. The input pulse width must
be at least two E-cycles to ensure an input capture under all
conditions.

24.
• Counter ($09:0A)
The key timer element is a 16-bit free-running counter which
is incremented by E (Enable). It is cleared during RES and is
read-only with one exception: a write to the counter ($09) will
preset it to $FFF8. This feature, intended for testing, can disturb serial operations because the counter provides the SCI's
internal bit rate clock. TOF is set whenever the counter contains
alII's.

Timer Control and Status Register ($08)
The Timer Control and Status Register (TCSR) is an 8-bit
register of which all bits are readable while bits (}-4 can be
written. The three most significant bits provide the timer's
status and indicate if:
• a proper level transition has been dtected,
• a match has been found between the free-running counter
and the output compare register, and
• the free-running counter has overflowed.
Each of the three events can generate an IRQ2 interrupt and
is controlled by an individual enable bit in the TCSR.

• Output Compare Register ($OB:OC)
The Output Compare Register is a 16-bit Read/Write register
used to control an output waveform or provide an arbitrary
timeout flag. It is compared with the free-running counter on
each E-cycle. When a match is found, OCF is set and OLVL is
clocked to an output level register. If Port 2, bit I, is configured
as an output, OLVL will appear at P 21 and the Output Compare
Register and OLVL can then be changed for the next compare.
The function is inhibited for one cycle after a write to its high
byte of the Compare Resister ($OB) to ensure a valid compare.

HD68P01 Internal Bus

Timer b~7~~~~~~__T-~~~~
Control
And .,...........-&..,-........,........,........,...1..........-Status
Register
$08

I

Bit 1
Port 2
DDR

.---I

_____ : Output Input
Level Edge
Bit 1 Bit 0
Port 2 Port 2

Figure 24

Block Diagram of Programmable Timer

297

HD68P01S0, HD68P01V05, HD68P01V07--------------------------------Timer Control and Status Register (TCSR)

7

654

Bit 0 OLVL

Bit 1 IEDG

Bit 2 ETOI

Bit 3 EOCI

Bit 4 EICI

Bit 5 TOF

Bit 6 OFC

Bit 7 ICF

3

2

1

• clock: external or internal bit rate clock
• Baud (or bit rate): one of 4 per E-clock frequency, or external bit rate (X8) input
• wake-up feature: enabled or disabled
• interrupt requests: enabled individually for transmitter
and receiver
• clock output: internal bit rate clock enabled or disabled

0

Output level. OLVL is clocked to the output
level register by a successful output compare and
will appear at P21 if Bit 1 of Port 2's Data Direction Register is set. It is cleared by RES.
Input Edge. IEDG is cleared by RES and controls
which level transition will trigger a counter transfer to the Input Capture Register:
IEDG =0 Transfer on a negative-edge
IEDG = 1 Transfer on a positive-edge.
Enable Timer Overflow Interrupt. When set, an
IRQ2 interrupt is enabled for a timer overflow;
when clear, the interrupt is inhibited. It is cleared
by RES.
Enable Output Compare Interrupt. When set, an
IRQ2 interrupt is enabled for an output compare; when clear, the interrupt is inhibited. It is
cleared by RES.
Enable Input Capture Interrupt. When set, an
IRQ2 interrupt is enabled for an input capture;
when clea~the interrupt is inhibited. It is
cleared by RES.
Timer Overflow Flag. TOF is set when the
counter contains all l's. It is cleared by reading
the TCSR (with TOF set) followed by the
counter's high byte ($09), or by RES.
Output Compare Flag. OCF is set when the Output Compare Register matches the free-running
counter. It is cleared by reading the TCSR (with
OCF set) and then writing to the Output Compare Register ($OB or $OC), or by RES.
Input Capture Flag. ICF is set to indicate a
proper level transition; it is cleared by reading
the TCSR (with ICF set) and then the Input
Capture Register High Byte ($00), or by RES.

• SERIAL COMMUNICATIONS INTERFACE (SCI)

A full-duplex asynchronous Serial Communications Interface
(SCI) is provided with a data format and a variety of rates. The
SCI transmitter and receiver are functionally independent, but
use the same data format and bit rate. Serial data format is
standard mark/space (NRZ) and provides one start bit, eight
data bits, and one stop bit. "Baud" and "bit rate" are used
synonymously in the following description.

tOP 22

• Port 2 (bit 3, 4): dedicated or not dedicated to serial I/O
individually for transmitter and receiver.

Serial Communications Registers

The Serial Communications Interface includes four addressable registers as depicted in Figure 25. It is controlled by the
Rate and Mode Control Register and the Transmit/Receive Control and Status Register. Data is transmitted and received utilizing a write-only Transmit Register and a read-only Receive
Register. The shift registers are not accessible to software.
Bit 7

I X

Rate and Mode Control Register

Bit 0

1 X 1 X 1 X 1 CCl 1 cco 1 551 1 sso 1$10
Transmit/Receive Control and Status Register

Receive Data Register

$12

Port 2

(Not Addressable)
Receive Shift Register

....- - - E

Tx
Bit
4

12
$13

Transmit Data Register

Figure 25

SCI Registers

• Wake-Up Feature

In a typical serial loop multi-processor configuration, the
software protocol will usually identify the addressee(s) at the
beginning of the message. In order to permit uninterested MPU's
to ignore the remainder of the message, a wake-up feature is
included whereby all further SCI receiver flag (and interrupt)
processing can be inhibited until its data line goes idle. An SCI
receiver is re-enabled by an idle string of ten consecutive l's or
by RES. Software must provide for the required idle string
between consecutive messages and prevent it within messages.

Rate and Mode Control Register (RMCR) ($10)

The Rate and Mode Control Register controls the SCI bit
rate, format, clock source, and under certain conditions, the
configuration of P22 . The ~ster consists of four write-only
bits which are cleared by RES. The two least significant bits
control the bit rate of the internal clock and the remaining two
bits control the format and clock source.
Rate and Mode Control Register (RMCR)

Programmable Options

7

6543210

The following features of the SCI are programmable:
• format: Standard mark/space (NRZ)

x

x

298

I I I I I I I
X

X

CC1

cco SS1

sso

$0010

---------------------------------HD68P01S0, HD68P01V05, HD68P01V07
Bit 1: Bit 0

SSl: SSO Speed Select. These two bits select the
Baud when using the internal clock. Four rates
may be selected which are a function of the MCU
input frequency. Table 6 lists bit time and rates
for three selected MCU frequencies.
Nit 3: Bit 2 CCI :CCO Clock Control Select. These two bits
select the serial clock source. If CCl is set, the
DDR value for Pn is forced to the complement
of CCO and cannot be altered until CC 1 is
cleared. If CCI is cleared after having been set,
its DDR value is unchanged. Table 7 defines the
clock source, and use of P22 .
If both CCI and CCO are set, an external TTL compatible
clock must be connected to P22 at eight times (8X) the desired
bit rate, but not greater than E, with a duty cycle of 50% (±
10%). IfCC1:CCO = 10, the internal bit rate clock is provided at
P22 regardless of the values for TE or RE.

Bit 2 TIE

Bit 3 RE

Bit 4 RIE

Bit 5 TORE

(Note) The source of SCI internal bit rate clock is the timer's free running counter. An MPU write to the counter can disturb serial
operations.

Transmit/Receive Control and Status Register (TRCSR) ($11)
The Transmit/Receive Control and Status Register controls
the transmitter, receiver, wake-up feature, and two individual
interrupts and monitors the status of serial operations. All eight
bits are readable while bits 0 to 4 are also writable. The register
is initialized to $20 by RES.

Bit 6 ORFE

Transmit/Receive Control and Status Register (TRCSR)
7

Bit 0 WU

Bit I TE

6

543

2

1

0

"Wake-up" on Idle Line. When set, WU enables
the wake-up function; it is cleared by ten consecutive 1's or by RES. WU will not set if the line
is idle.
Transmit Enable. When set, P24 DDR bit is set,
cannot be changed, and will remain set if TE is
subsequently cleared. When TE is changed from
clear to set, the transmitter is connected to P 24

Bit 7 RDRF

and a preamble of nine consecutive l's is transmitted. TE is cleared by RES.
Transmit Interrupt Enable. When set, an IRQ2
interrupt is enabled when TDRE is set; when
clear, the interrupt is inhibited. TE is cleared by
RES.
Receive Enable. When set, P23's DDR bit is
cleared, cannot be changed, and will remain clear
if RE is subsequently cleared. While RE is set,
the SCI receiver is enabled. RE is cleared by
RES.
Receiver Interrupt Enable. When set, an IRQ2
interrupt is enabled when RDRF and/or ORFE is
set; when clear, the interrupt is inhibited. RIE is
cleared by RES.
Transmit Data Register Empty. TDRE is set
when the Transmit Data Register is transferred to
the output serial shift register or by RES. It is
cleared by reading the TRCSR (with TDRE set)
and then writing to the Transmit Data Register.
Additional data will be transmitted only if TDRE
has been cleared.
Overrun Framing Error. If set, ORFE indicates
either an overrun or framing error. An overrun is
a new byte ready to transfer to the Receiver Data
Register with RDRF still set. A receiver framing
error has occurred when the byte boundaries of
the bit stream are not synchronized to the bit
counter. An overrun can be distinguished from a
framing error by the value of RDRF: if RORF is
set, then an overrun has occurred; otherwise a
framing error has been detected. Data is not
transferred to the Receive Data Register in an
overrun or framing error. condition. ORFE is
cleared by reading the TRCSR (with ORFE set)
then the Receive Data Register, or by RES.
Receive Data Register Full. RDRF is set when
the input serial shift register is transferred to the
Receive Data Register. It is cleared by reading
the TRCSR (with RDRF Ret), and then the Receive Data Register, or by ES.

Table 6 SCI Bit Times and Rates
SS1
0
0
1
1

: SSO
0
1
0
1

2.4576 MHz
614.4 kHz
26 ~s/38,400 Baud
20~s/4,800 Baud
1.67ms/600 Baud
-..- 6.67ms/150 Baud

4fo
E
E + 16
E + 128
E + 1024
E + 4096

4.0 MHz
1.0 MHz
16

~s/62,500

Baud
Baud
1.024ms/976.6 Baud
4.096ms/244.1 Baud
128~s/7812.5

Table 7 SCI Format and Clock Source Control
CC1, CCO
00
01
10
11

Format

Clock Source

Port 2 Bit 2

-

-

-

NRZ
NRZ
NRZ

Internal
Internal
External

Not Used
Output*
Input

* Clock output is available regardless of values for bits RE and TE.

* * Bit 3 is used for serial input if R E = "1" in TRCS; bit 4 is used for serial output if TE = "1" in TRCS.

299

Port 2 Bit 3
**
**
**
**

Port 2 Bit 4
**
**
**
**

HD68P01S0, HD68P01V05, HD68P01V07-------------------------------•

Internally Generated Clcok

If the user wishes for the serial I/O to furnish a clock, the following requirements are applicable:
• the values of RE and TE are immaterial.
• CCl, ceo must be set to 10
• the maximum clock rate will be E + 16.
• the clock will be at 1X the bit rate and will have a rising
edge at mid-bit.

Externally Generated Clock

If the user wishes to provide an external clock for the serial
I/O, the following requirements are applicable:
• the CCl, CCO, field in the Rate and Mode Control Register must be set to 11,
• the external clock must be set to 8 times (X8) the desired
baud rate and
• the maximum external clock frequency is 1.0 MHz.

Then the 8 data bits (beginning with bit 0) followed by the stop
bit (1), are transmitted. When the Transmitter Data Register has
been emptied, the TORE flag bit is set.
If the MCU fails to respond to the flag within the proper time, (TORE is still set when the next normal transfer from
the parallel data register to the serial output register should
occur) then a 1 will be sent (instead of a 0) at "Start" bit time,
followed by more 1's until more data is supplied to the data
register. No O's will be sent while TORE remains a 1.

Serial Operations

The SCI is initialized by writing control bytes first to the
Rate and Mode Control Register and then to the Transmit/Receive Control and Status Register.
The Transmitter Enable (TE) and Receiver Enable (RE) bits
may be left set for dedicated operations.
Transmit operations

The transmit operation is enabled by TE in the Transmit/Receive Control and Status Register. When TE is set, the output of
the transmit serial shift register is connected to P 24 and the
serial output by first transmitting to a ten-bit preamble of 1'so
Following the preamble, internal synchronization is established
and the transmitter section is ready for operation.
At this point one of two situation exist:
1) if the Transmit Data Register is empty (TORE = 1), a continuous string of ones will be sent indicating an idle line,
or,
2) if a byte has been written to the Transmit Data Register
(TORE = 0), it is transferred to the output serial shift register and transmission will begin.
During the transfer itself, the start bit (0) is first transmitted.

Receive Operations

The receive operation is enabled by RE _which configures
P23 • The receive operation is controled by the contents of the
Transmit/Receive Control and Status Register and the Rate and
Mode Control Register.
The receiver bit interval is divided into 8 sub-intervals for
internal synchronization. In the NRZ Mode, the received bit
stream is synchronized by the first 0 (space) encountered.
The approximate center of each bit time is strobed during
the next 10 bits. If the tenth bit is not a 1 (stop bit) a framing
error is assumed, and ORFE is set. If the tenth bit is ai, the
data is transferred to the Receive Data Register, and interrupt
flag RDRF is set. If RDRF is still set at the next tenth bit time,
ORFE will be set, indicating an over-run has occurred. When the
MCU responds to either flag (RDRF or ORFE) by reading
the status register followed by reading the Data Register, RDRF
(or ORFE) will be cieared.

INSTRUCTION SET

The HD68PO 1 is upward source and object code compatible
with the HD6800. Execution times of key instructions have
been reduced and several new instructions have been added,
including hardware multiply. A list of new operations added
to the HD6800 instruction set is shown in Table 8.
In addition, two new special opcodes, 4E and SE, are provided for test purposes. These opcodes force the Program Counter
to increment like a 16-bit counter, causing address lines used
in the expanded modes to increment until the device is reset.
These opcodes have no mnemonics.

Table 8 New Instructions
I nstructi on

Description

ABX
ADDD
ASLD
BRN
LDD
LSRD
MUL
PSHX
PULX
STD
SUBD

Unsigned addition of Accumulator B to Index Register
Adds (without carry) the double accumulator to memory and leaves the sum in the double accumulator
Shifts the double accumulator left howards MSB) one bit; the LSB is cleared and the MSB is shifted into the C-bit
Branch Never
Loads double accumulator from memory
Shifts the double accumulator right howards LSB) one bit; the MSB is cleared and the LSB is shifted into the C-bit
Unsigned multiply; multiplies the two accumulators and leaves the product in the double accumulator
Pushes the Index Register to stack
Pulls the Index Register from stack
Stores the double accumulator to memory
Subtracts memory from the double accumulator and leaves the difference in the double accumulator

300

---------------------------------HD68P01S0, HD68P01V05, HD68P01V07
• Addressing Modes
The MCU provides six addressing modes which can be used
to reference memory. A summary of addressing modes for all
instructions is presented in Table 9,10,11, and 12 where execution times are provided in E-cyc1es. Instruction execution times
are summarized in Table 13. With an input frequency of 4 MHz,
E-cycles are equivalent to microseconds. A cycle-by-cycle
description of bus activity for each instruction is provided in
Table 14 and a description of selected instructions is shown in
Figure 26.

• Programming Model
A programming model for the HD68POI is shown in Figure
10. Accumulator A can be concatenated with accumulator B
and jointly referred to as accumulator D where A is the most
significant byte. Any operation which modifies the double
accumulator will also modify accumulator A and/or B. Other
registers are defmed as follows:
Program Counter
The program counter is a 16-bit register which always points
to the next instruction.

Immediate Addressing
The operand or "immediate byte(s)" is contained in the following byte(s) of the instruction where the number of bytes
matches the size of the register. These are two or three byte
instructions.

Stack Pointer
The stack pointer is a 16-bit register which contains the address of the next available location in a pushdown/pullup
(LIFO) queue. The stack resides in random access memory at a
location defmed by the programmer.

Direct Addressing
The least significant byte of the operand address is contained
in the second byte of the instruction and the most significant
byte is assumed to be $00. Direct addressing allows the user to
access $00 through $FF using two byte instructions and execution time is reduced by eliminating the additional memory access. In most applications, the 256-byte area is reserved for
frequently referenced data.

Index Register
The Index Register is a 16-bit register which can be used to
store data or provide an address for the indexed mode of
addressing.
Accumulators
The MCU contains two 8-bit accumulators, A and B, which
are used to store operands and results from the arithmetic logic
unit (ALU). They can also be concatenated and referred to as
the D (double) accumulator.

Extended Addressing
The second and third bytes of the instruction contain the absolute address of the operand. These are three byte instructions.

Condition Code Registers
The condition code register indicates the results of an instruction and includes the following five condition bits: Negative (N), Zero (Z), Overflow (V), Carry/Borrow from MSB (C),
and Half Carry from bit 3 (H). These bits are testable by the
conditional branch instruction. Bit 4 is the interrupt mask
(I-bit) and inhibits all maskable interrupts when set. The two
unused bits, b6 and b7 are read as ones.

Table 9

Pointer Operations

Mnemonic

Index Register and Stack Manipulation Instructions

Immed
OP

-

Direct

Extend

Index

-

#

OP

-

#

OP

3

9C

5

2

AC 6

#

OP

-

Implied

#

OP

-

Boolean/
Arithmetic Operation

#

2 BC 6 3

Compare Index Reg

CPX

Decrement Index Reg

DEX

09

3

1

Decrement Stack Pntr

DES

34

3

1 SP - 1 - SP

Increment Index Reg

INX

08

3

1

X + 1 .... X

Increment Stack Pntr

INS

31

3

1

SP + 1 ..... SP

Load Index Reg

LOX

CE

3

3

Load Stack Pntr

LOS

8E

3

3

Store I ndex Reg

STX

Store Stack Pntr

STS

8C

4

Indexed Addressing
The unsigned offset contained in the second byte of the instruction is added with carry to the Index Register and used to
reference memory without changing the Index Register. These
are two byte instructions.

DE 4

2 EE 5
2 AE 5
OF 4 2 EF 5
9F 4 2 AF 5

9E

4

2
2
2
2

X - M: M+ 1
X-1 ..... X

FE

5

3

M .... XH, (M+1) .... XL

BE

5

3

M ..... SP H • (M+1) .... SP L

Index Reg ..... Stack Pntr

TXS

35

3

1

X H .... M. XL .... (M + 1)
SP H .... M, SP L -+ (M + 1)
X -1 ..... SP

Stack Pntr -+ Index Reg

TSX

30

3

1

SP + 1- X

Add

ABX

3A

3

1

B + X ..... X

Push Data

PSHX

3C

4

1

XL ..... MSp, SP -1 ..... SP

Pull Data

PULX

38

5

1

SP + 1 - SP, Msp .... X H

FF

5

3

BF

5

3

Condo Code Reg.
5

4

H

I N Z V






3

2 1 0

• t t
• • t
• • •
• • t
• • •


• •
• •

t
t
t
t

t
t
t
t

C

t t

• •
• •

• •
• •
R
R
R



R •
• •
• • • • • •

• • • • • •

• • • • • •
• • • • • •

XH .... MSp,SP -1 ..... SP
SP + 1 ..... SP, Msp ..... XL
The Condition Code Register notes are listed after Table 12.

301

• • • • • •

HD68P01S0, HD68P01V05, HD68P01V07-------------------------------Implied Addressing
The operand(s) are registers and no memory reference is
required. These are single byte instructions.
Relative Addressing
Relative addressing is used only for branch instructions. If

the branch condition is true, the Program Counter is overwritten
with the sum of a signed single byte displacement in the second
byte of the instruction and the current Program Counter. This
provides a branch range of -126 to 129 bytes from the ftrst
byte of the instruction. These are two byte instructions.

Table 10 Accumulator and Memory Instructions
Accumulator and
Memory Operations

Mnemonic

Immed
OP -

Direct

# OP -

Add Acmltrs

ABA

AddBtoX
Add with Carry

ABX
ADCA

Add

ADCB
ADDA

Add Double

ADDB
ADDD

CB 2 2
C3 4 3

And

ANDA

84

2 2

DB 3
03 5
94 3

ANDB

C4

2 2

04 3

Shift Left, Arithmetic

89

2 2

99

C9

2 2

8B

2 2

09 3
9B 3

3

ASL
ASLA

Shift Left Obi

ASLB
ASLD

Shift Right, Arithmetic

ASR
ASRA
ASRB

Bit Test

BITA

85

2 2

95

BITB

C5

2 2

05 3

Compare Acmltrs

CBA

Clear

CLR

3

CLRA
CLRB
Compare
1's Complement

CMPA

81

2 2

91

3

CMPB

C1

2 2

01

3

COM
COMA

Decimal Adj, A

COMB
DAA

Decrement

DEC
DECA
DECB

Exclusive OR
Increment

EORA

88

2 2

98

EORB

C8

2 2

08 3

3

INC
INCA
INCB

Load Acmltrs

LDAA
LDAB

C6 2

Load Double

LDD

CC 3

Logical Shift, Left

LSL
LSLA
LSLB
LSLD

Shift Right, Logical

LSR
LSRA
LSRB
LSRD

86

2 2

2
3

96

3

06 3
DC 4

Index
Extend
Implied
Boolean Expression
# OP - # OP - # OP - #
1B 2 1 A+B~A
3A 3 1 B+X ..... X
2 A9 4 2 B9 4 3
A+M+C ..... A
2 E9 4 2 F9 4 3
B+M+C ..... B
2 AB 4 2 BB 4 3
A+M ..... A
2 EB 4 2 FB 4 3
B+M ..... A
2 E3 6 2 F3 6 3
0+ M:M + 1 ..... 0
A·M ..... A
2 A4 4 2 B4 4 3
2 E4 4 2 F4 4 3
B·M ..... B
68 6 2 78 6 3
48 2 1
58 2 1
05 3 1
67 6 2 77 6 3
47 2 1
57 2 1
2 A5 4 2 B5 4 3
A'M
2 E5 4 2 F5 4 3
B'M
11 2 1 A-B
6F 6 2 7F 6 3
OO-+M
4F 2 1 OO-+A
5F 2 1 OO-+B
2 A1 4 2 B1 4 3
A-M
2 E1 4 2 F1 4 3
B -M
Jl ..... M
63 6 2 73 6 3
43 2 1 A"'" A
53 2 1 -e- ..... B
19 2 1 Adj binary sum to BCD
M -l ..... M
6A 6 2 7A 6 3
4A 2 1 A-1 ~A
5A 2 1 B -l ..... B
2 A8 4 2 B8 4 3
A(±)M ..... A
2 E8 4 2 F8 4 3
B(±)M ..... B
M+ l ..... M
6C 6 2 7C 6 3
4C 2 1 A+l ..... A
5C 2 1 B+ l ..... B
M ..... A
2 A6 4 2 B6 4 3
M ..... B
2 E6 4 2 F6 4 3
2 EC 5 2 FC 5 3
M:M + 1-+0
68 6 2 78 6 3
48 2 1
58 2 1
05 3 1
64 6 2 74 6 3
44 2 1
54 2 1
04 3 1

302

Condo Code Reg.
H I N Z V C

t • t t t t

• • • • • •

..
.

t~ •
~

~









••
••
• •
• •
••
• •
••
••
• •
• •



~ ~ t
~ ~ ~
t t ~
~ ~ ~
t t ~
~ ~ R
~ ~ R
~ ~ ~
~ ~ ~
~ ~ ~
~ ~ ~
~ ~ ~
~ ~ ~
~ ~ ~
~ ~ R
~ ~ R
...
~ ... ~

~

t
~
~

t

~
~
~
~
~
~
~

~

R S R R
S R R
R
R S R R

• ~
• t
• ~
• ~
• ~
• ~
• ~~
• ~
• ~

~ ~ ~
~ ~
~ R S
~ R S
~ R S

t

· ...
..
••






• •
••
• •
• •
• •

• •

••
• •
• •
••
• •
• •
• •
• •

~ ~ ~
~ ~
~ ~
~ ~
~ R •
~ ~ R •
~ ~ ~
~
~
~
~
~
~
~
~
~

~ ~

t

~

.

~ R •
~ R •
~

~
~
~
~
~
R
~
R
~
R
~

R •

~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
R
(Continued)

---------------------------------HD68P01S0, HD68P01V05, HD68P01V07
Table 10 Accumulator and Memory Instructions (Continued)
Accumulator and
Memory Operations

Mnemonic

Multiply

MUL

2'5 Complement
(Negate)

NEG

Direct

Immed
OP

-

# OP

-

Extend

Index

# OP
60

-

# OP

-

Implied

# OP

-

#

3D 10 1

6 2

70

6

AXB-+D
OO-M-+M

3

NEGA

Boolean Expression

40

2

1

OO-A-+A

NEGB

50

2

1

OO-B-+B

No Operation

NOP

01

2

1

PC + 1 -+PC

Inclusive OR

ORAA

8A 2

2

9A 3

2

AA 4

2

BA 4

3

A+M-+A

ORAB

CA 2

2

DA 3

2

EA 4

2

FA 4

3

B +M-+B

Push Data
Pull Data
Rotate Left

PSHA

36

3

1

A -+Stack

PSHB

37

3

1

B -+Stack

PULA

32

4

1

Stack -+A

PULB

33

4

1

Stack -+B

49

2

1

59

2

1

ROL

69

6 2

79

6

3

ROLA
ROLB
Rotate Right

ROR

66

76

6

3

RORA

46

2

1

56

2

1

10

2

1

SBA

Subtract with Carry

SBCA

82

2

2

SBCB

C2

2

2

3

2

02 3

92

A2 4

2

A-B-+A

B2

4

3

A-M-C-+A
B-M-C-+B

2

E2

4

2

F2

4

3

STAA

97

3

2

A7 4

2

B7

4

3

A-+M

STAB

07 3

2

E7

4

2

F7

4

3

B-+M

FD 5

3

STD
Subtract

2

RORB
Subtract Acmltr

Store Acmltrs

6

2

ED 5

2

3

2

AO 4

2 BO 4 3

A-M-+A

D-+M:M + 1

2

DO 3

2

EO

4

2

FO

4

3

B-M-+B

3

93

2

A3 6

2

B3

6

3

80

2

2

90

SUBS

CO

2

Subtract Double

SUBD

83

4

Transfer Acmltr

TAB

16

2

1

A-+B

TBA

17

2

1

B-+A

TSTA

40 2

1

A -00

TSTB

50 2

1

B -00

Test, Zero or Minus

TST

5

60 6

2

The Condition Code Register notes are listed after Table 12.

303

70 6

0- M:M

3

M-OO

I

N Z V

C
































• • •

t

~

~

t t ~
t t t

~

t t
t ~















DO 4

SUBA

Cond.Code Reg.
H

+ 1-+0














~

~

~

• • • •
R
R

• • •
•••

• • •
• • •
~

t

t t t
t t

~

~ ~
~ t

t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t

~

~

t
t
t
t
t
t

t
t
t
t
t
t

t
t
t
t
t
t R •
t R •
t R •
t t t
t t t
t t t
t R •
t R •
t R R
t R R
t R R

HD68P01S0, HD68P01V05, HD68P01V07-------------------------------Table 11 Jump and Branch Instructions

Operations

Direct

Mnemonic

OP
Branch Always

BAA

-

Relative

Index

# OP

-

# OP

20

3

2

-

Extend

# OP

-

Condo Code Aeg.

Implied

# OP

-

Branch Test

#
None

Branch Never

BRN

21

3

2

Branch If Carry Clear

BCC

24

3

2

None
CeO

Branch If Carry Set

BCS

25

3

2

C=1

Branch If = Zero

BEQ

27

3

2

Z"1

Branch If

~

Zero

BGE

2C

3

2

N <±'> VeO

Branch If

> Zero

BGT

2E

3

2

Z + (N <±'> V)-O

Branch If Higher

BHI

22

3

2

C+Z=O

Branch If Higher or Same

BHS

24

3

2

C=O

Branch If ~ Zero

BlE

2F

3

2

Z+ (N <±'> V)-1

Branch If Carry Set

BlO

25

3

2

Co:1

Branch If lower Or Same

BlS

23

3

2
2

C+Z"1
N(±>V=1

< Zero

BLT

20 3

Branch If Minus

BMI

2B

3

2

Branch If Not Equal Zero

BNE

26

3

2

Branch If Overflow Clear

BVC

28

3

2

VeO

Branch If Overflow Set

BVS

29

3

2

Vc 1

Branch If Plus

BPl

2A 3

2

N =0

Branch To Subroutine

BSA

80 6

2

Jump

JMP

Jump To Subroutine

JSR

No Operation

NOP

01

Return From Interrupt

RTI

3B 10 1

Return From Subroutine

ATS

39

Software Interrupt

SWI

3F 12 1

Wait For Interrupt

WAI

3E

Branch If

N" 1
N=O

6E
90 5

2

3

2

7E

3

3

AD 6

2

BD 6

3

js.. '''';''
Figure 26

2
5
9

4

3

H

I

N Z V

















•• • ••
• • • • •





"",,"';0"

1
1

5













2









1 0







Clear Carry

Mnemonic

OP

Figure 26

CLC

OC

2

1

O .... C

Clear Interrupt Mask

CLI

OE

2

1

0 .... 1

Clear Overflow

ClV

OA

2

1

0 .... V
1-C

Set Carry

SEC

00

2

1

Set Interrupt Mask

SEI

OF

2

1

1 .... 1

Set Overflow

SEV

OB

2

1

TAP

06

2

1

1 .... V
A .... CCA

TPA

07

2

1

CCA .... A

Accumulator A - CCA
CCR - Accumulator A

--------

LEGEND
OP Operation Code (Hexadecimal)
- Number of MPU Cycles
MSp Contents of memory location pointed to by Stack Pointer
# Number of Program Bytes
+ Arithmetic Plus
- Arithmetic Minus
• Boolean AND
X Arithmetic Multiply
+ Boolean Inclusive OA
<±'> Boolean Exclusive OA
fin Complement of M
-+ Transfer Into
OBit = Zero
00 Byte = Zero

CONDITION CODE SYMBOLS
H
I
N
Z
V
C
A
S

*

304

S

Condo Code Aeg.

#


•• • • ••

1

Boolean Operation

-

js.. "-;" """""OM ••* •* ••* ••* ••* ••*

Table 12 Condition Code Register Manipulation Instructions

Implied



• • •
•• • •
• • • • •
•••• •
• • • • •
•• • • •
••• ••
• • • • •
•••• •
• • • • •
• • • • •
• • • • •
••• ••

The Condition Code Register notes are listed after Table 12.

Operations

C

Half-carry from bit 3
I nterrupt mask
Negative (sign bit)
Zero (byte)
Overflow, 2's complement
Carry/Borrow from MSB
Aeset Always
Set Always
Affected
Not Affected

5

4

3

2

1

0

H

I

N

Z

V

C

• • •
• A •
• • •
• • •
• S •
• • •






• A
• •
A

• S
• •
S

•* •* •* •* •* •*

---------------------------------HD68P01S0, HD68P01V05, HD68P01V07
Table 13 Instruction Execution Times in E-Cycles
Addressing Mode

Addressing Mode
~

:c
(II

E

ABA
ABX
ADC
ADD
ADDD
AND
ASl
ASlD
ASR
BCC
BCS
BEQ
BGE
BGT
BHI
BHS
BIT
BlE
BlO
BlS
BlT
BMI
BNE
BPl
BRA
BRN
BSR
BVC
BVS
CBA
ClC
CLI
ClR
ClV
CMP
COM
CPX
DAA
DEC
DES
DEX
EOR
INC
INS

...
(J

e

$

"0
(II
"0

"0

$

(II

c:

(II

>
.+:;

0.

I'CI

x

.!!:!

"0

0

w

X

.:

•2


•3


•4


•4

2
3

2
4
2

3
5
3

4
6
4
6

4
6
4
6

•6





•4














•6
•4

•6






•4














•6
•4

6
6

6
6










•2















2

•4


•2









•3
















•3
•5



•3


•6

•4

•6

•4

6

6



•2
3
2




















•2
2
2
2
2


2
•2
2
3
3


•3

I'CI

:c

(II

"0

a::









•3

INX
JMP
JSR
lOA
lDD
lDS
lOX
lSl
lSlD
lSR
lSRD
MUl
NEG
NOP
ORA
PSH
PSHX
PUl
PUlX
ROl
ROR
RTI
RTS
SBA
SBC
SEC
SEI
SEV
STA
STD
STS
STX
SUB
SUBD
SWI
TAB
TAP
TBA
TPA
TST
TSX
TXS
WAI

3
3
3
3
3
3

•3
3
3
3
3
3
3
3
3
6

3
3














305

QI

"0

>
.+:;

"0

a::

3






































e

w

X

.:



•2


•5

•3

•3

6

,3
4
4
4

4

6
4

3
3
3








2









•2






•2
4
















3








•3



3
4
4
4
3
5









5
5
5
6

(II
(II

5
5
5
6

•6

•6

4



•6

•6

•6

4


6

6



•4




•4


5

5
5
5

4
6

4
6

4
5
5





•6


(II

.!!:!

0

1:)

"0

x

E

1)

"

"$c:

(II

•6

4




•6

0.







2
3
2
3
10
2
2

•3
4
4

5
2
2
10

5
2

•2
2
2







12
2
2
2
2
2
3
3
9

I'CI

1)





HD68P01S0, HD68P01V05, HD68P01V07-------------------------------• SUMMARY OF CYCLE BY CYCLE OPERATION
Table 14 provides a detailed description of the information
present on the Address Bus, Data Bus, and the Read/Write
(R/W) line during each cycle of each instruction;
The information is useful in comparing actual with expected
results during debug to both software and hardware as the
·program is executed. The information is categorized in groups
according to addressing mode and number of cycles per instruc-

tion. In general, instructions with the same addressing mode
and number of cycles execute in the same manner. Exceptions
are indicated in the table.
Note that during MPU reads of internal locations, the resultant value will not appear on the external Data Bus except in
Mode O. "High order" byte refers to the most significant byte
of a 16-bit value.

Table 14 Cycle by Cycle Operation
Address Mode &
Instructions

Data Bus

Address Bus

IMMEDIATE
2

1
2

Op Code Address
Op Code Address + 1

1
1

Op Code
Operand Data

LDS
LDX
LDD

3

1
2
3

Op Code Address
Op Code Address + 1
Op Code Address + 2

1
1
1

Op Code
Operand Data (High Order Byte)
Operand Data (Low Order Byte)

CPX
SUBD
ADDD

4

1
2
3
4

Op Code Address
Op Code Address + 1
Op Code Address + 2
Address Bus F F F F

1
1
1
1

Op Code
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector

3

1
2
3

Op Code Address
Op Code Address + 1
Address of Operand

1
1
1

Op Code
Address of Operand
Operand Data

STA

3

1
2
3

Op Code Address
Op Code Address + 1
Destination Address

1
1
0

Op Code
Destination Address
Data from Accumulator

LDS
LDX
LDD

4

1
2
3
4

Op Code Address
Op Code Address + 1
Address of Operand
Operand Address + 1

1
1
1
1

Op Code
Address of Operand
Operand Data (High Order Byte)
Operand Data (Low Order Byte)

STS
STX

4

1
2
3
4

Op Code Address
OP. Code Address + 1
Address of Operand
Address of Operand + 1

1
1
0
0

Op Code
Address of Operand
Register Data (High Order Byte)
Register Data (Low Order Byte)

CPX
SUBD
ADDD

5

1
2
3
4
5

Op Code Address
Op Code Address + 1
Operand Address
Operand Address + 1
Address Bus FFFF

1
1
1
1
1

Op Code
Address of Operand
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector

JSR

5

1
2
3
4
5

Op Code Address
Op Code Address + 1
Subroutine Address
Stack Pointer
Stack Pointer + 1

1
1
1
0
0

Op Code
Irrelevant Data
First Subroutine Op Code
Return Address (Low Order Byte)
Return Address (High Order Byte)

ADC
ADD
AND
BIT
CMP

EOR
LOA
ORA
SBC
SUB

DIRECT
ADC
ADD
AND
BIT
CMP

EOR
LOA
ORA
SBC
SUB

STD

(Continued)

306

--------------------------------HD68P01S0, HD68P01V05, HD68P01V07
Table 14 Cycle by Cycle Operation (Continued)
Address Mode &
Instructions

Address Bus

Data Bus

EXTENDED

3

JMP

1
2

3
ADC
ADD
AND
BIT
CMP

EOR
LDA
ORA
SBC
SUB

4

3
4
4

STA

1
2

1
2

3
4
LDS
LDX
LDD

5

STS
STX
STD

5

ASL
ASR
CLR
COM
DEC
INC

1
2

3
4
5
1
2

3
4
5
LSR
NEG
ROL
ROR
TST*

6

1
2

3
4
5
6

CPX
SUBD
ADDD

6

JSR

6

1
2

3
4
5
6
1
2

3
4
5
6

Op Code Address
Op Code Address + 1
Op Code Address + 2

1
1
1

Op Code
Jump Address (High Order Byte)
Jump Address (Low Order Byte)

Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand

1
1
1
1

Op Code
Address of Operand
Address of Operand (Low Order Byte)
Operand Data

Op Code Address
Op Code Address + 1
Op Code Address + 2
Operand Destination Address

1
1
1
0

Op Code
Destination Address (High Order Byte)
Destination Address (Low Order Byte)
Data from Accumulator

Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address of Operand + 1

1
1
1
1
1

Op Code
Address of Operand
Address of Operand
Operand Data (High
Operand Data (Low

(High Order Byte)
(Low Order Byte)
Order Byte)
Order Byte)

Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address of Operand + 1

1
1
1
0
0

Op Code
Address of Operand
Address of Operand
Operand Data (High
Operand Data (Low

(High Order Byte)
(Low Order Byte)
Order Byte)
Order Byte)

Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address Bus F F F F
Address of Operand

1
1
1
1
1
0

Op Code
Address of Operand (High Order Byte)
Address of Operand (Low Order Byte)
Current Operand Data
Low Byte of Restart Vector
New Operand Data

Op Code Address
Op Code Address + 1
Op Code Address + 2
Operand Address
Operand Address + 1
Address Bus FFFF

1
1
1
1
1
1

Op Code
Operand Address (High Order Byte)
Operand Address (Low Order Byte)
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector

Op Code Address
Op Code Address + 1
Op Code Address + 2
Subroutine Starting Address
Stack Pointer
Stack Pointer - 1

1
1
1
1
0
0

Op Code
Address of Subroutine (High Order Byte)
Address of Subroutine (Low Order Byte)
Op Code of Next Instruction
Return Address (Low Order Byte)
Return Address (High Order Byte)

• In the TST instruction, the line condition of the sixth cycle does the following: R/W = "High", AB = FFFF, DB = Low Byte of Reset Vector.

(Continued)

307

HD68P01S0, HD68P01V05, HD68P01V07-------------------------------Table 14 Cycle bv Cycle Operation (Continued)
Address Mode &
Instructions

Data Bus

Address Bus

INDEXED
JMP

3

1
2

3
ADC
ADD
AND
BIT
CMP

EOR
LDA
ORA
SBC
SUB

4

3
4
4

STA

1
2

1
2

3
4

5

LDS
LDX
LDD

1
2

3
4
5

5

STS
STX
STD

1
2

3
4
5

ASL
ASR
CLR
COM
DEC
INC

LSR
NEG
ROL
ROR
TST *

6

1
2

3
4
5
6

CPX
SUBD
ADDD

6

JSR

6

1
2

3
4
5
6
1
2

3
4
5
6

Op Code Address
Op Code Address + 1
Address Bus FFFF

1
1
1

Op Code
Offset
Low Byte of Restart Vector

Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register Plus Offset

1
1
1
1

Op Code
Offset
Low Byte of Restart Vector
Operand Data

Op Code Address
Op Code Address + 1
Address Bus F F F F
Index Register Plus Offset

1
1
1

0

Op Code
Offset
Low Byte of Restart Vector
Operand Data

Op Code Address
Op Code Address + 1
Address Bus F F F F
Index Register Plus Offset
Index Register Plus Offset + 1

1
1
1
1
1

Op Code
Offset
Low Byte of Restart Vector
Operand Data (High Order Byte)
Operand Data (Low Order Byte)

Op Code Add ress
Op Code Address + 1
Address Bus FFFF
Index Register Plus Offset
Index Register Plus Offset + 1

1
1
1

Op Code
Offset
Low Byte of Restart Vector
Operand Data (High Order Byte)
Operand Data (Low Order Byte)

0
0

Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register Plus Offset
Address Bus F F F F
Index Register Plus Offset

0

Op Code
Offset
Low Byte of Restart Vector
Current Operand Data
Low Byte of Restart Vector
New Operand Data

Op Code Address
Op Code Address + 1
Address Bus F F F F
Index Register + Offset
Index Register + Offset + 1
Address Bus F F F F

1
1
1
1
1
1

Op Code
Offset
Low Byte of Restart Vector
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector

Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register + Offset
Stack Pointer
Stack Pointer - 1

1
1
1
1

Op Code
Offset
Low Byte of Restart Vector
First Subroutine Op Code
Return Address (Low Order Byte)
Return Address (High Order Byte)

1
1
1
1
1

0
0

* In the TST instruction, the line condition of the sixth cycle does the following: R/IN = "High", AS = FFFF, DB = Low Byte of Reset Vector.

(Continued)

308

----------------------------------HD68P01S0, HD68P01V05, HD68P01V07
Table 14 Cycle by Cycle Operation (Continued)
Address Mode &
Instructions

Data Bus

Address Bus

IMPLIED
2

1
2

Op Code Address
Op Code Address + 1

1
1

Op Code
Op Code of Next Instruction

ABX

3

1
2

Op Code Address
Op Code Address + 1
Address Bus F F F F

1
1
1

Op Code
Irrelevant Data
low Byte of Restart Vector

ASlD
lSRD

3

Op Code Address
Op Code Address + 1
Address Bus FFFF

1
1
1

Op Code
Irrelevant Data
low Byte of Restart Vector

DES
INS

3

Op Code Address
Op Code Address + 1
Previous Register Contents

1
1
1

Op Code
Op Code of Next Instruction
Irrelevant Data

INX
DEX

3

Op Code Address
Op Code Address + 1
Address Bus F F F F

1
1
1

Op Code
Op Code of Next Instruction
low Byte of Restart Vector

PSHA
PSHB

3

Op Code Address
Op Code Address + 1
Stack Pointer

1
1

0

Op Code
Op Code of Next Instruction
Accumulator Data

TSX

3

Op Code Address
Op Code Address + 1
Stack Pointer

1
1
1

Op Code
Op Code of Next Instruction
Irrelevant Data

TXS

3

Op Code Address
Op Code Address + 1
Address Bus F F F F

1
1
1

Op Code
Op Code of Next Instruction
low Byte of Restart Vector

PULA
PUlB

4

Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1

1
1
1
1

Op Code
Op Code of Next Instruction
Irrelevant Data
Operand Data from Stack

Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1

1
1

0
0

Op Code
Irrelevant Data
Index Register (low Order Byte)
Index Register (High Order Byte)

4
5
1
2
3
4

Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
Stack Pointer +2
Op Code Address
Op Code Add ress + 1
Stack Pointer
Stack Pointer + 1

1
1
1
1
1
1
1
1
1

5

Stack Poi nter + 2

1

ABA
ASl
ASR
CBA
ClC
Cli
ClR
ClV
COM

DAA
DEC
INC
lSR
NEG
NOP
ROl
ROR
SBA

SEC
SEI
SEV
TAB
TAP
TBA
TPA
TST

3
1
2

3
1
2

3
1
2

3
1
2

3
1
2

3
1
2

3
1
2

3
4
PSHX

4

1
2

3
4
PUlX

5

1
2

3

RTS

5

Op Code
Irrelevant Data
Irrelevant Data
Index Register (High Order Byte)
Index Register (low Order Byte)
Op Code
Irrelevant Data
Irrelevant Data
Address of Next Instruction
(H igh Order Byte)
Address of Next Instruction
(low Order Byte)
(Continued)

309

HD68P01S0, HD68P01V05, HD68P01V07-------------------------------Table 14 Cycle by Cycle Operation (Continued)
Address Mode &
Instruction
WAI **

MUL

Cycles

9

10

Cycle

Address Bus

R/W
Line

1
2
3
4

Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer - 1

1
1
0
0

5
6
7
8
9

Stack
Stack
Stack
Stack
Stack

0
0
0
0
0

Op Code
Op Code of Next Instruction
Return Address (Low Order Byte)
Return Address
(High Order Byte)
Index Register (Low Order Byte)
Index Register (High Order Byte)
Contents of Accumulator A
Contents of Accumulator B
Contents of Condo Code Register

1
2
3
4
5
6
7

10

Op Code Address
Op Code Address + 1
Address Bus FFFF
Address Bus F F F F
Address Bus F F F F
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF

1
1
1
1
1
1
1
1
1
1

Op Code
Irrelevant
Low Byte
Low Byte
Low Byte
Low Byte
Low Byte
Low Byte
Low Byte
Low Byte

1
2
3
4

Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1

1
1
1
1

5

Stack Pointer + 2

1

6

Stack Pointer + 3

1

7

Stack Pointer + 4

1

8

Stack Pointer + 5

1

9

Stack Pointer + 6

1

10

Stack Pointer + 7

1

Op Code
Irrelevant Data
Irrelevant Data
Contents of Condo Code Reg.
from Stack
Contents of Accumulator B
from Stack
Contents of Accumulator A
from Stack
Index Register from Stack
(High Order Byte)
Index Register from Stack
(Low Order Byte)
Next Instruction Address from
Stack (High Order Byte)
Next Instruction Address from
Stack (Low Order Byte)

1
2
3
4

Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer - 1

1
1
0
0

5

10
11

Stack Pointer Stack Pointer Stack Pointer Stack Pointer Stack Pointer Stack Pointer Vector Address

2
3
4
5
6
7
FFFA (Hex)

0
0
0
0
0
1
1

12

Vector Address FFFB (Hex)

1

#

8
9
RTI

SWI

10

12

6
7

8
9

Pointer
Pointer
Pointer
Pointer
Pointer

-

2
3
4
5
6

Data Bus

Data
of Restart
of Restart
of Restart
of Restart
of Restart
of Restart
of Restart
of Restart

Vector
Vector
Vector
Vector
Vector
Vector
Vector
Vector

Op Code
Irrelevant Data
Return Address (Low Order Byte)
Return Address
(High Order Byte)
Index Register (Low Order Byte)
Index Register (High Order Byte)
Contents of Accumulator A
Contents of Accumulator B
Contents of Condo Code Register
Irrelevant Data
Address of Subroutine
(High Order Byte)
Address of Subroutine
(Low Order Byte)

** While the MCU is in the "Wait" state, its bus state will appear as a series of the MCU reads of an address which is seven locations
less than the original contents of the Stack Pointet'o Contrary to the HD6800, none of the ports are driven to the high impedance
state by a WAI instruction.

(Continued)

310

---------------------------------HD68P01S0, HD68P01V05, HD68P01V07
Table 14 Cycle by Cycle Operation (Continued)
Address Mode &
Instruction

Data Bus

Address Bus

RELATIVE

3

BCC BHT BNE BlO
BCS BlE BPl BHS
BEQ BlS BRA BRN
BGE BlT BVC
BGT BMT BVS
BSR

1
2

3

6

1
2

3
4
5
6

Op Code Address
Op Code Address + 1
Address Bus FFFF

1
1
1

Op Code
Branch Offset
Low Byte of Restart Vector

Op Code Address
Op Code Address + 1
Address Bus FFFF
Subroutine Starting Address
Stack Pointer
Stack Pointer - 1

1
1
1
1

Op Code
Branch Offset
Low Byte of Restart Vector
Op Code of Next Instruction
Retu rn Address (Low Order Byte)
Return Address (High Order Byte)

• SUMMARY OF UNDEFINED INSTRUCTIONS OPERATION
The MeU has 36 undefined instructions. When these are
carried out, the contents of Register and Memory in MPU
change at random.

0
0

When the op codes (4E, SE) are used to execute, the MPU
continues to increase the program counter and it will not stop
until the Reset signal enters. These op codes are used to test the
LSI.

Table 15 Op Codes Map
HD6SP01 MICROCOMPUTER INSTRUCTIONS
ACC
A

ACC
B

IND

EXT

0011

0100

0101

0110

0111

4

OP
CODE

~
LO

0000

0

0001

1

0010

2

0011

3

0100

4

0000

0001 0010

0

1

2

3

------

SBA

BRA

TSX

CBA

BRN

INS

/
/

BHI PULA (+1)

NOP

------ /
------

BLS PULB (+1)

LSRD (+1)

BCC

------6

5

7

I DIR

liND

ACCB or X

I EXT

IMM

1

9

I

A

I

C

B

*

I

SUBD (+2)

LSR

TXS

~

BIT

PSHA

ROR

LOA

0111

7

TPA

TBA

BEQ

PSHB

1000

S

INX (+1)

/

BVC PULX (+2)

1001

9

DEX (+1)

DAA

BVS

RTS (+2)

1010

A

CLV

/

BPL

ABX

BMI

RTI (+7)

1101

0

SEC

1110

E

CLI

1111

F

SEI

BYTE/CYCLE

1/2

BGE PSHX (+1)

//
/
1/2

BLT

MUL (+7)

BGT

WAI (+6)

BLE

SWI (+9)

2/3

1/3

6

~

STA

STA

7

8

ASL

EOR
AOC

9

DEC

ORA

A

TST

**---

JMP (-3)

CLR
112

3

ROL

INC

-

ADDD (+2)

5

BCS

~1

:

4

BNE

ASR

0

*

TAB

ABA

F

AND

/

/

I

1

TAP

SEV

E

2

ASLD (+1)

CLC

I

SBC

5

B

0

CMP

6

C

I

~

0110

1011

I EXT

SUB

0101

1100

liND

11001110111110J1111

1000 J1001 1101011011
S

I DIR

NEG

COM

DES

ACCA or SP
IMM

1/2

3/6

I

CPX (+2)

LDD (+1)

C

(+1>1

STD (+1)

0

I

LOX (+1)

)'1

E

STX (+1)

F

*

BSR
(+4)

I

JSR (+2)

*

:

LOS (+1)

.

STS (+1)

* (+1

.: (+1)
2/6

B

ADD

*

2/2

1

1 2/3 1 2/4 1 3/4

;

2/2

I

1 2/3

1 2/4

1 3/4

(NOTES) 1. Undefined Op codes are marked with ~.
2. (
) indicate that the number in parenthesis must be added to the cycle count for that instruction.
3. The instructions shown below are all 3 bytes and are marked with "*".
Immediate addressing mode of SUBD, CPX, LOS, ADDD, LOD and LOX instructions, and undefined op codes
(SF, CD, CF).
4. The Op codes (4E, 5E) are 1 byte/co cycles instructions, and are marked with "**".

In order to be pin compatible with the HD680 1V ROM of
the HD68POl must be located at $FOOO - $FFFF. Memory addresses $EOOO to $EFFF are not usable. The other addresses
are available same as the HD6801 V's.

• COMPATIBLE WITH THE HD6801S AND THE HD6801V
In order to be pin compatible with the HD6801S, ROM of
the HD68POl must be located at $F800 - $FFFF. Memory addresses $EOOO to $F7FF are not usable. The other addresses
are available same as the HD6801S's.
~11

.. Subr. Address of next instruction in Main Program to be executed upon return from subroutine RTNH" Most significant byte of Return Address RTN L = Least significant byte of Return Address ~ . Direct Address Main Program ~ INDXD ~ Stack --SP-2 ..... SL .2 Index Register (XL) Acmltr B SP-1 RTNH SP RTNL §f Stack RTI. $AD "JSR K" Offset RTN SP -1 Next Main Instr... K .8-bit Unsigned Value Figure 26 Special Operations 312 . . Subr. . Stack Pointer After Execution K . Jump Main Program ~ INDXD { $6E PC = JMP Acmltr B RTNH RTNL Main Program $7E =JMP K = Offset Exteooed I KH . Next Address K L " Next Address x+KI Next Instruction Next Instruction K Legend: RTN . . Software Interrupt Main Program ~NI $3F" SWI I r=> r=> r=> --SP-2 SP-1 ~NI $3E "WAI I t--------i RTNH SP '--_ _R_T_N. Wait for Interrupt Main Program Stack r=> SP -6 Condition Code SP .::L'--_-' SP Stack SP SP+ 1 --SP+2 ~ Stack --+SP-7 WAI. Return from Interrupt Interrupt Program ec $3B" RTI I q SP SP+ 1 Condition Code SP+2 SP+3 Acmltr A SP+4 Index Register (XH) SP+5 Index Register (XL) SP+6 --+SP+7 JMP..5 SP -4 Acmltr A SP -3 Index Register (XH) SP .. . BSR.. HD68P01V05. Branch to Subroutine ~ Main Program PC $80 = BSR ±K" Offset RTN Next Main Instr. . RTS.. RTN Next Main Instr. . . HD68P01V07-------------------------------JSR.. Jump to Subroutine Main Program ~ Direct $90" JSR K RTN Next Main Instr. Return from Subroutine Subroutine ~ $39'" RTS I SWI. Main Program ~ EXTND { $BD =JSR SH .. Addr..HD68P01S0. Addr.

HD68POSV07 uses HN462732 as EPROM. HD68POSVOS uses HN462S32 as EPROM. () ADR. It is designed for the user who needs an economical microcomputer with the proven capabilities of the HD6800-based instruction set. OADR. Bs B.(l ADR. Bo Do D. I/O and timer. As A_ A. c_ Cs A. ~ A.on ADRIIO 2 B. o ADA. . • • • • • • • • • • • HARDWARE FEATURES 8-Bit Architecture 96 Bytes of RAM Memory Mapped I/O Internal 8-Bit Timer with 7-Bit Prescaler Vectored Interrupts . 313 A. on-chip clock. Setting EPROM on the package. 1 o ADR. this MCU has the equivalent function as the HD680SU and HD680SV.HD68P05V05. B. Bs B_ AD~. HD68P05V07 Me U (Microcomputer Unit) The HD68POSV is the 8-bit Microcomputer Unit (MCV) which contains a CPU. A. A. . As A. B. A. Timer and Software 24 I/O Ports + 8 Input Port (8 Lines LED Compatible. RAM and I/O Compatible Instruction Set with HD6805 -PRELIMINARY - HD68P05V05 HD68P05V07 • PIN ARRANGEMENT (Top View) HD68P05V05 A. o ADA. o ADR. The following are some of the hardware and software highlights of the MCU. An B. o ~ss D. A. () ADRs () ADR. D.External. OADR. o ADA. o ADR6 OADRs o ADR. Ao B. o ADR. 7 Voltage Comparator Inputs) On-Chip Clock Circuit Master Reset Complete Development System Support by Evaluation Kit 5 Vdc Single Supply • • • • • • • • • • • • SOFTWARE FEATURES Similar to HD6800 Byte Efficient Instruction Set Easy to Program True Bit Manipulation Bit Test and Branch Instructions Versatile Interrupt Handing Powerful Indexed Addressing for Tables Full Set of Conditional Branches Memory Usable as Registers/Flags Single Instruction Memory Examine/Change 10 Powerful Addressing Modes • • All Addressing Modes Apply to ROM. () ADR. B. HD68P05V07 Vee XTAL EXTAL NUM TIMER Co 4 o Vee OADR. 00 . RAM. D. o 00 00.

ADR.HD68P05V06._--~--------~--------. ADR. Port 0 Input Lines 0. Condition Code Register CPU Control X cc Data Dir Reg 8 Program Counter "Low" PCl Port B Reg CPU Port C I/O Lines Stack Pointer 4 0. ADR. ADR2 ADR. ADR •• ADR" ADRu Address Output Buffer CE LJ 314 . HD68P05V07-----------------------------------------• BLOCK DIAGRAM RES NUM INT TIMER Port B I/O Lines Accumulator Port A I/O Lines 8 Port A Reg Data Dir Reg 5 Data Input Lines 0. ADR. Index Register SP Program Counter "High" PCH 5 °20. Address Output Lines ADR. A 8 ALU Data Dir Reg Port C Reg Data Input r-----~----------------. AD!'\. 0. Port 0 Reg Address Output~--~----------------~ Buffer Address Output Lines ADR. ADR. 0.0.

2 p.s INT Pulse Width t'WL teye + 250 - - ns RES Pulse Width tRWL teye + 250 - - ns TIMER Pulse Width t TWL t e2'G + 50 - - ns Oscillation Start-up Time (Crv.0 V 20 p.75 -50 - -1200 - Unit -20 XTAL (Crystal Mode) V -0.4 V-Vee V 4.6 V -0.A 50 p.8 0.3 -0.0 All Other Input "Low" Voltage min 4.4 - 4.5V.+150 °c Input Voltage (TIMER) With respect to (NOTE) • • V in Unit -0.A AC CHARACTERISTICS (Vcc=5. HD68P05V07 • ABSOLUTE MAXIMUM RATINGS Item * V -0. - - 100 ms Delay Time Reset tRHL External Cap.stal Mode) tose CL =22pF±20%.3 V .H Unit Vee V V 0. Ta=0-+70°C.) min typ max Clock Frequency fel 0. ELECTRICAL CHARACTERISTICS DC CHARACTERISTICS (Vcc=5.) Item Symbol Test Condition RES Input "High" Voltage INT V .5V.8 RES XTAL (Crystal Mode) Vee - INT Power Dissipation • max - 2.3.L V Vee 0. unless otherwise noted.3.-------------------------------------------HD68P05V05. Vss=GNO.55 .0 - 10 p.3-+7.A 0 p.0 MHz Cycle Time tcyc 1.25V ± 0.8 V 400 700 mW -0. unless otherwise noted.3 - 0. = 2. Rs=60n max.+12.0 All Other Input Leak Current typ 3.3 - Po LVR Low Voltage Recover TIMER INT I'L V in =0.25V ± 0. it could affect reliability of LSI.+7.0 V -0. Ta=0-+70°C.F 100 ms Vin=OV 25 - - 35 pF 6 10 pF Item Input Capacitance l I EXTAL All Other Symbol Cin Test Condition 315 . Normal operation should be under recommended operating conditions. If these conditions are exceeded.0 Vee * Input Voltage (EXCEPT TIMER) * Value Symbol Supply Voltage Vss (SYSTEM GND) Permanent LSI damage may occur if maximum ratings are exceeded.0 Operating Temperature Topr o -+70 V °c Storage Temperature T stg . VSS=GND.

(Port A and C) TTL Equiv. C.SV. Figure 1 Bus Timing Test Loads • SIGNAL DESCRIPTION The input and output signals for the MCV shown in PIN ARRANGEMENT are described in the following paragraphs. - * Port 0 as digital mput ** Port 0 as analog input TTL Equiv.4 - 1.4 V - - 0.S - V 2.3 Vin Port A Input Leak Current Test Condition IOH IlL Port B. Ta = 0"'" +70°C unless otherwise noted. • RES This pin allows resetting of the MCV at times other than the automatic resetting capability already in the MCV..25V ±O. B. • TIMER This pin allows an external input to be used to decrement the internal timer circuitry. 2.2SV ± O. Refer to TIMER for additional information about the timer circuitry.6mA Test Point Test Point Vi 40pF (NOTE) 30 pF 12 k!l 24 k!l 1. 4 MHz maximum) can be connected to these pins to provide the internal oscillator with varying degrees of stability. • NUM This pin is not for user application and should be connected to ground. C.S - - V 2.8V = 2V -300 - Vin = 0.6 mA IOL = 3.5V. All diodes are 152074 @or equivalent.2 - V Threshold Voltage Port 0**(0 7 ) VTH 0 0. Load capacitance includes the floating capacitance of the probe and the jig etc.) Symbol A Port B VOH Port C Port A and C Output "Low" Voltage Input "High" Voltage Input "Low" Voltage Port B Port A. Vss is the ground connection.4 - - V - - 0. HD68P05V07-----------------------------------------• PORT ELECTRICAL CHARACTERISTICS (Vee Item Port Output "High" Voltage = S. and 0* VOL min typ max = -10~A IOH = -100~A IOH = -200~A IOH = -1 mA IOH = -100~A IOL = 1.2mA Ii = 1. This pin provides the capability for applying an external interrupt to the MCV Refer to INTERRUPTS for additional information.HD68P05V05. 8xV ee V .2 mA IOL = 10mA 3.4V"'" Vee - - VIH 2. A crystal (AT cut. (Port B) Vee 2. Refer to RESETS for additional information.4 V - 1. Refer to INTERNAL OSCILLATOR for recommendations about these inputs.8 V - ~A ~A 20 ~A Input "High" Voltage Port 0** (Do"'" 0 6 ) V IH - VTH+0.0 V Vee V Vin = 0. • Vee and Vss • INT Power is supplied to the MCV using these two pins.4k!l Ij=3. Vee is +5.2 - V Input "Low" Voltage Port 0** (Do"'" 0 6 ) VIL - VTH-0. and 0 -SOO 20 Unit V 0. 316 .4 - - V 2. Vss = GNO. • XTAL and EXTAL These pins provide control input for the on-chip clock circuit.0 VIL -0.

hy reading S003 address. The MCli re~ponds to this interrupt hy saving the present Mel) state in the stack..0 7 ) These are 8-bit input lines.-------------------------------------------HD68P05V06.. which has two functions. • Stack Pointer (SP) The stack pointer is a 13-bit register that contains the ad.. • Interrupt (I) This bit is set to mask the timer and external interrupt (lNT)..ve _ ~~~- Interrupt Mask .. • Negative (N) Used to indicate that the result of the last arithmetic... and rotates. These bits can be individually tested by a program and specific action taken as a result of their sta te.:ted during bit test and hranch instructions. All lines are programmable as either inputs or outputs under software control of the data direction registers. these become TTL compatible inputs. Please refer 10 INPUT PORT for more detail.. hy reading S007 address. The other function of them is 7 Voltage comparators..... Band C). • TIMER The MeU timer circuitry is shown in Figure 3. HD68P06V07 • Input/Output Lines (Ao '" A 7 . This hit is also affe. The index register can also be used for limited calculations and data manipulations when using read/modify/write instructions. _ ..J(° Program Counter " L-_ _ _ _ _ _ pc_ _ _ _ _ " ° 5 4 LI0. Firstly. The timer interrupt can be masked by setting the timer interrupt mask hit (bit 6) in the time control TIMER Input Pin TCR bit 4 Timer Control Register (TCR) r/J 2 (Internal) . The six most significant bits of the stack pointer are permanently set to 00000011. I A Accumulator L -_ _ _ _ _ _. • Index Register (X) The index register is an 8-bit register used for the indexed addressing mode. • Half Carry (H) Used during arithmetic operations (ADD and ADC) to indicate that a carry occurred between bits 3 and 4. Programming Model • Accumulator (A) The accumulator is a general purpose 8-bit register used to hold operands and results of arithmetic calculations or data manipulations. fetching the timer interrupt vector from locations $OFF8 and $OFF9 and executing the interrupt routine. They are shown in Figure 2 and are explained in the following paragraphs. Co '" C 7 ) These 24 lines are arranged into three 8-bit ports (A. • Carry/Borrow (C) Used to indicate that a carry or borrow out of the arithmetic logic unit (ALU) occurred during the last arithmetic operation.. • Program Counter (PC) The program counter is a 13-bit register that wntains the address of the next instruction to be executed. Refer to INPUTS/OUTPUTS for additional information.Half Carry Figure 2 .LI_.. the index register can be used as a temporary storage area. Each individual condition code register bit is explained in the following paragraphs. Z Stack Pomt •• C -~~ ~ Condition Code Register Carry/Borrow Zero --~~. It contains an 8-hit address that may be added to an offset value to create an effective address.ero the timer interrupt request hit (bit 7) in the timer control register is set. logical or data manipulation was zero.I_ _ _ sP_---'1 I ~ l l N. During an MCU reset or the reset stack pointer (RSP) instruction.I_..--_ ... Timer Interrupt Mask Clock Input } Source Option Figure 3 Timer Block Diagram 317 .' \ TCR bit 5 Multiplex Prescaler } Address Bits Clock Input 8-bit Counter Timer Interrupt Req..J.. The is-bit counter is loaded under program control and counts down toward zero as soon as the clock input is applied..jress of the next free location on the stack. the stack point· er is set to location $007F and is decremented as data is being pushed onto the stack and incremented as data is being pulled from the stack. shifts.. the stack pointer is set to location $007F. • Condition Code Register (CC) The condition code register is a 5-bit register in which each bit is used to indica te or flag the r~sulLs of the instruction just executed.J..l_o.Negat.llndex Register . If an interrupt occurs while this bit is set it is latched and will be processed as soon as the interrupt bit is reset.. When not required by a code sequence being executed.. Bo '" B7 ...J. logical or data manipulation was negative (bit 7 in result equal to a logical one). Subroutines and interrupts may be nested down to location $0061 which allows the programmer to use up to 15 levels of subroutine calls. • Input Lines (Do . Iniually.I_0. • REGISTERS The MCU has five registers available to the programmer......I_o. • Zero (Zl Used to indicate that the result of the last arithmetic.... When the timer reaches I.lI_o...

The options of the dividing ratio are shown in Table 2. Crystal specifications are given in Figure 7. The bit 3 is not used. The bit 6 of timer control register is writable by program. The bit 2. The timer continues to count past zero and its present count can be monitored at any time by monitoring the timer data register. Connecting a capacitor to the IrnS input as shown in Figure 5 will provide sufficient delay. and is cleared by program or by hardware reset. The bit 5 and bit 4 of the timer control register is a clock input source. initialized to Input mode (DDR's are cleared) during RESET. All the I/O port are External Clock Figure 6 318 Internal Oscillator . HD88P05V07-----------------------------------------register.. a minimum of 100 milliseconds is needed before allowing the reset input to go "High". 128 1 - 6 EXTAl External Clock 5 XTAl H068P05V MCU Input • RESETS The MCV can be reset three ways: by initial powerup. RES Pin ---------1" ~:::~al _ _ _ _ _ _ _ _ _---1 Figure 4 Power and~Timing Part of HD68P05V MCU Figure 5 Power Up Reset Delay Circuit Table 1 Clock Input Source Option Timer Control Register (TCR) b4 bs 1 0 1 1 • INTERNAL OSCILLATOR The internal oscillator circuit has been designed to require a minimum of external components. This time allows the internal crystal oscillator to stabilize. The interrupt bit (I bit) in the condition code register will also prevent a timer interrupt from being processed. Upon power up.. The combinations are shown in Table 1. 0 0 0 0 b1 bo 0 0 0 Bypass Prescaler 1 1 0 Prescaler + 2 Prescaler . This allows a program to determine the length of time since a timer interrupt has occured and not disturb the counting process. 4 1 1 Prescaler + 8 1 1 0 0 0 Prescaler + 16 1 1 1 1 1 0 Prescaler + 32 Prescaler + 64 Prescaler .HD88P05V05. Both of those bits can be read by MPU. A prescaler option can be applied to the clock input that extends the timing interval up to a maximum of 128 counts before being applied to the counter... Clock Input Source tP2 (Internal Clock) TIMER Input Pin 6 EXTAl Table 2 Prescaler Dividing Ratio Option 4 Timer Control Register (TCR) :a~Z c:::J 5 XTAl HD68P05V MCU Prescaler Dividing Ratio b. The use of a crystal (AT cut. This timer data register and the prescaler are initialize with all logical ones at reset time. The different connection methods are shown in Figure 6. bit 1 and bit 0 are used to select a dividing ratio of the prescaler. The timer data register is 8-bit read/write register with address $008 on memory-map. Note that when the tP2 signal is used as the source it can be gated by an input applied to the TIMER input pin allowing the user to easily perform pulse-width measurements. by the external reset input (RES) and by an internal low voltage detect circuit (mask option) see Figure 4. 4 MHz max) is sufficient to drive the internal oscillator with varying degrees of stability. The clock input to the timer can be from an external source applied to the TIMER input pin or it can be the internal tP2 signal. An internal clock is selected as a clock input source and the dividing ratio of a prescaler is set at "Bypass Prescaler" at reset time. The timer interrupt request bit (bit 7 of timer control register) is set to one by hardware when timer count reaches zero.

. and the interrupt routine is executed. XTAl~~EXTAl 5 ~~ 6 AT . the address of the interrupt routine is obtained from the appropriate interrupt vector address. Prescaler 7F _TeR Figure 9 Interrupt Processing Flowchart 319 Interrupt Priority RES SWI INT TIMER 1 2 3 4 Vector Address $OFFE and $OFFF $OFFC and $OFFD $OFFA and $OFFB $OFF8 and $OFF9 ..Cut Parallel Resonance Crystal Co = 7 pF max. and a software interrupt instruction (SWI). This ensures that the program counter is loaded correctly as the stack pointer increments when it pulls data from the stack. and the vector address that contain the starting address of the appropriate interrupt routine. only PCH and PCl are stacked. A subroutine call will canse only 1 11 1 Condition Code Register n+1 n-3 Accumu lator n+2 n-2 Index Register n+3 .. the internal timer interrupt request. processing is suspended. the low order byte (PCL) of the program counter is stacked first. The interrupt service routines normally end with a return from interrupt (RTI) instruction which allows the MCV to resume processing of the program prior to the interrupt. Since the stack pointer decrements during pushes. HD68P05V07 the program counter (PCH. Figure 8 Interrupt Stacking Order Table 3 Interrupt Priorities 1-1 7F -sP O-OOR's CLR iNT Logic FF .-------------------------------------------HD68P05V05. the address of the interrupt routine is obtained from the appropriate interrupt vector address. This interrupt bit (I) in the condition code register is set. 8. f = 4 MHz Rs = son max. A flowchart of the interrupt processing sequence is given in Fig.. their priority. 9. PCL) contents to be pushed onto the stack. n+4 n-1 1 1 '1 PCH* PCl* n+5 Push * For subroutine calls. When any interrupt occurs. and the interrupt routine is executed. the interrupt bit (I) in the condition code register is set. then the high order five bits (pCH) are stacked. Table 3 provides a listing of the interrupts. the present MCV state is pushed onto the stack in the order shown in Fig. 6 5 4 3 2 0 Pull Figure 7 Crystal Parameters n-4 • INTERRUPTS The MCV can be interrupted three different ways: through the external interrupt (lNT) input pin. Timer 7F .

Port A Programmed as outputls) driving CMOS and TTL Load directly. INPUT/OUTPUT There are 24 input/ output pins. la) Port B Programmed as outputls) driving Darlington base directly. One of them is usual digital signal input port and the other is voltage compare type input port. Idi Figure 11 Typical Port Connections • INPUT Port D is 8-bit input port. All pins are programmable as either inputs or outputs under software control of the data direction registers. 10). Assume that bit 0 of port A is connected to a zero crossing detector circuit and that bit 1 of port A is connected to the trigger of a TRIAC which power the controlled hardware. Ib) +V +V R R Port B · ·•• ··• - Port C 10mA max ·· ·• · CMOS Inverter C. all I/O pins read latched output data regardless of the logic level at the output pin due to output loading (see Fig. and the other seven input pins (Do . HD68P05V07-----------------------------------------• programmed for outputs. Any bit in the page zero read only memory can be tested. D6 ) are analog level inputs. which are compared with Vrn (see Figure 12(a). Figure 12(c) shows the application of Port D to A/D converter. B. The example in Figure 13 illustrates the usefulness of the bit manipulation and test instructions. using the BRSET and BRCLR instructions. A capacitive touch panel interface and a diode isolated keyboard interface are the examples. In the former case. Figure 11 provides some examples of port connections. Port A lines are CMOS compatible as outputs while port Band C lines are CMOS compatible as inputs. and Figure 12(d) shows 3 levels inputs. it is capable of sinking 10 millamperes on each pin (VOL = IV max). which uses only seven ROM locations.. Ic) Port C Programmed as output(s) driving CMOS using external pull-up resistors. All input/output lines are ITL compatible as both inputs and outputs. This capability to work with any bit in RAM.HD68P05V05. BCLR). D7 (pin 17) is the input pin ofVrn (reference level). B. This function is effective in such case that unusual logic level inputs are used. which has two functions. Port B Programmed as outputls) driving LEDls) directly. the input data can be read by MPU at $003 address. "1" or "0" signals appear at internal data bus. if the input levels are higher or lower respectively when $007 address is read. • BIT MANIPULATION The MCU has the ability to set or clear any single random access memory or input/output bit (except the data direction registers) with a single instruction (BSET. ROM or I/O allows the user to have individual flags in RAM or to handle single I/O bits as control lines. When programmed as outputs.. The timer could also be incorporated to provide turnon at some later time which would permit pulse-width modulation of the controlled power. In the latter case.. provides turn-on of the TRIAC within 14 microseconds of the zero crossing. 320 . and the program branches as a result of its state. When port B is Data Direction Register Bit Output Data Bit Output State Input to MCU 0 1 0 1 3-State 0 1 Pin 1 1 0 x Figure 10 Typical Port I/O Circuitry Bo Ao ·· ··• Port A •• ··•• · Port B A. (b». This program.

Port I---"----Analog Input 6 o Do 1 .Analog Input 0 Analog Input 0 (b) Seven analog inputs and a refarence level input of Port 0 (c) Application to AID convertor 0. HD68P05V07 $003 Read Internal Bus (BitO .3V 1 1 0 3.0V ...--------------------------------------------HD68P05V05.7V -Vee 1 3 Levels Input 0 (d) Application to 3 levels input Figure 12 Configuration and Application of Port D 321 .. Referance Level 0.. Port 3 Levels Input 6 ~ 0 Do Input Voltage ($003) ($007) OV-O.3. VTH (= 3.Bit6) + $003 Read Input Port (07) Internal Bus (Bit 7) (a) The logic configuration of Port 0 Port C r----._0.8V 0 0 2. 0... Port Analog Input 6 ) 0 0' 0 0.5V) 0.

• Indexed (No Offset) Refer to Figure 18.HD88P06V06. The implied mode of addressing has no EA. In addition. The relative addressing mode applies only to the branch instructions. All implied addressing instructions are one byte long. The third byte is the relative address to be added to the program counter if the branch condition is met. 511 low memory locations are accessable. In direct addressing. ReI is the contents of the location following the instruction opcode with bit 7 being the sign bit. • Immediate Refer to Figure 14. PORT A. The byte to be tested is addressed by the byte following the opcode. All RAM space. The following paragraphs briefly explain each type. Such instructions are two bytes long. SELF 1 BSET 1. • Relative Refer to Figure 17. This mode of addressing applies to instructions which can test any bit fu the first 256 locations ($OO-$FF) and branch to any location relative to the PC. They can be divided into five different types: register/memory. Thus. • Indexed (16-bit Offset) Refer to Figure 20. PORT A BClR 1. They are explained and illustrated briefly in the following paragraphs. Direct operations on the accumulator and the index register are included in this mode of addressing. One operand is either the accumulator or the index register. • Extended Refer to Figure 16. EA={pC}+2+Rel. This mode of addressing applies to instructions which can set or clear any bit on page zero. These instructions are three bytes long. modify or test its contents. PORT A ·•• ·•• Figure 13 Bit Manipulation Example • ADDRESSING MODES The MCU has ten addressing modes available for use by the programmer. • INSTRUCTION SET The MCU has a set of 59 basic instructions. The lower three bits in the opcode specify the bit to be set or cleared while the byte following the opcode specifies the address in page zero. This mode of addressing accesses the lowest 256 bytes of memory. Refer to Table 6. If the branch is not taken Rel=O. and write the modified value back to memory or to the register. HD88P06V07----------------------------------------- SELF 1 •• • ••• • BRClR 0. In this mode the contents of the byte following the opcode is added to the program counter when the branch is taken. The effective address (EA) is the PC and the operand is fetched from the byte following the opcode. In this mode. Extended addressing is used to reference any location in memory space. I/O registers and 128 bytes of ROM are located in page zero to take advantage of this efficient memory addressing mode. • Register/Memory Instructions Most of these instructions use two operands. Refer to Table 4. bit manipulation. This addressing mode calculates the EA by adding the contents of the two bytes following the opcode to the index register. Instructions which use this addressing mode are three bytes long. These instructions are one byte long and'their EA is the contents of the index register. The EA is calculated by adding the contents of the byte following the opcode to the contents of the index register. Refer to Table 7. These instructions occupy two bytes. when a branch takes place. These instructions are two bytes long. branch. • Control Instructions The control instructions control the MCV operations during program execution. The other operand is obtained from memory using one of the addressing modes. All the instructions within a given type are presented in individual tables. the address of the operand is contained in the second byte of the instruction. All the information necessary to execute an instruction is contained in the opcode. • Implied Refer to Figure 23. and control. • Bit Test and Branch Refer to Figure 22. Direct addressing allows the user to directly address the lowest 256 bytes in memory. • Alphabetical Listing The complete instruction set is given in alphabetical order in Table 9. The EA is the contents of the two bytes following the opcode. • Read/Modify/Write Instructions These instructions read a memory location or a register. The value of the bit tested is written to the carry bit in the condition code register. The immediate addressing mode accesses constants which do not change during program execution. Extended addressing instructions are three bytes long. • Direct Refer to Figure 15. the entire memory space may be accessed. Refer to Table 5. Refer to Table 8. 322 . One group either sets or clears. control instructions such as SWI. The jump unconditional (JMP) and jump to subroutine (JSR) instructions have no register operand. • Branch Instructions The branch instructions cause a branch from the program when a certain condition is met. • indexed (8-bit Offset. The other group performs the bit test and branch operations. read/modify/ write. The individual bit within that byte to be tested is addressed by the lower three bits of the opcode. the program goes to somewhere within the range of +129 bytes to -127 of the present instruction. Refer to Figure 19. RTI belong to this group. • Bit Set/Clear Refer to Figure 21. • Bit Manipulation Instructions These instructions are used on any bit in the first 256 bytes of the memory. • Opcode Map Table 10 is an opcode map for the instructions used on the MCV. The test for negative or zero (TST) instruction is an exception to the read/modify/write instructions since it does not perform the write.

I I I Prog Count I I 20 Index Reg • ' ' : . HD68P05V07 EA Memory i I I I .. I Figure 14 Immediate Addressing Example I I I I I I I I f I I I CAT FCB 32 LOA CAT I I 0048 / Adder "" ol 20 0048 . 8 . Figure 15 Direct Addressing Example 323 I . PROG LOA #$F8 05SE 05BF Stack Point • A6 Prog Count Fa 05CO t-------t CC § . lEA + Memory A I 1 I I 0520 86 052E 48 Stack Point I I 052F CC ~ I I I .------------------------------------------HD68P05V05. PROG . . .

HD68P05V05. Figure 17 Relative Addressing Example 324 . I . HD68P05V07------------------------------------------- Memory i I I I I ~ PROG LOA 040A 06 040B E5 64 40 Index Reg Stack Point I I FCB A ~oo~J CAT Prog Count I I CAT 0000 040C 40 06E5 CC Figure 16 Extended Addressing Example EA Memory 04C1 : I I ~ A Index Reg Stack Point I I PROG BEQ PROG2 04A7 27 04A8 18 0000 § I .

• I I Prog Count I. Figure 19 Indexed (8·Bit Offset) Addressing Example 325 075E CC I .------------------------------------------HD68P06V06.~ • i I I 008C /' Adder I I TABL lEA Memory I FCB #BF 0089 BF FCB #86 OOSA 86 FCB #OB 008B DB FCB #CF 008C CF J I I I I t '" A f 1 CF I Index Reg I I 03 I Stack Point PROG LOA TABL. HD68P06V07 EA OOB8 Memory A TABL FCC t Lit OOB8 4C 4C 49 Index Reg B8 I PROG LOA X I Stack Point ~F4~ Prog Count 05F5 CC § . X 0758 E6 075C 89 I I I I § . I Figure 18 Indexed (No Offset) Addressing Example .

HD88P06V06. . X 0692 0693 A DB I'ndex Reg I 02 ~6 Stack Point 07 ~ 0694 _ _ _--J 7E Prog Count 0695 I TABl CC I FCB #BF 077E FCB #86 077F BF 86 FCB #OB 0780 DB FCB #CF 0781 CF Figure 20 Indexed (16·Bit Offset) Addressing Example Memory PORTB EQU 0001 BF A 0000 Index Reg PROG BelR 6. i I I ~ I PROG lOA TABl. HD88P06V07----------------------------------------- Me ory' . I • Figure 21 Bit Set/Clear Addressing Example 326 . PORT B 058F 0590 10 Stack POint t-------1 01 Prog Count 0591 I • CC t@ I I I I .

Prog Count 0000 0594 CC C I I ~ Figure 22 Bit Test and Branch Addressing Example Memory i • I I • ~ I PROG TAX E5 Index Reg •I E5 • O~A8 Prog Count 0588 cc .------------------------------------------HD68P06V06..• § Figure 23 Implied Addressing Example 327 . PORT C. HD68P06V07 PORT C EQU A FO 0002 2 Index Reg 0000 Stack Point PROG BRCLR 2.--.~----. PROG 2 0574 0575 05 1-------4 02 0576 r----:1.D..

HD68P05V07------------------------------------------Table 4 Register/Memory Instructions Addressing Modes Function Mnemonic Op Op # # Code Bytes Cycles Code Op # # Bytes Cycles Code Op # # Bytes Cycles Code Indexed (l6·Bit Offset) Op # # Bytes Cycles Code # # Bytes Cycles Load A from Memory LOA A6 2 2 B6 2 4 C6 3 5 F6 1 4 E6 2 5 06 3 6 Load X from Memory LOX AE 2 2 BE 2 4 CE 3 5 FE 1 4 EE 2 5 DE 3 6 Store A in Memory STA - - - B7 2 5 C7 3 6 F7 1 5 E7 2 6 07 3 7 Store X in Memory STX - - - BF 2 5 CF 3 6 FF 1 5 EF 2 6 OF 3 7 Add Memory'to A ADD AB 2 2 BB 2 4 CB 3 5 FB 1 4 EB 2 5 DB 3 6 Add Memory and Carry to A AOC A9 2 2 B9 2 4 C9 3 5 F9 1 4 E9 2 5 09 3 6 3 5 FO 1 4 EO 2 5 DO 3 6 6 2 BO 2 4 CO 2 2 B2 2 4 C2 3 5 F2 1 4 E2 2 5 02 3 2 2 B4 2 4 C4 3 5 F4 1 4 E4 2 5 04 3 6 AA 2 2 BA 2 4 CA 3 5 FA 1 4 EA 2 5 OA 3 6 EOR A8 2 2 B8 2 4 C8 3 5 F8 1 4 E8 2 5 08 3 6 CMP A1 2 2 B1 2 4 C1 3 5 F1 1 4 E1 2 5 01 3 6 CPX A3 2 2 B3 2 4 C3 3 5 F3 1 4 E3 2 5 03 3 6 BIT A5 2 2 B5 2 4 C5 3 5 F5 1 4 E5 2 5 05 3 6 Jump Unconditional JMP - - - BC 2 3 CC 3 4 FC 1 3 EC 2 4 DC 3 5 Jump to Subroutine JSR - - - BO 2 7 CD 3 8 FO 1 7 ED 2 8 DO 3 9 AO 2 SBC A2 AND A4 ORA Exclusive OR Memory with A Arithmetic Compare A with Memory Arithmetic Compare X with Memory Bit Test Memory with A (Logical Compare) Subtract Memory - Op # # Bytes Cycles Code Indexed (8·Bit Offset) Indexed (No Offset) Extended Direct Immediate Subtract Memory from A with Borrow AND Memory to A OR Memory with A SUB Table 5 Read/ModifylWrite Instructions Addressing Modes Function Implied (A) Mnemonic Op Code Implied (X) Op # # Bytes Cycles Code Indexed (No Offset) Direct Op # # Bytes Cycles Code Op # # Bytes Cycles Code Indexed (8-Bit Offset) Op # # Bytes Cycles Code # # Bytes Cycles Increment INC 4C 1 4 5C 1 4 3C 2 6 7C 1 6 6C 2 7 Decrement DEC 4A 1 4 5A 1 4 3A 2 6 7A 1 6 6A 2 7 Clear eLR 4F i 4 5F 1 4 3F 2 6 7F 1 6 6F 2 7 Complement COM 43 1 4 53 1 4 33 2 6 73 1 6 63 2 7 Negate (2's Complement) NEG 40 1 4 50 1 4 30 2 6 70 1 6 60 2 7 Rotate Left Thru Carry ROL 49 1 4 59 1 4 39 2 6 79 1 6 69 2 7 Rotate Right Thru Carry ROR 46 1 4 56 1 4 36 2 6 76 1 6 66 2 7 Logical Shift Left LSL 48 1 4 58 1 4 38 2 6 78 1 6 68 2 7 7 Logical Shift Right LSR 44 1 4 54 1 4 34 2 6 74 1 6 64 2 Arithmetic Shift Right ASR 47 1 4 57 1 4 37 2 6 77 1 6 67 2 7 Arithmetic Shift Left ASL 48 1 4 58 1 4 38 2 6 78 1 6 68 2 7 Test for Negative or Zero TST 40 1 4 50 1 4 3D 2 6 70 1 6 60 2 7 328 .HD68P05V05.

...... 7) - - Branch I F Bit n is clear BRClR n (n=O .. HD68P06V07 Table 6 Branch Instructions Relative Addressing Mode Mnemonic Function Op Code # # Bytes Cycles Branch Always BRA 20 2 4 Branch Never BRN 21 2 4 Branch IF Higher BHI 22 2 4 Branch I F lower or Same Branch I F Carry Clear BlS 23 2 4 BCC 24 2 4 (Branch IF Higher or Same) (BHS) 24 2 4 Branch I F Carry Set BCS 25 2 4 (Branch IF lower) (BlO) 25 2 4 Branch I F Not Equal BNE 26 2 4 Branch I F Equal BEQ 27 2 4 Branch I F Half Carry Clear BHCC 28 2 4 Branch I F Half Carry Set BHCS 29 2 4 Branch I F Plus BPl 2A 2 4 Branch IF Minus BMI 2B 2 4 Branch I F Interrupt Mask Bit is Clear BMC 2C 2 4 Branch I F Interrupt Mask Bit is Set BMS 20 2 4 Branch I F Interrupt Line is low Bil 2E 2 4 Branch IF Interrupt Line is High BIH 2F 2 4 Branch to Subroutine BSR AO 2 8 Table 7 Bit Manipulation Instructions Addressing Modes Function Mnemonic Bit Test and Branch Bit Set/Clear Op Code # # Bytes # # Cycles Op Code Bytes Cycles - 2 n 3 10 01+2 n 3 10 - Branch I F Bit n is set BRSET n (n=O . 7) - - Set Bit n BSET n (n=O ...... 7) 11+2 n 2 7 - - 0 0 0 0 Table 8 Control Instructions Implied Function Mnemonic Op Code # # Bytes Cycles Transfer A to X TAX 97 1 2 Transfer X to A TXA 9F 1 2 Set Carry Bit SEC 99 1 2 Clear Carry Bit ClC 98 1 2 Set Interrupt Mask Bit SEI 9B 1 2 Clear Interrupt Mask Bit CLI 9A 1 2 Software Interrupt SWI 83 1 11 Return from Subroutine RTS 81 1 6 Return from Interrupt RTI 80 1 9 Reset Stack Pointer RSP 9C 1 2 No-Operation NOP 90 1 2 329 .-------------------------------------------HD68P05V05.. 7) 10+2 n 2 7 - - Clear bit n BClR n (n=O ....

HD88P05Y06. HD88P06Y07-----------------------------------------Table 9 Instruction Set Condition Code Addressi n9 Modes Mnemonic Implied Immediate Direct Extended Relative Indexed Indexed Indexed (No (8 Bits) (16 Bits) Offset) x x x ADC x x x ADD x x x x x x x AND ASl x x ASR x x x x x x x x x x x Bit Set/ Clear Bit Test & Branch BCS x BEQ x BHCC x BHCS x BHI x BHS x BIH x Bil x x BIT x x x BlO x BlS x BMC x BMI x BMS x BNE x BPl x BRA x BRN x x x BRClA x BRSET x x BSET x BSR x ClC CLI x ClR x COM x x CMP x DEC x x x x x EOR x x x x CPX x x x x x x x x x x x x x x x x x x x x JMP x x x x x JSR x x x x x INC x lOA x x x x x x lOX x x x x x x Condition Code Symbols: H Half Carry (From Bit 31 I Interrupt Mask N Negative (Sign Bitl Z N Z C A A • • • • • • • • • • • • • • • • • • • • • • • • • • • • • A A A A A A A A A A A A • • • • • • • • • • • • • • • • • • • • x BClR I • • • • x BCC H • • • • • • • • A • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 0 • • • 0 • • A • • A • • A • • A • • A • • A • • • • • • • • A • • A • • • A • A A • • • • • • • • • • • • • • • • • • • • • • • • • • • • A • A • • • • • 0 • • 1 • A A A A A 1\ A 1 A • • • • • • • • • A A (to be continued) C A • Carry Borrow Test and Set if True. Cleared Otherwise Not Affected Zero 330 .

Cleared Otherwise Not Affected Load CC Register From Stack 331 • • • • • • • • • • • 1\ • • • 1\ 1\ • 1\ 1\ 1\ 1\ • ? • 1\ • • 1\ 1\ • • ? ? • • 1\ 1\ • 1 • • 1\ 1\ • 1\ 1\ • 1\ 1\ /\ • • • • • • 1\ 1\ • • • • .------------------------------------------HD68P05V05. HD68P05V07 Table 9 Instruction Set Addressing Modes Mnemonic LSL LSR NEG NOP ORA ROL ROR RSP RTI RTS SBC SEC SEJ STA STX SUB SWI TAX TST TXA Implied Immediate x Direct Extended Relative x x x x x x x x x x x x x x x x Condition Code Indexed Indexed Indexed (No (8 Bits) (16 Bits) Offset) x x x x x x x x x x x x Bit Setl Clear x Bit Test & Branch H I N Z C • • • • • • • • • • • • • • • • ? • • • 1 • • • 1 • • • 1\ 0 1\ 1\ 1\ 1\ 1\ 1\ ? x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Condition Code Symbols: H Half Carry (From Bit 3) I I nterrupt Mask N Negative (Sign Bit) Z Zero x C 1\ • ? x Carry!Borrow Test and Set if True.

( ) indicate that the number in parenthesis must be added to the cycle count for that instruction. 1/6 TAX lOA 8 BRSET4 9 BRClR4 I ClC NOP STA(+lI 7 EOR 8 ADD B I JMP(-1) C BSR*. HD88P06V07-----------------------------------------Table 10 Bit Manipulation 0 Set/ Clear Rei OIR 0 BRSETO 1 2 3 BSETO BRA I I A 4 I I Control Ragister /Memory IMM I OIR A I B 1 I )(2 I )(1 I . If used for HD6805U/V.. "Not Used" memory map may be used for HD68P05V but not used for HD6805U.. Undefined opcodes are marked with "-". Fig. 2/4 I 3/5 HIGH 0 4 0 • Read/Modify!Write Branch Test & Branch Opcode Map STX(+lI .HD88P06V05. HD68P05V will have the configuration shown in Fig.. The timer part of HD6805U/V is mask-option. Fig. 25(a) provides the configuration of HD68P05V used for HD6805U. 1/4 3/10 (NOTE) 2/7 2/4 2/6 . 2/5 F . require a different number of cycles as follows: RTI 9 RTS 6 SWI 11 BSR 8 3. the command to operate this bit is ignored because HD6805U/V doesn't have the bit 0 to 5 of the timer control register. 1/4 1. HD68P05V sets the bit 0 to 5 of timer control register in the program just after reset and selects the dividing ratio of the prescaler and the clock input source. 2. 3/6 . The number at the bottom of each column denote the number of bytes and the number of cycles required (Bytes/Cycles). HD68P05V USED FOR HD6805U/V Fig. 2/7 .. 25 provides the memory configuration of MeU.X1 I . 24 shows an example of the program which selects the external clock as an input source at 128 dividing. 25(b). lOA #$77 STA TCR ($009) • • ••• Figure 24 Example to initialize timer control register (TCA) 332 .XO IMP IMP 6 I 7 8 9 NEG RTI* - RTS* - CMP 1 - SBC 2 X 5 I I BClRO BRN - 2 BRSET1 BSET1 BHI - - 1 BRClRO EXT I C I SUB +- CPX 3 l AND 4 o BIT 6 W 6 3 BRClR1 BClR1 BlS COM SWI* BRSET2 BSET2 BCC lSR - SEC AOC 9 Cli ORA A 5 BRClR2 BClR2 BCS - 6 BRSET3 BSET3 BNE ROR 7 - BRClR3 BClR3 BEQ ASR BSET4 BHCC lSl/ASl BClR4 BHCS ROl A BRSET5 BSET5 BPl DEC B BRClR5 BClR5 BSET6 BMI - - SEI C BRSET6 BMC INC - RSP TXA - 1/· 1/2 2/2 BRClR6 BClR6 BMS TST E BRSET7 BSET7 Bil - F BRClR7 BClR7 BIH ClR . 1/4 . If used for HD6805V.XO 0 I E I F . Mnemonics followed by a . JSR(-3) 0 - - E lOX I. If the program specified by the HD68P05V is masked as HD6805U/V.

------------------------------------------HD68P05V05. HD68P05V07 o 7 000 127 128 76543210 $000 I/O Ports Timer RAM (96 Bytes) ROM 0 Port A $000 1 Port B $001 $07F 2 Port C $002 .\80 3 Port D (digital) $003** 4 Port A DDR $004* $OFF $100 5 Port B DDR $005* 6 Port C DDR $006* 7 Port D (analog) $007** 8 Timer Data Reg $008 9 Timer CTR L Reg $009 (128 Bytes) 255 256 Not Used $7FF $800 2047 2048 10 31 32 ROM (1920 Bytes) Not Used $OOA (22 Bytes) $01F RAM (96 Bytes) $020 S~Ck 1J 3967 3968 4087 4088 4095 Self-Test Interrupt Vectors $07F * Write Only Register -* Read Only Register $F7F $F80 $FF7 $FF8 $FFF (a) HD6805U Configuration o 7 000 127 128 76543210 $000 I/O Ports Timer RAM (96 Bytes) $07F $080 0 Port A $000 1 Port B $001 $002 2 Port C 3 Port D (digital) $003** 4 Port A DDR $004* 5 Port B DDR $005* 6 Port C DDR $006* 7 Port D (analog) $007** ROM 8 Timer Data Reg $008 (3840 Bytes) 9 Timer CTR L Reg 10 Not Used (22 Bytes) 31 32 RAM (96 Bytes) 1~ 3967 3968 4087 4088 4095 Self-Test Interrupt Vectors r Sta~ck $009 $OOA $01F $020 $07F * Write Only Register ** Read Only Register 7F F80 FF7 FF8 $FFF (b) HD6805V Configuration Figure 25 MCU Memory Configuration 333 .

334 .

8-BIT MICROCOMPUTER HMCS6800 MULTI-CHIP SERIES 335 .

336 .

A" A . 37 RES 40 A. BA 7 VMA 5 A. HD68BOOP (DP-40) • PIN ARRANGEMENT vss A is 25 AI. The HD6800 is capable of addressing 6Sk bytes of memory with its 16-bit address lines. 1. NMI 6 HALT 2 iRQ 4 HD6S00 0.. 11 A. Immediate. 14 A..Direct. HD68BOO (DC-40) HD6800P. The HD68AOO and HD68BOO are high speed versions. 31 01 32 0. 2B Os 29 0.HD6800.0 MHz) Halt and Single Instruction Execution Capability Compatible with MC6800. 33 0" 337 .. Compatible with TTL. HD68AOO... A..Internal Registers Saved in Stack Six Internal Registers . 0. and no external TTL devices for bus interface. Extended. HD68BOO M PU (Micro Processing Unit) The HD6800 is a monolithic 8-bit microprocessor forming the central control function for Hitachi's HMC'S6800 family. 27 O. 24 All 23 Au 22 All 20 A lo 19 At 18 A. • • • • • FEATURES Versatile 72 Instruction .5 MHz. making direct memory addressing and multiprocessing applications realizable. HD68AOOP. 17 A. Indexed. Rlii 34 A.0 MHz (HD6800 ..Variable Length (1~3 Byte) Seven Addressing Modes . HD68AOO. 1 MHz. The 8-bit data bus is bi-direc· tional as well as 3-state. A. Relative. 13 A. 12 A. 16 A. 30 0. A" (Top View) 26 0.Two Accumulators. Index Register. HD68AOO . HD68BOO . 10 A.. 15 A. A. 9 HALf <PI NC <P2 VMA DBE NMI NC Rffl ¢. Implied and Accumulator Variable Length Stack Vectored Restart Maskable Interrupt Separate Non-Maskable Interrupt . requires only one SV power supply.. Program Counter. MC68AOO and MC68BOO • BLOCK DIAGRAM • • • • • • • HD6800. the HD6800 as with all HMC'S1i800 system parts. 2. Do 3 ¢. TSC 39 As DBE 36 A. Stack Pointer and Condition Code Register Direct Memory Accessing (DMA) and Multiple Processor Capability Clock Rates as High as 2.

0 W 6. ¢1 Output Capacitance **.0 - -20 25 Topr • With respect to Vss (SYSTEM GNO) • • ELECTRICAL CHARACTERISTICS DC CHARACTERISTICS (Vee = 5V ± 5%. Ta = 25 C.75 5.4 V - V Symbol 0 0 -0.25V... Vee V IL -0.0. • RECOMMENDED OPERATING CONDITION Symbol Item min typ max Unit Supply Voltage 4.HD8800.6 - Vee + 0.4 "" 2.25 V O.0 V -0. If these conditions are exceeded.3.5 10 pF 10 12. f = 1 MHz -2.+7.. unless otherwise noted.5 pA -100 - 100 pA -10 - 10 pA -100 - 100 pA - 0. ¢2 V IHe V ee .. f = 1 MHz • Ta 2soe.5 1.5 pF - 25 35 pF - 45 70 pF - - 12 pF u Cout V in = OV.0 - Vee v Input "Low" Voltage Logic·· V IL .B V Vee 75 V °c Input Voltage Operating Temperature . R/W IOH = -205pA 2.6mA lin Yin = 0-5.55. Vss = OV. it could affect reliability of LSI.¢2 0 0 ""0. Output "High" Voltage A o-A 15 • R/W VMA V OH BA Output"Low" Voltage Logic*-* Input Leakage Current Three·State (Off-state) Input Current Ao""A15. ¢2 A o'. R..) Item min typ· max Unit Input "High" Voltage Logic·· V IH 2.B V Clock Input "High" Voltage ¢1. ¢2 VILe -0.*.1/12 and Do -0 7 :0 338 .3.W VMA BA Cin Yin = OV.5 - 2.+7.4 - - V IOH = -100pA 2. Item Symbol Supply Voltage Value Vee V in Input Voltage Operating Temperature Topr T stg Storage Temperature Unit -0.3 0. HD88AOO.3 V t::lock Input "Low" Voltage ¢1..0 5. Ta = 25°C.0. Ta = -20-+75°C. Normal operation should be under recommended operating conditions.4V Po Power Oissipation Logic··* Input Capacitance 0 0 ""0.3 V IH 2.4 - - V - - 0.4 V VOL IOL = 1.4 - IOH = -145pA 2. Test Condition ITSI V in = 0. HD88BOO----------------------------------------• ABSOLUTE MAXIMUM RATINGS .+150 °c • With respect to Vss (SYSTEM GNO) (NOTE) Permanent LSI damage may occur if maximum rating are exceeded.0 -20-+75 V °c . Vee:o 5V All inputs except 1/1 1 and 1/1 2 All inputs except 1/11 .3 - O.. A 15 . All other pins are connected to GNO ¢1.

.(tAD + tOSR ) tacc Fig._ -. s. 11. unless otherwise noted. 12 - 250 - - - 135 ns Fig.500 ns -- 180 max MHz - - 100 ns 0 440 - 4.0 - 10 I-/S 4... 12 20 Address Hold Time (Address. Ta = -2G-+75°C.------------------------------------------HD6800. 12 300 Data Bus Enable Rise and Fall Times tOBEr tOBEf Fig.. HD68AOO.0V Test Point 0-.. Fig.. 10 400 - 4..500 t r .500 4. 10 - tel Fig. A/W.. 11 100 - 60 - 165 tOSR - - 40 ns - - 530 - 360 - - - - 250 ns - 10 - 20 20 - - - 10 - - ns - 10 - - ns 280 - 220 - - ns Data Setup Time (Read) Peripheral Read Access Time tacc tUT ... C a Figure 1 Bus Timing Test Load 339 - . tP2 I tPl. 10 typ 0.- ns C = 130pF for Do -0 7 = 90pF for Ao -A. Fig. TIMING CHARACTERISTICS OF CLOCK PULSE Clock Pulse Width Rise and Fall Times - 1.500 - Unit -- 2. 12 = 10 - - 200 - - 160 ns - 120 - - 75 - - ns - - 250 - - 180 - - ns - - 25 - - 25 - 25 ns - - 140 - - 110 - - ns 100 - - 100 - - 100 ns - 165 - - 135 ns 270 - - 220 ns Processor Control Setup Time tpcs 200 Processor Control Aise and Fall Times tpcr tpCf Bus Available Delay Time (BA) tBA - - 250 - Three-State Delay Time tTSO - - 270 - 5. 11..1 f Frequency of Operation Cycle Time tP2 and min Symbol Item tPl Test Condition max typ min 230 - - - 100 - 4. 10 900 - tCYC I tPl. HD68BOO • AC CHARACTERISTICS (Vee =5V ± 5%. 12 150 - 225 Data Bus Enable Down Time (During tPl Up Time) Data Bus Enable Delay Time tOBEO Fig. 11 10 Output Data Hold Time tH Fig.500 ns - ns - 2 READIWRITE CHARACTERISTICS Symbol Item Address Delay Time Test Condition typ HD68BOO HD68AOO HD6800 min max min typ max min typ max Unit C=90pF tAo1 Fig.000 Fig. Vss = OV. R/W and VMA = 24kn for BA C includes Stray Capacitance.1 10 0. PWCH 2 Delay Time (Clock Internal) Clock "High" Level Time HD68AOO HD6800 Fig.. tP2 PWCH1.. 11. 12 450 - - Data Delay Time (Write) toow Fig. 12 10 - Enable "High" Time for DBE Input tEH Fig. All diodes are 152074 or equivalent.666 100 - HD68BOO max 0 600 1.500 0. tf Fig. 11 Input Data Hold Time tH Fig.1 10 0.5 typ min 0.500 tUT Fig..) 1. and VMA = 30pF for BA R = 11 kn for Do -0 7 = 16kn for Ao -A.. 12 - - 270 - - 180 - - 150 ns C=30pF t A02 Fig.0 1.s' R/W. VMA) tAH Fig. 12 - t5BE Fig. Fig. 10 0 - 4.

.HD6800.-_ _ _ RES 2.U Reset ¢I ---1 MPU Restart Sequence ____r \'-------J/ ~_-.4V BA Figure 3 Timing of HALT and SA -I- MP. HD68BOO------------------------------------------The Last Instruction Cycle BA Figure 2 Timing of HALT and SA Halt Cycle I nstruction Cycle -I' O.4V VMA Figure 4 RES and MPU Restart Sequence 340 L ..J/ ¢2 \ ' . HD68AOO.

.------.------. . HD68BOO WAIT Cycle or The Last Instruction Cycle -I- \'--_ _----J/ Interrupt Sequence \___---"r Vec .. HD68AOO.O.Jr \----s::=:··vL _tpcr SA Figure 6 WAllnstruction and BA Timing PWCHI (4.5 /JS max) tPl TSC R/W VMA SA __~~~~~V~-------4--~~--_ v ~ Indeterminate period Figure 7 TSC Input and MPU Output 341 .-----------------------------------------HD6800...\"'----_ _. I The last execution cycle of WAI instruction (#9) WAIT Cycle tP1--.!..\'--_ _----J1..6V (When WAIT Cycle) SA Figure 5 IRQ and NMI Interrupt Timing I -.

9) be provided to accomplish specific functions. • Data Bus (Do -0 7 ) Eight pins are used for the data bus.. Data Bus is placed in the three-state mode when DBE is "Low....4V (max. Bit 4 is the interrupt mask bit (I). When the output is turned off. The functions of pins are explained in this section. In those applications that require storage of information in the stack when power is lost.. 8.... • Program Counter (PC) The program counter is a two byte (16-bit) register that points to the current program address.. Zero (Z)... 10. ¢2 ) Two pins are used to provide the clock signals.. HD68AOO. • 0 15 Figure 9 Internal Block Diagram of MPU Accumulator A Clock (¢2. IH) Ptogrem Count.Half Carry (From Bit 3) Figure 10 Clock Timing Waveform Figure 8 Programming Model of the Microprocessing Unit • • Condition Code Register (CCR) The condition code register indicates the results of an Arithmetic Logic Unit operation: Negative (N). 9. The detail block diagram of the microprossingunit is shown in Fig.6V (min. HD68BOO----------------------------------------• MPU REGISTERS The MPU provides several registers in Fig. the stack must be nonvolatile.. 0 7 I I ACCA 7 15 I IX I PC I SP I I I 0 ACCB • Accumulator B 0 Index Register I I Program Counter MPU SIGNAL DESCRIPTION Proper operations of the MPU requires that certain control and timing signals (Fig. transferring data to and from the memory and peripheral devices. IH) Inc.. Condition Codes Register cfi • Carry (From Bit 7) VIHC Overflow cfi 2 Zero vov VILC --------1 VIHC = VCC . Carry from bit 7 (C).. it is essentially an open circuit... Putting TSC in its high state forces the Address bus to go into the three-state mode..r-'-T""'"r-. It also has three-state output buffers capable of driving one standard TTL load and 130pF..HD6800.... Overflow (V) .. It is bidirectional.. This permits the MPU to be used in DMA applications.. The outputs are three-state bus drivers capable of driving one standard TTL load and 90pF...... III Index Register (IX) The index register is a two byte register that is used to store data or a sixteen bit memory address for the Indexed mode of memory addressing.. A two-phase non-<>verlapping clock is provided as shown in Fig. and half carry from bit 3(H). Address Bus (A o"'"Al 5 ) Sixteen pins are used for the address bus. This stack is normally a random access Read/ Write memory that may have any location (address) that is convenient. • Accumulators (ACCA.) Vov = VSS + O...ement.O...) V I LC = VSS + O. 0 15 Stack Pointer 0 ... • StICk Pointer fH) Increment." 342 .6V Negative Interrupt Mask ' . • Stack Pointer (SP) St8c:k POinter fl) The stack pointer is a two byte register that contains the address of the next available location in an external push-down/ pop-up stack. ACCB) The MPU contains two 8-bit accumulators that are used to hold operands and results from an arithmetic logic unit (ALU). These bits of the Condition Code Register are used as testable conditions for the conditional branch instructions. which is available for use by the programmer... The unused bits of the Condition Code Register (b6 and b7) are" 1".. Each register is described below.

. .8V -=--t-..=====::.......- --~---------tacc--------- Data From Memory or Peripherals 2. HD68BOO ~----------------------tcvc----------------------~ cp...0V --:=-..po1'E'~'0Ilndeterminate period Figure 11 Read from Memory or Peripherals Address FromMPU~~!-~~~~-~~~--------+---------------------------~~ ~-----------tEHI------------~ Data From MPU Data Valid ~~ Indeterminate period Figure 12 Write to Memory or Peripherals 343 .J-~==~_ ---------------------------------=~~ O.. HD68AOO.------------------------------------------HD6800..

BA = "Low". all three-state output d. it will go to the "High" state indicating that the microprocessor has stopped and that the address bus is available. however in normal operation. FFFF) in memory will be loaded into the Program Counter to point to the beginning of the reset routine. After the power supply reaches 4. As for the characteristical values in Fig.::::::=--- Restart Routine Address Bits 8-15 ~A = Indeterminate period Figure 13 RES Timing 344 Restart Routine / Restart Routine Address 8its 0-7 / Instruction of Restart Routine . During an MPU read cycle. when the processor is halted. Three-State Control going "High" will turn R/W to the off (high impedance) state. and the Address Bus will contain the reset address FFFE." If additional data setup or hold time is required on an MPU write. If TSC is in the "High" state. The normal standby state of this signal is Read ("High").7SV.rivers will go to their off state and other outputs to their normally inactive level. Data Bus = high impedance. 13 (DBE ~ 4>2). 8 I 9 I n I n+ I I n+2 I n+3 I n+4 I n+5 uu-u-uu-L I Ij :~~~~~~l~~~~~~~~~~~~~~~~il ~~~. will make the bus driver off when in the "Low" state. When activated. HD68AOO. 12. R/W="High" (read state). the contents of the last two locations (FFFE. This input can also be used to reinitialize the machine at any time after start-up. it will be in the off state. Also. VMA = "Low". The minimum down time for DBE is tOBE as shown and must occur within 4>1 up time. If a "High" level is detected in this input. This output is capable of driving one standard TTL load and 90pF. At such time. • • Bus Available (BA) The BA signal will normally be in the "Low" state. 13 illustrates a power up sequence using the Reset control line. Bus Available will be "Low". This will occur if the HALT line is in the "Low" state or the processor is in the WAIT state as a result of the execution of a WAIT instruction. refer to the table of electrical characteristics. The processor is removed from the WAIT state by the occurrence of a maskable (mask bit 1= 0) or nonmaskable interrupt. Data Bus Enable (DBE) This input is the three-state control signal for the MPU data bus and will enable the bus drivers when in the "High" state. RES can go "High" asynchronously with the system clock any time after the eighth cycle. When it is desired that another device control the data bus such as in Direct Memory Access (DMA) applications. During the reset sequence. this will signal the MPU to begin the reset sequence. During these eight cycles. • ReadlWrite (R/W) This TTL compatible output signals the peripherals and memory devices whether the MPU is in a Read ("High") or 5 I 6 I 7 I Reset (RES) The RES input is used to reset and start the MPU from a power down condition resulting from a power failure or initial start-up of the processor. This input is TTL compatible. VMA will be in an indeterminate state so any devices that are enabled by VMA which could accept a false write during this time (such as a battery-backed RAM) must be disabled until VMA is forced "Low" after eight cycles. it would be driven by 4>2 clock. DBE should be held "Low. Fig. the data bus drivers will be disabled internally. While RES is "Low" (assuming a minimum of 8 clock cycles have occured) the MPU output signals will be in the following states. the interrupt mask bit is set and must be cleared under program control before the MPU can be interrupted by IRQ. During the reset routine. a minimum of eight clock cycles are required for the processor to stabilize in preparation for restarting. This output is capable of driving one standard TTL load and 30pF.~ .HD8800. the DBE down time can be decreased as shown in Fig. HD68BOO-----------------------------------------• Write ("Low") state.

J </>. and non-maskable (NMI). The handling of these interrupts by the MPU is the same except that each has its own vector address. The Interrupt Mask bit is set to prevent further interrupts. This technique speeds up the MPU's response to the interrupt because the stacking of I Cycle #7 I Cycle #8 I I Cycle #9 Cycle #10 ICycle ICycle ICycle I Cycle I Cycle I #11 #12 #13 #14 #15 C/>.f (NOTE) n 9 Cycle n+4 #n+5 n+3 In+1 n+2 .-----------------------------------------HD6800.2 cycles. Program Counter.. FFF9 for an IRQ interrupt. '1>2 A~~sess I #n Ie CYclelCYcie Icyclel Cycle ICYciel cyclel °t Cy I Cycle I #1 I I I 4 I I 6 I I 8 I . 14. HD68BOO The Reset control line may also be used to reinitialize the MPU system at any time during its operation. and Condition Code Register are stored away on the stack.. FFFD for an NMl interrupt and from FFF8. Accumulators (ACCX). • • Interrupt Request (IRQ) This level sensitive input requests that an interrupt sequence be generated within the machine. Next the MPU will respond to the interrupt request by setting the interrupt mask bit "1" so that no further interrupts may occur. the Interrupt Mask bit is restored to its condition prior to interrupts. IX. The HALT line must be in the "High" state for interrupts to be serviced. Fig. and CCR off of the stack. PC15 IX15 ... Index Register (IX). Accumulators. HD68AOO. If the interrupt mask bit in the Condition Code Register is not set. The RES pulse can be completely asynchronous with the MPU system clock and will be recognized during q.2. The interrupt shown could be either IRQ or NMI and can be asynchronous with respect to q. 14 which details the MPU response to an interrupt while the MPU is executing the control program. a 16-bit address will be loaded that points to a vectoring address which is located in memory locations FFF8 and FFF9.ruL1L1l-fLfL.p.. the execution of RTI will pull the PC. however a 3kn external resistor to Vee should be used for wire. The address of the interrupt service routine is then fetched from FFFC.ACCA ACCB CCR .2 if setu~e tPCS is met. X First Inst. the machine will begin an interrupt sequence.. Figure 15 WAI Instruction Timing 345 -X-' New P~~5 N'. mo I Cycle #1 I Cycle #2 I Cycle #3 I I Cycle #4 Cycle #5 I Cycle #6 Non-Maskable Interrupt (NMI) and Wait for Interrupt (WAI) The MPU is capable of handling two types of interrupts: maskable (IRQ) as described earlier. IRQ is maskable by the interrupt mask in the Condition Code Register while NMI is not maskable. a WAIT instruction has been executed in preparation for the interrupt. except in this case. The Index Register.IXO-IX7 IXB. ACCX. Upon completion of the interrupt service routine.-tt-_ _ _ _-.~~g~~ (NOTE) Midrange waveform indicates high impedance state.QR and optimum control of interrupts. Address Bus iROor NMT 1M Data Bus Inst (x) R/Vii PCO-PC7 PCB- \~ ACCA IXO-IX7 IX8- ACCB New PCB-PC15 NewPCO-PC7 First Inst of Address Address Interrupt Routine CCR PC15 IX15 __________________________________ __JI VMA Figure 14 Interrupt Timing Cycle ICYClel Cycle ICYciel Cycle ICYCle ICYCle I CYClel Cycle #2 #3 #4 #5 #6 #7 #8 #9 I #1 I Wa' C #n+1 #n+2 #n+3 #n+4 #n+5 VLn.slSU""Ul. Interrupt timing is shown in Fig. Interrupts will be latched internally while HALT is "Low".. This is accomplished by pulsing RES "Low" for the duration of a minimum of three complete q. The has a high impedance pullup device internal to the chip. The behavior of the MPU when interrupted is shown in Fig.. At the end of the cycle.~~~s-PC7 _______ _ PCO-PC7 PCB. An address loaded at these locations causes the MPU to branch to an interrupt routine in memory.. and the Condition Code Register (CCR) are pushed onto the stack. 15 is a similar interrupt sequence.x X FFF8-FFF9. The processor will wait until it completes the current instruction that is being executed before it recognizes the request.. ot Interrupt Routine . This instruction is not executed but instead the Program Counter (PC). The interrupt is shown going "Low" at time tpcs in cycle #1 which precedes the first cycle of an instruction (OP code fetch).New PC Address R/W -Instruction" SPlnl SPln-ll SPln-21 SPln-31 SPln-41 SPin-51 SPin-51 VMA f IM~~~~~5~f~ mnor ~ta Bus X Wait Inst X X X Jl Jl Jl Jl Jl --I I-tpcs (Zoonsl .

the Data Bus is also in the high impedance state while if>2 is being held "Low" since DBE=4I2. R!W and Data Bus are all in the high impedance state. Address Bus Rfiii VMA Data Bus 1112 DBE TSC Figure 16 TSC Control Timing 346 . While the MPU is waiting for the interrupt.) Since the MPU is a dynamic device. Data Bus. 2 cycle instruction such as ClRA. effectively removing the MPU from the system bus. Bus Available will go "High" indicating the following states of the control lines: VMA is "Low". The instruction illustrated is a one byte. One standard TTL load and 90pF may be directly driven by this active "High" signal. all activity in the machine will be halted. It is necessary to delay program execution while TSC is held "High". • Valid Memory Address (VMA) This output indicates to peripheral devices that there is a valid address on the address bus. and if either an NMI or IRQ interrupt occurs. This signal is not three-ltate. In this example. Because it is too late in cycle #5 to access memory. the MPU will go to a halted or idle mode. This input is level sensitive. After the interrupt occurs. TSC then can be used in a short Direct Memory Access (DMA) application. MPUIII. the Address Bus and the R/W line are placed in a high impedance State. The Address Bus and R/W line will reach the high impedance state at tTSD (three-ltate delay). VMA is forced "Low" so that the floating system bus will not activate any device on the bus that is enabled by VMA. Data Bus = high impedance. While the MPU is halted. (Logic levels of the clocks are irrelevant so long as they do not change. When TSC is returned "Low. if it is "Low". this signal should be utilized for enabling peripheral interfaces such as the PIA and ACIA. and the CCR is already done. The transition of HALT must occur tpcs before the trailingedge of if>1 of the last cycle of an instruction (point A of Fig. A response signal. IX. Table 1 Memory Map for Interrupt Vecton Vector MS FFFE FFFC FFFA FFF8 Description LS FFFF FFFD FFFB FFF9 Restart Non-maskable Interrupt Software Interrupt Interrupt Request Refer to Figure 18 for program flow for Interrupts. • Halt (HALT) When this input is in the "low" state. When BA is "High". When BA is "Low". At this point in time. Program execution resumes in cycle #6. a DMA transfer could occur on cycles #3 and #4. If a RES command occurs while the MPU is halted. HD88AOO. the MPU has halted and all internal activity has stopped.HD8800. it will be latched into the MPU and acted on as soon as the MPU is taken out of the halted mode. In normal operation. it is serviced as previously described. HALT must not go "Low" any time later than the minimum tpcs specified. the MPU will go to locations FFFE and FFFF for the address of the reset routine. Cycle #1 #2 I #3 I #4 I #5 I #6 System III. Fig. HD88BOO----------------------------------------the PC. ACCX. When HALT goes "Low". The HALT line provides an input to the MPU to allow control or program execution by an outside source. Bus Available (BA) provides an indication of the current MPU status. R/W = "High" (read state). 16 shows the effect of TSC on the MPU. 18 shows the timing relationships involved when halting the MPU." the MPU address and R/W lines return to the bus. all program activity is stopped. As soon as the HALT line goes "High". Fig. and R/W line will be in a high impedance state. the if>1 clock can be stopped for a maximum time PWCHI without destroying data within the MPU. the Address Bus. 18). this cycle is dead and used for synchronization. VMA and BA are forced "Low" when TSC = "High" to prevent false reads or writes on any device enabled by VMA. the following states occur: VMA = "Low". with VMA being forced "Low". and the Address Bus. and the Address Bus will contain address FFFE as long as RES is "Low". the MPU will execute the instructions. BA = "Low". If HALT is "High". the MPU is in the process of executing the control program. the MPU will halt after completing execution of the current instruction. • Three State Control (TSC) When the Three State Control (TSC) line is "High" level. if BA is "High". This is done by insuring that no transitions of if>1 (or if>2) occur during this period.

..Y_+ IRQ Ignored <Cycle> #1..2 #3. H068AOO.------------------------------------------H06800. H068BOO "">--..9 Y (FFFC) Fetch IM=1 Reset #10 (FFFS) Fetch #11 IM=1 Reset (~~~ #12 #13 Figure 17 MPU Interrupt Flow Chart 347 (~R~~ #11 .

the instruction Y is fetched from address M+ 1. shift. (The addressing modes which are available for use with the various executive instructions are discussed later. Oblique'lines indicate indeterminate range of data. BA will go "High" by time tBA (bus available delay time) after the last instruction cycle. VMA is "Low" and R/W.) The coding of the first (or only) byte corresponding to an executable instruction is sufficient to identify the instruction and the. When an instruction translates into two or three bytes of code. Figure 18 HALT and Single Instruction Execution for System Dubug Table 2 Operation States of MPU and Signal Outputs (Except the Execution of Instruction) Halt and Signals Reset state Halt state WAI state Reset state ilL" "l" BA "H" "H" ilL" VMA "L" "L" "L" R/W "H" ''T'' "H" ''T'' "T" (FFFE)16 (FFFEh6 "T" Ao -. addressing mode. ~ tpCf I :::::::::~~~~~A~_--~JJ~----~~~~r ~(N~O~T~E~l~)-----------J VMA R/W Address Bus Data Bus '" pc K BA . Table 2 shows the relation between the state of MPU and signal outputs. Included are binary and decimal arithmetic. 348 .HD8800. load. • MPU INSTRUCTION SET This Section will provide a brief introduction and discuss their use in developing HD6800 MPU control programs. 2 cycle instruction such as LSR is used for this example also. To do this. At this point in time. HD68BOO------------------------------------------ . store. I . 2. Data Bus.0 7 TSC state "l" "L" "T" "T" . Each of the 72 executable instructions of the source language assembles into 1 to 3 bytes of machine code. or second and third bytes contain(s) an operand. conditional or unconditional branch. the MPU would have halted after completion of the following instruciton. the second byte. I ~ ~ ~~_(~N~O~TE~2~)~n------------~ Execute ~!r?~--------4'JJ~----------~ ~~~~~~~------4J----------~ WA> W4> ~ M+1=1001 16 • Y=CLRB(OP 5F) Example: M=l 000. 59 of the 256 possible codes being unassigned. logical. Again. VMA and R/W lines are back on the bus. A single byte. HALT must be brought "High" for one MPU cycle and then returned "Low" as shown at point B of Fig. To debug programs it is advantageous to step through programs instruction by instruction. If HALT had not been "Low" at Point A but went "Low" during!P2 of the cycle. The hexadecimal equivalents of the binary codes. . During the first cycle. </I. The H06800 MPU has a set of 72 different executable source instructions. or information from which an address is obtained during execution.6' X=CLRA (OP 4F) (NOTE) ~ 1. 'T indicates high Impedance state • The fetch of the OP code by the MPU is the first cycle of the instruction. Midrange waveform indicates high impedance state.. rotate.. BA returns "High" at tBA on the last cycle of the instruction indicating the MPU is off the bus.Instruction Instruction Fetch Execution. if instruction Y had been three cycles. i8. Address Bus.A 1s "T" "T" "T" ''T'' Do -. indicating that the Address Bus. are shown in Table 3. an address. interrupt and stack manipulation instructions. There are 197 valid machine codes. the width of the BA "Low" time would have been increased by one cycle. The number of bytes depends on the particular instruction and on the addressing mode.HD88AOO. and the Data Bus are in the high impedance state. which result from the translation of the 72 instructions in all valid modes of addressing. the transitions of HALT must occur tpcs before the trailing edge of !P1' BA will go "Low" at t BA after the leading edge of the next !P1 .

Because of these features. B) 2 BRA (REL) 3 TSX (IMP) 4 NEG (A) 5 NEG (B) 6 NEG (lNO) 7 NEG (EXT) 8 ~~BM)(A) ~~~)(A) ~I~CM)(A) 9 ~~I~)(A) f~:)(A) ~~~)(A) A ~~~)(A) ~~~)(A) ~I~~)(A) B SUB (A) (EXT) C ~I~M)(B) ~~~iB) ~I~CM)IB) 0 ~~I~)(B) f~:)(B) ~~I~)(B) E ~I~~)(B) ~~~)(B) ~I~~)(B) F ~~:T)(B) 0 · INS (IMP) · · · · . BVS (REL) RTS (IMP) BPL (REL) . no I/O instructions as such are required. refer to Table 4. ~~~)(B) ~~~)(B) ~:~)(B) ~~~)(B) ~~~)(B) ~~:)(B) ~~~)(B) ?O~:)(B) ~~~)(Bl ~~~)(B) ~~O)(B) ~~~)(B) ~I~~)(B) ~~~)(Bl ~~~)(B) ~~~)(B) ~~~)(B) ~E~)(B) ~~~TiB) ~~X~)(B) ~.n(A) ~~:T)(A) ~EOX.')(A) ORA ~i'~)(A) (EXT) BIT (B) LOA (B) (OIR) (OIR) CLC (IMP) ABA (IMP) · ~~~)(B) C 8 SEV (IMP) . hence.I~)(A) ~~~)(A) ~~:)(A) ~~~)(A) ORA (OIR) · · · · · BGE (REL) RTI (IMP) (A) ~EN~)(A) ~~~T)(A) ~~:rlA) ~. (3) I/O instructions for transferring data between the microprocessor and peripheral devices. In addition.rect AddreSSIng Mode EXT = Extended Addressing Mode IMM= Immediate Addressing Mode · D SEC (IMP) (A) ~~)(A) f. (2) Program control operations. . (2) operating instructions that function without needing a memory reference. other classifications are more suitable for introducing the HD6800's instruction set: (1) Accumulator and memory operations. Table 3 Hexadecimal Values of Machine Codes MS8 ~ 0 1 2 3 · · · · . NOP (IMP) 1 SBA (A. ~~~)(A) ~~~)(A) ~:~)(A) BMI (REL) · · · · ADD (A) (lMM) INC (A) INC · BLT (REL) · TST (A) E CLI (IMP) · F SEI (IMP) · BGT (REL) BLE (REL) WAI (IMP) SWI (IMP) · · CLR (A) (8) TST (B) INC (IND) TST (lNO) JMP (lND) CLR (lNO) INC (EXT) TST (EXT) JMP (EXT) CLR (EXT) ~~XM)(A) BSR (REL) LOS (lMM) · STS (OIR) CLR (B) · LOS (OIR) ~~~)(A) ~~~)(A) ~~~)(A) ~~~)(A) ~~~)(A) JSR (lNO) LOS (lNO) STS (lNO) JSR f::T)(A) (EXT) LOS (EXT) STS (EXT) STA (A) (lND) ~~~)(B) ~~M)(B) ~~~)(B) OIR = D. 5 · · 6 7 TAP (IMP) TPA (IMP) TAB (IMP) TBA (IMP) 8 INX (IMP) . DAA (IMP) A CLV (IMP) . In many instances. ~~~iA) ~~M)(A) ~~~iA) AND (A) (OIR) ~~R)(A) LOA (A) (OIR) ~~~)(A) ~~O)(A) ~~~)(A) BVC (REL) 9 DEX (IMP) BHI (REL) f~:T)(A) ~:~T)(A) fEM:T)(B) 4 . the HD6800 MPU performs the same operation on both its internal accumulators and the external memory locations. so called because they operate on specific memory locations.. (3) Condition Code Register operations.B) CBA (A.:TiB) ~2:T"B) ~~~"B) ?E~~iB) ~E~~)(B) A = Accumulator A B = Accumulator 8 INO = Index AddreSSIng Mode IMP = Implied Addressing Mode REL= Relative Addressing Mode 349 · · · · LOX (lMM) · ~~~)(Bl ~~I~)(BI · · LOX (lNO) STX (lND) · · LOX (EXT) STX (EXT) . For Accumulator and Memory Operations.-----------------------------------------HD6800. HD68AOO. the HD6800 MPU allow the MPU to treat peripheral devices exactly like other memory locations. (1) memory reference. HD68BOO Microprocessor instructions are often devided into three general classifications. BLS (REL) BCC (REL) BCS (REL) BNE (REL) BEO (REL) PUL (A) PUL (B) DES (IMP) TXS (IMP) PSH (A) PSH (B) COM (A) LSR (A) ROR (A) ASR (A) ASL (A) ROL (A) DEC (A) COM (B) LSR (B) ROR (B) ASR (B) ASL (B) ROL (B) DEC (B) COM (lND) LSR (lNO) ROR (lNO) ASR (lNO) ASL (lNO) ROL (lND) DEC (lNO) COM (EXT) LSR (EXT) ROR (EXT) ASR (EXT) ASL (EXT) ROL (EXT) DEC (EXT) · · · · ~:~T)(B) · · · · · · · .

A B+M--B A+B--A A+M+C--A B+M+C--B A·M--A B oM __ B AoM BoM oo .SP...# 8B CB 2 2 9B 3 2 2 2 DB 3 2 B9 2 2 99 3 2 A9 5 2 B9 2 1 4 3 C9 2 2 D9 3 2 E9 5 2 F9 4 3 B4 2 2 94 3 2 A4 5 2 B4 4 3 C4 85 C6 2 2 04 2 2 95 2 2 05 3 2 E4 3 2 A5 3 2 E5 6F 5 2 F4 5 2 B5 5 2 F5 7 2 7F 81 Cl 2 2 91 2 2 01 3 2 Al 3 2 El 5 2 5 2 63 60 6A 88 C8 2 2 98 2 2 08 3 2 3 2 7 2 Bl Fl 73 7 2 70 7 2 7A A8 5 2 B8 E8 5 2 F8 6C 7 2 7C 4 4 4 6 3 3 3 3 4F 5F 2 2 1 1 11 2 1 43 53 2 2 40 60 19 2 2 2 4A 5A 2 2 4 3 4 3 6 6 6 4 4 6 4 4 4 4 49 2 2 1 1 3 3 3 2 2 86 2 2 96 3 2 A6 5 2 B6 4 3 C6 2 2 06 3 2 E6 5 2 F6 4 3 89 BA 4 3 FA 4 3 7 2 79 6 3 59 66 7 2 76 6 3 68 7 2 6 3 46 56 78 68 2 2 1 1 47 57 2 2 1 1 44 2 2 1 1 48 67 7 2 77 6 3 64 7 2 74 6 3 2 1 2 1 :} :} :} :} :J LO-C[[[I]J:Il:J C b7 +- bO LO(J . Arithmetic Shift Right.t: Operand . A Decrement Exclusive OR Increment Load Acmltr Or. HD88BOO----------------------------------------Table 4 Accumulator and Memory Operations Addressing Modes ()peretion Add Add Acmltrs Add with Carrv And Bit Test Clear Compere Compere Acmltr. Msp -.Msp.HD8800. 350 • t t t t t • R R R . 1'. M OO--A 00-. 2'.B A-M B-M A-B ~--M 3 3 5 H A8 5 2 BS 4 3 EB 5 2 FB 4 3 lB Booleanl Arithmetic Operation bO C O.# OP-# OP.Zero V Overflow.a::rihro-o bOC b7 <D® l <D® t t t t t t t t t t t t t t t t t t t t @ @ • @ • @ • R R ® ® ® • R R R R t t ® t t ® l t ® t ® t t t ® ~ t t ® t t ® ® ® ® t t ® t t ® t ® • R R ® @ R A-. Arithmetic Shift Right.# OP-# OP. Code Reg. Msp -> B 4C 5C 8A 2 2 9A 3 2 AA 5 2 CA 2 2 DA 3 2 EA 5 2 A '+ M-. Complement. INegatel Decimal Adjust. clearad otherwise Transfer Into Z Zero Ibvtel • Not Affectad o Bit . Logic Store Acmltr Subtract Subtract Acmltrs Subtr with Carrv Transfer Acmltrs Test Zero or Minus Mnemonic ADDA ADDB ABA ADCA ADCB ANDA ANDB BITA BITB CLR CLRA CLRB CMPA CMPB CBA COM COMA COMB NEG NEGA NEGB DAA DEC DECA DECB EORA EORB INC INCA INCB LDAA LDAB ORAA ORAB PSHA PSHB PULA PULB ROL ROLA ROLB ROR RORA RORB ASL AS LA ASLB ASR ASRA ASRB LSR LSRA LSRB STAA STAB SUBA SUBB SBA SBCA SBCB TA8 TBA TST TSTA iSiS LEGEND: OP Operation Code IHexadecimall Number of MPU Cvcles # Number of Program Bvtes + Arithmetic Plus Arithmetic Minus 800lean AND Msp Contents of memory location pointad to be Stack Pointer Cond.01111111 prior to execution? @ IBit VI Test: Set equal to result of N<!)C after shift has occurred. Binarv Add of BCD Characters into BCD Format M-l--M 1 A-l--A 1 B-l--B A(!)M--A B(!)M--B M+l--M 1 A+l--A 1 B+l--B M--A M--B A+M--A B+M--B 1 A-.SP 1 SP + 1 -.SP. I 3 2 1 0 N Z V C t l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l R S l R S l R S l <D® l "1 l l l l l l l l R R R R R S R R R S R R R S R R 36 37 32 33 3 4 ·· ·· ····· ·· ···· ·· ·· ···· ····· ····· ····• * ··· ··· ** * * ··· ··· ** · ···· ···· * ··· ····· ····· · · · ····· ···· ···· ··· ··· ··· ··· ··· ··· ** ** ····· ····· *** ** *** ** * ····· ···· ** *** ·· ·· * * ·* ···· ··· * ** ···· ····· * · · ··· ·· l l l l l 1 JI:--A 1 IJ--B oo-M--M 1 oo-A--A 1 oo-B--B 1 Convert. Complement. SP .A 1 SP + 1 -.Msp.SP -l--SP 1 B -. 1JiiiiII):J C b7 00- C bO mmm-o bO b7 ~-o b7 .. CONDITION CODE REGISTER NOTES: IBit set if test is true and clearad otherwise) <D IBit VI Test: Result = lOOOOOOO? ® IBit CI Test: Result" OOOOOOOO? @ IBit CI Test: Decimal value of most significant BCD Character greater than nine? INot cleared if previouslV set..M t R B--M R t 80 2 A-M->A t CO 2 B-M--B t t t 10 2 1 A-B--A t t t 82 2 2 92 3 2 A2 5 2 B2 4 3 A-M-C--A t t C2 2 2 02 3 2 E2 5 2 F2 4 3 8-M-C--8 t t t 16 2 1 A--B t t R 17 2 1 B--A t t R M -00 60 7 2 70 6 3 t t R 40 2 1 A-oo t t R 50 2 1 B -00 t t R CONDITION CODE SVMBOLS: Boolean Inclusive OR H Half-carrv from bit 3 R Reset Alwavs Boolean Exclusive OR I Interrupt mask S Set Alwavs Complement of M N Negative Isign bitl t Test and set if true. Inclusive Push Data Pull Data Rotate Left Rotate Right Shift Left.1 @ IBit VI Test: Operand a 10000000 prior to execution? @ IBit VI Te. 2's complement 00 Bvte· Zero C CarrV from bit 7 54 97 4 2 A7 07 4 2 E7 2 90 3 2 AO 2 DO 3 2 EO 6 6 5 5 2 B7 2 F7 2 BO 2 FO 5 3 5 3 4 3 4 3 INotel Accumulator addressing mode instructions are includad in the column for IMPLI ED addressing. HD88AOO. IMMED DIRECT INDEX EXTND IMPLIED OP.1 -.

The H06800 MPU instruction set and interrupt structure allow extensive use of the stack concept for efficient handling of data movement. The "stack" can be thought of as a sequential list of data stored in the MPU's read/write memory. Execution of the Branch to Subroutine (BSR) and Jump to Subroutine (JSR) instructions cause a return address to be save on the stack as shown in Figs.(M+ll 1 X-1-+X 1 SP -1 -+ SP 1 X+l-+X 1 SP + 1 -+ SP M -+ X H . The code required for BSR or JSR may be either two Qr three bytes. LOS). 26. the return address is the memory location following the bytes of code that correspond to the BSR and JSR instruction. the Program Counter is automatically incremented the correct number of times to be pointing at the location of the next instruction. 24. Program Control operation can be subdivided into two categories: (I) Index Register/Stack Pointer instructions: (2) Jump and Branch operations_ • Index Register/Stack Pointer Operations The instructions for direct operation on the MPU's Index Register and Stack Pointer are summarized in Table 5. in the example. The instructions can be used to establish one or more "stacks" anywhere in read/ write memory. HD68BOO • PROGRAM CONTROL OPERATIONS this example) to be stored in memory at the location indicated by the Stack Pointer. 1A is still in location (m+ 1) following execution of PULA. XL -+ (M + 1) SP H -+ M. A subsequent PUSH instruction would overwrite than location with the new "pushed" data.(M). causes the return address to be retrieved and loaded into the Program Counter as shown in Fig. Operation of the Stack Pointer with the Push and Pull instructions is illustrated in Figs. 25. MPU status is restored by the Return from interrupt. INS). (XL) . The TSX instruction causes the Index Register to be loaded with the address of the last data byte put onto the "stack". The Compare instruction. (M+l) -+ XL M -+ SP H . The Stack Pointer contains a 16-bit memory address that is used to access the list from one end on a last-in-first-out (LIFO) basis in contrast to the random access mode used by the MPU's other addressing modes. CPX. The stack is decremented after each byte of the return address is pushed onto the stack. This causes the next byte to be pulled from the "stack" to come from the location indicated by the Index Register. The Return from Subroutine instruction. and store (STX. can be used to compare the Index Register to a 16-bit value and update the Condition Code Register accordingly.1 -+ SP 1 SP + 1 -+ X • • • • • • • • • • • ® • CD t • t • • = 1? ® (Bit V) Test: 2's complement overflow from subtraction of ms bytes? @ (Bit N) Test: Result less than zero? (Bit 15 Boolean! Arithmetic Operation • • · • • • · • • • • t • • • • • @@ t RR t • @@ t RR • t • • • • • • • • · • • • • • • · . The utility of these two instructions can be clarified by describing the "stack" concept relative to the HMCS 6800 system. The Stack Pointer is automatically incremented by one just prior to the data transfer so that it will point to the last byte stacked rather than the next empty location. in~rement (INX. as shown in Fig. STS) instructions are provided for both. subroutines and interrupts.-------------------------------------------HD6800. HD68AOO. SP L -+ (M + 1) 1 X . RTI. 19 and 20. For both of the these instructions. DES). (M+1) -+ SP L X H -+ M. The Stack Pointer is automatically decremented by one following the storage operation and is "pointing" to the next empty stack location. load (LOX. EXTND OP - # OP - # OP - # OP - # 8C 3 3 9C 4 2 AC 6 2 BC 5 3 3 3 3 3 DE 9E OF 9F 4 4 5 5 2 2 2 2 EE AE EF AF 6 2 6 2 7 2 7 2 FE BE FF BF 5 5 6 6 OP 09 34 08 31 I CE 8E IMPLIED 4 4 4 4 3 3 3 3 35 30 (Bit N) Test: Sign bit of most significant (MS) byte of result 4 4 = 1) 351 2 1 0 5 4 3 # H I N Z V C (XH) . The TXS instruction loads the Stack Pointer with a value equal to one less than the current contents of the Index Register. 21 through 23. The Pull instruction (pULA or PULB) causes the last byte stacked to be loaded into the appropriate accumulator. There are several operations that cause the status of the MPU to be saved on the stack. Note that the PULL instruction does not "remove" the data from memory. Decrement (DEX. RTS. The Software Interrupt (SWI) and Wait for Interrupt (WAI) instructions as well as the maskable (IRQ) and non-maskable (NMI) hardware interrupts all cause the MPU's internal registers (except for the Stack Pointer itself) to be stacked as shown in Fig. Before it is stacked. depending on whether the JSR is in the indexed (two bytes) or the extended (three bytes) addressing mode. Stack length is limited only by the amount of memory that is made available. The Push instruction (PSHA) causes the contents of the indicated accumulator (A in Table 5 Index Register and Stack Pointer Instructions Addressing Modes Operation Mnemonic Compare Index Reg Decrement Index Reg Decrement Stack Pntr Increment Index Reg Increment Stack Pntr Load Index Reg Load Stack Pntr Store Index Reg Store Stack Pntr Index Reg -+ Stack Pntr Stack Pntr -+ Index Reg CPX DEX DES INX INS' LOX LOS STX STS TXS TSX CD IMMED DIRECT INDEX Condo Code Reg.

. { Stacked Data 0 7F m+2 63 m+3 FD m New Data !!! III Previously Stacked Data { F3 m+1 7F m+2 63 m+3 FD PC----PC----(a) Before PSHA (b) After PSHA Figure 19 Stack Operation (Push Instruction) ACCA o ACCA m-2 m-2 m-1 m-1 t m SP-m I Previously Stacked Data m+1 SP-m+1 1A m+2 m+2 3C Previously Stacked Data { m+3 m+3 PC-------<.O""V m+1 ..... m-1 SP-m-1 :::J SP In • m ~.. HD68AOO. (b) Before PU LA Figure 20 Stack Operation (Pull Instruction) 352 After PULA .- PULA PC- (a) Next Instr. HD68BOO----------------------------------------MPU MPU ACCA [ill ACCA m-2 m-2 . 05 EC_ _.HD6800.

n+3 Next Main Instr. Addr.-------------------------------------------HD6800. n+1 SH = Subr. Addr. ~ *K = Signed 7·Bit Value PC--(n+2) ± K (a) Before Execution (b) After Execution Figure 21 Program Flow for BSR m-2 ---- m-3 SP--m-2 m-1 m-1 sP-m (n+3)H m (n+3)L m+1 7E m+1 7E m+2 7A m+2 7A -pc--.n - 70 JSR = BO n n+1 SH = Subr. HD68BOO m-2 SP-m-2 m-1 m-1 (n+2)H SP---m m (n+2)L m+1 7E PC-------n - 7E m+1 7A r---- BSR n+1 ±K* BSR = Offset Next Main Instr. n+2 n+1 ±K* = Offset n+2 Next Main Instr. PC---S (5 formed from SH and SL) (b) After Execution (a) Before Execution Figure 22 Program Flow for JSR (Extended) 353 . JSR Addr. n+2 SL = Subr. = Subr. n+2 SL Addr. HD68AOO. n+3 Next Main Instr.

Addr. n+2 SL = Subr. n+2 SL = Subr. Last Subr. HD68AOO. HD68BOO----------------------------------------- m-2 SP--m-2 m-1 m-1 (n+2)H m (n+2)L SP-m m+1 7E m+1 7E 7A 7A ~ Pc-n JSR = AD n+1 K* n+2 = Offset n+1 Next Main Instr. Addr. Addr.HD6800. n+1 SH = Subr. PC-Sn RTS (b) After Execution (a) Before Execution Figure 24 Program Flow for RTS 354 . *K = 8·Bit Unsigned Value n+2 PC-X** + K 1st Subr. Next Main Instr. Instr. * *Contents of Index Register (b) After Execution (a) Before Execution Figure 23 Program Flow for JSR (Indexed) SP-m-2 m-2 m-1 (n+3)H m-1 m (n+3)L SP----m m+1 7E m+1 -- 7A JSR --- (n+3)H (n+3)L --7E 7A = BD JSR = BD n+1 SH = Subr. Addr. Instr.

HD68AOO.-------------------------------------------HD6800. HD68BOO Wait for Interrupt Main Program Software Interrupt Main Program Hardware Interrupt or Non-Maskable Interrupt (NMI) Main Program n+1 Yes Stack SP--. Mem. MS Non·Maskable Int. B m-4 Acmltr. LS Restart MS FFFF Restart FFFD (NOTE) LS c:::::> First Instr. Addr. Formed By Fetching 2-Bytes From Per. LS MS = Most Significant Address Byte LS = Least Significant Address Byte Figure 25 Program Flow for Interrupts 355 NMI .m-7 c:::::> m-6 Condition Code m-5 Acmltr.A m-3 Index Register (X H ) Index Register (XL) m-2 SWI m-1 PC(n+1 )H m PC(n+llL WAI HDWR INT No FFF8 FFF9 Interrupt Memory Assignment FFF8 Hardware Int. MS FFF9 FFFA Hardware Int. Software MS FFFB Software LS FFFC FFFE Non·Maskable Int. Assign.

RTI. Inst. Note that the Program Counter is properly in- cremented to be pointing at the correct return address before it is stacked. NOP. The BSR instruction requires less opcode than JSR (2 bytes versus 3 bytes) and also executes one cycle faster than JSR. that is. it stacks the MPU contents and then waits for the interrupt to occur. Last Inter. The opcode for the BRA instruction requires one less byte than lMP (extended) but takes one more cycle to execute. it adds the offset to the value in the Index Register and uses the result as the address of the next instruction to be executed. Note that as in the case of the subroutine instructions. 26) is used at the end of an interrupt routine to restore control to the main program. The Branch Always (BRA) instruction is similar to the JMP (extended) instruction except that the relative addressing mode applies and the branch is limited to the range within -125 or + 127 bytes of the branch instruction itself. Its only effect is to increment the Program Counter by one. SWI. It is also used for equalizing the execution time through alternate paths' in a control program. the address of the next instruction to be executed is fetched from the two locations immediately following the JMP instruction. Execution of the Jump Instruction.:. 356 . When the MPU encounters the Jump (Index) instruction. affects program flow as shown in Fig. is a jump operation in a very limited sense. The No Operation instruction. it can be used to stop operation and put the MPU registers in memory where they can be examined. Operation of the Branch to Subroutine and Jump to Subroutine (extended) instruction is similar except for the range. RTS. 25. HD68AOO.HD6800.. HD68BOO------------------------------------------- SP-m-7 m-7 m-6 CCR m-6 CCR m-5 ACCB m-5 ACCB m-4 ACCA m-4 ACCA m-3 XH (Index Reg) m-3 XH m-2 XL (Index Reg) m-2 XL m-1 PC(n+1 )H m-1 PCH m PC(n+1)L SP---m PCL . and their relationship to the hardware interrupts is shown in Fig. BRA. 24. effectively removing the stacking time from a hardware interrupt sequence. The effect of executing the Software Interrupt.n+1 ~ PC-n+1 Next Main Instr. the Program Counter is incremented to point at the correct return address before being stacked. The SWI instruction is useful for inserting break points in the control program. It is useful during program development as a "stand-in" for some other instruction that is to be determined during debug. 27. SWI causes the MPU contents to be stacked and then fetches the starting address of the interrupt routine from the memory locations that respond to the addresses FFF A and FFFB. while included here.----. - Next Main Instr.2. Pc---Sn RTI (a) Before Execution (b) After Execution Figure 26 Program Flow for RTI • Jump and Branch Operation The Jump and Branch instructions are summarized in Table 6. 21 through 23. is used at the end of a subroutine to return to the main program as indicated in Fig. The Return from Interrupt instruction. (Fig. and Branch Always. The effect on program flow for the Jump to Subroutine (JSR) and Branch to Subroutine (BSR) is shown in Figs. These instructions are used to control the transfer of operation from one point to another in the control program. The Return from Subroutine. In the extended addressing mode. WAI. JMP. The WAI instruction is used to decrease the time required to service a hardware interrupt. and the Wait for Interrupt.

Four of the pairs are used for simple tests of status bits N. N + V=O.-------------------------------------------HD6800. V= 1 . Branch On Equal (BEQ) and Branch On Not Equal (BNE) are used to test the zero status bit.I-• S• • • ® • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • ~r • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • I-. BlT BGE N~ V= 1. 357 . 28. Z=O. 2.I-• • • • • • l Load Condition Code Register from Stack. HD68BOO Table 6 JUMP/BRANCH Instruction Cond. BHI BlS C+Z=O. N. C+Z= 1. Z. Code Reg. V. PC PC Main Program 6E = JMP {" K = Offset n+1 INDXD INDEX RELATIVE Mnemonic EXTND Next Instruction X+K {" Main Program n+1 KH = Next Address n+2 K L = Next Address K Main Program 7E = JMP ·· 20= BRA n+1 (n+2) ± K K* = Offset I Next Instruction INext Instruction *K = Signed 7-bit value (b) 8ranch (a) Jump Figure 27 Program Flow for JUMP/BRANCH Instructions BMI BPl N= 1. Z + (N C±> V) = 0 . BEQ BNE Z=1. These two instructions are useful following a Compare (CMP) instruction to test for equality between an accumulator and the operand. Figure 28 Conditional Branch Instructions The conditional branch instructions. Addressing Modes Operation Branch Always Branch If Carry Clear Branch If Carry Set Branch If = Zero Branch If ~ Zero Branch If> Zero Branch If Higher Branch If ~ Zero Branch I f lower Or Same Branch If < Zero Branch If Minus Branch If Not Equal Zero Branch If Overflow Clear Branch If Overflow Set Branch If Plus Branch To Subroutine Jump Jump To Subroutine No Operation Return From Interrupt Return From Subroutine Software Interrupt Wait for Interrupt BAA BCC BCS BEQ BGE BGT BHI BlE BlS BlT BMI BNE BVC BVS BPl BSR JMP JSR NOP RTI RTS SWI WAI CD (Alii ® (Bit I) OP - # 20 24 25 27 2C 2E 22 2F 23 2D 2B 26 28 29 2A 8D 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 8 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 OP - IMPLIED EXTND # OP - # OP - Branch Test # 2 2 7E 3 BD 9 3 3 01 2 1 3B 10 1 39 5 1 3F 12 1 3E 9 1 4 3 2 1 0 H I N Z V C • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • None C=O C=1 Z=1 N(±)V=O Z + (N@ V) = 0 C+Z=O Z + (N @ V) = 1 C+Z=1 N <±>V=1 N=1 z=o v=o V =1 N=O 6E 4 AD 8 5 Advances Prog Cntr Only • • • • • • • • • • • • . (See Special Operations) Set when interrupt occurs.and C: 1. They are used to test the results of the preceding operation and either continue with the next instruction in sequence (test fails) or cause a branch to another point in the program (test succeeds). C= 1 . If previously set. a Non-Maskable interrupt is required to exit the wait state. They are also used following the Bit Test (BIT) to determine whether or not the same bit positions are set in an accumulator and the operand. HD68AOO. BCC BCS C= 0. to determine whether or not the result of the previous operation was equal to "0". respectively. to determine if the previous result was negative or positive. Branch on Minus (BMI) and Branch On Plus (BPL) tests the sign bit. consists of seven pairs of complementary instructions. BlE BGT : : Z + (N C±> V) = 1 . N = 0. BVC BVS V=O. Fig. Z.

BCS will cause a branch if the accumulator value is lower than the operand. cleared by CLI instruction. cleared otherwise. the complement to BLT. The Fifth complementary pair. The action of BLE is identical to that for BLT except that a branch will also occur if the result of the previous result was "0". This larger number of instructions results from the fact that many of the executive instructions have more than one addressing mode. (Normally not used in arithmetic operations. cleared if no b3 to b4 carry. respectively. Conversely. Branch On Carry Clear (BCC) and Branch On Carry Set (BCS) tests the state of the C bit to determine if the previous operation caused a carry to occur. depending on where it is encountered in the control program. Branch On Less Than Or Equal Zero (BLE) and Branch On Greater Than Zero (BGT) test the status bits for Z Ef) (N + V) = "1" and Z E£> (N + V) = "0". BGT is similar to BGE except that no branch will occur following a "0" result. if used following a CMP. The bits are defined in Fig. cleared otherwise. set if result V C = Carry. Branch On Higher (BHI) and Branch On Lower or Same (BLS) are in a sense complements to BCe and BCS. = "0". The instructions shown in Table 7 are available to the user for direct manipulation of the CCR. 29. HD88AOO. Z = = Zero. In addition. HD68BOO-----------------------------------------3. BLT will always cause a branch following an opeiation in which two negative numbers were added. Conversely. set if there was a carry from the most significant bit (b7) of the result. Table 7 Condition Code Register Instructions Operations Clear Carry Clear Interrupt Mask Clear Overflow Set Carry Set Interrupt Mask Set Overflow Acmltr A -+ CCR CCR -+ Acmltr A Mnemonic CLC CLI CLV SEC SEI SEV TAP TPA Add ressmg Mode IMPLIED OP - OC OE OA 00 OF OB 06 07 2 2 2 2 2 2 2 2 Cond. 5 4 3 2 1 H I N Z V C 0-+ C 0-+ I 0-+ V 1 -+ C 1-+ I 1 ~ V A ~CCR • • • • • • • R • • S • • • • • • • • • • • • • • R R • CCR-+ A •I•I• Boolean Operation # 1 1 1 1 1 1 1 1 R = Reset S = Set • = Not affected CD (ALL) Set according to the contents of Accumulator A. In addition. Code Reg. The HD6800 MPU has 72 unique instructions. 4. the orientation is higher or lower. it will cause a branch following a CMP in which the value in the accumulator was negative and the operand was positive. cleared otherwise. BCC following a comparison (CMP) will cause a branch if the (unsigned) value in the accumulator is higher than or the same as the value of the operand. Systems which require an interrupt window to be opened under program control should use a CLI-NOP-SEI sequence rather than CLI-SEI. The last pair. BCC and BCS are useful for testing relative magnitude when the values being tested are regarded as unsigned binary numbers. • CONDITION CODE REGISTER OPERATIONS The Condition Code Register (CCR) is a 6-bit register within the MPU that is useful in controlling program flow during system operation. will cause a branch following operations in which two positive values were added or in which the result was "0". Branch On Overflow Clear (BVC) and Branch On Overflow Set (BVS) tests the state of the V bit to determine if the previous operation caused an arithmetic overflow. it recognizes and takes action on 197 of the 256 possibilities that can occur using an 8-bit word length. not affected by other instructions. Interrupt Mask. b5 b4 H H = b3 b2 bl bO N Z v C Half-carry. BLS will cause a branch if the unsigned binary value in the accumulator is lower than or the same as the operand. The remaining two pairs are useful in testing results of operations in which the values are regarded as signed two's complement numbers. Figure 29 Condition Code Register Bit Definition • ADDRESSING MODES The MPU operates on 8-bit binary numbers presented to it via the Data Bus. ABA. Branch On Less Than Zero (BLT) and Branch On Greater Than Or Equal Zero (BGE) test the status bits for NEf)V = "I" and N E£> V = "0". the MPU automatically sets or clears the appropriate status bits as many of the other instructions on the condition code register was indicated as they were introduced. BLT will never cause a branch following a CMP in which the accumulator value was positive and the operand negative. This differs from the unsigned binary case in the following sense: In unsigned.HD8800. ADC. however. it will cause a branch if the value in the accumulator is higher than the operand. set if there was arithmetic overflow as a result of the operation. the comparison is between larger or smaller where the range of values is between -128 and +127 . BHI tests for both C and Z = "0". respectively. A given number (byte) may represent either data or an instruction to be executed. the values are in the range "00" (lowest) of "FF" (highest). set whenever a carry from b3 to b4 of the result is generated by ADD. Conversely.) Restored to a "0" as a result of an RTI instruction if 1M stored on the stacked i~ "0" N = Negative. in signed two's complement. cleared otherwise. 358 CD 0 • • • • S S ·• I•I•I• . BGE. set by hardware of software interrupt or SEI instruction. set if high order bit (b7) of result is set. Overflow. that is.

X n+2 Next Instr. • • • • (K = One-Byte Operand) Z • FO Instruction Example: CMPA Z & 256~65535 • • K = Operand (n+2)±K & If Branch Test False. and Extended modes may all be used with the ADD instruction. X n+1 Z = Offset Addr. Indexed. the Assembler selects the Direct mode if the operand value is in the range 0-255 and Extended otherwise. Range: n+2 ZL = Operand Address n+3 Next Instr. Range: -125 to +129 Relative to n. Range = 0~255 & n+1 Z = Operand Address n+2 (K = Two·Byte Operand) Z Instruction n Immediate: Example: LDAA #K (K = One·Byte Operand) Next Instr. Z KH = Operand Z+1 KL = Operand Instruction Relative: ill IfIf ZZ ~> 255... LDX and LDS) Instruction n n+1 KH = Operand K = Operand n+2 KL = Operand OR n+3 Next Instr. 9B.. the Immediate mode is selected by the DO Instruction Direct: Example: SUBB Z Addr. the mnemonic instruction itself is enough for the Assembler to determine addressing mode.ffi If Branch Test True. For instance. For the instructions that use both Direct and Extended modes. The addressing modes are summarized in Fig. n+1 K = Operand n+2 Next Inst. Selection of the desired addressing mode is made by the user as the source statements are written. HD88AOO. Range: 0~255 Relative to Index Register. therefore. If manual translation is used. &. Next Instr.. Similarly. There are a number of instructions for which the Extended mode is valid but the Direct is not. Translation into appropriate opcode then depends on the method used. or BB. 30. 1_ _ .. The programmer must have a method for addressing the MPU's internal registers and all of the external memory locations. the Assembler a utomatically selects the Extended mode even if the operand is in the 0-255 range.-------------------------------------------HD8800. Extended: n n+1 ZH = Operand Address Addr. For example. the addressing mode is inherent in the opcode.& • Addr. Indexed: • • OR (K = Two-Byte Operand) Z KH = Operand Z+1 KL = Operand • • (Z = 8-Bit Unsigned Value) Figure 30 Addressing Mode Summary X+Z K_=_o_p_e_r_an_d_ _. Direct. respectively. The source statement format includes adequate information for the selection if an assembler program is used to generate the opcode. the Immediate. Extended Mode is selected Example: BNE K n+1 (K = Signed 7-Bit Value) n+2 ± K = Branch Offset Next Instr. HD88BOO These addressing modes refer to the manner in which the program causes the MPU to obtain its instructions and data. • • • • (K = One-Byte Operand) Assembler whenever it encounters the "#" symbol in the operand field. The proper mode is determined by selecting (hexidecimal notation) 8B. OR (K = Two·Byte Operand) (CPX.I L . For these instructions. an "X" in the operand field causes the Indexed mode to be selected. n Instruction Example: ADD A Z. AB. Assembler Select Direct Mode 255. Only the Relative mode applies to the branch instructions.

Operator ADDA or ADDB Operand MPU MPU Inherent (Includes" Accumulator Addressing" Mode) RAM RAM Comment MEM12 MEM12 ADD CONTENTS OF MEM12 TO ACCA ADD CONTENTS OF MEM12 TO ACCB PC = 5001 j---. In these figures. INDEX 199. the instruction ABA causes the MPU to add the contents of accumulators A and B together and place the result in accumulator A. require 16-bit values. The immediate mode is selected by preceding the operand value with the "#' symbol. another example of "accumulator addressing"."". Load Index Register (LOX). The operand format allows either properly defmed symbols or numerical values. HD68AOO.. increment the Index Register. Cycle-by-cycle operation of the inherent mode is shown in Table 8. Program flow for instructions of this type is illustrated in Figures 31 and 32. Since Compare Index Register (CPX). TST. For instance. An exception to this rule occurs for instructions that use dual addressing in the operand field and for instructions that must distinguish between the two accumulators. resulting in apparent four character mnemonics for those instructions. INX.20 RAM PC PC = 5000 1--". Except for the instructions CPX. the immediate mode for these three instructions requie two-byte operands. A and B are "operands" but the space between them and the operator may be omitted."--1" General Flow PC RAM RAM Program Memory Program Memory I--~~-t/ General Flow Example PC = 5002 I--'~~~/ Example Figure 33 Immediate Addressing Mode Figure 31 Inherent Addressing 360 . provides an example of dual addressing in the operand fields.. The addition instruction.HD6800. LOX. the operand may be any value in the range 0 '" 255."'-I' The example used earlier for the test instruction. HD68BOO----------------------------------------• AceB ~ The successive fields in a statement are normally separated by one or more spaces. also applies to the accumulators and uses the "accumulator addressing mode" to designate which of the two accumulators is being tested: Example General Flow Figure 32 Accumulator Addressing Operator TSTB or TSTA Comment TEST CONTENTS OF ACCB TEST CONTENTS OF ACCA A number of the instructions either alone or together with an accumulator operand contain all of the address information that is required. itself. Table 9 shows the cycle-by-cycle operation for the immediate addressing mode. the operand is the value that is to be operated on... For instance.:~:"'. causes the contents of the Index Register to be increased by one. no further address reference is required.. Numerical examples are in decimal notation. the general case is shown on the left and a specific example is shown on the right. the instruction Operator Operand LDAA #25 Comment LOAD 25 INTO ACCA causes the MPU to "immediately load accumulator A with the value 25". Load Stack Pointer (LOS). causes the contents of accumulator B to be increased by one. 33. "inherent" in the instruction. MPU MPU • I mmediate Addressing Mode In the Immediate addressing mode. In these cases. The instruction INCB.:. This is commonly done. that is. Similarly. and LOS. Instructions of this type require only one byte of opcode. ADO. Program flow for this addressing mode is illustrated in Fig.

-. VMA Line # R/W Address Bus Data Bus Line Op Code Address II Op Code Address + 1 2 Op Code Op Code of Next Instruction I I I -+-_.-.- Op Code Address Op Code Address + 1 Index Register New Stack Pointer 9 2 10 . +--...---_.- ..--. 1 o o o o o o o Op Code Irrelevant Data (NOTE 2) Irrelevant Data (NOTE 1) Contents of Condo Code Register from Stack Contents of Accumulator B from Stack Contents of Accumulator A from Stack Index Register from Stack (High Order Byte) Index Register from Stack (Low Order Byte) Next Instruction Address from Stack (High Order Byte) Next Instruction Address from Stack (Low Order Byte) Op Code Irrelevant Data (NOTE 1) Return Address (Low Order Byte) Return Address (High Order Byte) Index Register (Low Order Byte) Index Register (High Order Byte) Contents of Accumulator A Contents of Accumulator B Contents of Condo Code Register Irrelevant Data (NOTE 1) Address of Subroutine (High Order Byte) Address of Subroutine (Low Order Byte) If deVice which IS addressed dUring thiS cycle uses VMA.2 Stack Pointer . -..1 TSX 3 4 ··----r-·· ··--·1-·· 1 2 3 4 RTS 1 2 3 5 4 5 -... Op Code Address Op Code Address + 1 Previous Register Contents ! 1 Op Code Address + 1 1 1 1 1 1 1 1 0 1 1 Stack Pointer Stack Pointer Stack Pointer Stack Pointer Stack Pointer Stack Pointer Stack Pointer Stack Pointer Vector Address Vector Address ----t·· 1 1 2 3 4 5 6 7 FFFA (Hex) FFFB (Hex) NOTE 1. While ~e MPU is waiting for the interrupt. HD68BOO Table 8 Inherent Mode Cycle by Cycle Operation Address Mode and Instructions ABA ASL ASR CBA CLC CLI CLR CLV COM DAA DEC INC LSR NEG NOP ROL ROR SBA Cycle Cycle SEC SEI SEV TAB TAP TBA TPA TST ._C_o_n__t_e_nt_s.':.s·----- 12 -. Bus Available will go "High" indicating the following states of the control lines: VMA is "Low"..... Data is ignored by the MPU. -.__N. then the Data Bus Will go to the high Impedance three-state condition. 361 ..-.--l__ lrr~l_evant ~-0 +_..5 Stack Pointer . _ ..... _________ ~---+i PSH 4 1 1 ~ ~ __4__ PUL 1 1 1 Op Code Address Op Code Address + 1 Stack Pointer Stack Pointer . __ ...... -- Op Code Address Op Code Address + 1 Stack Pointer Stack Pointer .- Code Code of Next Instruction Irrelevant Data Irrelevant Data 1 1 0 1 1 Code Address Code Address + 1 Stack Pointer Stack Pointer + 1 Stack Pointer + 2 1 1 1 1 1 Op Code Irrelevant Data (NOTE 2) Irrelevant Data (NOTE 1) Address of Next Instruction (High Order Byte) Address of Next Instruction (Low Order Byte) 1 1 0 0 0 Op Code Op Code of Next Instruction Return Address (Low Order Byte) Return Address (High Order Byte) Index Register (Low Order Byte) Index Register (High Order Byte) Contents of Accumulator A Contents of Accumulator B Contents of Condo Code Register 1~ 1 1 1 .. .- 1 1 0 0 1 1 1 1 1 3 4 5 9 o Data (NOTE 1) Op Code Op Code of Next Instruction Accumulator Data i .-----.._-----_._w__ 1 2 3 4 .- _- DES ~NESX 4 __I_N_X ____..-. data from the previous cycle may be retained on the Data Bus.__.---....------------- o~ 1 ------+.. HD68AOO.. NOTE 3._ . - 1 2 i 1 o 4 Op Code Op Code of Next Instruction Irrelevant Data (NOTE 1) 1 1 1 1 1 1 2 TXS I Op Code Address Op Code Address + 1 Stack Pointer Stack Pointer + 1 0 4 4 1 1 -.··--t. RTI II ._.1 Stack Pointer .-----_.. Address Bus..----+------...~..-Ad·dre.3 Stack Pointer .--------------------~ o 1 1 1 1 1 1 5 6 7 8 9 Stack Pointer + 7 10 2 3 4 5 6 7 8 9 10 11 12 1 1 1 1 1 1 1 1 1 Op Code Address Op Code Address + 1 Stack Pointer Stack Pointer + 1 Stack Pointer + 2 Stack Pointer + 3 Stack Pointer + 4 Stack Pointer + 5 Stack Pointer + 6 -·-1--1~---O~-c~d. --.....-------------------·--t· 1 4 I 1 1 R_eg_i_st_e_r.._ ..6 (NOTE 3) .4 Stack Pointer ..... and Data Bus are all in the high impedance state'._.-.----. _. NOTE 2.R/W.. _ ...Dat~ ____...- 1 1 1 1 1 3 4 SWI --.I··· ..._.. _________ i 1 Op Code Op Code of Next Instruction Irrelevant Data (NOTE 1) Operand Data from Stack 1 1 0 0 Op Code Address Op Code Address + 1 Stack Pointer New Index Register 1 1 1 1 I Op Code Op Code of Next Instruction Irrelevant Data (NOTE 1) Irrelevant Data (NOTE 1) 6 7 8 --_._e... Depending on bus capacitance._ .------------------------------------------HD6800.._.------. __ .+ . WAI Accum~a~.._+___1 .

since only one address byte is required. In most applications. that is. the direct addressing range. memory locations 0 "" 255. Fig. data from the previous cycle may be retained on the Data Bus. HD88BOO---------------------------------------Table 9 Immediate Mode Cycle by Cycle Operation Address Mode and Instructions ADC ADD AND BIT CMP EOR LOA ORA SBC SUB CPX LOS LOX • Cycle Cycle #" VMA Line Address Bus R/W Line Data Bus 1 2 1 1 Op Code Address Op Code Address + 1 1 1 Op Code Operand Data 1 2 3 1 1 1 Op Code Address Op Code Address + 1 Op Code Address + 2 1 1 1 Op Code Operand Data (High Order Byte) Operand Data (Low Order Byte) 2 3 Direct and Extended Addressing Modes In the Direct and Extended modes of addressing.ycle operations of this mode. It then sets the program counter equal to the value found there (l00 in the example) and fetches the operand. The Direct and Extended modes differ only in the range of memory locations to which they can direct the MPU. are reserved for RAM. HD88AOO. They are used for data buffering and temporary storage of system variables. Direct addressing. the area in which faster addressing is of most value. after encountering the opcode for the instrution LOAA (Direct) at memory location 5004 (program Counter = 5(04). can address only memory locations 0 "" 255. it is a method of reaching anyplace in memory. Extended addressing. provides a faster method of processing data and generates fewer bytes of control code. Depending on bus capacitance. Table 10 Direct Mode Cycle by Cycle Operation Address Mode and Instructions ADC ADD AND BIT CMP CPX LOS LOX EOR LOA ORA SBC SUB Cycle Cycle # VMA Line 3 1 2 3 1 1 1 Op Code Address Op Code Address + 1 Address of Operand 1 1 1 Op Code Address of Operand Operand Data 1 2 3 4 1 1 1 1 Op Code Address Op Code Address + 1 Address of Operand Operand Address + 1 1 1 1 1 Op Code Address of Operand Operand Data (High Order Byte) Operand Data (Low Order Byte) 4 1 2 3 4 1 1 0 1 Op Code Address Op Code Address + 1 Destination Address Destination Address 1 1 1 0 OpCode Destination Address Irrelevant Data (NOTE 1) Data from Accumulator 1 1 0 1 1 Op Code Address Op Code Address + 1 Address of Operand Address of Operand Address of Operand + 1 1 5 1 2 3 4 5 1 1 0 0 Op Code Address of Operand Irrelevant Data (NOTE 1) Register Data (High Order Byte) Register Data (Low Order Byte) 4 STA STS STX Address Bus RIW Line Data Bus NOTE 1. 256 "" 65535. the operand field of the source statement is the address of the value that is to be operated on. Table 10 shows the cycle-by-<. 34. looks in the next location. If device which is address during this cycle uses VMA. Direct addressing generates a single 8-bit operand and. 5005.ycle operation is shown in Table 11 for Extended Addressing. then the Data Bus will go to the high impedance three-state condition. For instructions requiring a two-byte operand such as LOX (Load the Index Register). hence. enabling the MPU to reach the remaining memory locations. 35. in this case a value to be loaded into accumulator A. a two byte operand is generated for Extended addressing. An example of Direct addressing and its effect on program flow is illustrated in Fig. The MPU. for the address of the operand. Cycle-by-<. Extended addressing can be thOUght of as the "standard" addressing mode.HD8800. from that location. 362 . is similar except that a twobyte address is obtained from locations 5007 and 5008 after the LOAB (Extended) opcode shows up in location 5006. the operand bytes would be retrieved from locations 100 and 101.

_-1. Depending on bus capacitance.. then the Data Bus will go to the high impedance three-state condition. HD68AOO.\ = 5006 I------i 5007 50081-_ _ _1 5009 ADDR ~ 256 General Flow Example Example Figure 35 Extended Addressing Mode Figure 34 Direct Addressing Mode 363 . data from the previous cycle may be retained on the Data Bus.-------------------------------------------HD6800. 2. MPU MPU MPU RAM RAM ADDR = 100 ADDR ADDR Program Memory Program Memory Program Memory PC PC = 5004 5005 PC PC-1 ADDR = 0 ~255 General Flow = 3001--""':".:. For TST. VMA = 0 and Operand data does not change.2 Op Code Address + 2 Op Code Address + 2 STS STX JSR 9 8 9 JMP 3 ADC EOR ADD LOA AND ORA BIT SBC CMP SUB 5 STAA STA B 5 ASL ASR CLR COM DEC INC NOTE 1.1 Stack Pointer . NOTE LSR NEG ROL ROR TST 6 1 1 1 1 0 0 1 1 1 1 0 0 1 1 1 Op Code Address of Operand (High Order Byte) Address of Operand (Low Order Byte) Irrelevant Data (NOTE 1) Operand Data (High Order Byte) Operand Data (Low Order Byte) Op Code Address of Subroutine (High Order Byte) Address of Subroutine (Low Order Byte) Op Code of Next Instruction Return Address (Low Order Byte) Return Address (High Order Byte) I rrelevant Data (NOTE 1) Irrelevant Data (NOTE 1) Address of Subroutine (Low Order Byte) Op Code Address Op Code Address + 1 Op Code Address + 2 1 Op Code Jump Address (High Order Byte) Jump Address (Low Order Byte) 1 1 1 1 Op Code Address Op Code Address + 1 Op Code Address + 2 Address of Operand 1 1 1 1 Op Code Address of Operand (High Order Byte) Address of Operand (Low Order Byte) Operand Data 1 2 3 4 5 1 1 1 1 Op Code Address Op Code Address + 1 Op Code Address + 2 Address of Operand Address of Operand + 1 1 Op Code Address of Operand Address of Operand Operand Data (High Operand Data (Low 1 2 3 4 5 1 2 CPX LOS LOX 1 1 0 0 1 Data Bus Line 1 1 1 2 3 1 4 1 R/W Address Bus 3 4 1 2 3 4 5 6 1 1 1 1 0 1 1 1 1 1 0 1/0 (NOTE 2) Op Code Op Code Op Code Operand Operand 1 1 1 1 1 1 Address Address + 1 Address + 2 Destination Address Destination Address 1 1 1 1 0 1 Op Code Address Op Code Address + 1 Op Code Address + 2 Address of Operand Address of Operand Address of Operand 1 1 1 1 0 (High Order Byte) (Low Order Byte) Order Byte) Order Byte) Op Code Destination Address (High Order Byte) Destination Address (Low Order Byte) Irrelevant Data (NOTE 1) Data from Accumulator Op Code Address of Operand (High Order Byte) Address of Operand (Low Order Byte) Current Operand Data Irrelevant Data (NOTE 1) New Operand Data (NOTE 2) If device which is addressed during this cycle uses VMA. HD68BOO Table 11 Extended Mode Cycle by Cycle Address Mode and Instructions Cycle Cycle # VMA Line 6 1 2 3 4 5 6 1 1 1 0 1 1 Op Code Address Op Code Address + 1 Op Code Address + 2 Address of Operand Address of Operand Address of Operand + 1 1 2 3 4 5 6 7 1 1 1 Op Code Address Op Code Address + 1 Op Code Address + 2 Subroutine Starting Address Stack Pointer Stack Pointer .

the destination of the branch instruction must be within -126 to +129 memory locations of the branch instruction itself. If. the relative address used in execution of branch instructions is a constant numerical value. and return from subroutine (RTS) are used. one for the instruction opcode and one for the "relative" address (see Fig. implemented for the MPU's branch instructions. the MPU continues execution with the next instruction (in location 5010 in Fig. For transferring control beyond this range. it tests the Zero bit in the Condition Code Register. the branch condition is satisfied and the MPU adds the offset. Since it is desirable to be able to branch in either direction. This result in a relative addressing range of ±127 with respect to the location of the branch instruction itself. indicating a non-zero result.------f Next Instr. PC 5010 (PC+2) + (Offset) . If the previous result was zero. Cyc1e-by-cycle operation is shown in Table 12 for relative addressing. In Fig. 1-------1 PC 5025 Figure 36 Relative Addressing Mode 364 . If that bit is "0". the next instruction is located at PC+2. The remaining seven bits represent the numerical value. the unconditional jump (JMP). or (PC+2) -128~ D~ (PC+2) + 127 PC -126 ~ 0 ~ PC + 1 29 that is. 36). specifies a memory location relative to the Program Counter's current location. the 8-bit address byte is interpreted as a signed 7-bit value. "0" =plus and "I" =minus. jump to subroutine (JSR). the branch range is computed with respect to the next instruction that would be executed if the branch conditions are not satisfied. However. the address obtained by the MPU is an absolute numerical address. HD68AOO. the range is then. when the MPU encounters the opcode for BEQ (Branch if result of last instruction was zero). to PC+2 and branches to location 5025 for the next instruction. Branch instructions generate two bytes of machine code. HD68BOO-----------------------------------------• Relative Address Mode In both the Direct and Extended modes. Since two byte are generated. The Relative addressing mode.-. MPU MPU RAM RAM Program Memory Program Memory PC 1---"'. D is defined as the address of the branch destination. the 8th bit of the operand is treated as a sign bit.HD6800. 36). 36.''''--11'' PC 5008 (PC+2) Next Instr. 15 in this case. The branch instructions allow the programmer to efficiently direct the MPU to one point or another in the control program depending on the outcome of test results_ Since the control program is normally in read-only memory and cannot be changed."'''.

the Indexed addressing mode provides a dynamic "on the fly" way to modify program activity. the operand is equivalent to 0. etc. When the MPU encounters the LDAB (Indexed) opcode in location 5006.------------------------------------------HD6800. STAA X. In the operand format.. • The operand field can also contain a numerical value that will be automatically added to X during execution. In the earlier example.. INX. HD68AOO.. Since there are instructions for manipulating X during program execution (LDX.I / Program Memory PC = 5006 OFFSET .. HD68BOO Table 12 Relative Mode Cycle-by-Cycle Operation Address Mode and Instructions BCC BCS BEQ BGE BGT BHI BlE BlS BlT BMI Cycle BNE BPl BRA BVC BVS Cycle # 1 4 BSR 1 1 2 3 4 1 8 VMA line 2 3 4 5 6 7 8 R/W line Address Bus 0 0 Op Code Address Op Code Address Op Code Address Branch Address 1 1 0 1 1 0 0 0 Op Code Address Op Code Address + 1 Return Address of Main Program Stack Pointer Stack Pointer .. MPU MPU RAM RAM ADDR = INDXt--::-:~:---V + OFFSET Program Memory PC t -. Depending on bus capacitance. DEX.1 Stack Pointer . If device which IS addressed dUring thiS cycle uses VMA. the "0" may be omitted when the desired address is equal to X.).2 Return Address of Main Program Subroutine Address +1 +2 Data Bus 1 1 1 1 Op Code Branch Offset Irrelevant Data (NOTE 1) Irrelevant Data (NOTE 1) 1 1 1 0 0 1 1 1 Op Code Branch Offset Irrelevant Data (NOTE 1) Return Address (Low Order Byte) Return Address (High Order Byte) Irrelevant Data (NOTE 1) Irrelevant Data (NOTE 1) Irrelevant Data (NOTE 1) .. Table 13 shows the cycle-by-cycle operation for the Indexed Mode of Addressing_ Indexed Addressing Mode With Indexed addressing the numerical address is variable and depend on the current contents of the Index Register _A source statement such as Operator Operand Comment STAA X PUT A IN INDEXED lOCATION causes the MPU to store the contents of accumulator A in the memory location specified by the contents of the Index Register (recall that the label X is reserved to designate the Index Register)."'.'."--1/ Example Figure 37 Indexed Addressing Mode 365 . X . the offset may be represented by a label or a numerical value in the range 0 '" 255 as in the example. NOTE 1.£ 255 General Flow 1-=.. .. data from the previous cycle may be retained on the Data Bus.. that is. then the Data Bus will go to the high Impedance three-state condition . This format is illustrated in Fig. it looks in the next memory location for the value to be added to X (5 in the example) and calculates the required address by adding 5 to the present Index Register value of 400. 37.

HD88AOO. If Device which IS addressed during this cycle uses VMA.1 Stack Pointer . NOTE 2.HD8800. Depending on bus capacitance.. data from the previous cycle may be retained on the Data Bus. 366 . HD88BOO-----------------------------------------Table 13 Indexed Mode Cycle by Cycle Address Mode and Instructions Cycle JMP 4 Cycle # VMA Line Address Bus R/W Line 1 2 3 1 1 0 0 Op Code Address Op Code Address + 1 Index Register Index Register Plus Offset (w/o Carry) 1 1 1 Op Code Offset Irrelevant Data (NOTE 1) Irrelevant Data (NOTE 1) 1 1 0 0 1 Op Code Address Op Code Address + 1 Index Register Index Register Plus Offset (w/o Carry) Index Register Plus Offset 1 1 1 1 1 Op Code Offset Irrelevant Data (NOTE 1) Irrelevant Data (NOTE 1) Operand Data 1 1 0 0 1 1 Op Code Address Op Code Address + 1 Index Register Index Register Plus Offset (w/o Carry) Index Register Plus Offset Index Register Plus Offset + 1 1 1 1 1 1 1 Op Code Offset Irrelevant Data (NOTE 1) Irrelevant Data (NOTE 1) Operand Data (High Order Byte) Operand Data (Low Order Byte) 1 1 0 0 0 1 Op Code Address Op Code Address + 1 Index Register Index Register Plus Offset (w/o Carry) Index Register Plus Offset Index Register Plus Offset 1 1 1 1 1 0 Op Code Offset Irrelevant Data (NOTE 1) Irrelevant Data (NOTE 1) Irrelevant Data (NOTE 1) Operand Data 1 1 0 0 1 0 Op Code Address • Op Code Address + 1 Index Register Index Register Plus Offset (w/o Carry) Index Register Plus Offset Index Register Plus Offset Index Register Plus Offset 1 1 1 1 1 1 0 Op Code Offset Irrelevant Data (NOTE 1) Irrelevant Data (NOTE 1) Current Operand Data Irrelevant Data (NOTE 1) New Operand Data (NOTE 2) 1 1 0 0 0 1 1 Op Code Address Op Code Address + 1 Index Register Index Register Plus Offset (w/o Carry) Index Register Plus Offset Index Register Plus Offset Index Register Plus Offset + 1 1 1 1 1 1 0 0 Op Code Offset Irrelevant Data (NOTE 1) Irrelevant Data (NOTE 1) Irrelevant Data (NOTE 1) Operand Data (High Order Byte) Operand Data (Low Oder Byte) 1 1 0 1 1 0 0 0 Op Code Address Op Code Address + 1 Index Register Stack Pointer Stack Pointer .2 Index Register Index Register Plus Offset (w/o Carry) 1 1 1 0 0 1 1 1 Op Code Offset Irrelevant Data (NOTE 1) Return Address (Low Order Byte) Return Address (High Order Byte) Irrelevant Data (NOTE 1) Irrelevant Data (NOTE 1) Irrelevant Data (NOTE 1) 4 ADC ADD AND BIT CMP EOR LOA ORA sac 5 4 SUB CPX LOS LOX 1 2 3 5 6 1 2 3 4 5 6 STA 6 ASL ASR CLR COM DEC INC LSR NEG ROL ROR TST 1 2 3 4 5 6 1 2 3 7 4 5 6 7 1/0 1 Data Bus (NOTE 2) STS STX 1 2 3 7 4 5 6 7 JSR 1 2 3 8 NOTE 1. For TST. 4 5 6 7 8 . then the Data Bus will go to the high Impedance three-state condition. VMA = 0 and Operand data does not change.

Figure 38 Example of Excution Timing in Each Addressing Mode 367 Next Inst. PC ± Offset Next Inst.c::::~::::)~::::).LJ7---+-~-----r---+I I I I I R/W:t~--~:~--~:-----T:----~l~~~-----+----~----~----~ I Data Bus 1 ::x:::::::x::::_____x:=:x=:::x_____ ABA RELATIVE PSH I Data Next Inst...------------------------------------------HD6800. I I tS:t.. I I : -' I I I [ DataBus= LOA Data Next Inst.~_.. INDEXED I I RIW'J:! I VMA Data Bus I: --+---t t-/'---+-----.--t--"1'---"~ VMA [ 1 D. DIRECT I VMA Rffl --'j -' I I I : I I I ! I I I I : [I .--t" t-j---j... _. HD68AOO. -)..Ll7 I -=x:::::::x::::_______x::::::x::=:::x___________x::::x=: LOA VMA I : .R:'J ::-:.I.. I I [ I I I Offset Data STA EXTENDED Offset : Data I RfflJ [ Data Bus I I I L_L.. \ : ~-L-b I r"J I '--......~"""'---+-----+-Ji.....L..-' I I [ Data B u s = : : : : : : : : : : x : : : : : : x _ _ _ _ _ LOA Address Data ST A Address ACCA Next Data Inst.J.--~_).. I I : VMA~-i-----T-----T-l.......---'---!-It·i--..I-.17 I LOA Address Address Data STA IMPLIED Address Address I ACCA Data I ::J--+--..J.--+t.--...(: Branch Inst.....LJ7 [ I L.-~.:::1::~::::)(::::~:::::~::::. HD68BOO IMMEDIATE VMA 4 3 2 I 5 8 7 6 9 10 I 12 11 13 I ----l---~---J--- --"1 ~~I----_4I----~I----~----~----~-__~--~----~----~----~----+_----1 RIW --.

Rfii Ao-A. the HD6802 has 128 bytes of RAM on the chip located at hex addresses 0000 to 007F.s RiW D. A" A" --. BA D. 0. RE A. CJ Control { VeeStandbv BA HD6802 0 0 -0. may be retained in a low power mode by utilizing V cc standby. same chip. _ _ _ _ _ _.t. A" A.J - (Top View) 368 Vss . at hex addresses 0000 to OOIF. 0. The HD6802 is completely software compatible with the HD6800 as well as the entire HMCS6800 family of parts. 0.. XTAL D.32 bytes of RAM.. _Ie> '. .HD6802---------------M PU (Microprocessor with Clock and RAM) The HD6802 is a monolithic 8-bit microprocessor that contains all the registers and accumulators of the present HD6800 plus an internal clock oscillator and driver on the. RE NMI Vee E MPU VMA EXTAL C Crystal 0. The first.J. In addition. Hence. the HD6802 is expandable to 65k words.. • • • • • • • FEATURES On-Chip Clock Circuit 128 x 8 Bit On-Chip RAM 32 Bytes of RAM are Retainable Software-Compatible with the HD6800 Expandable to 65k words Standard TTL-Compatible Inputs and Outputs • • • • 8 Bit Word Size 16 Bit Memory Addressing Interrupt Capability Compatible with MC6802 • BLOCK DIAGRAM (DC-40) • PIN ARRANGEMENT Vee Vee Vec Standby Vss Vee Vee RES HALT EXTAL XTAL MR Counter/ { Timer I/O es o 'J!tn Parallel I/O 'iRci 1 E VMA Clock R/W TIm MR VMA RES 0. thus facilitating memory retention during a power-down situation.

. +75 Storage Temperature Tstg -55 . Ta =25°C. VMA. +75°C. 0 7 A o -A 15 .. VMA VOH BA Output "Low" Voltage Three State (Off State) Input Current OO-o? Input Leakage Current Except 0 0 ..D - Vee V RES 4...5 - 6. unless otherwise noted. Vss=OV..25 V V -0....75 5.lA ~n V - 2..8 Except RES 2...4V is regarded as "Low" level when it goes up from **** Does not include EXTAL and XTAL.0V±5%. maximum power dissipation is less than 42mW ..) typ ** max Symbol Test Condition Item min Input "High" Voltage Input "Low" Voltage Except RES RES Except RES RES V1H Ao-A 15 .5 10 - - 12 2. BA..5 - 2. • RECOMMENDED OPERATING CONDITIONS Item Symbol Vee * Vee Standby* VIL * Supply Voltage Input Voltage l VIH * typ max Unit 4. 0 7 **** Output Capacitance VOL ITS1 lin 0 0 . Normal operation should be under recommended operating conditions.3 .lA - 0..4 IOL = 1.5 J.3 IOH = -145J... Rm. +7.lA Po * Power Dissipation Input Capacitance 4.-25" e..E - - 0.2 W 10 12. which are crystal inputs. Ta=-20.6mA Vee -0.lA -2. Vee Standby=5. If these conditions are exceeded.0 av.0V±5%.3 IOH = -205J.------------------------------------------------------------HD6802 • ABSOLUTE MAXIMUM RATINGS Item Supply Voltage Input Voltage Symbol Value Unit Vee * Vee StandbY* Vin * -0. f=1.0MHz • In power-down mode..25 *** V1L 00-0 7 .4 V -10 - 10 J.25V - -0. Ta =25°C. 369 0. E Output "High" Voltage 2.. f=1.6 1.3 - 0.0 5..8 Unit - 2. +7. applied voltage up to 2.4 V Vin = Q-5.4 Vin=OV.. R/W ..4 Caut Vin=OV.0 V Operating Temperature Topr -20 .. - V V pF pF . V =5V ••• As ~ inpu~as histeresis character.lA Vin = 0.3 . 0 7 Except 0 0 .0MHz Vee 0. it could affect reliability of LSI...8 IOH = -100J.0 V -0.. •• T.4-2.25 - V -20 25 Vee 75 I Operation Temperature min Topr °c * With respect to Vss (SYSTEM GND) • ELECTRICAL CHARACTERISTICS • DC CHARACTERISTICS (Vee =5.... +150 °c °c • With respect to Vss (SYSTEM GND) (NOTE) Permanent LSI damage may occur if maximum ratings are exceeded...

J.0 1. 16 0 - 200 ns Item Symbol Test Condition *tRES = 20 msec min. 12 max Unit 270 ns 530 ns - ns - - ns - - ns - 165 225 ns - 250 ns 200 - - ns - - 100 ns ns *Ta = 25°C. 3) PW4JL at 0. Ta=-20~+75°C. for R type. Fig. 4. 50 msec min. for S type. Fig. Fig. 3 PW4JH at 2. 5. 370 Unit ns - ms - ns . 3 Fig. tpcr tpCf Fig. 2. Fig. 2.1 - 1. 2. Fig.2. CLOCK TIMING CHARACTERISTICS Item Frequency of Operation Symbol min typ max I Input Clock -. Fig. POWER DOWN SEQUENCE TIMING. 13 150 - RAM Enable Reset Time (2) tRE2 Fig. 3 10 Data Delay Time (Write) toow Bus Available Delay tSA Processor Controls Processor Control Setup Time Processor Control Rise and Fall Time (Measured at 0. Vee Standby=5. 7. POWER UP RESET TIMING AND MEMORY READY TIMING min typ max RAM Enable Reset Time (1) tRE1 Fig. 6 - Peripheral Read Access Time tacc Fig.) 1. 3) tcp 0. 2 - Data Setup Time (Read) tOSR Fig.8V ~ 2.0V) tpcs Fig. Fig.Fig. 16 Item Symbol Fig. 3. Fig. 2. 12 0 Memory Ready Setup Time tSMR Fig. 7..HD6802----------------------------------------------------------• AC CHARACTERISTICS (Vee=5. 2 100 Input Data Hold Time tH Fig.0V±5%.4V(Fig. Fig.0V±5%. Fig. Fig. 3 20 Address Hold Time (Address. Fig.4V (Fig. 2. 2 10 - Output Data Hold Time tH Fig. 4~Fig.8V and 2. 12 20* RAM Enable Reset Time (3) tRE3 Fig.0 I Crystal fXTAL 1. 8 4~Fig. Fig. R/W.8V (Fig.4 f 0. unless otherwise noted.s 2. 7. 12. 16 300 - - ns Memory Ready Hold Time tHMR Fig. Vss=OV. VMA) tAH Fig.3) Unit MHz J. Vcc = 5V 3. 13 E-3 cycles Reset Release Time tLRES Fig.0 10 450 - 4500 ns - - 25 ns Frequency Cycle Time I "High" Level Clock Pulse Width I "Low" Level Clock Fall Time Test Condition fcyc Fig. READIWRITE TIMING typ* Test Condition min Address Delay tAD Fig.0 - 4. 13.

All diodes are 152074 (ft or equivalent.0V R L = 2Akn C = 130pF for Do ~D7' E = 90pF for Ao ~Als.:o. and VMA = 24kn for BA C includes stray Capacitance...----------------------------------------------------------------HD6802 5...0V --:::.8V--="4----~==F ~ Data Not Valid Figure 2 Read Data from Memory or Peripherals ~----------------------tcyc----------------------~ PWcI>H E OAV Address From MPU VMA tDDW 2.R/W..... R/W..1-.-1----+ C R Figure 1 Bus Timing Test Load ~-----------------------tcyc----------------------~ E 2AV o RM Address From MPU VMA Data From Memory or Peripherals 2. Test Point 0-_--+--.===~ --------------------------------~~ 0.oo.4V Data From MPU OAV ~ Data Not Valid Figure 3 Write Data in Memory or Peripherals 371 . and VMA = 30pF for BA R = 11 kn for Do ~D7' E = 16kn for Ao ~A1S ....

.BV 2.4V Figure 5 Timing of HALT and BA MPU Restart Sequence MPU Reset E RES VMA _ _ Figure 6 -----'~24V RES and MPU Restart Sequence 372 .4V .4V O..4V 2.0V O.HD6802----------------------------------------------------------- I- The Last Instruction Cycle HALT Cycle + 2.BV tPcr tpcs tBA \ BA ~O. 1/ O.4V SA Figure 4 Timing of HALT and BA HALT Cycle I nstruction Cycle -I- I -- --'r '-O..0V HALT -. 2.

.4V Figure 7 I- IRQ and NMI Interrupt Timing The last execution cycle of WAI instruction (#9) + WAIT Cycle 2.4V E IRQ.--..4V BA Figure 8 WAI Instruction and BA Timing • MPU REGISTERS • A general block diagram of the HD6802 is shown in Fig..-.(When WAIT Cycle) --'\ \ BA O. Zero(Z). 11 shows the order of saving the microprocessor status within the stack. 9.... • Stack Pointer (SP) The stack pointer is a two byte (16-bit) register that contains the address of the next available location in an external push.. As shown. The 128 x 8 bit RAM has been added to the basic MPU. • Condition Code Register (CCRI The condition code register indicates the results of an Arithmetic Logic Unit operation: Negative(N).register that is used to store data or a sixteen bit memory address for the Indexed mode of memory addreSSing. the stack must be non-volatile.-----.-. Bit 4 is the interrupt mask bit(I). Fig.. NMI . Overflow(V). the number and configuration of the registers are the same as for the HD6800. The used bits of the Condition Code Register (B6 and B7) are ones. 373 . In those applications that require storage of information in the stack when power is lost. Carry from bit7(C)...4V E 2. ACCB) The MPU contains two 8-bit accumulators that are used to hold operands and results from an arithmetic logic unit(ALU)..-. and half carry from bit3(H). The first 32 bytes may be operated in a low power mode via a Vee standby. 10). The MPU has three 16-bit registers and three 8-bit registers available for use by the programmer (Fig. This stack is normally a random access Read/Write memory that may have any location (address) that is convenient. These bits of the Condition Code Register are used as testable conditions for the conditional branch instructions. • Index Register (IX) Accumulators (ACCA.-. The index register is a two byte . These 32 bytes can be retained during power-up and power-down conditions via the RE signal. • Program Counter (PC) The program counter is a two byte (16-bit) register that points to the current program address.----------------------------------------------------------HD6802 WAIT Cycle or The Last Instruction Cycle Interrupt Sequence 2..down/pop-up stack.

0. Higher Order B Bits Program Counter. 1i AI 10 MR 3 E 37 40 NMI 6 HAIT 2 11m 4 EXTAl39 XTAl38 BA 7 VMA 5 RM 34 Rn" Vee Pins 8.---1 m.. Lower Order 8 Bits m. 16 15 14 13 12 A.2 Program Counter.. 31 0.. A~ A4 A . 0" Figure 9 Expanded Block Diagram 7 I I 0 I I ACCA Accumulator A 7 15 I I I 0 Accumulator B ACCB 0 IX 15 0 PC 15 I' I ndex Register Program Counter 0 I SP Stack Pointer 0 Interrupt mask L . 32 33 0.35 VSS' Pin.8 m-7 m-6 SP CC ACCB ACCA IXH IXl PCH PCl Stack Pointer Condition Codes (Also called the Processor Status Byte) Accumulator B Accumulator A Index Register.9 m. 29 30 0. 28 0. Lower Order 8 Bits m-l ---r SP CC m.. 27 0.2 m-l PCH IXl PCl m +1 m m+ 1 m+2 +2 Before After Figure 11 Saving The Status of The Microprocessor in The Stack 374 "' ... Higher Order 8 Bits Index Register.HD6802--------------------------------------------------------A"/ At.21 Q 26 0.H a l f Carry (From Bit 3) Figure 10 Programming Model of The Microprocessing Unit I I I I I I :. 1..5 ACCB m-4 ACCA m -3 IXH m.

the interrupt mask bit is set and must be reset before the MPU can be interrupted by IRQ. Accumulators. This signal is not three-state. • HALT When this input is in the "Low" state. resulting from a power failure or an initial start-up of the processor. In the halt mode. Data Bus will be in the output mode when the internal RAM is accessed. Valid Memory Address will be at a "Low" state. • I nterrupt Request (I RQ) This level sensitive input requests that an interrupt sequence be generated within the machine. External RAM at $0000 to $007F must be disabled when internal RAM is accessed. This prohibits external data entering the MPU. tP2 input. inter~sequence 375 . the MPU is inactive and the information in the registers will be lost. When activated. RAM Enable (RE) Crystal Connections EXTAL and XTAL Memory Ready(MR) Vee Standby Enable tP2 Output(E) The following is a summary of the H06802 MPU signals: • Address Bus (Ao "" A 15 ) Sixteen pins are used for the address bus. This is good engineering design practice in general and necessary to insure proper operation of the part. the machine will begin an interrupt sequence. this will signal the MPU to begin the restart sequence. A 3kn external register to Vee should be used for wire-OR and optimum control of interrupts. all activity in the machine will be halted: This input is level sensitive. This is good engineering design practice in general and necessary to insure proper operation of the part. It is bidirectional. This will start execution of a routine to initialize the processor from its reset condition. An address loaded at these locations causes the MPU to branch to a non-maskable interrupt routine in memory. In normal operation. At that time. The HALT line must be in the "High" state for interrupts to be serviced. • Data Bus (Do "" 0 7 ) Eight pins are used for the data bus. this signal should be utilized for enabling peripheral interfaces such as the PIA and ACIA. At the end of the cycle. 13 respectively. IRQ and NMI should be tied "High" if not used. An address loaded at these locations causes the MPU to branch to an interrupt routine in memory. and two unused pins have been eliminated. tPl . DBE. Fig. When the processor is halted. If a "High" level is detected on the input. It should be noted that the internal RAM is fully decoded from $0000 to $OO7F. transferring data to and from the memory and peripheral devices. FFFF) locations in memory will be used to load the program that is addressed by the program counter. Next the MPU will respond to the interrupt request by setting the interrupt mask bit high so that no further interrupts may occur. This will occur if the HALT line is in the "Low" state or the processor is in the wait state as a result of the execution of a WAI instruction. The index Register. a 16-bit address will be loaded that points to a vectoring address which is located in memory locations FFF8 and FFF9. The address bus will display the address of the next instruction. It also has three-state output buffers capable of driving one standard TTL load and 130pF. Table 1 gives the memory map for interrupt vectors. The outputs are capable of driving one standard TTL load and 90pF. At such time. This output is capable of driving one standard TTL load and 30pF. Accumulators. • Non-Maskable Interrupt (NMI) A low-going edge on this input requests that a non-maskbe generated within the processor. This output is capable of driving one standard TTL load and 9OpF. Bus Available will be at a "High" state.-----------------------------------------------------------HD6802 • HD6802 MPU SIGNAL DESCRIPTION Proper operation of the MPU requires that certain control and timing signals be provided to accomplish specific functions and that other signal lines be monitored to determine the state of the processor. the machine will stop at the end of an instruction. These control and timing signals for the H06802 are similar to those of the H06800 except that TSC. the processor will complete the current instruction that is being executed before it recognizes the NMI signal. The processor is removed from the wait state by the occurrence of a maskable (mask bit 1=0) or nonmaskable interrupt. HALT should be tied "High" if not used. Inputs IRQ and NMI are hardware interrupt lines that are sampled when E is "High" and will start the interrupt routine on a "Low" E following the completion of an instruction. One standard TTL load and 90pF may be directly driven by this active high signal. All the higher order address lines will be forced "High". a 16-bit address will be loaded that points to a vectoring address which is located in memory locations FFFC and FFFD. • Bus Available (BA) The Bus Available signal will normally be in the "Low" state. At the end of the cycle. The processor will wait. Power-up and reset timing and power-down sequences are shown in Fig. Program Counter. For the restart. A 3kn external resistor to Vee should be used for wire-OR and optimum control of interrupts. 12 and Fig. Program Counter. Interrupts will be latched internally while HALT is "Low". • Valid Memory Address (VMA) This output indicates to peripheral devices that there is a valid address on the address bus. aU three-state output drivers will go to their off state and other outputs to their normally inactive level. if the interrupt mask bit in the Condition Code Register is not set. 14 is a flowchart describing the major decision paths and interrupt vectors of the microprocessor. • Reset (RES) This input is used to reset and start the MPU from a power-down condition. As with the IRQ signal. the last two(FFFE. it will be in the logical one state ("High"). transition of the HALT line must not occur during the last 250ns of E and the HALT line must go "High" for one Clock cycle. When this line is "Low". and Condition Code Register are stored away on the stack. During the restart routine. The normal standby state of this signal is Read ("High"). and the following signal and timing lines have been added. it will go to the "High" state indicating that the microprocessor has stopped and that the address bus is available (but not in a three-state condition). The Index Register. • ReadlWrite (R/W) This TTL compatible output signals the peripherals and memory devices whether the MPU is in a Read ("High") or Write ("Low") state. until it completes the current instruction that is being executed before it recognizes the request. and Condition Code Register are stored away on the stack. The interrupt mask bit in the Condition Code Register has no effect on NMI. To insure single instruction operation.

RES ------~--~I Option 1 (See Note below) RES --------~I Option 2 See Figure 8 for Power Down condition ~2'~OV.HD6802------------------------------------------------------------- VCC E !--tpcs >4.~___________________ If option 1 is chosen.8~~ RE VMA O.4 { I .0V tAE2 O...8V tPCr ____--J/ (NOTE) fI~-----------------.---------H----~tL+------------l--.-_ it ______________O~.25V ... Figure 12 Power-up and Reset Timing VCC E l-t RE AE1 tPCf3f1 2..8V j ----------- Figure 13 Power-down Sequence Figure 14 MPU Flow Chart 376 . RES and RE pins can be tied together...

it may not be halted for more than 4... This is good engineering design practice in general and necessary to insure proper operation of the part. HD6802 38 pin EXTAL and XTAL The HD6802 has an internal oscillator that may be crystal controlled. and requires the external clock to retain information.4V / E ~tSMR tPCr MR Figure 16 Memory Ready Control Function 377 . the on-chip memory is enabled to respond to the MPU controls.7SV during power-down. If an external clock is used.5tL s. ~----------------------------------------~J~-------------------------_ ~ \. When MR is "Low". 16. This is good engineering design practice in general and necessary to insure proper operation of the part. In the "Low" state. Pin38 is to be left open in this mode_ An RC network is not directly usable as a frequency source on pins 38 and 39.5tLs.----. When MR is "High". A divide-by-four circuit has been added to the HD6802 so that a 4MHz crystal may be used in lieu of a IMHz crystal for a more cost-effective system. RE should be tied to the correct "High" or "Low" state if not used. E will be in normal operation. • Recommended Oscillator (4MHz) 39 pin LJ------. MR should be tied "High" if not used..-0.----------------------------------------------------------HD6802 Conditions for Crystal (4 MHz) • AT Cut Parallel resonant • Co =7 pF max. RAM enable must be "Low" three cycles before Vee goes below 4. = C2 = 22pF ± 20% Figure 15 Crystal Oscillator When using the crystal. • Rl = 80n max. The HD6802 is a dynamic part except for the internal RAM. Table 1 Memory Map for Interrupt Vectors Vector Description MS LS FFFE FFFF Restart FFFC FFFD Non-Maskable Interrupt (NMI) FFFA FFFB Software Interrupt (SWI) FFFB FFF9 Interrupt Request (IRQ) (RES) Co • Crystal Equivalent Circuit RAM Enable (RE) A TTL-compatible RAM enable input controls the on-chip RAM of the HD6802. Memory Ready timing is shown in Fig. E may be stretched integral multiples of half periods. An RC network type TTL or CMOS oscillator will work well as long as the TTL or CMOS output drives the HD6802. A maximum stretch is 4.. These connections are for a parallel resonant fundamental crystal (AT cut). Pin39 of the HD6802 may be driven externally by a TTL input signal if a separate clock is required. When placed in the "High" state. • Memory Ready (MR) MR is a TTL compatible input control signal which allows stretching of E. RAM is disabled. This pin may also be utilized to disable reading and writing the on-chip RAM during a power-down situation.. see the note for Board Design of the Oscillation Circuit in HD6802. C. thus allowing interface to slow memories..

• NOTE FOR BOARD DESIGN OF THE OSCILLATION CIRCUIT IN HD6802 In designing the board. This clock may be conditioned by a Memory Ready Signal. rotate. the following notes should be taken when the crystal oscillator is used. Must be avoided i~ i~ / ' \\ -+----. This is equivalent to <1>2 on the HD6800.. shift. The following design must be avoided. This is a single phase. or standby condition is guaranteed at the range of 4. • Vee Standby This pin supplies the dc voltage to the first 32 bytes of RAM as well as the RAM Enable (RE) control logic. conditional or unconditional branch.HD6802------------------------------------------------------------• • MPU INSTRUCTION SET Enable (E) This pin supplies the clock for the MPU and the rest of the system. logical. interrupt and stack manipulation instructions.:.0 V to 5..------ 38 Signal C A signal line or a power source line must not cross or go near the oscillation circuit line as shown in the left figure to prevent the induction from these lines and perform the correct oscillation. TIn [Normal oscillation may be disturbed when external noise is] induced to pin 38 and 39..---. ~... load. The HD6802 has a set of 72 different instructions.. power-down..25 V.f . ~ t-'-~..". or nonnal oscillation may be disturbed when E signal is feedbacked to XTAL.2SV is 8mA.. Thus retention of data in this portion of the RAM on a power up. This instruction set is the same as that for the 6800MPU(HD6800 etc. The resistance among XTAL. Don't wire them in parallel. Maximum current drain at S.. Included are binary and decimal arithmetic.. EXTAL and other pins should be over 10M!"!.'. store.'. HD6802 Figure 17 Note for Board Design of the Oscillation Circuit 378 . _____ Crystal oscillator and load capacity CL must be placed near ______ the LSI as much as possible.=-4----f~ HD6802 ~ Pin 38 signal line should be wired apart from pin 37 signal line as much as possible. TTL compatible clock.) and is not explained again in this data sheet.

HD6802 Figure 18 Example of Board Design Using the Crystal Oscillator 379 .---..-----------------------------------------------------------HD6802 . .... / E signal is wired apart from 38 pin /' and 39 pin.Other signals are not wired in th is area .

0. The first 32 bytes of RAM. HD6802 Expandable to 65k words Standard TTL-Compatible Inputs and Outputs • • • 8 Bit Word Size 16 Bit Memory Addressing Interrupt Capability HD6802WP (DP-40) • PIN ARRANGEMENT • BLOCK DIAGRAM RES Vss HALf Vee Vee Vee Standby EXTAL XTAL VMA RE Vee Vee vee RM D. *C' 380 (Top View) Standby . A. Internal RAM has been extended from 128 to 256 bytes to increase the capacity of system read/write memory for handling temporary data and manipulating the stack. D. at hex addresses 0000 to 001 F. A" XTAL CJ Control { A. 0. the H06802W is expandable to 65k words. Hence. • • • • • • • FEATURES On-Chip Clock Circuit 256 x 8 Bit On-Chip RAM 32 Bytes. Counterl { Timer 1/0 11m MR HD6802W RES 0.HD6802W MPU (Microprocessor with Clock and RAM) H06802W is the enhanced version of HD6802 which contains MPU. 1m Parallel 0.-A" AI> Crystal Vss EXTAL C'.r. if R/W HD6802W NMI IMPUI BA 0. The internal RAM is located at hex addresses 0000 to OOFF. The HD6802W is completely software compatible with the H06800 as well as the entire HMCS6800 family of parts.. may be retained in a low power mode by utilizing Vee standby. RE 1/0 0. clock and 256 bytes RAM.of RAM are Retainable Software-Compatible with the HD6800. 2 0. thus facilitating memory retention during a power-down situation.-0 7 A" A.

. may be retained in a low power : : _____________ } retention by Vee Standby 0020 OOFF L. 30 OJ 31 O2 32 0.21 27 28 0._ _ _ _ _ _-----' Figure 2 Address Map of HD6802W 381 . thus facilitating memory retention during a power-down situation.---------------------------------------------------------HD6802VV A expanded block diagram of the HD6802W is shown in Fig.35 Vss = Pins 1. 0. The first 32 bytes of RAM. As shown. The HD6802W has 256 bytes of RAM on the chip located at hex addresses 0000 to OOFF. Os 29 D. at hex addresses 0000 to 001 F.. 33 Do Figure 1 Expanded Block Diagram mode by utilizing Vee standby and setting RAM Enable Signal "Low" level. MR 3 E 37 RES 40 NMI 6 HALT 2 Tm:i 4 EXTAL 39 XTAL 38 SA 7 VMA 5 Rm 34 26 Vee = Pins 8. Address Map of RAM is shown is Fig. the number and configuration of the registers are the same as the HD6802 except that the internal RAM has been extended to 256 bytes. 1. 2.

0MHz - - 12 VOL ITS1 lin *** IOL = 1.0 I nput Voltage V . • RECOMMENDED OPERATING CONDITIONS Item Symbol Supply Voltage min Vee* 4.75 - -20 25 Vee 75 I Except RES * typ Topr V °c * With respect to Vss (SYSTEM GND) • ELECTRICAL CHARACTERISTICS • DC CHARACTERISTICS (Vee=5. Normal operation should be under recommended operating conditions.LA - 0. maximum power dissipation is less than 42mW.0V±5%. 0 0 ""0 7 Except 0 0 ""0 7 Ao""A 1s .4V is regarded as "Low" level when it goes up from OV.0 V Input Voltage Yin * -0.4 - Symbol Except RES RES Except RES RES Do-0 7 . E Output "High" Voltage Ao-A 15 .5 c'n Vin=OV.5 - 2.75 Vee Standby * V .6mA Po **** ~\I\Ier Dissipation Input Capacitance Test Condition va. If these conditions are exceeded. **** In power-down mode. which are crystal inputs. applied voltage up to 2. BA.LA 2.8 IOH = -205J.LA 2.0V±5%.3 .4 - IOH = -100J.HD6802W----------------------~--------------------------------- • ABSOLUTE MAXIMUM RATINGS Item Supply Voltage Symbol Value Unit Vee * Vee Stand by * -0. unless otherwise noted. VMA - Unit V V V - - - 0.LA Yin = Q-5.0 Vcc-O.8 -0. R/W.2 W - 10 12.0 - Vee Vee -0.0MHz 6.L * 4. it could affect reliability of LSI. Vss=OV.0 Operating Temperature Topr Tstg -20.7 1.H 2.H Operation Temperature I RES max Unit 5. f=1. 382 pF pF .0 5.5 J.) Item Input "High" Voltage Input "Low" Voltage min typ* max V.25V -2.25 V V -0.+150 °c Storage Temperature V * With respect to Vss (SYSTEM GND) (NOTE) Permanent LSI damage may occur if maximum ratings are exceeded.+7. f=1.+75 °c -55 .8 2. Ta=25°C. Ta=-2o-+75°C.3.3 - 0.3 - Vee 0.4 V Yin = 0.4""2.5 10 Caut Vin=OV. Ta=25°C. =5V ** As RES input has histeresis character. Vee Standby=5. VMA VOH BA Output "Low" Voltage Three State (Off State) Input Current 0 0 ""07' Input Leakage Current Except Do -0 7 Output Capacitance * T a =25° C.4 V -10 10 J. R/W.L -0.4 - - IOH = -145J..+7.LA 2.75 - Vee ** V.3 - 0. *** Does not include EXTAL and XTAL.

4. READ/WRITE TIMING Item Symbol Test Condition min typ* max Unit 270 ns Fig.4V(Fig..4 10 - Output Data Hold Time tH Fig.. 2.SV and 2.0 4. Fig.p 0.) 1.8V . Fig. 14 - - 100 ns max Unit Processor Controls Processor Control Setup Time Processor Control Rise and Fall Time (Measured at O. 6. VMA) tAH Fig. 12 150 RAM Enable Reset Time (2) tRE2 Fig. Vee Standby=5. 8 Peripheral Read Access Time tace Data Setup Time (Read) Input Data Hold Time tH Fig. 14 0 383 - ms 200 ns ns ns ns . Fig.0V) 530 ns ns ns ns ns 3.8V (Fig. Fig.1 1.0 fXTAL 1. Fig.12. Ta=-20~+75°C. 11. CLOCK TIMING CHARACTERISTICS I Input Clock -. 9. Fig. 6"'" Fig.4 I Crystal Frequency Frequency of Operation Cycle Time I "High" Level I "Low" Level Clock Pulse Width min typ max f 0. 9. 7. 5 PWc/>H at 2. POWER DOWN SEQUENCE TIMING. Fig. 5. 10 - - 250 ns tpcs Fig. 14 300 Memory Ready Hold Time tHMR Fig.4. 6"'" Fig. 4. Fig. Fig. 5) t.0 1..5 20 - Address Hold Time (Address.4 - tOSR Fig. 11 20 RAM Enable Reset Time (3) tRE3 Fig. 5 10 - - Data Delay Time (Write) toow Fig. Fig. 9.. Vss=OV. tpCf Fig. 4. 4. 5) PWc/>L at 0. 11 200 - - ns tpcr.Fig. Fig.4 100 Address Delay tAD Fig.0V±5%. unless otherwise noted. 5 - 165 225 ns Bus Available Delay tSA Fig. Fig. R/W. 11 0 Memory Ready Setup Time tSMR Fig.4V(Fig.5) 10 Unit MHz Ils 2.0 - 450 - 4500 ns - - 25 ns Symbol Item Clock F all Time Test Condition fcye Fig.0V±5%. POWER UP RESET TIMING AND MEMORY READY TIMING min typ RAM Enable Reset Time (1) tRE1 Fig. 12 E-3 cycles - Item Symbol Test Condition Reset Release Time tLRES Fig.--------------------------------------------------------HD6802W • AC CHARACTERISTICS (Vee=5. Fig.. 4.

R/W. and VMA = 30pF for BA R = 11 kn for Do -0" E _ = 16kn for Ao -A IS . C R L = 2.0V -::::=-~.4V ~ --:::~~=~~=::::~~ ---'''''''''4-=======~r Data Not Valid Figure 5 Write Data in Memory or Peripherals 384 . R/W. . All diodes are 1S2074@or equivalent.-.!==~"'--- --------------------------------------~~ O.8V---=-'f-===~ ~ Data Not Valid Figure 4 Read Data from Memory or Peripherals ~---------------------tcyc----------------------~ PWtPH E O.OV Test Point 0-_--_--.4kn C = 130pF for 0 0 -0" E = 90pF for Ao -A 1S .. R Figure 3 Bus Timing Test Load ~-----------------------tCyC----------·----------~ .4V E R/W Address From MPU VMA Data From Memory or Peripherals 2.HD6802W-------------------------------------------------------- S. and VMA = 24kn for SA C includes stray Capacitance.--.4V From MPU O..4V R/W Address From MPU VMA Data 2.

:.0V HALT O...:...O.-.4V Figure 7 Timing of HALT and BA MPU Restart Sequence E 2.y_CI_e_ _ _ _ _"\ E .j BA O.* " I• tpcs ....4V O..-.4V Figure 6 Timing of HALT and BA HALT C.4V 2.4V VMA Figure 8 RES and MPU Restart Sequence 385 ..4V BA 2...~ ~ Instruction Cycle _ _ _ _ _ _ _.8V tpc.---------------------------------------------------------HD6802VV I_ The Last Instruction Cycle E HALT Cycle + 2. .

.4V E 2.-...--.....I~ WAIT Cycle 2..4V E IRQ..HD6802VV--------------------------------------------------------- WAIT Cycle or The Last Instruction Cycle Interrupt Sequence 2.4V Figure 9 IRQ and NMI Interrupt Timing The last execution cycle of WAI instruction (~#9_)_ _ _ _ _" ..---.....4V BA Figure 10 WAI Instruction and BA Timing 386 .-. NMI (When WAIT Cycle) ....-.- '\ \ BA O..

As with the IRQ signal. An address loaded at these locations causes the MPU to branch to a non-maskable interrupt routine in memory. In normal operation. All the higher order address lines will be forced "High". The processor will wait. the MPU is inactive and the information in the registers will be lost. this signal should be utilized for enabling peripheral interfaces such as the PIA and ACIA. It should be noted that the internal RAM is fully decoded from $0000 to $OOFF. it will be in the logical one state ("High"). Program Counter. transition of the HALT line must not occur during the last tpcs of E and the HALT line must go "High" for one Clock cycle. Bus Available (BA) The Bus Available signal will normally be in the "Low" state. This prohibits external data entering the MPU. External RAM at $0000 to $OOFF must be disabled when internal RAM is accessed. This signal is not three·state. HALT should be tied "High" if not used. At the end of the cycle.--------------------------------------------------------HD6802W • HD6802W MPU SIGNAL DESCRIPTION • Address Bus (Ao '" A 15 ) Sixteen 'pins are used for the address bus. It is bidirectional. • Reset (RES) This input is used to reset and start the MPU from a power·down condition. This will occur if the HALT line is in the "Low" state or the processor is in the wait state as a result of the execution of a WAI instruction. This output is capable of driving one standard TTL load and 9OpF. During the restart routine. • Data Bus (Do '" 0 7 ) Eight pins are used fpr the data bus. 13 is a flowchart describing the major decision paths and interrupt vectors of the microprocessor. Accumulators. This output is capable of driving one standard TTL load and 30pF. FFFF) locations in memory will be used to load the program that is addressed by the program counter. Next the MPU will respond to the interrupt request by setting the interrupt mask bit high so that no further interrupts may occur. Fig. Bus Available will be at a "High" state. • Valid Memory Address (VMA) This output indicates to peripheral devices that there is a valid address on the address bus. Table 1 gives the memory map for interrupt vectors. At that time. II and Fig. One standard TTL load and 90pF may be directly driven by this active high signal. To insure single instruction operation. The Index Register. This is good engineering design practice in general and necessary to insure proper operation of the part. This is good engineering design practice in general and necessary to insure proper operation of the part. if the interrupt mask bit in the Condition Code Register is not set. and Condition Code Register are stored away on the stack. resulting from a power failure or an initial start-up of the processor. the last two(FFFE. The processor is removed from the wait state by the occurrence of a maskable (mask bit 1=0) or nonmaskable interrupt. At such time. The outputs are capable of driving one standard TTL load and 90pF. The address bus will display the address of the next instruction. transferring data to and from the memory and peripheral devices. Accumulators. When activated. the interrupt mask bit is set and must be reset before the MPU can be interrupted by IRQ. Program Counter. • Read/Write (R/W) This TTL compatible output signals the peripherals and memory devices whether the MPU is in a Read ("High") or Write ("Low") state. the machine will begin an interrupt sequence. Data Bus will be in the output mode when the internal RAM is accessed. Interrupts will be latched internally while HALT is "Low". In the halt mode. the processor will complete the current instruction that is being executed before it recognizes the NMI signal. Inputs IRQ and "WI are hardware interrupt lines that are sampled when E is "High" and will start the interrupt routine on a "Low" E following the completion of an instruction. inter~sequence 387 . Valid Memory Address will be at a "Low" state. all activity in the machine will be halted: This input is level sensitive. The HALT line must be in the "High" state for interrupts to be serviced.QR and optimum control of interrupts. The index Register. 12 respectively. At the end of the cycle. When the processor is halted. and Condition Code Register are stored away on the stack. The interrupt mask bit in the Condition Code Register has no effect on NMI. IRQ and NMI should be tied "High" if not used. this will signal the MPU to begin the restar(sequence. • Non·Maskable Interrupt (NMU A low-going edge on this input requests that a non-maskbe generated within the processor. A 3kO external register to Vee should be used for wire. The normal standby state of this signal is Read ("High"). An address loaded at these locations causes the MPU to branch to an interrupt routine in memory. . Power-up and reset timing and power·down sequences are shown in Fig. all three-state output drivers will go to their off state and other outputs to their normally inactive level. A 3kO external resistor to Vee should be used for wire-OR and optimum control of interrupts. until it completes the current instruction that is being executed before it recognizes the request. a 16·bit address will be loaded that points to a vectoring address which is located in memory locations FFF8 and FFF9. This will start execution of a routine to initialize the processor from its reset condition. It also has three·state output buffers capable of driving one standard TTL load and 130pF. • HALT When this input is in the "Low" state. When this line is "Low". it will go to the "High" state indicating that the microprocessor has stopped and that the address bus is available (but not in a three-state condition). If a "High" level is detected on the input. • Interrupt Request (IRQ) This level sensitive input requests that an interrupt sequence be generated within the machine.. For the restart. a 16-bit address will be loaded that points to a vectoring address which is located in memory locations FFFC and FFFD. the machine will stop at the end of an instruction.

75V __--------------~~--------~+------------l---Option 1 (See Note below) Option 2 See Figure 12 for Power Down condition iC RE { DV O.8V~ Figure 12 Power-down Sequence Figure 13 MPU Flow Chart 388 .-tRE2--l O.0V rl-t RE1 '1\ l.8V O. Figure 11 Power-up and Reset Timing Vcc E tPCf=:j RE 2.HD6802W-------------------------------------------------------- Vcc E !--tpcs >VCC-O. RES and RE pins can be tied together.8V tpcr (I / VMA (NOTE) \ If option 1 is chosen.

• Rl = 80n max.5~s. When MR is "Low".. When placed in the "High" state.. This is good engineering design practice in general and necessary to insure proper operation of the part. MR should be tied "High" if not used. An RC network is not directly usable as a frequency source on pins 38 and 39. This pin may also be utilized to disable reading and writing the on-chip RAM during a power-down situation... Table 1 Memory Map for Interrupt Vectors Vector Description MS LS FFFE FFFF Restart FFFC FFFD Non-Maskable Interrupt (NMI) FFFA FFFB Software Interrupt (SWI) FFF8 FFF9 Interrupt Request (IRQ) (RES) Co • Crystal Equivalent Circuit RAM Enable (RE) A TTL-compatible RAM enable input controls the on-chip RAM of the HD6802W. In the "Low" state. = 22pF ±. E will be in normal operation.20% When using the crystal.. HD6802W 38 pin n------.4V I==tSMA tPCr tpCf MR Figure 14 Memory Ready Control Function 389 / .. This is good engineering design practice in general and necessary to insure proper operation of the part. • Memory Ready (MR) MR is a TTL compatible input control signal which allows stretching of E. An RC network type TTL or CMOS oscillator will work well as long as the TTL or CMOS output drives the HD6802W. RAM is disabled. The HD6802W is a dynamic part except for the internal RAM. EXTAL and XTAL The HD6802W has an internal oscillator that may be crystal controlled. O.. the on-chip memory is enabled to respond to the MPU controls.. These connections are for a parallel resonant fundamental crystal (AT cut). Pin38 is to be left open in this mode.. thus allowing interface to slow memories.. Memory Ready timing is shown in Fig. Pin39 of the HD6802W may be driven externally by a TTL input signal if a separate clock is required...S~s. A maximum stretch is 4. When MR is "High". E may be stretched integral multiples of half periods.. ~--------------~r~----------~\ E ~ :t. see the note for Board Design of the Oscillation Circuit in HD6802W. RE should be tied to the correct "High" or "Low" state if not used. A divide-by-four circuit has been added to the HD6802W so that a 4MHz crystal may be used in lieu of a lMHz crystal for a more cost-effective system.7SV during power-down. it may not be halted for more than 4... and requires the external clock to retain information.4V C.--. 2. RAM enable must be "Low" three cycles before Vee goes below 4. • Recommended Oscillator (4MHz) 39 pin Q------.. 14. If an external clock is used. = C.---------------------------------------------------------HD6802W Conditions for Crystal (4 MHz) • AT Cut Parallel resonant • Co =7 pF max.

This clock may be conditioned by a Memory Ready Signal. MPU INSTRUCTION SET The HD6802W has a set of 72 different instructions. The resistance among XTAL. shift.HD6802W--------------------------------------------------------• • Enable (E) This pin supplies the clock for the MPU and the rest of the system.. ~. This is a single phase.. Included are binary and decimal arithmetic. the following notes should be taken when the crystal oscillator is used.. HD6802W Figure 15 Note for Board Design of the Oscillation Circuit 390 . Thus retention of data in this portion of the RAM on a power-up. This is equivalent to ¢2 on the HD6800. interrupt and stack manipulation instructions..0 V to 5. power-down. ~ 1--'-'--.. conditional or unconditional branch.:=-+-----1 ~ HD6802W ------- 37 Pin 38 signal line should be wired apart from pin 37 signal line as much as possible.2SV is 8mA. • NOTE FOR BOARD DESIGN OF THE OSCILLATION CIRCUIT IN HD6802W In designing the board. or nonnal oscillation may be disturbed when E signal is feedbacked to XTAL. _____ Crystal oscillator and load capacity CL must be placed near _______ the LSI as much as possible. logical. EXT AL and other pins should be over lOMn. store.. rotate. This instruction set is the same as that for the 6800MPU (HD6800 etc. Maximum current drain at S.'. Must be avoided ~~ /'\ ~ ~ \ -+--~-+-----. 38 7h (NOrmal oscillation may be disturbed when external noise is] induced to pin 38 and 39."":". or standby condition is guaranteed at the range of 4. TTL compatible clock..25 V. The following design must be avoided.) and is not explained again in this data sheet.Signal C 38 A signal line or a power source line must not cross or go near the oscillation circuit line as shown in the left figure to prevent the induction from these lines and perform the correct oscillation. load. Don't wire them in parallel. • Vee Standby This pin supplies the dc voltage to the first 32 bytes of RAM as well as the RAM Enable (RE) control logic.----1.

--------------------------------------------------------HD6802W .....--Other signals are not wired in this area • . HD6802W Figure 16 Example of Board Design Using the Crystal Oscillator 391 ./" and 39 pin.. / E signal is wired apart from 38 pin ....

HD6809.Interfaces with All HMCS6800 Peripherals • Software . HD68A09. HD68B09P HD6800 COMPATIBLE • Hardware . HD68A09P.HD68B09 HD6809P. instructions and addressing modes.. The basic instructions of any computer are greatly enhanced by the presence of powerful addressing modes_ The H06809 has the most complete set of addressing modes available on any 8-bit microprocessor today. The HD6809 has hardware and software features which make it an ideal processor for higher level language execution or standard controller applications. (Top View) • SOFTWARE FEATURES • 10 Addressing Modes • HMCS6800 Upward Compatible Addressing Modes • Direct Addressing Anywhere in Memory Map • Long Relative Branches • Program Counter Relative • True Indirect Addressing • Expanded Indexed Addressing: 392 . The specification of the H068809 is preliminary. This third-generation addition to the HMCS6800 family has major architectural improvements which include additional registers. 0.HD68A09. • Single Bus-Cycle RESET • Single 5-Volt Supply Operation • NMI Blocked After RESET Until After First Load of Stack Pointer • • Early Address Valid Allows Use With Slower Memories Early Write-Data for Dynamic Memories • Compatible with MC6809.Upward Source Code Compatible Instruction Set and Addressing Modes • • • • ARCHITECTURAL FEATURES Two 16-bit Index Registers Two 16-bit Indexable Stack Pointers Two 8-bit Accumulators can be Concatenated to Form One 16-Bit Accumulator • Direct Page Register Allows Direct Addressing Throughout Memory • • • • HARDWARE FEATURES On Chip Oscillator DMA/BREQ Allows DMA Operation or Memory Refresh Fast Interrupt Request Input Stacks Only Condition Code Register and Program Counter • MRDY Input Extends Data Access Times for Use With Slow Memory • Interrupt Acknowledge Output Allows Vectoring By Devices SYNC Acknowledge Output Allows for Synchronization to External Event • (DP-40) • PIN ARRANGEMENT HALi' XTAL EXTAL IRO m-s FIRO BS MROY o DMA7BREo Riw 0. reentrancy. HD68B09- M PU (Micro Processing Unit) The HD6809 is a revolutionary high performance 8-bit microprocessor which supports modern programming techniques such as position independence. HD6809. and modular programming. MC68A09 and MC68B09 A.

. ..RES NMI _ .XTAL EXTAL MRDY '----. ...-----------------------------------------HD6809~ HD68A09. .. or 16-bit Constant Offsets 8. HD68B09 0. 5..DMA/BREQ R/iii HALT BA BS . 8. . .. or 16-bit Accumulator Offsets • • • • • • • Auto-Increment/Decrement by 1 or 2 Improved Stack Manipulation 1464 Instructions with Unique Addressing Modes 8 x 8 Unsigned Multiply 16-bit Arithmetic Transfer/Exchange All Registers Push/Pull Any Registers or Any Set of Registers Load Effective Address • BLOCK DIAGRAM ~Vcc +--vss . E ~--""Q 393 ...

4 - - 2.H Input "Low" Voltage Input leakage Current Three State (Off State) Input Current V'L Except EXTAl.0 - -20 Supply Voltage Input Voltage V'H * ~- Operating Temperature ----. it could affect reliability of lSI. Normal operation should be under recommended operating conditions.Vee -0.2 Vee 4.2 4.8 H068809 min tvP* max 2.5 -2.4 - - 2.3 . BA.3 -+7.) Item Input "High" Voltage Symbo' Except RES RES V . Cin Ao-A.8 V .0 15 10 - - 12 2.BS Cout I LOAO""2mA Vin""OV.0 15 10 - - 12 - - - - - 7 0.-.5 -100 -10 Unit - 10 7 0.. Output "High" Voltage Ao-A.8 - V - 2. f""1MHz i' 394 min 2. Topr max Unit - V 5. Except Do -D.2 4.25 0.0 5.A.8 HD68A09 min tvP* max 2.s' RIW. Vee""min I LOAO=-100".A -10 10 100 -100 - 10 100 -10 -100 10 100 ".4 - - 2. a. • RECOMMENDED OPERATING CONDITIONS Item Symbol min typ Vee * V'L * 4.4 - 2. Ta = -2G-+75°C.4V.75 -0.5 - 2.- I Logic -_ _____ L~ .5 ". XTAl 0 0 -0.0 -0.5 1. If these conditions are exceeded. Ta""25°C.HD88A09.s' RIW. unless otherwise noted.5 1.4 - 2.5 2.+75 -55 .5 1.0.Vce * - Vce * 25 75 V °c * With respect to Vss (SYSTEM GND) • ELECTRICAL CHARACTERISTICS • DC CHARACTERISTICS (Vee =5V±5%.0 .0 Vee -0.3 2. VSS = OV. Vee""min I LOAO""-145". HD88B09----------------------------------------• ABSOLUTE MAXIMUM RATINGS Item Symbol Value Unit Vee * Vin * -0. Vee""max Vin""0.+150 V Supply Voltage Input Voltage Operating Temperature Topr Tstg Storage Temperature V °c °c * With respect to Vss (SYSTEM GND) (NOTE) Permanent lSI damage may occur if maximum ratings are exceeded.4 V -2.4 - - 2.A - 2.3 0.4 - - - - - 10 - 7 0.0 -0. BS Output Capacitance Vin""0-5. E 'VOH BA.Vee 4.4 - - 2.. lin ITS' Ao-A 1s ' R/W Do-O.A.25V.4-2.3-+7.. Vee""min Output "low" Voltage Power Dissipation Input Capacitance Test Condition VOL Po Do-D.5 HD6809 typ* max - Vee Vee 0.3 -2..0 -20 .2 .HD8809.0 15 10 - 12 10 V V W pF pF . Vee""max I LOAO""-205#.A.

BUS TIMING Item Address Delay Address Valid to QHigh Peripheral Read Access Time (tUT-tAO-tOSR=tACC) Data Set Up Time (Read) Input Data Hold Time Address Hold Time Ao-A ls . VSS = OV.!':101 tpCSR tpCSO tPCr. PROCESSOR CONTROL TIMING Item MRDY Set Up Time Interrupts Set Up Time HALT Set Up Time RES Set Up Time DMA/BREQ Set Up Time Processor Control Rise and Fall Time Crystal Oscillator Start Time Symbol Test Condition tpCSM tpr.4 - Cycle Time tcyc 1000 Total Up Time tUT 975 - Processor Clock "High" tPWEH 450 Processor Clock" Low" tpwEL 450 E Rise and Fall Time tEr. 3 Ta=-20-0°C Fig. 3 - max min typ 4 0. unless otherwise noted. 2.tof - - 25 - QLow to E Falling tOE 200 - - 133 min typ max 165 - ns - ns - ns 20 ns 125 ns ns 2. Fig. RtW Data Delay Time (Write) Output Hold Time Symbol tAO tAO tACC Fig. 6-Fig. Fig. HD68B09 • AC CHARACTERISTICS (VCC=5V±5%. 14. Fig. 3 Ta=0-+75°C Fig.4 - 8 10000 500 - 10000 - max MHz ns - 480 - - 220 - 210 25 - - - 220 - - 25 - 20 ns - 100 - - ns min typ max 110 ELow to QHlgh Time tAVS - - 250 - Q Clock "High" tpWOH 450 - - 280 Q Rise and Fall Time tor. tpCf tRC Fig. Fig. 15 395 HD6809 HD68A09 min 125 200 200 200 125 typ max - - - min 125 140 140 140 125 - - 100 - - - 50 - - - - HD68B09 - max - - - - Unit ns ns ns ns ns . CLOCK TIMING HD6809 Item Symbol HD68A09 HD68B09 Test Condition Unit min typ Frequency of Operation (Crystal or External Input) fXTAL 0.4 - 10000 667 - - 640 - 280 25 - 295 max min typ 6 0. HD68A09. 3 Fig. 3 tDDW tOHW Fig.3 Ta=-20-0°C HD68A09 HD68B09 min typ max - - 200 - - 140 - 25 - 15 - 440 - - 330 - 60 10 - - - - 40 10 20 - - 20 10 - - 10 20 - - 10 - - - 225 - - 30 - - 30 - - 20 - - 20 - 50 tOSR tOHR tAH HD6809 Test Condition 695 - 80 10 - Unit - - ns ns ns - ns ns - ns - ns 145 30 - - ns - 20 - - ns typ max tyD - - min 125 110 110 110 125 - - 100 - - 100 ns 30 - - 30 ms 180 - ns 3. 10 Fig. 2.) 1.-----------------------------------------HD6809. tEf Fig. Fig.!': tpr. Ta = -20~+75°C. 2.3 Ta-0-+75°C Fig. 2.

C includes Stray Capacitance. Certain instructions concatenate the A and B registers to form a single 16-bit accumulator. The content of this register appears at the higher address outputs (As-At 5) during Direct Address~ ing Instruction execution. This is referred to as the D register. E.lid *Hold time for SA. B. .lid *Hold time for SA. under program control. Figure 2 Read Data from Memory or Peripherals ~NotV. • Direct Page Register (DP) The Direct Page Register of the HD6809 serves to enhance the Direct Addressing Mode.0.30pF (SA. AiW) • A" 11kn (00 . the HD6809 adds three registers to the set available in the HD6800. This allows the direct mode to be used at any place in memory. D) The A and B registers are general purpose accumulators which are used for arithmetic calculations and manipulation of data.) 16kn (A. • Accumulators (A.HD6809.0" E. 0) 90pF (Ao . the User Stack pointer and a second Index Register. HD68A09. and is fonned with the A register as the most significant byte. all bits of this register are cleared during Processor Reset.ov Test Point • C . A/W) 24kn (SA. HD68B09----------------------------------------s. SS) o------4I~---4I~-_M~_4 A All diodes are 1S20 749 or equivalent. 0. 396 . To ensure HD6800 compatibility. Figure 1 Bus Timing Test Load -r RiW _ _ _ ~NotV.Au. Figure 3 Write Data to Memory or Peripherals • PROGRAMMING MODEL As shown in Figure 4. as not specified. SS not specified. SS) 130pF (00 . The added registers include a Direct Page Register.Au.

/ ~ D 7 0 D_P_ _ _ ~ L . • Bit 5 (H) Bit 5 is the half-carry bit. and SWI all are set I to a one. This address may be used to point to data directly or may be modified by an optional constant or register o 15 x- Index Register Y ._________________________________________ HD6809. • Carry Overflow L . • CONDITION CODE REGISTER DESCRIPTION • Bit 0 (C) Bit 0 is the carry flag. S) may be used as index registers.. Both Stack Pointers have the same indexed mode addressing capabilities as the X and Y registers.. S) The Hardware Stack Pointer (S) is used automatically by the processor during subroutine calls and interrupts. SUB. U. SBC) and is the complement of the carry from the binary ALU. IRQ. Thus..User Stack Pointer Po. and is set to a one if the resul t of the previous operation was identically zero. The state of this flag is 397 . SWI2 and SWI3 do not affect I.Index Register ) U . During some indexed modes.. Bit 3 (N) Bit 3 is the negative flag.. C is also used to represent a 'borrow' from subtract like instructions (CMP. • Program Counter The Program Counter is used by the processor to point to the address of the next instruction to be executed by the processor.. in contrast to the HD6800 stack pointer. but also support Push and Pull instructions." S . The 16-bit address in this register takes part in the calculation of effective addresses. NEG.g. and is used to indicate a carry· from bit 3 in the ALU as a result of an 8-bit addition only (ADC or ADD). • Index Registers (X... I_ _ _ _ _ 7 Direct Page Register 0 I E IF I H I I I N I z I V I C I cc - Condition Code Register Figure 4 Programming Model of The Microprocessing Unit • Stack Pointer (U. NMI. RES. • Bit 2 (Z) Bit 2 is the zero flag.. The User Stack Pointer (U) is controlled exclusively by the programmer thus allowing arguments to be passed to and from subroutines with ease. HD68B09 offset. Relative Addressing is provided allowing the Program Counter to be used like an index register in some situations.Entire Flag Figure 5 Condition Code Register Format Bit 4 (I) Bit 4 is the IRQ mask bit. This overflow is detected in an operation in which the carry from the MSB in the ALU does not match the carry from the MSB-1. Y. Y) The Index Registers are used in indexed mode of addressing. 5.. See Fig. • Bit 1 (V) Bit 1 is the overflow flag. the contents of the index register are incremented and decremented to point to the next item of tabular type data. This bit is used by the DAA instruction to perform a BCD decimal add adjust operation. R..".Zero L -_ _ _ _ Negative L -_ _ _ _ _ IRQ Mask L -_ _ _ _ _ _ _ Half Carry L-_ _ _ _ _ _ _ _ FIRQ Mask ' . • • Condition Code Register The Condition Code Register defines the State of the Processor at any given time. The processor will not recognize interrupts from the ~ line if this bit is set to a one. HD68A09. and is set to a one by an operation which causes a signed two's complement arithmetic overflow. a negative two's-complement result will leave N set to a one.~.Hardware Stack Pointer PC I A \ Program Counter B Accumulators . which pointed to the next free location on the stack. and is usually the carry from the binary ALU.. This allows the H06809 to be used efficiently as a stack processor. greatly enhancing its ability to support higher level languages and modular programming... FIRQ. The stack pointers of the HD6809 point to the top of the stack. All four pointer registers (X.. which contains exactly the value of the MSB of the result of the preceding operation.

a halted state (BA· BS=I) can be achieved by pulling HALT "Low" while ~ is still "Low". See Figs. and when set to a one indicates that the com{>lete machine state (all the registers) was stacked. SWI. When the processor does not require the bus for a data transfer. While halted. All address bus drivers are made high impedance when output Bus Availalbe (BA) is "High". and RES all set F to a one. SWI. The BS output signal. Table 2 MPU State Definition • BA BS 0 0 1 1 0 1 0 1 MPU State Normai (Running) Interrupt or RESET Acknowledge SYNC Acknowledge HALT or Bus Gfant Interrupt Acknowledge is indicated during both cycles of a hardware-vector-fetch (RES. • • Address Bus (Ao -A 15 ) Sixteen pins are used to output address information from the MPU onto the Address Bus. 7. This higher threshold voltage ensures that all peripherals are out of the reset state before the Processor. • SIGNAL DESCRIPTION Power (Vss. Because the HD6809 Reset pin has a Schmitt-trigger input with a threshold voltage higher than that of standard peripherals. During initial power-on.HD6809. The processor will not recognize interrupts from the FIRQ line if this bit is a one. DMA/BREQ). 6. as is also "High" which indicates the processor is in the Halt or Bus Grant state. when decoded with BA. the processor will reach the last cycle of the instruction (by reverse cycle stealing) where the machine will then become halted. IfDAM/BREQ and HALT are both pulled "Low". BS) The BA output is an indication of an internal control signal which makes the MOS buses of the MPU high impedance. The E bit of the stacked CC is used on a return from interrupt (RT!) to determine the extent of the unstacking. HD68B09----------------------------------------Table 1 Memory Map for Interrupt Vectors undefined in all subtract-like instructions. it will output address FFFF16 . During the Halt state Q an~ continue to run normally. the current E left in the Condition Code Register represents past action. Each pin will drive one Schottky TTL load or four LS TTL loads. See Table 1. R/W = "High". this is a "dummy access" or VMi\ cycle. IRQ) although DMA/BREQ will always be accepted. FIRQ. Bus Available. SWI3). the Reset line should be held "Low" until the clock oscillator is fully operational. and typically 130 pF. and typically 90 pF. If the MPU is not running (RES. Refer to Figs. Sync Acknowledge is indicated while the MPU is waiting for external synchronization on an interrupt line. and NMI or RES will be latched for later response. and BS = "Low". 398 . SWI2 and SWI3 do not affect·F. FIRQ. as opposed to the subset state (pC and CC). the MPU will not respond to external real-time requests (FIRQ. The Reset vectors are fetched from locations FFFE16 and FFFF16 (Table 1) when Interrupt Acknowledge is true. This signal does not imply that thr. as shown in Fig. 8 and 16. while VCC is +5. Halt/Bus Grant is true when the HD6809 is in a Halt or Bus Grant condition. This signal. 2 and 3). Reset (RES) A "Low" level on this Schmitt-trigger input for greater than one bus cycle will reset the MPU. R/W is valid on the rising edge of Q. • Read/Write (R/W) This signal indicates the direction of data transfer on the data bus. bus will be available for more than one cycle. When halted. • Bit 7 (E) Bit 7 is the entire flag. Memory Map For Vector Locations • Bit 6 (F) Bit 6 is the FIRQ mask bit. Therefore. Bus Status (BA. NMI. Addresses are valid on the rising edge of Q (see Figs. (BA • BS=I). SWI2. represents the MPU state (valid with leading edge of Q). HD68A09. Each pin will drive one Schottky TTL load or four LS TTL loads. • • Data Bus (Do -0 7 ) These eight pins provide communication with the system bi-directional data bus. plus decoding of the lower four address lines. NMI.0V ±5%. See Fig. iRO. an additional dead cycle will elapse before the MPU acquires the bus. When BA goes "Low". MS LS FFFE FFFC FFFA FFF8 FFF6 FFF4 FFF2 FFFO FFFF FFFD FFFB FFF9 FFF7 FFF5 FFF3 FFF1 Interrupt Vector Description RES NMI SWI IRQ FIRQ SWI2 SWI3 Reserved • HALT A "Low" level on this input pin will cause the MPU to stop running at the end of the present instruction and remain halted indefinitely without loss of data. Ved Two pins are used to supply power to the part: VSS is ground or 0 volts. iRQ. 2 and 3. R/W is made high impedance when BA is "High". can provide the user with an indication of which interrupt level is being serviced and allow vectoring by device. the BA output is driven "High" indicating the buses are high impedance. a simple R/C network may be used to reset the entire system. A "Low" indicates that the MPU is writing data onto the data bus.

Cout :r: c m CO :a:o CD :::t C m 7 Crystal Connections and Oscillator Start Up CO m o CD .Vee lIB" --+---: W r' Ad::" \\\\\\\ ANi . J.75V Vcc E :::t C RES m CO tAC o ~ HD6809 YI 8 MHz 6 MHz 4 MHz Figu~ Cin Cout 18pF±20% 18 pF ± 20% 22pF±20% 22 pF ± 20% 22pF±2091: 22 pF ± 20% 381 VI 39 o YnJ.\\S\\\S\ssf~ ~~ N\\\\\\\~ SA \\\\\\\\s{~ \\'L\\mss:~ rs VMA I \ \lUX rl I \ _ _ _ __ hgure 6 RES Timing W <0 <0 4.

.. 2nd To Last Last Cycle Of Cycle Of Current Current Dead ~1. J ' _ _ ' ' _ IXH DP ACCB ACCA ceR c \~---------------------------------------------=--~I I Figure 9 fRO and NMllnterrupt Timing 400 \ ... . HD88A09.~ln~st~ . and also has a higher priority than FIRQ. the interrupt will not be recognized until the next cycle. 9.. the entire machine state is saved on the Fig..J''.._. .~I-. Data Bus I'----~---- c::x::)------ s Instruction Opcode Figure 8 HALT and Single Instruction Execution for System Debug A~. A non-maskable interrupt cannot be inhibited~ the program...J"__"___J'_ __.HD8809. an NMI will not be recognized until the first program load of the Hardware Stack Pointer (5).-~Jf~________~H=a~lw~d~__________~~~~--~--~~~~~~~~Ha=l=w~d-- a ~--~J~---------------c::x::)~----- Address Bus Fetch Execute r---~~--~~------~r~-------------------------------JI \.i BS ______________--ir-----~If'------------------~.J'-~"___"___J \ __.. During recognition of an NMI. See A negative edge on this input requests that a non-maskable interrupt sequence be generated....."s~--~..~ln=st~·~.. The pulse width of NM1 "Low" must be at least one E cycle. HD88B09----------------------------------------• Non Maskable Interrupt (NMI)* hardware stack.._--v_--~--~--~r_~~--~--~­ Bus FFFF 5P-1 5P-t 5P-3 5P-4 5P-5 5P-6 5P-7 8P-8 5P-9 5P-10 5P-11 5P-12 FFFF ~~~~~: ~~~~~li: FFFF NewPC PC+' Data Bus ___" ___. After reset.J'o_ InSlructlon RIW M§Y BA ::ss\\SS\ BS \'SSSSSS\ PCl PCH USl USH IYl IYH IXl _''_~''_ __J\.A__J \ __.~Cy~c~le~._.____________ .J''___''_~''___J\.~~J_--~--~--~~~~--v_--~--_v--~r_-v_--~--~--~r_~.-______1 f BA _ _ _ _ _ _ _ _ _ _ _ _.. IRQ or software interrupts..••~I. __J'_ __.J'I.. If the NMI input does not meet the minimum set up with respect to Q.

Alternately. See Fig. and is fast in the sense that it stacks only the contents of the condition code register and the program counter.--~. 12 to prevent the induction from these lines and perform the correct oscillation. Normal oscillation may be disturbed when E or Q signal is [ feedbacked to pin 38 and 39. HD88A09.g. the pin EXTAL may be used as a TTL level input for external timing by grounding XTAL.------- Figure 10 FIRQ Interrupt Timing • Fast-Interrupt Request (FIRO)* A "Low" level on this input pin will initiate a fast interrupt sequence provided its mask bit (F) in the CC is clear. HD6809 • XTAL.---~. EXTAL These inputs are used to connect the on-chip oscillator to an external parallel-resonant crystal. Cout must be placed 1 Figure 11 Board Design of the Oscillation Circuit. IRQ also has a lower priority than FIRQ. near the LSI as much as possible. See Fig..~--~. 2) Pin 38 and 39 signal line should be wired apart from other Signal line as much as possible. Again.--~r---~.. HD88B09 a A~r_~~~~~--~. a delay of at least one bus cycle will occur before the interrupt is serviced by MPU. The crystal or external frequency is four times the bus frequency. <THE FOLLOWING DESIGN MUST BE AVOIDED> A silUlalline or a power source line must not cross or go near the oscillation circuit line as shown in Fig.. See Fig. EXT AL and other pins should be over 10Mil. The resistance among XT AL. Proper RF layout techniques should be observed in the layout of printed circuit boards. 1) Crystal oscillator and load capacity Cin. Don't wire them in parallel. This se~nce has priority over the standard Interrupt Request (IRQ). 7.--~.'-____----J/ BA~ BS~ I \\. the interrupt service routine should clear the source of the interrupt before doing an RTI. 10. < NOTE FOR BOARD DESIGN OF THE OSCILLATION CIRCUIT> In designing the board. except during cycle stealing operations (e.-----------------------------------------HD8809.~-- Bus Data Bus _ 1 ' .' Instruction RlWmssw V'MA PCl PCH VMA CCR New PCH New pel VMA ht Inst. From this point. The interrupt service routine should clear the source of the interrupt before doing an RTI. FIRQ and IRQ requests are latched by the falling edge of every Q. Since IRQ stacks the entire machine state it provides a slower response to interrupts than FIRQ.~--~~--~. Of Interrupt Service Routine . the following notes should be taken when the crystal oscillator is used. DMA) where only NMI is latched. 401 . r-~~~~__~ICO~ ch • NMI._ . 9. Normal oscillation may be disturbed when external noise is] [ induced to pin 38 and 39.---~~--~.---~. • Interrupt Request (lRO)* A "Low" level input on this pin will initiate an interrupt Request sequence provided the mask bit (I) in the CC is clear..

.t fr-l102~~V pc r .SV 1 : E X-_O_os_V_ _ _ _ _-J a l--... Q is a quadrature clock signal which leads E.--. HD88B09---------------------------------------• «m iiii e..HD8809. 1\ • MRDY This input control signal allows stretching of E and Q to extend data-access time.----r-1--if~S----'I 2.4V"\ I I a MRDY I I tPCfj ~ \\\\\~ Figure 14 MRDY Timing 402 ll.. 14. 13.. A maximum . Data is latched on the falling edge of E.. Addresses from the MPU will be valid with the leading edge of Q. Timing for E and Q is shown in Fig.:. : -----Signal C Cout ~ t-~~-----fcih HD6809 Figure 12 Example of Normal Oscillation may be Disturbed..... ~ I I iii iii E. Start OJ Cycle I End of Cycle' Latch Data) I ~ O.. Must be avoided.. thus allowing interface to slow memories..Q E is similar to the HD6800 bus timing signal t/>2.. E and Q may be stretched in integral multiples of quarter (1/4) bus cycles. HD88A09. as shown in Fig. E and Q operate normally while MRDY is "High". When MRDY is "Low".1~~----~ ~~ I I I tAVS \ I ~·---~I------ I Address Valid Figure 13 E/Q Relationship f~ \-----1 !'------\-----11 \\. Q has no parallel on the HD6800.

False memory accesses may be prevented during and dead cycles by developing a system DMAYMA signal which is "Low" in any cycle when BA has changed. 15. When BA goes "Low" (either as a result of DMA/BREQ = "High" or MPU self-refresh). the DMA controller will request to use the bus by asserting DMA/BREQ pin "Low" on the leading edge of E. When the MPU replies by setting BA and BS to a one. MRDY may also be used to stretch clocks (for slow memory) when bus control has been transferred to an external device (through the use of HALT and DMA/BREQ). but is a system requirement for DMA. to allow transfer of bus mastership without contention. HD68B09 stretch is 10 microseconds.BS DMAVMA* ADDA (MPU) ADDA (DMAC) \ / ~ / ) C ( *DMAVMA is a signal which is developed externally. • DMA/BREQ The DMA/BREQ input provides a method of suspending execution and acquiring the MPU bus for another use. this inhibits slowing the processor during "don't care" bus accesses.-----------------------------------------HD6809. Another dead cycle will elapse before the MPU accesses memory. that cycle will be a dead cycle used to transfer bus mastership to the DMA controller. Transition of DMA/BREQ should occur during Q. the DMA device should be taken off the bus. This DEAD DEAD DMA MPU E Q DMA/BAEQ BA. as shown in Fig. Self-refresh requires one bus cycle with a lead- MPU ing and trailing dead cycle. The requesting device will now have up to 15 bus cycles before the MPU retrieves the bus for self-refresh. HD68A09. 16. During nonvalid memory access (WA cycles) MRDY has no effect on stretching E and Q. A "Low" level un this pin will stop instruction execution at the end of the current cycle. Typically. Figure 15 Typical DMA Timing «14 Cycles) 403 > . • MPU OPERATION During normal operation. The MPU will acknowledge DMA/BREQ by setting BA and BS to "High" level. See Fig. the MPU fetches an instruction from memory and then executes the requested function. Typical uses include DMA and dynamic memory refresh.

• Extended Addressing In Extended Addressing. however. DAA. only 256 locations (one page) can be 404 .BS ~ I I I I I ~~----------------------------------------------~~------------ *DMAVMA is a signal which is developed externally. SWI3. Fig.HD8809. Software instructions that alter nonnal MPU operation are: SWI. the contents of the two bytes immediately following the opcode fully specify the 16-bit effective address used by the instruction. • Immediate Addressing In Immediate Addressing. Since only one byte of address is required in direct addreSSing. this mode requires less memory and executes faster than extended addressing. • ADDRESSING MODES The basic instructions of any computer are greatly enhanced by the presence of powerful addressing modes. SWI2. "1" level of indirection may be added to Exten. Examples of instructions with Immediate Addressing are: LDA #$20 LDX #$FOOO LDY #CAT (NOTE) # Signifies Immediate addressing. For example. HALT or DMA/BREQ can also alter the normal execution of instructions.Refresh DMA Timing (Reverse Cycle Stealing) sequence begins at RES and is repeated indefinitely unless altered by a special instruction or hardware occurrence. Examples of Extended Addressing include: CAT LDA STX MOUSE LDD $2000 • Extended Indirect As a special case of indexed addressing (discussed below). [CAT] LDA LDX [$FFFE] STU [DOG] • • Direct Addressing Direct addressing is similar to extended addressing except that only one byte of address follows the opcode. Note that the address generated by an extended instruction defines an absolute address and is not position independent. This byte specifies the lower 8-bit of the address to be used. the HD6809 has 59 basic instructions. The HD6809 uses both 8 and 16-bit immediate values depending on the size of argument specified by the opcode. SWI. An interrupt. CWAI. the effective address of the data is the location immediately following the opcode (i. HD68A09.. In Extended Indirect. I I I I I I I I I I I I E I ani DMA/BREQ I ~~I~~ I ____________________________________________~I__~__~~----------- --Y I DMAVMA* r I I BA. it recognizes 1464 different variations of instructions and addressing modes. 17 illustrates the flow chart for the HD6809. the opcode of the instruction contains all the address information necessary. $ signifies hexadecimal value. The following addressing modes are available on the HD6809: (1) Implied (Includes Accumulator) (2) Immediate (3) Extended (4) Extended Indirect (5) Direct (6) Register (7) Indexed Zero-Offset Constant Offset Accumulator Offset Auto Increment/Decrement (8) Indexed Indirect (9) Relative (10) Program Counter Relative Implied (Includes Accumulator) In this addressing mode. Figure 16 Auto . Of course. RTI and SYNC. the data to be used in the instruction immediately follows the opcode of the instruction). the two bytes following the postbyte of an Indexed instruction contain the address of the data.e. HD68B09----------------------------------------- ~IDEAOI MPU IDEA~OMA___ IOEAOII-------------14 OMA cvcles------------il. and CLRB. but is a system requirement for DMA.ded Addressing. ASRA.. The HD6809 has the most complete set of addressing modes available on any microcomputer today. Examples of Implied Addressing are: ABX. The addressing modes support modern programming techniques. The upper 8-bit of the address are supplied by the direct page register.

f'il!m. Figure 17 Flowchart for HD6809 Instruction BS o C CD 00 l> o U) o l: C CD 00 .~ I>->DPR l-+F.:D oU) . f l-+RJW Clr TiIJM Logic ~ ~ o U1 l: C CD 00 o U) ~ HD6809 Interrupt Structure Bus State 0 I nterrupt or Reset Acknowledge I 0 Sync Halt/Bus Grant (NOTE) I BA Running Asserting RES will result in entering the reset sequence from any point in the flow chart.

Fig. X..PC + 8 Bit Offset EA = .R 1RR00110 1 0 lA.R + 5 Bit Offset 1 R R 0 0 0 1 0 . and sometimes PC) is used in a calculation of the effective address of the operand to be used by the instruction. Indirect ' .R 1 RROOO10 2 0 Decrement By 1 . Some examples of direct addressing are: LDA $30 $10 (Assembler directive) SETDP LDB $1030 <CAT LDD Indexed Addressing Mode Post-Byte Register Bit (NOTE) < is an assembler directive which forces direct ad- dressing. This is called a postbyte...PCRl 1xx11100 4 1 16 Bit Offset n.Addressl 1 ------- EA EA Addressing Mode Field Indirect Field (Sigh bit when b7 = 0) Non Indirect {o.Register Field: RR 00 = X 01 = y 10= U 11 = S x = Don't Care • Indexed Addressing In all indexed addressing..HD6809. B Exchanges A with B PSHS A. Y Push Y. HD68B09----------------------------------------accessed without redefining the contents of the DP register. Rl 1 RR10110 4 0 B Register Offset B.-R 1 R R 0/1 0 0 1 1 ..Rl 1RR10011 6 0 Constant Offset F rom PC (2's Complement Offsets) a Bit Offset n.- [n. HD68A09... Rl 1RR11000 16 Bit Offset n.... R 1 RR01001 4 2 [n..... Rl 1RR11011 7 0 Increment By 1 .. Y. Rl 1 RR10101 4 0 o Register Offset D.R ++ 1 RROOO01 3 0 .. B and A onto S X...R ++ EA = . Five basic types of indexing are available and are discussed below.R + ACCB Offset EA = . Some examples of register addressing are: X.. direct addressing on the HD6809 is compatible with direct addressing on the HD6800. Y Transfers X into Y TFR EXG A. 1 . R 1 RR01000 1 1 [n.. Table 3 gives the assembler form and the number of cycles and bytes Figure 1a Index Addressing Postbyte Register Bit Assignments Table 3 Indexed Addressing Mode Non Indirect Type Forms Constant Offset From R (2's Complement Offsets) Accumulator Offset From R (2's Complement Offsets) Auto Increment/Decrement R Assembler Form Indirect + + Postbyte OP Code -# No Offset . X. B.. one of the pointer registers (X. D Pull D. R + 8 Bit Offset EA = .R 1RR01011 4 0 [0. 406 .R 1 RR00101 1 0 [B..R 1 RROO011 3 0 L .. PCRl Extended Indirect [nl 10011111 5 2 R = X.R + 16 Bit Offset EA = .R + D Offset EA =. U.-. Rl 1RR11001 7 2 A Register Offset A. PCR 1xx01100 1 1 [n.R 1 R R 1 0 0 R R 0/1 0/1 0 1 0 1 0 1 1 R R 0/1 0 1 1 0 1 R R 0/1 1 0 0 0 1 R R 0/1 1 0 0 1 1 R R 0/1 1 0 1 1 1 x 1 1 0 0 x x x 011 1 0/1 1 1 0 1 R R 1 1 1 1 1 = .... Indirection is not allowed in direct addressing. Since the DP register is set to $00 on Reset. Y. • Register Addressing Some opcodes are followed by a byte that defmes a register or set of registers to be used by the instruction. 18 lists the legal formats for the postbyte. U orS x = Don't Care ~ and - - RR: 00= X 01 = Y 10= U 11 = S :# indicate the number of additional cycles and bytes for the particular variation.R + 0 0 0 1 .PC + 16 Bit Offset EA = [. not allowed LR ++l 1 RR10001 6 0 not allowed Decrement By 2 . X.R + 0 Offset = . The postbyte of an indexed instruction specifies the basic type and variation of the addressing mode as well as the pointer register to be used. PCR 1xx01101 1xx11101 a 2 16 Bit Address 5 2 .R + ACCA Offset EA = .R) + + Postbyte OP Code -# 1 RR10100 3 0 defaults to a-bit 4 1 a Bit Offset n. Y. R ORRnnnnn 1 0 Assembler Form [. S...R + 1 RROOOOO 2 0 Increment By 2 . and Y from U PULU 7 6 5 4 0 R R 1 R R 1 R R 3 2 1 0 x x x x x 0 0/1 0 0 0 0 .R 1 RR00100 0 0 5 Bit Offset n.

S LDY 300.X LDX -2. post-increment nature of these modes allow them to be used to geate additional software stacks that behave identically to. Zero-Offset Indexed In this mode. the pointer register is decremented prior to use as the address of the data. or for the creation of software stacks.X] LDD [10. Before Execution A = xx (don't care) X= $FOOO $0100 LDA [$IO. As in relative addressing.X LDU CAT. The predecrement.--S • Indexed Indirect All of the indexing modes with the exception of auto increment/decrement by one. or a ±4·bit offset may have an additional level of indirection specified. In indirect addressing. Some examples are: LDA B.Y LDX D. All of memory can be reached in long relative addressing as an effective address is interpreted modulo 216 • Some examples of relative addressing are: CAT DOG RAT RABBIT BEQ BGT LBEQ LBGT • • •NOP CAT DOG RAT RABBIT (short) (short) (long) (long) NOP • Program Counter Relative The PC can be used as the pointer register with 8 or 16-bit signed offsets. is most efficient in use of bytes and cycles. moving data.. The use of auto decrement is similar to that of auto increment. The pointer register's initial content is unchanged by the addition. are scanned from the "High" to "Low" addresses.-Y LDX . This addressing mode is useful in stepping through tables. The advantage of an accumulator offset is that the value of the offset can be calculated by a program at run-time. Some examples of indexed indirect are: LDA [. Examples are: LDD O.X++] • Relative Addressing The byte(s) following the branch opcode is (are) treated as a signed offset which may be added to the program counter.Y++ STD LDB . therefore. Program execution continues at the new location as indicated by the PC. the effective address is contained at the location specified by the contents of the Index register plus any offset.S] LDA [B. The contents of both the accumulator and the pointer register are unchanged by the addition. Three sizes of offsets are available: 5-bit (-16 to +15) 8-bit (-128 to +127) 16-bit (-32768 to +32767) The two's complement 5-bit offset is included in the postbyte and.Y LEAX B. The two's complement 16-bit offset is in the two bytes following the postbyte. HD68A09. The two's complement 8-bit offset is contained in a single byte following the postbyte.the U and S stacks. B or D) and the contents of one of the pointer registers are added to form the effective address of the operand. short (I byte offset) and long (2 bytes offset) relative addressing modes are available. The postbyte specifies which accumulator to use as an offset and no additional bytes are required. the pointer register contains the address of the operand. In most cases the programmer need not be concerned with the size of this offset since the assembler will select the optimal size automatically. HD68B09 added to the basic values for indexed addressing for each variation.-----------------------------------------HD6809.X Auto Increment/Decrement Indexed In the auto increment addressing mode. after the pointer register is used it is incremented by one or two. the A accumulator is loaded indirectly using an effective address calculated from the Index register and an offset. In the example below. In auto decrement. The effective address is then used as the address of the operand or data.Y] LDD [.g. auto increment/decrement by I indirect). Some examples of the auto increment/decrement addressing modes are: LDA . If the branch condition is true then the calculated address (pC + signed offset) is loaded into the program counter. This is the fastest indexing mode.X] EA is now $FOIO $FOIO $FOll $FI $50 $F ISO is now the newEA $F150 $AA After Execution A = $AA Actual Data Loaded X= $FOOO All modes of indexed indirect are included except those which are meaningless (e. a two's-complement offset and the contents of one of the pointer registers are added to fonn the effective address of the operand. Then. The size of the increment/decrement can be either one or two to allow for tables of either 8 or 16-bit data to be accessed and is selectable by the programmer. Examples of constant-offset indexing are: LDA 23.. the offset is added to the current PC to create the effective address.X+ . etc.X LDA S Constant Offset Indexed In this mode.Y Accumulator·Offset Indexed This mode is similar to constant offset indexed except that the two's-complement value in one of the accumulators (A. but the tables. the selected pointer register contains the effective address of the data to be used by the instruction. Program Counter Relative Addressing is used for writing 407 .

This makes all the features of the internal addressing hardware available to the programmer.. Some of the new instructions and addressing modes are described in detail below: PSHU/PSHS The push instructions have the capability of pushing onto either the hardware stack (S) or user stack (U) any single register.e. Both short (8-bit) and long (16·bit) branches are available. S 10. .. In this mode. when it is executed. Three are denoted as follows: 10.X 001O-Y 0011 . Some of the implications of this instruction are illustrated in Table 4... By writing MSGI. HD88A09.. the number of available opcodes (with different addressing modes) has risen from 197 to 1464. Position independent code can be easily generated through the use of relative branching. U -10. Y -10.TFR/EXG Within the HD6809. i.PeR] ~ou~C~ IDE~TI~AT!ONI • • HD6809 INSTRUCTION SET The instruction set of the HD6809 is similar to that of the HD6800 and is upward compatible at the source code level. if the branch is to be taken.Stu ' .. LEAX/LEA Y /LEAU/LEAS The LEA (Load Effective Address) works by calculating the effective address used in an indexed instruction and stores that address value.. 'MESSAGE' This sample program prints: 'MESSAGE'. Bits 4-7 of postbyte define the source register. any register may be transferred to or exchanged with another of like-size. PCR. the assembler computes the distance between the present address and MSG I...PC +.. HD88B09----------------------------------------position independent programs. Examples are: LDA LEAX 0000 .Pull Order Push Order -+ PC U Y X DP B A CC FFFF .. The byte immediately following the push or pull opcode determines which register or registers are to be pushed or pulled.. Table 4 LEA Examples PUSH/PULL POST BYTE Instruction LEAX LEAX LEAY LEAY LEAU LEAS LEAS LEAX CC A '----... or set of registers with a single instruction. For example: MSG I. as shown in below. an additional level of indirection is available.. rather than the data at that address.D 0001 .increasing memory address . +.. 408 . PCR 0101 1000 1001 1010 1011 - PC A B CC DP (NOTE) All other combinations are undefined and INVALID.. The LEA instruction also allows the user to access data in a position independent manner. PCR] [DOG... in a pointer register. the 8 or 16-bit signed offset is added to the value of the program counter to be used as the effective address. 8-bit to 8-bit or 16-bit to 16-bit. This result is placed as a constant into the LEAX instruction which will be indexed from the PC value at the time of execution. S 5. S Operation Comment X + 10 -+ X X + 500 -+ X Y+A -+Y Y+D -+Y U-l0-+U S-10-+S S + 10 -+ S S+5 -+X Adds 5·bit constant 10 to X Adds 16·bit constant 500 to X Adds 8·bit accumulator to Y Adds 16·bit D accumulator to Y Subtracts 10 from U Used to reserve area on stack L1sed to 'clean up' stack Transfers as well as adds • MUL Multiplies the unsigned binary numbers in the A and B accumulator and places the unsigned result into the 16-bit D accumulator.U 0100 .. Long And Short Relative Branches The HD6809 has the capability of program counter relative branching throughout the entire memory map. but because of the expanded architecture and additional addressing modes.. This unsigned multiply also allows multipleprecision multiplications. 0000 PC S Y X DP B A CC .. the computed offset from the PC will put the absolute address of MSG 1 into the X pointer register. in reverse order. The actual PUSH/pULL sequence is fIXed... This code is totally position independent... Tables related to a particular routine will maintain the same relationship after the routine is moved. Since program counter relative is a type of indexing.PCR TABLE. This allows the program to branch anywhere in the 64k memory map.DP '-------x '--------y .B ' . LDA LDU TRANSFER/EXCHANGE POST BYTE I [CAT. Y D. while bits 0-3 represent the destination register. if referenced relative to the Program Counter..S CAT. No matter where the code is located. The number of opcodes has been reduced from 72 to 59.HD8809. PCR LEAX LBSR PDATA (print message routine) • • MSGI FCC • • PULU/PULS The pull instructions have the same capability of the push instruction. X A.. X 500. each bit defines a unique register to push or pull.

HD68A09. • CYCLE-BY-CYCLE OPERATION The address bus cycle-by-cycle performance chart illustrates the memory-access sequence corresponding to each possible instruction and addressing mode in the HD6809. SWI3. pushes and pUlls . compares. the operation of each opcode will follow the flow chart. If the pending interrupt is maskable (FIRQ. If the pending interrupt is non-maskable (NMI) or maskable (FIRQ.) Next. SWI2. VMA is an indication of FFFF16 on the address bus. LBSR (Branch taken) Cycle # 1 2 3 4 5 6 7 8 9 opcode Fetch opcode + opcode + VMA VMA ADDR VMA STACK (write) STACK (write) DEC (Extended) Cycle # 1 2 3 4 5 6 7 opcode Fetch opcode + opcode + VMA ADDR (read) VMA ADDR (write) 409 • HD6809 INSTRUCTION SET TABLES The instructions of the HD6809 have been broken down into five different categories. . the processor will clear the Sync state and continue processing by executing the next inline instruction. The following examples illustrate the use of the chart. 20. While that opcode is being mternally decoded. They are as follows: 8-Bit operation (Table 5) 16-Bit operation (Table 6) Index register/stack pointer instructions (Table 7) Relative branches (long or short) (Table 8) Miscellaneous instructions (Table 9) HD6809 instruction set tables and Hexadecimal Values of instructions are shown in Table 10 and Table 11. adds. software debugging. Since FIRQ and IRQ are not edge-triggered. so this technique considerably speeds thrOUghput. 19 depicts Sync timing. and software development systems. R/W="High" and BS="Low". stores. These instructions include loads. the processor will clear the Syne state and perform the normal interrupt stacking and service routine. and are prioritized in the following order: SWI. exchanges. and its associated vector fetch. a "Low" level with a minimum duration of three bus cycles is required to assure that the inte~t will be taken. (Mo~t instructions will use the next byte. see Fig. HD68B09 • SYNC After encountering a Sync instruction. the MPU enters a Sync state. Software Interrupts A Software Interrupt is an instruction which will cause an interrupt. stops processing instructions and waits for an interrupt. IRQ) with its mask bit (F or I) clear. memory mapping. IRQ) with its mask bit (F or I) set. 16-Bit Operation The HD6809 has the capability of processing 16-bit data. Each instruc~ion begins with an opcode fetch. trace operations. Fig.-----------------------------------------HD6809. transfers. These Software Interrupts are useful in operating system calls. subtracts. Three levels of SWI are available on this HD6809. the next program byte is always fetched.

.£2!!tinues with this cycle as (M.. if the interrupt is accepted (NM1 or an unmasked FIRQ or IRQ) the opcode address (placed on the bus from cycle M + 1) remains on the bus and interrupt~cessin8. VMA ADDR I (NOTE) R+D i7MA .!Slcle will continue the instruction fetched from the previous cycle. If the associated mask bit is set when the interrupt is requested. If mask bits are clear. a M+1 Address Fetch Data A/W BA BS :{ (NOTE) :=:x=A'--________1 ~~-----------------~r------~-------------------------------See Note 2 tpcs 1.-vk vkwkvk VMA I Stack (Write) Stack (Write) Write operation during store instruction. + wk. Execute Dead Cycle . IRQ and FIRQ must be held low for three cycles to guarantee interrupt to be taken. Opcode + Opcode + Opcode + Opcod. HD68B09----------------------------------------Last Cycle Of Previous Sync Opcode Inst. whwk. . + Opcode + Ope ode + Opcode + Opcod. although only one cycle is necessary to bring the processor out of SYNC.. Fetch I.. Figure 19 Sync Timing ~ Opcode (Fetch) Short Branch Indexed Immediate & Inherent Opcode + Opcode + ACCAOffset ACCBOflset R + 5 Bit R + 8 Bit PC + 8 Bit wh Auto Auto R + 16·Bit Inc/Dec InclDec By 1 By 2 VMA VM wk. Figure 20 Address Bus Cycle-by-Cycle Performance 410 PC + Ex tendltd No Offset 16-8it Indirect VMA -L.I . HD68A09. thi. However. 9 and 10 (Interrupt Timing).I . + 2) on Figs. . . 2.HD6809. I.I SYNC Acknowledge .

HD68A09. VECTOR VMA VJ. Figure 20 Address Bus Cycle-by-Cycle Performance (Continued) Non-Implied ADCA ADCB AOOA AOOB ANOA ANDB BITA BITB CMPA CMPB EORA EORB LOA LOB ORA ORB SBCA SBCB STA STB SUBA SUBB LDD LOS LOU LOX LOY ANOCC ORCC ASL ASR CLR COM DEC INC LSL LSR NEG ROL ROR TST ADDD CMPO CMPS CMPU CMPX CMPY SUBD JSR STD STS STU STX STY VMA STACK VM'A VM'A ADDR + i~~b·~ ADDR + TAO'"rl~rr' Figure 20 Address Bus Cycle-by-Cycle Performance (Continued) 411 .~----~--~--~--~----+---~------------~---+----ff---ASLA ASLB ASRA ASR6 CLRA CLRB COMA COMB DAA DECA DECB INCA INCB LSLA LSLB LSRA LSRB NEGA NEGB NOP ROLA ROLB RORA RORB SEX TSTA TSTB ABX RTS EXG TFR MUL SWI PULU PULS PSHU PSHS RTI CWAI SWI2 SWI3 STACK ADDR I 12XSTACK (wrr) STACK 112 ( IWrite) ~ STACK STACK wkI VMA V A V"fA STACK' (Dumnjv Read) VMA VMA ImA VMA VMA I 12XSTACK (Wre) (VMA I II 1 VECTOR VECTOR VECTOR.fA I I nr~ STACK (Write) (NOTE) STACK': STACK": 12 I~ Address stored in stack pointer before execution. HD68B09 Implied Page ~~. Address set to stack pointer as the result of the execution.-----------------------------------------HD6809.

PSHU (PULS. PULU) instructions. LSLA. R2 = A. TSTB Test accumulator or memory location TFR Rl. ASLA. LSRB Logical shift right accumulator or memory location Unsigned multiply (A x B -+ D) MUL ~emory NEG. DP) (NOTE) A. LSRA. ORB Or memory with accumulator ROL. CC. R Exchange 0 with X. S. CMPB Compare memory from accumulator COM. NEGB Negate accumulator or ORA. CC. U or PC to 0 (NOTE) 0 may be pushed (pulled) to either stack with PSHS. S. ADDB Add memory to accumulator ANDA. R2 =A.HD88A09.HD8809. LOB Load accumulator from memory LSL. R Transfer 0 to X. RORB Rotate accumulator or memory right SBCA. U or PC TFR R. PSHU (PULS. PULU) instructions.ANDB And memory with accumulator ASL. Y. ADCB Add memory to accumulator with carry ADDA. CC or DP may be pushed to (pulled from) either stack with PSHS. DECA. TSTA. ASRA. U or PC LDD Load 0 accumulator from memory SEX Sign Extend B accumulator into A accumulator STD Store 0 accumulator to memory SUBD Subtract memory from 0 accumulator TFR 0. Y. I NCA. EORB Exclusive or memory with accumulator EXG Rl. DP) I Ne. COMB Complement accumultor or memory location DAA Decimal adjust A accumulator DEC. B. COMA. NEGA. HD88B09---------------------------------------Table 58-Bit Accumulator and Memory Instructions Mnemonic(s) Operation ADCA. STB Store accumulator to memory SUBA. 8. I NCB Increment accumulator or memory location LOA.BITB Bit test memory with accumulator CLR.SBCB Subtract memory from accumulator with borrow STA. DECB Decrement accumulator or memory location EORA. R2 Transfer Rl to R2 (Rl. ASLB Arithmetic shift of accumulator or memory left ASR. RORA.D Transfer X. S. LSLB Logical shift left accumulator or memory location LSR. CLRA. ROLA. SUBB Subtract memory from accumulator TST. R2 Exchange Rl with R2 (Rl. 412 . CLRB Clear accumulator or memory location CMPA. B. ROLB Rotate accumulator or memory left ROR. Table 6 l6-Bit Accumulator and Memory Instructions Mnemonic(s) Operation ADDD Add memory to 0 accumulator CMPD Compare memory from 0 accumulator EXG 0. Y . ASRB Arithmetic shift of accumulator or memory right BITA.

LBGT Branch if greater (signed) SIGNED BRANCHES BGE. LEAY Load effective address into index register LOS. X. X. S. LBNE Branch if not equal BMI. 0. CC. B.-L-B-L-T-----4---B-ra-nch if less than (signed) UNSIGNED BRANCHES BHI. STU Store stack pointer to memory STX.LBHS Branch if higher or same (unsigned) BEQ. Y. S. X. LBRN Branch never OTHER BRANCHES 413 .LBCC Branch if carry clear BVS. STY Store index register to memory TFR Rl.LBSR Branch to subroutine BRA. U or PC to 0. HD68A09. LEAU Load effective address into stack pointer LEAX. LBRA Branch always BRN. HD68B09 Table 7 Index Register/Stack Pointer Instructions Mnemonic(s) Operation CMPS. LBGE Branch if greater than or equal (signed) BEQ. R2 Transfer 0. LBVC Branch if overflow clear BGT.LBCS Branch if carry set BCC. Y. CC. X. 0.LBPL Branch if plus BCS. CMPU Compare memory from stack pointer CMPX. 0. or PC onto hardware stack PSHU Push A. OP. LBMI Branch if minus BPL. Y. OP. U or PC with 0. Y. OP. CMPY Compare memory from index register EXG Rl. S or PC from user stack STS. B. LOU Load stack pointer from memory LOX. S. B. X. LBLE Branch if less than or equal (signed) -----B-L-T-. U. LBEQ Branch if equal SIMPLE BRANCHES BNE. Y. LBHI Branch if higher (unsigned) BHS. LBEQ Branch if equal BLE. or PC onto user stack PULS Pull A. Y. OP. LBEQ Branch if equal BLS. LBVS Branch if overflow set BVC. Y.LBLO Branch if lower (unsigned) BSR. B. S. LBLS Branch if lower or same (unsigned) BLO. 0. U or PC LEAS. X. U or PC ABX Add B accumulator to X (unsigned) Table 8 Branch Instructions Mnemonic(s) Operation BEQ. X. Y. S. X. LOY Load index register from memory PSHS Push A. CC.-----------------------------------------HD6809. R2 Exchange 0. CC. U or PC from hardware stack PULU Pull A.

HD68A09. SWI2. SWI3 Software interrupt (absolute indirect) SYNC Synchronize with interrupt line 414 .HD6809. then wait for interrupt NOP No operation OReC OR condition code register JMP Jump JSR Jump to subroutine RTI Return from interrupt RTS Return from subroutine SWI. HD88B09----------------------------------------Table 9 Miscellaneous Instructions Mnemonic(s) Operation ANDCC AND condition code register CWAI AND condition code register.

HD68B09 Table 10 HD6809 Instruction Set Table HD6809 ADDRESSING MODES INSTRUCTION/ FORMS IMPLIED - # 3A 3 1 OP ABX DIRECT OP - # EXTENDED IMMEDIATE OP OP - # - # INDEXEO<D OP - # RELATIVE OP 1 0 V C • • • • • t t t t UN~G~ED) ADCA ADCB 99 D9 4 4 2 2 B9 F9 5 5 3 3 89 C9 2 2 2 2 A9 4+ E9 4+ 2+ 2+ A + + ---> A B+M+C--->B ADD ADDA ADDB ADDD 9B DB D3 4 4 6 2 2 2 BB FB F3 5 5 7 3 3 3 8B CB C3 2 2 4 2 2 3 AB 4+ EB 4+ E3 6+ 2+ 2+ 2+ A+M---> A B + M---> B D + M:M + 1---> D AND ANDA ANDB ANDCC 94 D4 4 4 2 2 B4 F4 5 5 3 3 84 C4 1C 2 2 3 2 2 2 A4 4+ E4 4+ 2+ 2+ ASL AS LA ASLB ASL 48 58 2 2 1 1 ASRA ASRB ASR 47 57 2 2 1 1 t t t t t t t t AAM--->A B AM ---> B eCA IMM---> CC t t t t t t t t t • •• tt 00 • • (-r.r' 07 6 2 77 7 3 67 6+ 2+ ~}~ @ t @ t @ t • • • • • • • • BCC BCC lBCC 24 10 24 3 2 5(6) 4 Branch C=O Long Branch C=O BCS BCS LBCS 25 10 25 2 3 5(6) 4 Branch C=1 Long Branch C=1 BEQ BEQ LBEQ BGE BGE LBGE BGT BGT lBGT 2E 10 2E 2 3 5(6) 4 Branch ZV(N<±lV)=O • Long Branch ZV(N (BV)=O BHI BHI lBHI 22 10 22 2 3 5(6) 4 Branch CVZ=O Long Branch CVZ=O BHS BHS 24 LBHS 10 24 BIT BITA BITB BlE BlE lBlE 3 ~ + X---> X ADC ASR 2 H N Z 5 DESCRIPTION -® # 3 2 \27 10 5(6) 4 27 2C 3 2 10 5(6) 4 2C 95 D5 4 4 2 2 B5 F5 5 5 3 3 85 C5 2 2 2 2 I A5 4+ E5 4+ 3 2 5(6) 4 2+ 2+ 2F 10 2F 3 2 5(6) 4 25 10 25 2 3 5(6) 4 Branch Z =1 Long Branch Z==1 Branch N (BV=O Long Branch N(B V=O • • • • • Branch C=O Long Branch C=Q BitTestA(MAA) • Bit Test B (M AB) • B.~h ZVIN(j)VI-' Long Branch ZVIN (BV)=1 Branch C=1 Long Branch C=1 Branch CVZ=1 Long Branch CVZ=1 I' • :. HD68A09.-----------------------------------------HD6809..• BlO BLO LBLO BLS BLS 23 LBLS 10 23 5(6) 4 BLT BLT lBlT 2D 10 2D 2 3 5(6) 4 Branch N (BV=1 Long Branch N (BV=1 • • • • BMI BMI lBMI 2B 10 2B 3 2 5(6) 4 Branch N=1 Long Branch N=1 •• BNE BNE lBNE 3 26 3 '0 26 15161 2 2 4 BPL BPl lBPl 2 2A 3 10 5(6) 4 2A BRA BRA lBRA 20 16 3 5 2 3 BRN BRN LBRN 21 10 21 3 5 2 4 • • Branch N = 0 • long Branch • N=O Branch Always • Long Branch/ • Always Branch Never • Long Branch Never • Branch Z =0 long Branch Z=O • • • • • • • • • •• • • • • • • • • • • • • • • • • • t t t t t t t t t t • • • • • • • • • • • • • • • • • 0 0 • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • t t t • • • • • • • • • • • • • • • • •• • • • • • • • • • • • • • • • • (to be continued) 415 .(f) r-I-) @ t @ t @ t t t t t t t t t t t t 08 6 2 78 7 3 68 6+ 2+ ~) DiJ III "J.

R2 1E 7 2 R1 . • • t •• 0-.-------~ FORMS IMPLIED DIRECT EXTENDED IMMEDIATE INDEXED(t) RELATIVE # OP BSR OP # - # OP - OP # - OP - # OP # -@ Branch V = 0 Long Branch V=O • • • • • • • • • • 3 2 5(6) 4 Branch V = 1 Long Branch V= 1 ••••• ••••• 0-+ A 0. R2@ H-@)~ ) INC INCA INCB INC 4C 5C 2 1 1 A+1-+A B+1-+B M+1-+M EAQ.--------~~~--~~~~--~. • t to. • t to... 2 B6 F6 FC 10 FE FE BE 10 BE 3 3 3 6E JSR 4 8 5 5 6 7 3 4+ 4+ 5+ 6+ 2+ 2+ 2+ 3+ M-A M-+B M: M + 1 -+ D M: M + 1 -+ S 6 6 3 A6 E6 EC 10 EE EE AE 10 AE 5+ 5+ 6+ 2+ 2+ 3+ M: M + 1 -+ U M: M + 1 -+ X M: M + 1 -+ Y 32 33 30 31 4+ 4+ 4+ 4+ 2+ 2+ 2+ 2+ EA@ .. t t t t t t • • t t t • • OC 6 2 7C 7 3 6C 6+ 2+ JMP OE 3 2 7E 3+ 2+ 9D 7 4 4 5 2 BD AD 7+ 2+ Jump to Subroutine.--' •• t t t t t t t t t t t t ~+1-+M .. S EA@..B'tttt No Operation I •••• (11) @ (to be continued) 416 . • t to.B 0-+ M • • • 2 9 3 BVC BVC LBVC 28 10 28 BVS BVS LBVS 29 10 29 CLR CLRA CLRB CLR CMP CMPA CMPB CMPD CMPS CMPU CMPX CMPY COM COMA COMB COM CWAI 43 53 3C DAA 2 2 20 19 2 4A 5A 2 2 OF 6 2 7F 91 D1 10 93 11 9C 11 93 9C 4 4 7 2 2 3 B1 F1 10 B3 11 BC 11 B3 BC 7 3 7 3 6 2 10 9C 7 3 03 6 2 7 3 5 3 5 8 4 3 8 4 8 4 7 3 10 BC 8 4 73 7 3 81 C1 10 83 11 8C 11 83 8C 10 8C 2 2 5 2 2 4 5 4 5 4 4 3 5 4 6F 6+ 2+ A1 E1 10 A3 11 AC 11 A3 AC 4+ 4+ 7+ 2+ 2+ 3+ 7+ 3+ 7+ 3+ 6+ 2+ 10 7+ AC 3+ 63 2+ 1 1 Compare M from Compare M from Compare M: M + from D Compare M: M + from S Compare M: M + from U Compare M: M + from X Compare M: M + from Y 2 0 0 0 1 0 1 0 1 0 0 0 0 A @ t B @ t 1 • t t 1 • t t t t 1 • t t t t 1 • t t t t 1 • t t t A-+ A B .n-+M • • • B -+ 6+ 1 0 3 2 5(6) 4 7 17 2 2 • • • • • •• • • • 8D LBSR 2 3 H N Z V C Branch to Subroutine Long Branch to Subroutine BSR 4F 5F 5 DESCRIPTION CC 1\ IMM -+ CC (except 1-+E) Wait for Interrupt Decimal Adjust A t t t t t t t t t 0 t 0 t 0 (-I-<I. HD88A09. · t • ~ t t t t t t t t Ii@.U EA@-+ X EA@-Y • • • • • •• •• •t •• •• A} • LD LDA LDB LDD LDS 96 D6 DC 10 DE DE 9E 10 9E LDU LDX LDY 2 6 2 3 5 5 6 2 2 3 7 3 4 3 4 86 C6 CC 10 CE CE 8E 10 8E 2 2 3 4 3 3 4 2 2 3 4 3 3 4 LEA LEAS LEAU LEAX LEAY LSL LSLA LSLB LSL 48 58 LSRA LSRB LSR 44 54 2 2 1 1 3D 11 1 AxB-+D (Unsigned) 40 50 2 2 1 1 A+1-+A B+1-+B LSR MUL NEG NOP NEGA NEGB NEG 2 2 08 6 2 78 7 3 68 6+ 2+ 04 6 2 74 7 3 64 6+ 2+ 00 12 2 6 2 70 7 3 60 1 6+ 2+ ~ - • • • • • • • • • • t to.---------...HD8809. • t to.. • t to. -+ PC • • 2 OA 6 2 7A 7 98 D8 4 4 2 2 B8 F8 5 5 3 3 3 88 C8 2 2 2 2 6A 6+ 2+ A-1-+A B-1-+B M-1-M A8 4+ E8 4+ 2+ 2+ AEf)M-+A BEf)M-+B t t • t t t • • • t t • t to. HD88B09----------------------------------------HD6809 ADDRESSING MODES INSTRUCTION/ ~-------. • t to.Ho- • • • t t t t t t t t 1 1 1 ) @ t DEC DECA DECB DEC EOR EORA EORB EXG R1. • t to.

JY : Return From Interrupt 4 4 2 2 B2 F2 5 5 3 3 82 C2 2 2 2 2 A2 4+ E2 4+ 2+ 2+ 2 STA STB STD STS SWI3@ 2 92 02 10 SUBA SUBB SUBD SWI® SWI2@ 6 5 97 D7 DO 10 OF OF 9F 10 9F STU STX STY SUB 09 1 SBCA SBCB SEX 5 • • • ) • Pull Registers from ( r-. • • t t 5+ 5+ 6+ 2+ 2+ 3+ U. DP The 16 bit registers are: X.--------~--------.) S Stack Pull Registers from (-I'-. Y.M: M+ 1 5 -+ M: M + 1 • t to. @> Condition Codes set as a direct result of the instruction if CC is specified.@ 1. PC @ EA is the effective address.) U Stack PULS PULU ROL DESCRIPTION _® # Push Registers on S Stack Push Registers on U Stack PSHU PUL RELATIVE OP 90 DO 93 4 4 5 6 5 5 6 4 4 6 2 2 2 3 2 2 3 B7 F7 FD 10 FF FF BF 10 SF 5 5 6 7 4 6 6 3 3 7 4 BO FO B3 5 5 7 3 3 3 f f (-I--j (J) r-. ® Special Case .CC • t to.-----------------------------------------HD8809. (NOTES) <D This column gives a base cycle and byte count.M 0. to. • ) ) 0 (--CV • • • • • • • I- ~}q}M: ~19JiIDID. HD68B09 INSTRUCTIONI FORMS HD6809 ADDRESSING MODES ~-------.@) I-. (j) Conditions Codes set as a direct result of the instruction. @ 5(6) means: 5 cycles if branch not taken.M: M + 1 • • • t t t AO 4+ EO 4+ A3 6+ 2+ 2+ 2+ (ill t (ij) t to. to.M: M + 1 Y. @ SWI sets 1 and F bits. to.R2 1F 6 2 R1 ~ R2'ID (-r-.) Return From Subroutine • • • • • A-M-C-A B-M-C-B @ t @ t t t t t Sign Extend B into A • t •• t 2+ 2+ 2+ 3+ A. to.M: M + 1 X. 6 cycles if taken.M B.-------_4 IMPLIED # OP OR PSH ORA ORB ORCC DIRECT OP 9A DA 4 4 EXTENDED # OP - 2 2 BA FA 5 5 IMMEDIATE # OP 3 3 8A CA 1A 2 2 3 INDEXEDCD # OP - # 2 2 2 AA 4+ EA 4+ 2+ 2+ PSHS ROR ROLA ROLB ROL 49 59 2 1 2 1 RORA RORB ROR 46 2 2 1 1 56 RTI 3B 6/15 RTS 39 SBC ST SWI SYNC 79 7 3 69 6+ 2+ 06 6 2 76 7 3 66 6+ 2+ 3 2 1 0 H N Z V C AVM-A BVM-B CCV IMM . R1 and R2 may be any pair of 8 bit or any pair of 16 bit registers. • t to. to. @ The PSH and PUL instructions require 5 cycle plus 1 cycle for each byte pushed or pulled._------~. To obtain total count. Tt!e 8 bit registers are: A.Carry set if b7 is SET. @ Value of half-carry flag is undefined._--------. SWI2 and SWI3 do not affect I and F. LEGEND: OP Operation Code (Hexadecimal) Z Zero (byte) Number of MPU Cycles V Overflow. B. and the values obtained from the INDEXED ADDRESSING MODES table. CC. to.D Software I nterrupt1 Software Interrupt2 • • • t • • t t t • • 20 2 Software I nterrupt3 • • • 13 ~2 1 3F 10 3F 11 3F 2 2 2 80 CO 83 2 2 4 2 2 3 t t 4+ 4+ 5+ 6+ A7 E7 ED 10 EF EF AF 10 AF 3 3 3 ! Ii If: Synchronize to Interrupt t t t • • • • • • • • • • • TFR R1.@). S.M: M + 1 . U. 2's complement C Carry from bit 7 # Number of Program Bytes + Arithmetic Plus t Test and set if true. HD68A09. and not affected otherwise. 0.) TST TSTA TSTB TST 40 50 2 2 1 1 Test A Test B Test M • • • 00 6 2 70 7 3 6D 6+ 2+ t t t to. 19 20 1 2 A-M-A B-M-B D . cleared otherwise Arithmetic Minus • Not Affected X Multiply CC Condition Code Register ~ Complement of M Concatenation V Logical or Transfer Into H Half-carry (from bit 3) 1\ Logical and N Negative (sign bit) <±> Logical Exclusive or @ 417 .

HD68B09---------------------------------------Table 11 Hexadecimal Values of Machine Codes OP Mnem Mode 00 01 02 03 NEG Direct 04 05 06 07 08 09 OA OB OC 00 OE OF COM LSA 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 10 1E 1F } See Next Page NOP SYNC 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 20 2E 2F OP Mnem Mode 2 2 2 LEAX LEAY LEAS LEAU PSHS PULS PSHU PULU Indexed 6 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 6 AOA ASA ASL.LSLB AOLB DECB 2 2 2 2 2 INCB TSTB 2 2 Implied LEGEND: ~ Number of MPU cycles (less possible push pull or indexed-mode cycles) # Number of program bytes * Denotes unused opcode 418 2 70 71 72 73 2 INCA TSTA CLAB # 2+ 2+ 2+ 2+ 2 2 2 2 2 75 76 77 78 79 7A 7B 7C 70 7E 7F 80 81 82 83 84 85 86 87 88 89 8A 88 8C 80 8E 8F # 6+ 2+ COM LSA 6+ 6+ 2+ 2+ AOA ASA ASL. BCC BLO. HD68A09. LSL AOL DEC INC TST JMP CLA # 6 6 Direct Implied Implied LBAA LBSA Aelative Aelative DAA OACC Implied Immed ANDCC SEX EXG TFA Immed Implied . LSL AOL DEC 6+ 6+ 6+ 6+ 6+ 2+ 2+ 2+ 2+ 2+ INC TST JMP CLA Indexed 6+ 6+ 3+ 6+ 2+ 2+ 2+ 2+ NEG Extended 7 3 COM LSA 7 7 3 3 AOA ASA ASL. Implied BAA BAN BHI BLS BHS.HD6809. BCS BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE Aelative Aelative 6 2 2 6 6 6 2 2 2 6 6 2 3 2 2 6 2 2 2 5 9 3 3 2 3 2 3 2 2 1 2 8 6 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 40 4E 4F 2 50 51 52 53 2 2 54 55 2 2 56 57 58 59 5A 5B 5C 50 5E 5F 2 2 2 2 2 2 2 2 2 2 2 l Indexed Implied 4+ 4+ 4+ 4+ 5+ 5+ 5+ 5+ OP Mnem Mode 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 60 6E 6F NEG Indexed 5 3 ATS ABX ATI CWAI MUL 6.15 20 11 SWI Implied 19 NEGA Implied 2 COMA LSAA AOAA ASAA ASLA. LSL AOL DEC 7 7 7 7 7 3 3 3 3 3 INC TST JMP CLA 7 7 4 7 3 3 3 3 2 2 2 4 2 2 2 2 2 2 SUBA CMPA SBCA SUBD ANDA BITA LOA EOAA ADCA OAA ADDA CMPX BSA LOX . Extended Immed Immed Aelative Immed 2 2 2 2 4 7 3 3 2 2 2 2 2 2 2 3 2 3 (to be continued) . LSLA AOLA DECA 2 2 N 2 2 2 2 2 2 CLAA Implied 2 NEGB Implied 2 COMB LSAB 2 2 AOAB ASAA ASLB.

HD68A09.LBCC LBCS._________________________________________ HD6809. t '"di~ E"r 4 6 6 6+ 6+ 7 7 20 5 5 7 7 7+ 7+ 8 8 4 3 3 3+ 3+ 4 4 2 4 4 3 3 3+ 3+ 4 4 . HD68B09 OP Mnem Mode 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 90 9E 9F SUBA CMPA SBCA SUBD ANOA BITA LOA STA EORA AOCA ORA ADOA CMPX JSR LOX STX Direct AO Al A2 A3 A4 AS A6 A7 A8 A9 AA AB AC AD AE AF SUBA CMPA SBCA SUBD ANOA BITA LOA STA EORA ADCA ORA ADOA CMPX JSR LOX STX Indexed BO Bl B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BO BE BF SUBA CMPA SBCA SUBD ANOA BITA LOA STA EORA AOCA ORA ADOA CMPX JSR LOX STX Extended CO Cl C2 C3 C4 C5 SUBB CMPB SBCB AOOD ANOB BITB 4 4 4 6 4 Direct Indexed # OP Mnem Mode 2 2 CS C7 C8 C9 CA CB CC CO CE CF LOB Immed 2 2 2 4 4 4 4 4 4 4 6 7 2 2 2 2 2 2 2 5 5 2 2 4+ 4+ 4+ 6+ 4+ 4+ 4+ 4+ 4+ 4+ 4+ 4+ 6+ 7+ 5+ 5+ 2+ 2+ 2+ 2+ 2+ 2+ 2+ 2+ 2+ 2+ 2+ 2+ 2+ 2+ 2+ 2+ 5 5 5 7 5 5 5 5 5 5 5 5 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 7 8 Extended 6 6 'T~ 2 2 2 4 Immed 2 2 2 2 2 2 2 3 2 2 EORB ADCB ORB AOOB LCD I I LOU Immed 00 01 02 03 04 05 06 07 08 09 OA DB DC 00 DE OF SUBB CMPB SBCB AOOO ANOB BITB LOB STB EORB AOCB ORB AOOB LOO STO LOU STU Direct EO El E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF SUBB CMPB SBCB AOOO ANOB BITB LOB STB EORB AOCB ORB AOOB LOO STD LOU STU Indexed FO Fl F2 F3 F4 F5 F6 F7 F8 F9 FA FB