com
147452Linear
Integrated Circuits.
Integrated Circuits.
INDEX
EXPT.NO
PAGE
NO
INSTRUMENTATION AMPLIFIER
13
17
25
35
41
49
53
10
STUDY OF SMPS
59
11
61
PSPICE NETLISTS
12
79
Integrated Circuits.
Rf
+15v
R1=10K
IC 741
Signal
Generator
Vin
+
15v
+
CRO
TABULATION:
S.No
Rf (K)
1.
1K
2.
10K
3.
33K
4.
100K
Vin (Volts)
Vout (Volts)
Theoretical Gain
A = Rf / R1
Practical Gain
A = V0 / Vin
MODEL GRAPH:
Vin
INPUT
Time (ms)
Vout
OUTPUT
Time (ms)
Integrated Circuits.
DATE:
AIM:
To design the Inverting, NonInverting and Differential Amplifiers using
Opamp IC741 and test their performance.
APPARATUS REQUIRED:
S.NO
COMPONENTS
RANGE
QUANTITY
01
EACH 01
EACH 02
01
1.
IC 741
2.
RESISTORS
3.
1K, 33K
10K, 100 K.

4.
SIGNAL GENERATOR
(03)MHz
01
5.
(030)MHz
01
6.
CONNECTING WIRES

FEW
THEORY:
Opamp in openloop configuration has a very few application because
of its enormous openloop gain. Controlled gain can be can be achieved by taking a
part of output signal to the input with the help of feedback. This is called as ClosedLoop Configuration. The three basic types of closedloop amplifier configuration
are: 1. Inverting amplifier.
2. Noninverting amplifier.
3. Differential amplifier.
The entire configuration can be operated with either AC or DC input.
INVERTING AMPLIFIER:If the input signal is applied to the inverting terminal through an input
resistance, a part of output is feedback to the inverting terminal through feedback
resistance Rf and the noninverting terminal grounded, then the configuration is said
to be Inverting Amplifier. It provides 1800 phase shift or polarity reversal for the
given input.
The circuit closedloop voltage gain is
Avcl
Rf
.
R1
4
Integrated Circuits.
Rf
+15v
R1=10K
+
2
3
Signal Vin
Generator 
7
IC 741
15v
+
CRO

TABULATION:
S.No
Rf (K)
1.
1K
2.
10K
3.
33K
4.
100K
Vin
(Volts)
Vout
(Volts)
Theoretical Gain
A = 1+(Rf / R1)
Practical Gain
A = V0 / Vin
MODEL GRAPH:
Vin
INPUT
Time (ms)
OUTPUT
Vout
Time (ms)
Integrated Circuits.
If the input signal is given to non inverting terminal & the feedback
from output is connected to inverting terminal of an opamp through a potential
divider network, then it is called as NonInverting Amplifier Configuration. It
operates in a same way as a voltage follower (unity gain buffer), except that the
output voltage is potentially divided before it is fedback to the inverting input
terminal. No phase shift or change in the circuit closed loop polarity occurs voltage
gain is Avcl 1
Rf
R1
PROCEDURE(INVERTING & NONINVERTING AMPLIFIER):1. Select R1 as a constant value and choose a value of Rf.
2. Connect the circuit as per as the circuit diagram.
3. Apply the constant amplitude input voltage to the circuit.
4. Measure the output voltage amplitude for different value of Rf from CRO.
5. Calculate the practical gain for different value of Rf & compare it with
theoretical gain.
6. Practical gain & theoretical gain should be approximately equal.
7. Plot the graph of the input wave versus output wave for any one practical case.
Integrated Circuits.
R1=10K
Vin2
7
IC 741
+
3
4
R2=100K
15v
+
CRO

TABULATION:
S.No
Vin1
(Volts)
Vin2
(Volts)
Vin2  Vin1
(Volts)
V0
(Volts)
Theoretical Gain
A = Rf / R1
Practical Gain
A=V0 / (Vin2  Vin1)
1.
2.
3.
Integrated Circuits.
THEORY(DIFFERENTIAL AMPLIFIER):A
configuration
which
combines
inverting
&
noninverting
configuration with both input terminals are supplied with Vin1 & Vin2, then it is
called as Differential Amplifier configuration. This circuit amplifies the difference
between the two inputs. Differential amplifier with a single opamp has the exact gain
of an inverting amplifier and it is given as
AD (Using One OpAmp)
AVCL
Vo
(Vin1 Vin 2 )
Rf
R1
A differential amplifier with two opamps has the exact gain of a noninverting
amplifier and it is given as:
AD (Using Two OpAmps)
AVCL
Vo
(Vin1 Vin 2 )
Rf
.
R1
PROCEDURE:
1. Select the value of R1, R2, R3 & Rf such that R1=R2 and R3=Rf.
2. Connect the circuit as per as the circuit diagram.
3. Provide constant input voltage Vin1 to Noninverting terminal of opamp
through R1 & constant input voltage Vin2 to inverting terminal of opamp
through R2.
4. Measure the output voltage using CRO.
5. Calculate the theoretical gain and compare it with practical gain.
6. Practical gain & theoretical gain should be approximately equal.
7. Plot the graph of the input wave versus output wave for any one practical case.
RESULT:
Thus the Inverting, NonInverting and Differential Amplifiers are
designed and their performance was successfully tested using opamp IC 741.
8
Integrated Circuits.
INTEGRATOR:
CIRCUIT DIAGRAM:Cf=0.01uf
Rf=15k
+15v
2 7
IC 741
R1=1.5k
Signal
Generators
+
Vin
1.5K
Rcomp
+
RL=10k
15v
CRO

TABULATION:
S.No
Frequency
(Hz)
Output Voltage
(Volts)
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
MODELGRAPH:
Integrated Circuits.
COMPONENTS
RANGE
QUANTITY

01
100 , 1.5K
Each 02
10K, 15K
Each 01
0.1f, 0.01f
Each 01
0.001f,
05
1.
IC 741
2.
RESISTORS
3.
CAPACITOR
4.

01
5.
6.
SIGNAL GENERATOR
(03)MHz
01
01
7.
CONNECTING WIRES
(030)MHz

FEW
THEORY (INTEGRATOR):A circuit in which the output voltage waveform is the integral of the
input voltage waveform is the integrator or integration amplifier; Such a circuit is
obtained by using basic inverting amplifier configuration, if the feed back resistor R f
is replaced by a capacitor Cf. The Output voltage expression is given as
VO
1
R1C f
Vin dt
C.
1
2 R1C f
The point up to which the gain is constant & maximum is called as gain limiting
frequency & given as fa
1
2 Rf C f
the stability & rolloff problems. Between fa & fb the circuit acts as an integrator and
it is similar to a LPF. Integrator is most commonly used in analog computers, A/D
converter & signal wave shaping circuits.
Integrator as LPF (Characteristics of integrator)
Design of integrator with a lower frequency (Break Frequency) limit of
integration at fa = 1 KHz & the frequency at which 0dB results fb = 10 KHz.
PROCEDURE:
1. From the given frequency fa & fb, the values of Rf, Cf, R1 & Rcomp are
calculated as given in the design procedure.
2. Connect the circuit as shown in the circuit diagram.
3. Apply the sinusoidal input as the constant amplitude to the inverting terminal
of opamp.
4. Gradually increase the frequency & observe the output amplitude.
5. Calculate the gain with respect to frequency & plot its graph.
10
Integrated Circuits.
CIRCUIT DIAGRAM:
Cf=0.005f
Rf=1.5k
R1=100 C1=0.1f
+
Signal
Generators
+15v
7
IC 741
ROM=100
TABULATION:
R3=10K
15v
+
CRO

1.
Frequency (Input)
2.
3.
4.
5.
MODEL GRAPH:
(i) SINE WAVE INPUT
11
Integrated Circuits.
R f C1
dVin
dt
PROCEDURE:
1. Select fa equal to the highest frequency of the input signal to be differentiated.
Calculate the component values of C1 & Rf.
2. Choose fb = 20fa & calculate the values of R1 & Cf, so that R1C1=Rf Cf.
3. Connect the components as shown in the circuit diagram.
4. Apply a sinusoidal & square wave input to the inverting terminal of opamp
through R1 C1.
5. Observe the shape of the output signal for the given input in CRO.
6. Note down the reading and plot the graph of input versus output wave for both
cases.
(ii) SQUARE WAVE INPUT
12
Integrated Circuits.
1
2 Rf C f
= 1KHz.
Always take Cf < f and
Let Cf = 0.01f
Rf =
1
2 C f fa
Rf = 15.9K
Rf = 15K
Take fb =
R1 =
1
= 10KHz.
2 R1C f
1
= 1.59K.
2 fbC f
R1 1.5K
Rcomp = R1 // Rf =
R1 R f
R1
Rf
Rcomp = 1.5K
DESIGN PROCEDURE(DIFFERENTIATOR):Design a differentiator to differentiate an input signal that varies in frequency
from 10Hz to 1KHz. Apply a sine wave & square wave of 2Vpp & 1KHz frequency
& observe the output.
To find Rf & C1
Given: fa = 1KHz.
fa =
1
2 R f C1
fa = 1KHz.
Assume C1 = 0.1f
Rf = 1.59K 1.5K
13
Integrated Circuits.
To find R1 & Cf
Select fb = 20fa with R1 C1 = Rf Cf
fb = 20KHz =
1
2 R1C1
R1 = 79.5 100
RC
82 X 0.1X 10
Cf = 1 1 =
Rf
1.5K
Cf = 0.005f.
Rom R1 // Rf = 100
f=1KHz
Vp = 1V,
Vin = Vp sin
= sin (2 )(103)t
Vo = Rf c1
dVin
dt
= (1.5K) (0.1f)
d
[sin [(2 )(103)t]
dt
RESULT:
Thus an Integrator and Differentiator using opamp are designed and their
performance was successfully tested using opamp IC 741.
14
Integrated Circuits.
CIRCUIT DIAGRAM:
+15v
3
Rf=1K
IC 741
6
+15v
R2=1K
15v
R1=1K
IC 741
RG 22K
+
V1

R1=1K
15v
R2=1K
+15v
2
+
V
R1=1K
IC 741
+
V2

15v
15
Integrated Circuits.
INSTRUMENTATION AMPLIFIER
EXP.NO: 03
AIM:
DATE:
IC741.
APPARATUS REQUIRED:
S.NO
COMPONENTS
1.
IC 741
2.
RESISTORS
3.
RANGE
QUANTITY
03
1K.
22K
06
01

01
4.
SIGNAL GENERATOR
(03)MHz
02
5.
01
6.
CONNECTING WIRES
(030)MHz

FEW
THEORY:
An instrumentation amplifier is the intermediate stage of a instrumentation
system. The signal source of the instrumentation amplifier is the output of the
transducer. Many transducers output do not have the ability or sufficient strength to
drive the next following stages. Therefore, instrumentation amplifiers are used to
amplify the lowlevel output signal of the transducer so that it can drive the following
stages such as indicator or displays.
The major requirements of a instrumentation amplifier are precise,
lowlevel signal amplification where lownoise, low thermal and time drifts, high
input resistance & accurate closedloop gain, low power consumption, high CMRR &
high slew rate for superior performance.
16
Integrated Circuits.
TABULATION:
COMMON MODE GAIN CALCULATION AC
S.No
RG
(K)
VI
(Volts)
V2
(Volts)
Vo
(Volts)
Ac =
Vo
V1 V2
2
1.
2.
3.
4.
5.
RG (K)
V1
(Volts)
V2
(Volts)
Vo
(Volts)
Ad =
Vo
V1 V2
CMRR =
20 log ( Ad
)(dB)
Ac
1.
2.
3.
4.
5.
17
Integrated Circuits.
PROCEDURE:
1. Select the entire resistor with same value of resistance R. Let RG be the gain
varying resistor with different values of resistance for simplicity let RG, be a
constant value.
2. Connect the circuit as shown in the circuit diagram.
3. Give the input V1 & v2 to the noninverting terminals of first & second opamp respectively.
4. By varying the value of RG, measure the output voltage for common mode and
differential mode operation. Since RG is selected as constant value, provide
different input value of V1 & V2.
5. Calculate the differential mode gain Ad and common mode gain Ac to
calculate the CMRR as CMRR=20 log
Ad
.
Ac
RESULT:
Thus an instrumentation amplifier was constructed and CMRR is
tested using opamp IC 741.
18
Integrated Circuits.
LOWPASS FILTER:
CIRCUIT DIAGRAM:R1=27K
RF=20K
+15v
2
Signal
Generator
+
Vin
1.5K
3
0.1uf
7
IC 741
6
RL=10K
15v
+
CRO

TABULATION:
S.No
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
Frequency
(Hz)
Output Voltage
(Volts)
MODEL GRAPH:
19
Integrated Circuits.
DATE:
AIM:
To design an Active Lowpass and Band Pass Filter using opamp and to test
their performance
APPARATUS REQUIRED:
S.NO
COMPONENTS
RANGE
QUANTITY

02
EACH 02
10K
01
0.1f, 0.01f
01
1.
IC 741
2.
RESISTORS
3.
CAPACITORS
4.

01
5.
SIGNAL GENERATOR
(03)MHz
01
6.
(030)MHz
01
7.
CONNECTING WIRES

FEW
THEORY (ACTIVE LPF):A filter circuit which allows only low frequency range up to a higher
cutoff frequency fH is called as Low Pass Filter. An active filter uses transistor and
components such as resistor & capacitor for its design. An active filter offers the
following advantages over a passive filter.
1. Gain & frequency adjustment flexibility.
2. No loading problem because of high input impedance & low output impedance.
3. More economical because of variety of opamps and absence of inductors.
From the frequency response, when f<fH; the gain is maximum lAl. When
f=fH; the gain is 70.7% of the maximum gain
A
2
and when f
is called
20
Integrated Circuits.
0.1f
3
7
IC 741
6
RL=10K
1.5K
TABULATION:
Frequency
S.No
(Hz)
1.
15v
Output Voltage
(Volts)
+
CRO

2.
3.
4.
5.
6.
7.
8.
9.
10.
MODEL GRAPH:
21
Integrated Circuits.
THEORY (ACTIVE HPF):An active high pass filter is simply formed by interchanging the
frequency determining resistor and capacitor in lowpass filter. A filter circuit which
allows only high frequency range greater then a lower cutoff frequency fL is called
as HIGH PASS FILTER. From the frequency response, when f<fL; the gain
gradually increases from the lowest value. When f = fL; the gain reaches 70.7% of the
maximum gain
A
2
and when f > fL, the gain is maximum lAl. The frequency range
Vo
Vin
Af ( f / f L )
1 ( f / f H )2
22
Integrated Circuits.
RF=20K
RF=20K
+15v
+15v
2
Signal
Generator
0.1uf
Vin
TABULATION:
S.No
1.5K
0.01uf
1.5K
Frequency
(Hz)
IC 741
IC 741
3
15v
CRO
15v
RL=10K
Output Voltage
(Volts)
MODEL GRAPH:
23
Integrated Circuits.
THEORY (ACTIVE BANDPASS FILTER):A filter which has a pass band between two cutoff frequencies fH & fL
is called as Bandpass filter. Where fH > fL BPF is basically of two types
(i) Wide band pass filter. (ii) Narrow band pass filter.
Based on figure of merit or quality factor Q, the types are classified as follows. If
Q<10, selectivity is poor & allows higher bandwidth & such BPF is called as wide
BPF.
If Q > 10, selective is more and allows only narrow bandwidth & such
BPF is called as Narrow BPF. Relationship between Q & center frequency fC is
given as
fc
BW
fc
fH
&
fL
fc
fH fL
When frequency fL < f < fH then gain is maximum. At f < fL the gain is
gradually increasing (positive rolloff) from lower value & at f > fH the gain is
gradually decreasing (Negative rolloff) & exactly when f = fL & f = fH the gain is
70.7% of maximum gain
A
2
PROCEDURE:
1. Select the lower and higher cutoff frequency and calculate the value of R & C
for the given frequencies.
2. Design for LPF & HPF separately and then combine the circuit by first placing
the HPF followed by a LPF (i.e) HPF in series with LPF.
3. Connect the circuit as shown in the circuit diagram.
4. Apply a constant voltage input sinusoidal signal to the noninverting terminal
of opamp.
5. Tabulate the output voltage Vo with respect to different values of input
frequency.
6. Calculate passband gain and plot the graph of frequency versus voltage gain &
check the graph to get approximately the same characteristic as shown in the
model graph.
24
Integrated Circuits.
1
;
2 (1KHz )(0.1X 10 6 )
R = 1.59K R=1.5K
4. Then design the LPF by taking fH = 10KHz. Assume the value of C < 1f. Let
C = 0.01f.
5. Calculate R from the expression fH =
R=
1
1
; Therefore R =
2 fHC
2 RC
1
;
2 (10 KHz )(0.01X 10 6 )
R = 1.59K R=1.5K
6. Calculate the values of Rf & R1 with the use of pass band gain.
Overall P.B gain of BPF = 4 = 2 (HPF) X 2 (LPF)
Therefore for both HPF & LPF the value of Rf = R1 to obtain a individual
P.B gain of 2.
Af = (1+
Rf
) = 2 (for HPF)
R1
Rf
) = 2 (for LPF)
R1
Let Rf = R1 = 22K.
Af = (1+
fc
fc
=
B.W
fH fL
Af T (
[1
f
)
fL
f 2
f 2
) ][1 (
) ]
fH
fL
25
Integrated Circuits.
1
2 RC
1
R=
2 fHC
R=
R = 1.5K
1
= 1.5K
2 X 1X 10 3 X 0.1 f
C = 0.1f
4. Determine the value of R1 & Rf from pass band gain of the filter.
Rf
Af = 1 +
= 2.
R1
Therefore Rf =R1 to select Af = 2.
Assume Rf = R1 = 22K
&
Assume RL = 10K
Vo
=
Vin
Af
1 ( f / f H )2
Af P.B gain.
f Input frequency.
fH Higher cutoff frequency of LPF.
RESULT:
Thus an Active Lowpass, High pass and Band Pass Filters are designed
and tested using opamp IC 741.
26
Integrated Circuits.
7
IC 741
R2=DRB
+
CRO
Vref
R1=10K
TABULATION:
Waveforms
Amplitude
(volts)
DESIGN VALUE
tH
(ms)
tL
(ms)
(ms)
OBSERVED VALUE
F
(Hz)
tH
(ms)
tL
(ms)
F
(Hz)
(ms)
Output
waveform
Capacitive
waveform
MODEL GRAPH:
27
Integrated Circuits.
DATE:
AIM:
To design an Astable, Monostable multivibrator and Schmitt trigger
using opamp IC 741 and to test their characteristics.
APPARATUS REQUIRED:
S.NO
COMPONENTS
RANGE
QUANTITY

01
100, 100K,
10K, 47K,
EACH 01
EACH 03
(010)M
01
0.01f, 0.1f
01
1N4007
02
1.
IC 741
2.
RESISTORS
3.
DRB
4.
CAPACITORS
5.
DIODE
6.

01
7.
SIGNAL GENERATOR
(03)MHz
01
7.
(030)MHz
01
8.
CONNECTING WIRES

FEW
R2
of the output is
R1 R 2
fedback to the positive input terminal of opamp. The charge in the capacitor
increases & decreases upto a threshold value called Vsat. This charge in the
capacitor triggers the opamp to stay either at +Vsat or Vsat. Asymmetrical square
wave can also be generated with the help of zener diodes. Astable multivibrator do
not require a external trigger pulse for its operation & output toggles from one state to
another and does not contain a stable state. Astable multivibrator are mainly used in
timing applications & waveforms generators.
28
Integrated Circuits.
1
2 RC ln[1 (2 R1 / R2 )]
1
2 RC
R2 = 1.16K (10K)
R2 = 11.6K (DRB)
1
2 RC
Let C = 0.01f
R=
1
1
=
3
2 f oC
2 X (1X 10 )(0.01X 10 6 )
R = 50K R = 47K
R1
lVSATl where is the feedback ratio.
R1 R 2
29
Integrated Circuits.
PROCEDURE:
1. Calculate the value of components using the design procedure given.
2. Connect the circuit as per as the circuit diagram.
3. As there is no specific input signal for this circuit switch ON the power
supply.
4. Note down the reading for output square wave (i.e) time & amplitude and
tabulate it.
5. Note down the reading for capacitor voltage & tabulate it.
6. Plot the reading in the graph and compare it with model graph.
30
Integrated Circuits.
R3=47K
IC 741
C=0.01uf
D1
6
R1=10K
15V
+
CRO
D2
C1=0.1uf
R2=10K
Triggering
Input
Vin
R4=100
TABULATION:
Amplitude
(volts)
S.No
Waveforms
1.
Input waveform
2.
Output waveform
3.
Capacitive waveform
Time period
(ms)
MODEL GRAPH:
INPUT
TIME (ms)
AMPLITUDE
OUTPUT
TIME (ms)
31
Integrated Circuits.
THEORY  (MONOSTABLE MULTIVIBRATOR):A multivibrator which has only one stable and the other is quasistable
state is called as Monostable multivibrator or oneshort multivibrator. This circuit is
useful for generating single output pulse of adjustable time duration in response to a
triggering signal. The width of the output pulse depends only on the external
components connected to the opamp. Usually a negative trigger pulse is given to
make the output switch to other state. But, it then returns to its stable state after a time
interval determined by circuit components. The pulse width T can be given as T =
0.69RC. For Monostable operation the triggering pulse width Tp should be less then
T, the pulse width of Monostable multivibrator. This circuit is also called as time
delay circuit or gating circuit.
DESIGN PROCEDURE:
1. Assume R1 = R2 = 10K & calculate from expression
R1
10 K
=
=
= 0.5.
R1 R 2 20 K
2. Find the value of R & C from the pulse width time expression.
(1 V D / Vsat )
1
(1 V D / Vsat )
T = RC ln
0.5
T 0.69RC.
T = RC ln
Integrated Circuits.
ROM=R1//R2
10K
3
+
Vin
15V
RL=10K
R2=100K
R1
+
CRO

10K
TABULATION:
I/P Voltage
(Volts)
I/P Time
(ms)
O/P
Voltage
(ms)
O/P Time
(ms)
MODEL GRAPH:
33
Integrated Circuits.
THEORY(SCHMITT TRIGGER):A circuit which converts a irregular shaped waveform to a square wave
or pulse is called a Schmitt trigger or squaring circuit. The input voltage Vin triggers
the output Vo every time it exceeds certain voltage levels called upper threshold
voltage VUT and lower threshold voltage VLT. The threshold voltages are obtained by
using the voltage divider. A comparator with positive feedback is said to exhibit
hysteresis, a dead band condition. The hysteresis voltage is the difference between
VUT & VLT.
There are two types of Schmitt trigger based on where the irregular wave is
given. They are, Inverting & noninverting Schmitt trigger. Schmitt trigger finds
application in wave shaping circuits. The other name given to Schmitt trigger is
regenerative comparator.
34
Integrated Circuits.
DESIGN PROCEDURE:1. Select the desire value of Vut & Vlt with same magnitude & opposite polarity.
Let Vut = 1V & Vlt = 1V.
2. For Opamp 741C Vsat 13V to 14V. And assume Vref = 0, Since the
another end of R1 is grounded.
3. if Vo = +Vsat the voltage at the positive terminal will be (voltage from
potential divider R1 & R2).
Vut = Vref +
R1
(Vsat  Vref )
R1 R 2
Therefore Vref = 0.
Vut =
R1
(+ Vsat).
R1 R 2
R1
) Vsat.
R1 R 2
5. Sub Vut & assume R1 or R2 & find the other component value.
1V =
R1
(13)
R1 R 2
R1 + R2 = 13R1
R2 = 12R1
6. Calculate ROM by
ROM = R1 // R2 =
ROM =
1000 K
110 K
R1R 2
R1 R 2
(10 K )(100 K )
.
110 K
R1
[+Vsat (Vsat)]
R1 R 2
10 K
[26V]
110 K
= 0.0909 [26V]
Vhy = 2.363V
35
Integrated Circuits.
PROCEDURE:
1. Design the value of circuit components and select VUT & VLT as given in the
design procedure.
2. Connect the circuit as shown in the circuit diagram.
3. Apply the input signal to the input terminal of opamp & set VUT & VLT
values.
4. Note down the readings from the output waveform.
5. Plot the graph & show the relationship between Input sine wave & Output
square wave.
RESULT:
Integrated Circuits.
Rf=1M
+15v
R1=33K
R1//Rf
33K
C=0.1f
C=0.1f0
7
IC 741
15v
C=0.1f
+
CRO

R=3.3K
R=3.3K
R=3.3K
TABULATION:.
OBSERVED OUTPUT WAVEFORM
Amplitude
Time period
Frequency
(volts)
(ms)
(Hz)
Design Frequency
(Hz)
MODEL GRAPH:
Vout
OUTPUT
Time (ms)
37
Integrated Circuits.
DATE:
To design RC Phase Shift and Wien Bridge Oscillator using opamp IC
COMPONENTS
1.
IC 741
2.
RESISTORS
3.
CAPACITORS
4.
5.
6.
CONNECTING WIRES
RANGE
QUANTITY

01
EACH 03
10 K 22 K, 1M,
EACH 01
0.1f
03

01
(030)MHz
01

FEW
THEORY:
RC phase shift oscillator produces 360 of phase shift in two parts. Firstly,
each and every RC pair in the feedback network produces 60 phase shift and totally
there were three pairs, thus producing 180 Phase shift and secondly, the feedback
input is given to the inverting terminal of opamp to produce another 180 phase shift
and a total phase shift of 360.
The frequency of oscillation is given by f0 =
1
2
6 RC
; If an inverting
amplifier is used, the gain must be atleast equal to 29 to ensure the oscillations with
constant amplitude that is, AV
DESIGN PROCEDURE:
Design a RC phase shift oscillator to oscillate at 200Hz.
1. Select fo = 200Hz.
2. Assume C = 0.1f & determine R from fo.
1
1
fo =
=R=
= 3.3K.
2 6 f oc
2 6 RC
3. To prevent the loading of amp because it is necessary that R1>>10R.
Therefore R1=10R=33K.
4. At this frequency the gain must be atleast 29 (i.e)Rf / R1 =29.
Therefore Rf = 29R1.
Rf = 29 (33K) = 957K.
Therefore use Rf = 1M.
38
Integrated Circuits.
Rf=22K
R1=10K
+15v
2
IC 741
R=1.5K
15v
C=0.1uf
+
CRO
C=0.1uf
R=1.5K
TABULATION:
OBSERVED OUTPUT WAVEFORM
Amplitude
Time period
Frequency
(volts)
(ms)
(Hz)
Design Frequency
(Hz)
MODEL GRAPH:
Vout
OUTPUT
Time (ms)
39
Integrated Circuits.
PROCEDURE (RC PHASE SHIFT):1. Select the given frequency of oscillation f0 = 200Hz.
2. Assume either R or C to find out the other using formula f0 =
.
2 6 RC
3. The gain is selected such that Rf / R1 = 29K. Assume Rf or R1 to find the other.
1
.
2 RC
DESIGN PROCEDURE:
(i)
1
. Also
2 RC
Integrated Circuits.
Features of 555 IC:1. The load can be connected to o/p in two ways i.e. between pin 3 & ground 1 or
between pin 3 & VCC (supply)
2. 555 can be reset by applying negative pulse, otherwise reset can be connected to
+Vcc to avoid false triggering.
3. An external voltage effects threshold and trigger voltages.
4. Timing from micro seconds through hours.
5. Monostable and bistable operation
6. Adjustable duty cycle
7. Output compatible with CMOS, DTL, TTL
8. High current output sink or source 200mA
9. High temperature stability
10. Trigger and reset inputs are logic compatible.
Supply voltage
Timing
Sink current
Temperature stability
:
:
:
:
:
Applications:1.
2.
3.
4.
5.
6.
7.
8.
9.
Integrated Circuits.
Integrated Circuits.
+5V
6.8K
RA
HI
3.3K
RB
IC 555
6
+
CRO Vo

Vc
0.01uf
C=0.1f
TABULATION:
Waveforms
Amplitude
(volts)
DESIGN VALUE
tH
(ms)
tL
(ms)
(ms)
OBSERVED VALUE
F
(Hz)
tH
(ms)
tL
(ms)
F
(Hz)
(ms)
Output
waveform
Capacitor
waveform
(Capacitor
voltage Vc)
43
Integrated Circuits.
DATE:
To Design and test Astable and Monostable multivibrator using 555 timer IC.
APPARATUS REQUIRED:
S.NO
COMPONENTS
RANGE
QUANTITY

01
3.3K,6.8K,10K.
EACH 01
0.1f, 0.01f.
EACH01
1.
IC 555
2.
RESISTORS
3.
CAPACITORS
4.

01
5.
SIGNAL GENERATOR
(03)MHz
01
6.
(030)MHz
01
7.
CONNECTING WIRES

FEW
THEORY:
When the power supply VCC is connected, the external timing capacitor C
charges towards VCC with a time constant (RA+RB) C. During this time, pin 3 is high
(VCC) as Reset R=0, Set S=1 and this combination makes Q = 0 which has
unclamped the timing capacitor C.
When the capacitor voltage equals 2/3 VCC, the upper comparator triggers the
control flip flop on that Q =1. It makes Q1 ON and capacitor C starts discharging
towards ground through RB and transistor Q1 with a time constant RBC. Current also
flows into Q1 through RA. Resistors RA and RB must be large enough to limit this
current and prevent damage to the discharge transistor Q1. The minimum value of R A
is approximately equal to VCC/0.2 where 0.2A is the maximum current through the
ON transistor Q1.
During the discharge of the timing capacitor C, as it reaches VCC/3, the lower
comparator is triggered and at this stage S=1, R=0 which turns Q =0. Now Q =0
unclamps the external timing capacitor C. The capacitor C is thus periodically
charged and discharged between 2/3 VCC and 1/3 VCC respectively. The length of
time that the output remains HIGH is the time for the capacitor to charge from 1/3
VCC to 2/3 VCC.
The capacitor voltage for a low pass RC circuit subjected to a step input of VCC
volts is given by VC = VCC [1 exp (t/RC)]
Total time period T = 0.69 (RA + 2 RB) C
f = 1/T = 1.44/ (RA + 2RB) C
44
Integrated Circuits.
MODEL GRAPH:
45
Integrated Circuits.
DESIGN PROCEDURE:Design of Astable multivibrator of operation frequency = 1 KHz & duty cycle of 30%
using 555 timer IC.
Given Frequency=1000Hz
Duty cycle=30%
D= T low/T high = RB/RA+2RB*100 (1)
T high =0.69(RA+RB)C
T low = 0.69 RBC
From equation 1
0.30 T high = T low
0.30 * 0.69(RA+RB)C = 0.69 RBC
0.201(RA+RB)C = 0.69 RBC
0.483 RB0.207 RA= 0 (2)
given f=1khz we know that T=1/f
T=1ms
T= T high + T low
0.69(RA+RB)C +0.69 RBC= 1ms.
0.69(RA+RB) +0.69 RB = 1ms./C
Let C=0.1F
0.69RA+0.69RB +0.69 RB = 1ms./0.1*106
0.69RA+1.38RB = 10 4 (3)
Solving equation 2 & 3 we get
RA=6.8K
RB= 2.674K 3.3K
Procedure:
1. Calculate the component values using the design procedure.
2. Connect the circuit as shown in the circuit diagram.
3. Observe and note down the output waveform.
4.
Measure the frequency of oscillations and duty cycle and then compare with
the given values.
Integrated Circuits.
+5V
10K
7
IC 555
6
0.1uf
Vc
Trigger
Input
Vin
+
CRO Vo

0.01uf
TABULATION:
S.No
Waveforms
1.
Input waveform
2.
Output waveform
3.
Capacitive waveform
(Capacitor voltage Vc)
Amplitude
(volts)
Time period
(ms)
MODEL GRAPH:
47
Integrated Circuits.
THEORY (MONOSATBLE):A Monostable Multivibrator, often called a oneshot Multivibrator, is a pulsegenerating circuit in which the duration of the pulse is determined by the RC network
connected externally to the 555 timer. In a stable or stand by mode the output of the
circuit is approximately Zero or at logiclow level. When an external trigger pulse is
given, the output is forced to go high ( VCC). The time for which the output remains
high is determined by the external RC network connected to the timer. At the end of
the timing interval, the output automatically reverts back to its logiclow stable state.
The output stays low until the trigger pulse is again applied. Then the cycle repeats.
The Monostable circuit has only one stable state (output low), hence the name
Monostable. Normally the output of the Monostable Multivibrator is low.
DESIGN PROCEDURE:Let, RA = 10K
Out put pulse width tp = 10s
tp=1.1RAC
C= 0.909F
C=0.1F
RESULT:
Thus the Astable and Monostable multivibrator is designed and tested using
555 timer IC
48
Integrated Circuits.
Pin Configuration:
Specifications:
1. Operating frequency range
6 to 12V
4. Input impedance
10 K typically
1mA typically
1.5%/V maximum
10mA typically
max.
fL
2 (3.6) x10 3 xC 2
1/ 2
Applications:
1. Frequency multiplier
2. Frequency shift keying (FSK) demodulator
3. FM detector
49
Integrated Circuits.
PLL IC 565
THEORY:The Signetics SE/NE 560 series is monolithic phase locked loops. The SE/NE
560, 561, 562, 564, 565, & 567 differ mainly in operating frequency range, power
supply requirements and frequency and bandwidth adjustment ranges. The device is
available as 14 Pin DIP package and as 10pin metal can package. Phase comparator
or phase detector compare the frequency of input signal fs with frequency of VCO
output fo and it generates a signal which is function of difference between the phase of
input signal and phase of feedback signal which is basically a d.c voltage mixed with
high frequency noise. LPF remove high frequency noise voltage. Output is error
voltage. If control voltage of VCO is 0, then frequency is center frequency (f o) and
mode is free running mode. Application of control voltage shifts the output frequency
of VCO from fo to f. On application of error voltage, difference between fs & f tends
to decrease and VCO is said to be locked. While in locked condition, the PLL tracks
the changes of frequency of input signal.
PROCEDURE:
1. Determine the component values using the design procedure given here.
2. Connect the components as shown in the circuit diagram.
3. Note down the readings of output waveform with respect to input signal.
50
Integrated Circuits.
CIRCUIT DIAGRAM:
51
Integrated Circuits.
DATE:
To design & test the characteristics of PLL and to construct and test frequency
multiplier using PLL IC565.
APPARATUS REQUIRED:
S.NO
COMPONENT
VALUE
QUANTITY
IC 565

01
IC 555

01
RESISTORS
12K, 54.5 K,
6.8K
Each one
0.01F
0.1 f, 10f, 1 f
EACH 01

01
CAPACITORS
(0 30V), 1A
(0 30MHz)
CONNECTING WIRES

FEW
52
Integrated Circuits.
(a): Input
(b): PLL output under locked conditions without 555
(c): Output at pin4 of 565 with 555 connected in the feedback
53
Integrated Circuits.
Theory:
The frequency divider is inserted between the VCO and the phase
comparator of PLL. Since the output of the divider is locked to the input frequency
fIN, the VCO is actually running at a multiple of the input frequency .The desired
amount of multiplication can be obtained by selecting a proper divide by N
network ,where N is an integer. To obtain the output frequency fOUT=2fIN, N = 2 is
chosen. One must determine the input frequency range and then adjust the free
running frequency fOUT of the VCO by means of R1 and C1 so that the output
frequency of the divider is midway within the predetermined input frequency range.
The output of the VCO now should be 2fIN . The output of the VCO should be
adjusted by varying potentiometer R1. A small capacitor is connected between pin7
and pin8 to eliminate possible oscillations. Also, capacitor C2 should be large enough
to stabilize the VCO frequency.
SAMPLE READINGS:
PARAMETER
INPUT
OUTPUT
Amplitude (Vpp)
Frequency (KHz)
PROCEDURE:1. The circuit is connected as per the circuit diagram.
2. Apply a square wave input to the pin2 of the 565
3. Observe the output at pin4 of 565 under locked condition.
4. Give the output of 565 to the pin2 of 555 IC.
5. Observe the output of 555 at pin3.
6. Now give the output of 555 as feedback to the pin5 of the 565.
7. Observe the frequency of output signal fo at pin4 of 565 IC.
8. Plot the waveforms in graph.
RESULT:
Thus the PLL characteristics are designed and tested and Frequency multiplier
using IC 565 is constructed and tested.
54
Integrated Circuits.
PIN DIAGRAM:
HI
Vref=5V
HI
Vin (030) V
12
11
10
R4=100E
Vo
R1=1K
IC 723
5
R2=3.3K
3
R3=30E
7
13
4
C=220pf
55
Integrated Circuits.
DATE:
To design and test the power supply voltage regulator using LM317 and
LM723
APPARATUS REQUIRED:
S.NO
COMPONENTS
RANGE
QUANTITY

EACH 01
EACH 01
1.
2.
RESISTORS
3.

01
4.
ANALOG VOLTMETER
(010)V
01
5.
(030)V
01
THEORY:
A voltage regulator is a circuit that supplies a constant voltage regardless of
changes in load current and input voltage variations. Using IC 723, we can design
both low voltage and high voltage regulators with adjustable voltages.
For a low voltage regulator, the output VO can be varied in the range of
voltages Vo < Vref, where as for high voltage regulator, it is VO > Vref. The voltage
Vref is generally about 7.5V. Although voltage regulators can be designed using Opamps, it is quicker and easier to use IC voltage Regulators.
IC 723 is a general purpose regulator and is a 14pin IC with internal short
circuit current limiting, thermal shutdown, current/voltage boosting etc. Furthermore
it is an adjustable voltage regulator which can be varied over both positive and
negative voltage ranges. By simply varying the connections made externally, we can
operate the IC in the required mode of operation. Typical performance parameters are
line and load regulations which determine the precise characteristics of a regulator
56
Integrated Circuits.
TABULATION:
S.NO
INPUT VOLTAGE
(Volts)
OUTPUT VOLTAGE
(Volts)
1.
2.
3.
4.
5.
6.
7.
8.
MODEL GRAPH:
57
Integrated Circuits.
3.3K
58
Integrated Circuits.
PIN DIAGRAM:
MODEL GRAPH:
59
Integrated Circuits.
TABULATION:
S.NO
INPUT VOLTAGE
(Volts)
OUTPUT VOLTAGE
(Volts)
PROCEDURE:
1) Connections are made as per the circuit diagram.
2) The reference voltage of 5v is set and the input voltage is varied between (030) v
3) The corresponding output is taken using voltmeter.
4) The readings are tabulated and the graph is plotted.
RESULT:
The 723 & 317 voltage regulators are designed and the regulation of supply voltage
was tested.
60
Integrated Circuits.
PIN DETAILS:
PIN NO.
FUNCTION
Inverting input
Oscillator output
(+)CL sense
()CL sense
RT
CT
Compensation
10
Shutdown
11
EmitterA
12
CollectorA
13
CollectorB
14
EmitterB
15
Vin
16
Vref
TECHNICAL INFROMATION:
DESCRIPTION
TEMPERATURE
RANGE
0 C to 70 C
SG3524F(16pin cerdip)
0 C to 70 C
SG3524D(16pin SO)
0 C to 70 C
61
Integrated Circuits.
STUDY OF SMPS
EXP.NO: 10
DATE:
AIM:
To study the control of SMPS
THEORY:
The switching regulator is also called as switched mode regulator. In
this case, the pass transistor is used as a controlled switch and is operated at either
cutoff or saturated state. Hence the power transmitted across the pass device is in
discrete pulses rather than as a steady current flow. Greater efficiency is achieved
since the pass device is operated as a low impedance switch. When the pass device is
at cutoff, there is no current and dissipated power. Again when the pass device is in
saturation, a negligible voltage drop appears across it and thus dissipates only a small
amount of average power, providing maximum current to the load. The efficiency is
switched mode power supply is in the range of 7090%.
A switching power supply is shown in figure. The bridge rectifier and
capacitor filters are connected directly to the ac line to give unregulated dc input. The
reference regulator is a series pass regulator. Its output serves as a power supply
voltage for all other circuits. The transistors Q1, Q2 are alternatively switched on &;
off, these transistors are either fully on or cutoff, so they dissipate very little
power. These transistors drive the primary of the main transformer. The secondary is
centre tapped and full wave rectification is achieved by diodes D1 and D2. This
unidirectional square wave is next filtered through a two stage LC filter to produce
output voltage Vo.
SG 3524:
FUNCTION:
Switched Mode Power Supply Control Circuit
FEATURES:
Complete PWM Power Controlled circuitry.
Single ended or pushpull outputs.
Line and Load regulation of 0.2%.
1% maximum temperature variation.
Total Supply current is less than 10mA
Operation beyond 100KHz
RESULT:
Thus the control of SMPS IC SG3524 had been studied.
62
Integrated Circuits.
Instrumentation Amplifier:
63
Program:
Integrated Circuits.
.LIB EVAL.LIB
VCC1 4
0
VEE1 0
5
VCC2 9
0
VEE2 0
10
VCC3 14 0
VEE3 0
15
V1 7
0
V2 1
0
R1 3
2
R2 8
6
R3 2
6
R4 3
11
R5 8
12
RF 11
13
R6 12
0
X1 1
2
X2 7
6
X3 12
11
.TRAN 0 20MS
.OP
.PROBE
.END
DC 15
DC 15
DC 15
DC 15
DC 15
DC 15
SIN(0 5V 100)
SIN(0 3V 100)
1K
1K
500
1K
1K
1K
1K
4
5
3
10
8
9
14
15
13
UA741
UA741
UA741
64
Integrated Circuits.
Lowpass Filter:
65
Program:
Integrated Circuits.
.LIB EVAL.LIB
VCC 5
0
DC
VEE 0
6
DC
VIN 2
0
AC
R1 1
0
22K
R2 1
4
22K
R3 2
3
1.5K
RL 4
0
10K
C1 3
0
0.1U
X1 3
1
5
.AC DEC 10 10 1MEG
.OP
.PROBE
.END
15
15
4
UA741
66
Integrated Circuits.
Highpass Filter:
67
Program:
Integrated Circuits.
.LIB EVAL.LIB
VCC 5
0
DC
VEE 0
6
DC
VIN 2
0
AC
R1 1
0
22K
R2 1
4
22K
C1 2
3
0.1U
RL 4
0
10K
R3 3
0
1.5K
X1 3
1
5
.AC DEC 10 10 100K
.OP
.PROBE
.END
15
15
4
UA741
68
Integrated Circuits.
69
Program:
Integrated Circuits.
.LIB EVAL.LIB
VCC 5
0
DC 15
VEE 0
6
DC 15
VCC110
0
DC 15
VEE1 0
11
DC 15
VIN 2
0
AC 4
R1 1
0
22K
R2 1
4
22K
R3 3
0
1.5K
R4 4
7
1.5K
R5 8
0
22K
R6 8
9
22K
RL 9
0
10K
C1 2
3
0.1U
C2 7
0
0.01U
X1 3
1
5
6
X2 7
8
10
11
.AC DEC 10 10 10MEG
.OP
.PROBE
.END
4
9
UA741
UA741
70
Integrated Circuits.
Astable Multivibrator:
71
Program:
Integrated Circuits.
.LIB EVAL.LIB
VCC 4
0
DC 15
VEE 0
5
DC 15
R1 2
0
10K
R2 2
3
11.6K
R3 1
3
50K
C1 1
0
0.01U
X1 2
1
4
5
.TRAN 0 5MS UIC
.OP
.PROBE
.END
UA741
72
Integrated Circuits.
Monostable Multivibrator:
73
Program:
Integrated Circuits.
.LIB EVAL.LIB
VCC 6
0
DC 15
VEE 0
7
DC 15
VIN 4 0 PULSE(4 0
1MS 0.001MS 0.001MS 1MS 2MS)
R1 5
2
10K
R2 2
0
10K
R3 1
5
50K
R4 3
0
100
C1 4
3
0.1U
C2 0
1
0.1U
D1 1
0
D1N4148
D2 2
3
D1N4148
X1 2
1
6
7
5
UA741
.TRAN 0 20MS
.OP
.PROBE
.END
74
Integrated Circuits.
Schmitt Trigger:
75
Program:
Integrated Circuits.
.LIB.EVAL.LIB
VCC 5
0
VEE 0
6
VIN 1
0
R1 3
0
R2 3
4
R3 1
2
RL 4
0
X1 3
2
.TRAN 0 30MS
.OP
.PROBE
.END
DC 15
DC 15
SIN(0 4 100)
10K
100K
10K
10K
5
6
4
UA741
76
Integrated Circuits.
77
Integrated Circuits.
Program:
.LIB EVAL.LIB
VCC 7
0
VEE 0
8
IS
3
0
50US 0MA
R1 1
2
R2 2
4
R3 5
0
R4 6
0
R5 1
0
R6 3
0
C1 5
4
C2 6
5
C3 1
6
X1 3
2
.TRAN 0 1
.OP
.PROBE
.END
DC 15
DC 15
PWL(0US 0MA 10US 0.1MA
10MS 0MA)
33K
1.02MEG
3.3K
3.3K
3.3K
33K
0.1U
0.1U
0.1U
7
8
4
UA741
40US 0.1MA
78
Integrated Circuits.
79
Integrated Circuits.
Program:
.LIB EVAL.LIB
VCC 5
0
VEE 0
6
IS
2
0
50US 0MA
R1 1
0
R2 1
4
R3 2
3
R4 2
0
C1 3
4
C2 2
0
X1 2
1
.TRAN 0 1
.OP
.PROBE
.END
DC 15
DC 15
PWL(0US 0MA 10US 0.1MA
10MS 0MA)
15K
30.2K
1.5K
1.5K
0.1U
0.1U
5
6
4
UA741
40US 0.1MA
80
Integrated Circuits.
ADDITIONAL EXPERIMENTS
81
Integrated Circuits.
CIRCUIT DIAGRAM:
Rf=2R
+15v
R
3
2R
2R
2R
2R
IC
+
7
741
4
15v
2R
b0
b1
b2
(010)V
b3
INPUT  SWITCH
(ON1 & OFF0)
TABULATION:
DECIMAL
EQUIVALENT BINARY
bo
b1
b2
b3
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
13
14
15
PRACTICAL THEORTICAL
VOLTAGE
VOLTAGE
82
Integrated Circuits.
DATE:
To design and test the operation of a 4 bit R 2R ladder type digital to analog
COMPONENTS
1.
IC 741
2.
RESISTORS
3.
4.
VOLTMETER
5.
CONNECTING WIRES
RANGE
QUANTITY

01
10 K
03
22K
06

01
(010)V
01

Few
THEORY:
Most DACs architectures are based on the popular R2R ladder. Starting from
the left hand side of the circuit to the right hand side, one can easily prove that the
equivalent resistance to the right of each labeled node equals 2R. Consequently, the
current flowing downward, away from each node equal to the current flowing toward
the right; twice this current enters the node from the left. The currents and, hence, the
node voltages are binary weighted.
With a resistance spread of only 2to1, R2R ladders can be fabricated
monolithically to a high degree of accuracy and stability. Depending on how ladders
are used, there were many DAC architectures available. There were two common
types of R2R DACs available based on current or voltage.
They are Current mode DAC and Voltage mode DAC based on whether the
circuit operated on current or voltage respectively. The major advantage of R2R
ladder architecture when compared with the binary weighted type is the use of only
two value resistors. These two values R and 2R make the design simple for any
resolution and thus easily realizable as an integrated circuit.
83
Integrated Circuits.
MODEL GRAPH:
0
0
0
0
1
0
0
0
0
1
0
0
1
1
0
0
1
0
1
1
0
1
1
1
1
1
1
1 Binary I/P
O/P VOLTAGE
(V)
DESIGN PROCEDURE:
1. Assume any value of R & find 2R.
2. Let R = 10K; therefore 2R = 20K 22K.
3. Let Rf = 2R = 22K.
84
Integrated Circuits.
PROCEDURE:
1. Select the given resolution as 24 = 16.
2. Assume the value of Resistor R and thus select another resistor with twice a value
of the first resistor (2R).
3. Connect the circuit as shown in the circuit diagram. Connect the series resistances
R finally to the inverting terminal of the opamp.
4. Connect the other end of the parallel arm resistors 2R to the digital switch to
represent binary logic conditions.
5. Calculate the output voltage from the voltmeter. Since negative output results from
opamp connect the output of opamp to the negative terminal of the voltmeter, to
get Positive deflections.
6. Plot the graph for output voltage versus input binary combinations.
RESULT:
Thus the R 2R ladder type digital to analog converter is designed & tested
using opamp IC 741.
85
Integrated Circuits.
86
Integrated Circuits.
Integrated Circuits.
Integrated Circuits.
Integrated Circuits.
19. What is the maximum voltage that can be given at the inputs?
Ans: The inputs must be given in such a way that the output should be less than Vsat.
20. How to construct a Subtractor?
Ans: A basic differential amplifier can be used as a subtractor. Input signals
can be scaled to the desired values by selecting appropriate values for the resistors.
When this is done, the circuit is referred to as scaling amplifier. However in this
circuit all external resistors are equal in value. So the gain of amplifier is equal to
one. The output voltage Vo is equal to the voltage applied to the noninverting
terminal minus the voltage applied to the inverting terminal; hence the circuit is called
a subtractor.
X      X       X
90
Integrated Circuits.
EXPT NO: 2
INTEGRATOR AND DIFFERENTIATOR USING OPAMP.
1. Express the output voltage of an Integrator.
Ans: The expression for the output voltage of an opamp integrator is given as
t
1
Vin dt + C
Vo = R1Cf 0
Where R1 Input Resistance
Cf Feedback Capacitance
Vin Input Voltage and
C Constant
2. Why opamp integrator is called as precision Integrator?
Ans: The opamp integrator has a high degree of accuracy. And it can
precisely implement the output voltage expression. Because of this, opamp integrator
is often called as precision integrator.
3. Mention some of the applications of integrator.
Ans: Opamp integrator finds wide application in function generators
(Triangle and sawtooth wave generators), active filters (State variable & biquad
filters, Switched Capacitor filters), Analog to Digital Converters (Dualslope
converters, Quantized feedback converters) and Analog controllers (PID Controllers).
4. What are the problems faced by basic ideal integrator and how can we
overcome ?
Ans: The input offset voltage Vio and the part of input current charging the
feedback capacitor Cf produces the error voltage at the output of the ideal integrator.
Therefore, in practical integrator, to reduce the error voltage at the output, a resistor
Rf is connected in parallel to Cf. This Rf, limits the lowfrequency gain and hence
minimizes the variations in the output voltage. Both stability and the rolloff problems
in basic ideal integrator can be corrected by additional resistor Rf.
5. What is other name given to practical integrator?
Ans: The method of preventing saturation in integrator is to place a parallel
resistance Rf with Cf. The resulting circuit is called as lossy integrator (Practical
Integrator) which can still provide integration function. But, only over a limited
frequency range. In most applications, integrators are placed in a control loop to
avoid saturation and there is no need for Rf in such applications.
6. What is meant by negative resistance?
Ans: Negative resistance indicates the release of power. Negative resistance
can be used to neutralize unwanted ordinary resistance, as in the design of current
sources or to control the pole location, as in the design of active filters and oscillators.
7. Integrator is otherwise called as fixed frequency, variable gain LPF. True or
False?
Ans: True.
91
Integrated Circuits.
Integrated Circuits.
X     X      X
93
Integrated Circuits.
EXPT NO: 3
INSTRUMENTATION AMPLIFIER
1. What are the important requirements of an instrumentation Amplifier?
Ans: The requirements of an instrumentation amplifier are low noise, low
thermal and time drifts, high input impedance, accurate closedloop gain, high CMRR
and high Slew Rate.
2. List the characteristics of a basic three opamp instrumentation amplifier.
Ans: For 3 opamp instrumentation amplifier, the characteristics are
i) The voltage gain, from differential input to single ended output is set
by
only one resistor.
ii)
The input resistance of both inputs are very high and does not
change as
the gain is varied.
iii) Vo does not depend on the voltage common to both inputs (Commonmode rejection) but, only on their difference.
3. Mention some of the applications of an instrumentation amplifier.
Ans: Instrumentation Amplifier is used in data acquisition unit, sensing,
measurement & Control of physical parameters such as temperature, used as signal
conditioning circuit, Lightintensity meter, Measurement of flow and thermal
conductivity, Analogweight scale, Active guard drive, digitally programmable gain
and output Offsetting.
4. What are the Different configurations of instrumentation amplifier? What are
the merits and demerits?
Ans: There were four configurations. They are
a. Triple opamp IAs
b. Dual opamp IAs
c. Monolithic IAs
d. FlyingCapacitor IAs
Triple opamp IA :
Offers high impedance because of buffer stage and too many components used.
Dual opamp IA:
Offers less Complexity in circuit (with fewer resistors & opamps) with
Significant boost in performance. But it treats the input asymmetrically with
Some delay.
Monolithic IA :
Better optimization of CMRR, gain linearity and noise reduction.
FlyingCapacitor IA :
Excellent CMRR, as common mode signals are completely ignored.
5. How many stages does a three opamp instrumentation amplifier contain?
And what are they?
Ans: A common opamp instrumentation amplifier uses 3 opamps and seven
resistors which is splitted into two stages. i) Buffer stage (High impedance)
Differential
input differential output stage.
ii) Difference amplifier stage.
94
Integrated Circuits.
Ad
Ac
The Differential mode gain is preferred than common mode gain. Common
mode gain indicates the gain of opamp when common mode noise signals are
present.
CMRR (dB) = 20 log
95
Integrated Circuits.
EXPT NO.4 :
ACTIVE FILTER (LP, HP & BP) USING OPAMP 741
1. What is meant by passive and active filters?
Ans: Passive filters: Uses Resistors, Capacitors and inductors as elements.
Active Filters: Uses Transistors or opamps in addition to Resistors and Capacitors.
2. Why active filters are not suitable for high frequency applications?
Ans: Above MHZ range the opamp openloop gain rollsoff with increase in
frequency.
3. List some of the applications of filters.
Ans: Filters are an integral part of electronic networks and are used in
application from audio circuits to Digital Signal Processing (DSP) Systems such as
speech, audio, Video, Image processing etc.,
4. How Active filters are superior than passive filters?
Ans: Advantage of active filters over passive filters
i) Gain and frequency adjustment flexibility.
ii)
No loading problem.
iii)
Low Cost.
5. How Filters are classified and what are they?
Ans: Based on passband, stopband and cutoff frequency, filters are classified
into Lowpass, Highpass, Bandpass, Bandstop and Allpass filters.
6. What are poles and zeros?
Ans: Zeros are numerator and poles are denominator polynomials of the
transfer function of a filter. Poles and Zeros determine the characteristics of a filter.
7. Does a filter affect both amplitude and phase of the input signal?
Ans: Yes.
8. What is the use of bode plot?
Ans: The Bode Plots are plots of decibels and degrees versus decades (or
Octaves).
The purpose of bode plot is to represent both logarithmic and semilogarithmic scales.
9. In what basis the order of the filter is decided?
Ans: Based on the parameter n, the order of the filter is decided. n=1; First
order, n=2; Second order and so on. The parameter n decides the accuracy of the
filter primarily at the stopband (Rolloff). Higher the value of n, better the filter will be
and complex the design will be.
10. Define Bandwidth of a filter.
Ans: Bandwidth of a filter is defined as higher cutoff frequency minus lower
cutoff frequency. Or in other words it is the difference between Upper cutoff
frequency and Lower cutoff frequency. Bandwidth is expressed in HZ.
B.W = fH fL HZ
96
Integrated Circuits.
A
2
Case iii: If the input frequency fin is greater than the higher cutoff frequency f H, then
magnitude of the gain is maximum and it is given as passband gain of the filter AF.
12. What were the different types of BPF? Explain.
Ans: BPF is classified either as Narrowband and Wideband filter based on the
Quality factor (Figure of merit) Q. It is expressed as
Q=
fc
fh
fl
fc
; where fc =
B.W
fhfl
97
Integrated Circuits.
Vo
=
Vin 1
Af
j ( f / fh)
ACL = Af / 1+ (f/fh)2
ACL(HPF) =
Vo
= Af
Vin
; = tan 1(f/fh)
( 1 j(jf( f/ /fl)fl) )
; = tan 1(f/fl)
98
Integrated Circuits.
EXPT NO.5:
ASTABLE, MONOSTABLE MULTIVIBRATOR AND
SCHMITT TRIGGER USING OPAMP
1. Define multivibrator.
Ans: A multivibrator is an oscillatory circuit capable of generating waveforms
without any Specific input signal. The circuit only has supply voltage connections,
from which the two amplifiers saturates one another to generate vibrations.
2. State the relationship between Astable multivibrator and a comparator.
Ans: Astable multivibrator is almost a comparator except the trigger or
threshold voltage will be generated on its own.
3. Express the frequency of oscillation of an Astable Multivibrator.
Ans: The frequency of oscillation of free running multivibrator is given as
fo =
1
1
=
2 RC ln(1 2 R1 / R 2)
T
T = 2RC ln
( 2R1R2 R2 )
99
Integrated Circuits.
R1
(Vsat)
R1 R 2
100
Integrated Circuits.
EXPT NO.6:
1
2 RC
101
Integrated Circuits.
EXPT NO.7:
Ton
Ttotal
Example: If a square wave is On for 1ms of time and if the total time is 2ms,
The duty cycle is 0.5 or in terms of percentage = 50%.
6. Express the free running frequency of oscillation and total period of Astable
mode of 555 timer.
Ans: The free running frequency of oscillation is given as
f=
1.44
1
=
and thus the total period of oscillation T is
( Ra 2 Rb)C
T
T = 0.695 (Ra+2Rb)C
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EXPT. NO: 8
102
Integrated Circuits.
1. What is a PLL?
A PLL is a Phase Locked Loop Circuit used to track any changes in the input
frequency.
2. What are the operating modes of an PLL?
A PLL functions in any in any one of the mode described here.
1) Free Running mode
2) Capture mode
3) Lock mode and
4) Tracking mode/range
3. What are the basic building blocks of a PLL IC?
The basic building blocks of PLL IC are 1) Phase comparator 2) Low
Pass Filter and 3) Error Amplifier.
4. What is meant by free running mode of a PLL?
A PLL is said to be in this mode when there is no input frequency
given to phase comparator for comparison. When no input is given, PLL runs
freely without any locking or tracking and so it is called as free running mode
of PLL.
5. Name some of the applications of PLL IC 565.
PLL ICs are mostly used in frequency application circuits such as
Frequency synthesizer, frequency multiplier, frequency divider, phase
comparator, FM demodulator, PM demodulator, Phase magnitude comparator,
etc.,
6. Why PLL Circuit is mostly preferred in Frequency Applications?
It is preferred in most of the frequency applications because the
frequency content of a signal is indirectly proportional to Phase of the same
signal. As we compare the phase of the two signals, we indirectly compare the
frequency of the same signal. This is due to the fact that direct phase is
nothing but indirect frequency and direct frequency is nothing but indirect
phase.
7. What happens when the two input signals given to PLL is having same
frequency or same phase?
When both the inputs are same, the PLL will start functioning in the
Lock mode and if once lock has been occurred, the PLL will start tracking the
Phase or frequency changes in the input signal.
8. What is VCO?
VCO is the integral part of PLL. A VCO is the Voltage Controlled
Oscillator. As the name implies it generates oscillations according to the input
voltage. This VCO is placed in the feedback path of a PLL. The output of the
VCO is changing according to the Error output voltage from the error
amplifier placed finally in the forward path.
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103
Integrated Circuits.
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104