Digital System Design

(Tutorials)

Name

: Naveen Singh

Roll No : 00410402813
Batch

: ECE 2013-17

Tutorial 3
Answer 1)
Generate Statement: Concurrent statements can be conditionally selected or replicated during the elaboration phase using the generate statement. There are two
forms of generate statement :
1. Using the for generation scheme, Concurrent statement can be replicated a
predetermined number of times.
2. With the if generation scheme, Concurrent statement can be conditionally
elaborated.
Answer 2)
Package declaration:
Package declaration contains a set of declarations that may possibly be shared by
many design units.
Syntax :
package package name is
package item declaration
- - subprogram declaration
- - type declaration
- - Subtype declaration
- - constant declaration
- - Signal Declaration
- - Variable Declaration
- - file declaration
end [package][package name]

Package Body :
A package body primarily contains the behavior of the subprogram and the values
of preferred constant declared in the package declaration.
Syntax :
Package body package name is
package body item declaration
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- - subprogram bodies
- - complete constant declaration
- - Subprogram declaration
- - Type and subtype declaration
end[packagebody][package name];
Answer 3)
Functions :
The functions are usually used for computing a single value. A function executes
in zero simulation time.
Procedures :
Procedures may be used to partition large behavioral description. Procedures can
return zero or more values. A procedure may or may nit execute in zero simulation
time, depending on whether it has wait statement or not.

Answer 4)
Subprogram Overloadibg:
Sometimes it is convenient to have two or more subprogram with the same name.
In such a case, the subprogram name is said to be overloaded.; also the corresponding subprogram are said to be overloaded.
e.g.,
function COUNT(N AM E : IN T EGER)
return INTEGER;
function COUNT(AN OT HER N AM E : IN T EGER)
return INTEGER;

So, both functions are overloaded, since both functions have the same
name COUNT.

Answer 5)
Operator Overloading :
Operator overloading is one of the most useful feature in the language when a standard operator symbol is made to behave differently based on the type if operands,
the operator is said to be overloaded. The need to be overloaded arises from the
fact that the predefined operator in the language are defined only for operands of
certain predefine types.
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For e.g., The AND operation is defined for assignment of type bit and Boolean
and for one dimensional array of BIT and BOOLEAN only.

Answer 6)
Generics :
Generics of an entity are declared along with its ports in the entity declaration.
A generic declares a constant object of mode in and can be used in the entity
declaration and its corresponding architecture bodies. The value of this constant
can be specified as a globally static expression in one of the following:

1. Entity Declaration
2. Component Declaration
3. Component Instantiation
4. Configuration Specification
5. Configuration Declaration
Answer 7)
Attributes in VHDL :
An attribute is a value, function, type, range or constant that can be associated
with the certain names within a VHDL description.
These names could be among others, an entity name, an architecture name, an
label or a signal.
1. User Defined attribute : User defined attribute are the constant of any type.
Syntax :
attribute Attribute name : Value type;
2. Predefined Attribute : There are 5 classes of predefined attributes :
(a) Value Attribute : Return a constant value
(b) Function Attribute : It calls a function that return a value.
(c) Signal Attribute : It create a new signal.
(d) Type attribute : It return a type name.
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(e) Range Attribute : It return a range.

Answer 8)
Postponed process :
It is used to trigger a process only at the end of all the delta of simulation time,
instead of executing it in every delta in which the process resumes execution
Syntax :
postpones process
--------Begin
-------end postpones process

Such a process executes only at the end of all deltas of the simulation
time which are event triggered the process to resume execution.

Answer 9)
Resolution Function:
A resolution function is a function that defines how the value of multiple source
of a given signal are to be resolved into single value for that signal.
Syntax :
function function name(parameter) return type;
function function name(parameter) return type is
declaration
begin
sequential statement
end function function name;

Answer 10)
Constant is an object whose value cant be changed once defined for the design.
Constant may be explicitly declared oe they may be sub elements of explicitly
declared constant or interface constant. Constants declared in packages may be
constant.
Syntax :
constant constant name : type := value
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