80286

Architecture- Introduction

Instruction Unit
(IU)

PIPELINING
BU
IU
EU
AU

BU
Performs all memory and I/O reads and writes,
Prefetches instruction bytes
Controls transfer of data to and from processor extension devices

IU
IU
Fully Decodes up to three prefetched instructions and holds them in a
queue
Where the execution unit can access them

EU
EU
16-bit ALU to execute instructions

AU
Computes the physical addresses that will be sent out to memory or
I/O by the BU

BIU

Address Unit
Selected
Address

Base Reg
Protection
Info
Protection
Logic
Address
Information
Registers
ALU
Multiplier
Execution Unit

Data

Address
Drivers
Data
Buffers
Instruction
Prefetch
Code
Queue

Instructions
Code

Decoded
Instructions

Translator

Inst
Queue
Instruction
Unit

Address

Data

Control

80286
Pin Out

80286
PEREQ
PEACK
BUSY
ERROR

A23 A0

D15 D0
BHE

NMI
INTR
HLDA
HOLD
LOCK

M/IO
S1
S0
COD/INTA
CLK
RESET

READY

BUS CONTROL SIGNALS

COD/INTA M/IO S1

S0

Bus Cycle

INTA

None, Not a status cycle

HALT/SHUTDOWN(A1)

MEMR

MEMW

None, Not a status cycle

IOR

IOW

None, Not a status cycle

Instruction Read

None, Not a status cycle

REGISTERS
MSW
TS

EM MP PE

Flag Register
NT

IO

PL

OF

DF

IF

TF

SF

ZF

AF

PF

CF

80386
PIN OUT

80386
PEREQ
BUSY
ERROR

NMI

INTR
HLDA
HOLD
LOCK

A31 A2
D31 D0
BE0
BE1
BE2
BE3'

M/IO
R/W
D/C
ADS
NA
CLK2
RESET
READY
BS16

80386
Architecture

80386 - ARCHITECTURE

BIU
Interface to the outside world -Responsible for
Fetching instruction
Reading and writing of data for memory
Inputting and outputting of data for input/output peripherals

Information transfers over the microprocessor bus

De-multiplexed bus
386DX
32-bit data bus

Real-mode: 20-bit address, 1M-byte physical address

space
Protected-mode: 32-bit address bus, 4G-byte physical
address space

PREFETCH UNIT
Instruction Stream queue
Whenever the queue is not full, prefetch the next sequential
instructions
Queue16-byte; 4-byte/memory cycle
Prioritizes bus accessesdata operands highest priority

FIFO instruction queue

Holds bytes of instruction code until the decode unit is ready
to accept them
Bus unit Idle state - If queue is full and the execution unit is
not requesting access to data in memory, BIU does not
perform bus cycles

DECODE UNIT
Offloads the responsibility of instruction decoding from the
execution unit.
Reads machine code instructions from the output side of the
instruction queue
Decodes the instructions into the microcode instruction format used by
the execution unit
Contains an instruction queue that holds 3 fully decoded instruction
Decoded instructions are held until requested by the execution unit

EXECUTION UNIT
Responsible for executing instructions
Arithmetic/logic unit (ALU)
Performs the operation identified by the instruction: ADD, SUB,AND, etc.

Flags register
Holds status and control information

General-purpose registers
Holds address or data information

Special multiply, shift, and barrel shift hardware

Accelerate multiply, divide, and rotate operations

SEGMENTATION & PAGING UNIT

Memory management & Protection Status

80486
Architecture & Pin Out

32 bit Data Bus

32
32

32 bit Data Bus

Linear Address Bus

BUS
INTERFACE

32
Barrel
Shifter

Register
File

Segmentation
Unit
Base /
Index
Bus
32

ALU

Paging Unit

Translation
Lookaside
Buffer

Physical
Address

8k Byte
Cache

32

Write
Buffers
Data Bus
Treansceivers

Displacement Bus
32

BRDY#
BLAST#

Control
Rom

Prefetcher

Bus Size
Control

KEN#
FLUSH#
AHOLD,
EADS#

Cache
Control

Control and
Protection
test Unit

Instruction
Decode
Decode
Instruction
Path

Code 32 Byte Code

Stream
Queue
24

D0 - D31

Bus Control
Request
Sequencer
Burst Bus
Control

Micro Instruction

F.P. Register
File

Address
Drivers

32

128

Floating
point Unit

32

A2 A 31
BE0# - BE3#

20

Descriptor
Register

Limit and
Attribuite PLA

Cache
Unit

Parity Generation
and Control
PCHK# DP0-DP3

A31 A2

DP0
DP1
DP2
DP3
PCHK

BRDY
BLAST
NMI
INTR
KEN
FLUSH
IGNE
FERR
AHOLD
EADS
LOCK
PLOCK
PCD
PWT

D31 D0
BE0
BE1
BE2
BE3'
BS8
BS16
A20M

80486

M/IO
R/W
D/C
ADS
BREQ
BOFF
HLDA
HOLD
CLK2
RESET
READY