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IEEE 1801

UPF Solutions Guide

July 2009

IEEE 1801-2009 is an IEEE Standard for Design and Verification of


Low Power Circuits
The power supplied to elements in an electronic design affects the way circuits
operate. Although this is obvious when stated, todays set of high-level design
languages have not had a consistent way to concisely represent the regions
of a design with different power provisions, nor the states of those regions or
domains. This standard provides an HDL-independent way of annotating a
design with power intent. In addition, the level-shifting and isolation between
power domains may be described for a specific implementation, from highlevel constraints to particular configurations. When the logic in a power domain
receives different power supply levels, the logic state of portions of the design
may be preserved with various state- retention strategies. This standard provides mechanisms for the refined and specific description of intent, effect, and
implementation of various retention strategies. Incorporating components into
designs is greatly assisted by the encapsulation and specification of the characteristics of the power environment of the design and the power requirements
and capabilities of the components; this information encapsulation mechanism
is also described in this standard. The analysis of the various power modes of a
design is enabled with a combination of the description of the power modes and
the collection, generation, and propagation of switching information.
Order On-Line at: http://standards.ieee.org/prod-serv/index.html
Part Number: STD95919 Format: PDF ISBN: 978-0-7381-5929-4
UPF is a Copyright of Accellera. All other trademarks and copyrights belong
to their respective owners. There is no intent to violate anyones rights.
Latest UPF Solutions Guide can be downloaded from:
http://www.accellera.org/upf/SolutionsGuide.pdf
All the information contained in this solution guide about products and contacts
is provided by respective vendors. The user of this solution guide is requested
to check the latest product information by contacting the respective vendor.
This solution guide should not be used as the sole source of information for
making decisions regarding suitability of UPF or any UPF related products for
any purpose.
Original Version: July 2007
4th Edition: July 2009
For corrections and additions, please contact Yatin Trivedi, trivedi@synopsys.com

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Low Power Design & Verification Flow


UPF
HDL
(RTL)

UPF
Verilog
(Netlist)

P&R

Simulation, Logical Equivalence Checking,

Synthesis

UPF
Verilog
(Netlist)

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MPSim

UPF Specification

RT
L

Test
bench

Simulate power off corruption


Simulate retention and
save/restore of states
Simulate isolation and clamping

Designer

MPSim
Simulation

Protometer
Coverage

Designer
Debug

Visualize power switch states


Visualize the states of powered
off blocks throughout simulation
Annotate powered off signals

ProtoMeter

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Trace complete power network


and switches

Automate power verification


combinations
Verify all possible power
combinations
Power verification closure

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RTL

RTL

Synthesis

Synthesis

Initial Place

Initial Place
Verilog
netlist

Phys. Opt.

Placed
DEF

SDC

Phys. Opt.
Verilog
netlist

Placed
DEF

SDC

CTS

CTS

Rubix

PowerCentric
Post-CTS Opt.

Post-CTS Opt.
Verilog
netlist

Placed
DEF

Routing

Routing

PRO

PRO

GDSII

GDSII

PowerCentric Clock Tree


Synthesis

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Verilog
netlist

Placed
DEF

Rubix Clock Concurrent


Optimization

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Electronic System Platform : Board, SoC, SiP, IP :


Power intents, power related parameters,
Specification architecture
structure, thermal behavior

Use cases

Activity

High Level Model Builder

IP
Power Model Database

Platform model

Use Case model

ACEplorer
Fast Electro-thermal Simulator

Architecture

exploration, use case profiling


Power and Temperature estimation
Automatic generation of UPF format
Package and cooling technique selection
Early

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System Structure

Power Characterization

Low power architecture capture :


Power domains, voltage/clock network, power
reduction techniques modelling

ACEplorer
High Level Power Model
XML based

UPF
Standard RTL to GDSII flow

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Memory Compilers
Hi-Performance and Low Power
Full Redundancy (Single & Dual
Port SRAM, 1, 2 & 4-Port RegFile

Memories
Standard Cells

Custom Memory and


BCAM/TCAM
High Speed/High Density
Standard Cells >1GHZ Designs
Ultra High Density and Low Power

I/O Blocks
Specialty Blocks

Specialty High Speed I/Os and


Standard I/O cells
SERDES and PLL

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Vista Architect
PowerPower-Aware TLM
Power-Aware
TLM

Catapult HLS

TestKompress
Olympus SoC

Questa
Questa

0
-In
In CDC
0-In

FormalPro
FormalPro

RTL Synthesis

IEEE
(UPF)
1801 (UPF)
IEEE 1801

Architectural
Architectural
TradeTrade-Off Analysis
Trade-Off
Analysis

MultiMulti-Corner MultiMulti-Mode
Multi-Corner
Multi-Mode
Place
Place &
& Route
Route

Calibre PERC

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UPF
UPF
HDL
HDL
(RTL)
(RTL)

FormalPro
FormalPro

UPF
UPF
Verilog
Verilog
(Netlist)
(Netlist)

Questa
Questa

Synthesis

P&R

UPF
UPF
Verilog
Verilog
(Netlist)
(Netlist)

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Floating-Point
Algorithm
Memory Architecture

Floating-Point
C++ Model

Quality Requirements
and Synthesis Style

Fixed-Point
C++ Model

Performance, Area,
Power and Interface
Requirements

Catapult
Interface
Constraint

Catapult

Area + Static
Performance
Estimates

Dynamic
Performance Data

MicroArchitecture
Constraint
Simulation

Power Consumption
Accurate Timing and Area

Formal
Verification

Power
Analysis
RTL Synthesis
+ P and R
Hardware
ASIC/FPGA

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mimasic
Low Power SoC Design and Verification Services

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Predictable Success

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RTL
code
RTL Simulation
MVSIM

Logic Synthesis & STA


Design Compiler

PrimeTime

Netlist
Floor Planning
IC Compiler
Floor plan

Place & Route


IC Compiler
Multi-Voltage Rule Checker
Power Analysis (PrimeRail)
Formal Checking (Formality)

Chip Finishing
RC Extraction (Star-RCXT)

UMC UPF Solutions


Standard Cell Libraries
UPF tags/header embedded
Timing & Power Models

Technology Files
Based on UMCs premium
device models
DRC / LVS / LPE included

Reference Design Flow(*)


EDA script examples
Application notes
Silicon experimental documents
(*) Slated for availability in Q3 2008

DRC/LVS (Hercules)

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ISBN: 978-0-387-71818-7

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What is UPF?
Unified Power Format (UPF), a format to describe low power intent for
design implementation, analysis and verification, is the standard developed by
Accellera as UPF 1.0 in February 2007 and ratified by IEEE as IEEE 1801
Standard for Design and Verification of Low Power Circuits in March 2009.
It enables open, multi-vendor tool flows and solutions for low-power ASIC
and SoC design. The true value of a single, widely adopted standard is demonstrated by interoperability of products from a range of EDA suppliers who
support the UPF standard. Designers of modern, low-power ICs are the ultimate
beneficiaries of UPF.
UPF 1.0 standard from Accellera is accessible to everyone. The latest version of
this document can be downloaded from Accelleras website at:
http://www.accellera.org.
IEEE 1801 standard can be purchased from IEEE Standards website:
http://standards.ieee.org/prod-serv/index.html
For more details on the IEEE 1801 Working Group activity, you can sign up for
1801 email group by sending an email to owner-p1801@eda.org.

July 2009

UPF Solutions Providers

Dolphin Technology