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Dual 8-Bit, 60 MSPS A/D Converter

AD9059
FEATURES
Dual 8-Bit ADCs on a Single Chip
Low Power: 400 mW Typical
On-Chip 2.5 V Reference and Track-and-Hold
1 V p-p Analog Input Range
Single 5 V Supply Operation
5 V or 3 V Logic Interface
120 MHz Analog Bandwidth
Power-Down Mode: <12 mW
APPLICATIONS
Digital Communications (QAM Demodulators)
RGB and YC/Composite Video Processing
Digital Data Storage Read Channels
Medical Imaging
Digital Instrumentation

FUNCTIONAL BLOCK DIAGRAM


PWRDN

VD

VDD

AD9059
AINA

T/H

ADCA

8
D7AD0A

VREF
ENCODE
2.5V
AINB

T/H

ADCB

8
D7BD0B

GND

PIN CONFIGURATION
PRODUCT DESCRIPTION

The AD9059 is a dual 8-bit monolithic analog-to-digital converter


optimized for low cost, low power, small size, and ease of use.
With a 60 MSPS encode rate capability and full-power analog
bandwidth of 120 MHz typical, the component is ideal for
applications requiring multiple ADCs with excellent dynamic
performance.

AINA 1

28 AINB

VREF 2

27 GND
26 ENCODE

PWRDN 3

25 VD

VD 4
GND 5

AD9059

24 GND

VDD 6

TOP VIEW 23 VDD


D7A (MSB) 7 (Not to Scale) 22 D7B (MSB)

To minimize system cost and power dissipation, the AD9059


includes an internal 2.5 V reference and dual track-and-hold
circuits. The ADC requires only a 5 V power supply and an
encode clock. No external reference or driver components are
required for many applications.

D6A 8

21 D6B

D5A 9

20 D5B

D4A 10

19 D4B

D3A 11

18 D3B

D2A 12

17 D2B

The AD9059s single encode input is TTL/CMOS compatible


and simultaneously controls both internal ADC channels. The
parallel 8-bit digital outputs can be operated from 5 V or 3 V
supplies. A power-down function may be exercised to bring
total consumption to <12 mW when ADC data is not required
for lengthy periods of time. In power-down mode, the digital
outputs are driven to a high impedance state.

D1A 13

16 D1B

D0A (LSB) 14

15 D0B (LSB)

Fabricated on an advanced BiCMOS process, the AD9059


is available in a space-saving 28-lead shrink small outline
package (28-lead SSOP) and is specified over the industrial
temperature range (40C to +85C).
Customers desiring single-channel digitization may consider the
AD9057, a single 8-bit, 60 MSPS monolithic based on the
AD9059 ADC core. The AD9057 is available in a 20-lead shrink
small outline package (20-lead SSOP) and is specified over the
industrial temperature range.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.


Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
2003 Analog Devices, Inc. All rights reserved.

AD9059SPECIFICATIONS
(V = 5 V, V

ELECTRICAL CHARACTERISTICS

Parameter

DD

= 3 V, external reference, ENCODE = 60 MSPS, unless otherwise noted.)

Temp

Test Level

Min

RESOLUTION

AD9059BRS
Typ
Max
8

DC ACCURACY
Differential Nonlinearity

25C
Full
25C
Full
Full
25C
Full
Full

I
VI
I
VI
VI
I
VI
V

25C
25C
Full
25C
25C
25C
25C

V
I
VI
V
V
I
V

CHANNEL MATCHING (A to B)
Gain Delta
Input Offset Voltage Delta

25C
25C

V
V

BAND GAP REFERENCE


Output Voltage
Temperature Coefficient

Full
Full

VI
V

2.4

SWITCHING PERFORMANCE
Maximum Conversion Rate
Minimum Conversion Rate
Aperture Delay (tA)
Aperture Uncertainty (Jitter)
Output Valid Time (tV)2
Output Propagation Delay (tPD)2

Full
Full
25C
25C
Full
Full

VI
IV
V
V
IV
IV

60

25C
25C

V
V

25C
25C

I
V

25C
25C

Integral Nonlinearity
No Missing Codes
Gain Error1
Gain Temperature Coefficient1
ANALOG INPUT
Input Voltage Range (Centered at 2.5 V)
Input Offset Voltage
Input Resistance
Input Capacitance
Input Bias Current
Analog Bandwidth

0.75
0.75

6
8

15
25

Bits
2.0
2.5
2.0
2.5

Guaranteed
2.5
+6
+8
70
1.0
0
150
2
6
120

+15
+25

16

1
4
2.5
10

4.0

LSB
LSB
LSB
LSB
% FS
% FS
ppm/C
V p-p
mV
mV
k
pF
A
MHz
% FS
mV

2.6

5
2.7
5
6.6
9.5

Unit

14.2

V
ppm/C
MSPS
MSPS
ns
ps, rms
ns
ns

DYNAMIC PERFORMANCE
Transient Response
Overvoltage Recovery Time
Signal-to-Noise Ratio (SINAD) (with Harmonics)
fIN = 10.3 MHz
fIN = 76 MHz
Effective Number of Bits (ENOB)
fIN = 10.3 MHz
fIN = 76 MHz
Signal-to-Noise Ratio (SNR) (Without Harmonics)
fIN = 10.3 MHz
fIN = 76 MHz
Second Harmonic Distortion
fIN = 10.3 MHz
fIN = 76 MHz
Third Harmonic Distortion
fIN = 10.3 MHz
fIN = 76 MHz
Two-Tone Intermodulation Distortion (IMD)
Channel Crosstalk Rejection
Differential Phase
Differential Gain

9
9

ns
ns

40

44.5
43.5

dB
dB

I
V

6.35

7.1
6.9

Bits
Bits

25C
25C

I
V

42

46
45

dB
dB

25C
25C

I
V

50

62
54

dBc
dBc

25C
25C
25C
25C
25C
25C

I
V
V
V
V
V

46

60
54
52
50
0.8
1.0

dBc
dBc
dBc
dBc
Degrees
%

REV. A

AD9059

SPECIFICATIONS (continued)
Parameter

Temp

Test Level

Min

DIGITAL INPUTS
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Input Capacitance
Encode Pulsewidth High (tEH)
Encode Pulsewidth Low (tEL)

Full
Full
Full
Full
25C
25C
25C

VI
VI
VI
VI
V
IV
IV

2.0

Full
Full
Full

VI
IV
VI

Full
Full
Full
Full
25C

VI
VI
VI
VI
I

DIGITAL OUTPUTS
Logic 1 Voltage (VDD = 3 V)
Logic 1 Voltage (VDD = 5 V)
Logic 0 Voltage (VDD = 3 V or 5 V)
Output Coding
POWER SUPPLY
VD Supply Current (VD = 5 V)
VDD Supply Current (VDD = 3 V)4
Power Dissipation5, 6
Power-Down Dissipation
Power Supply Rejection Ratio (PSRR)

AD9059BRS
Typ
Max

0.8
1
1
4.5
6.7
6.7

166
166

2.95
4.95
0.05
Offset Binary Code
72
13
400
6
3

92
15
505
12

Unit
V
V
A
A
pF
ns
ns
V
V
V

mA
mA
mW
mW
mV/V

NOTES
1
Gain error and gain temperature coefficient are based on the ADC only (with a fixed 2.5 V external reference).
2
tV and tPD are measured from the 1.5 V level of the ENCODE to the 10%/90% levels of the digital output swing. The digital output load during test is not to exceed
an ac load of 10 pF or a dc current of 40 A.
3
SNR/harmonics based on an analog input voltage of 0.5 dBFS referenced to a 1.0 V full-scale input range.
4
Digital supply current based on V DD = 3 V output drive with <10 pF loading under dynamic test conditions.
5
Power dissipation is based on 60 MSPS encode and 10.3 MHz analog input dynamic test conditions (V D = 5 V 5%, VDD = 3 V 5%).
6
Typical thermal impedance for the RS style (SSOP) 28-lead package: JC = 39C/W, CA = 70C/W, and JA = 109C/W.
Specifications subject to change without notice.

EXPLANATION OF TEST LEVELS

ABSOLUTE MAXIMUM RATINGS*

Test Level
I 100% production tested.

VD, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VD + 0.5 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VD + 0.5 V
VREF Input . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VD + 0.5 V
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature . . . . . . . . . . . . . . . . . . 55C to +125C
Storage Temperature . . . . . . . . . . . . . . . . . . . . 65C to +150C

II

100% production tested at +25C and sample tested at


specified temperatures.

III

Sample tested only.

IV

Parameter is guaranteed by design and characterization


testing.

Parameter is a typical value only.

VI

100% production tested at +25C; guaranteed by design


and characterization testing for industrial temperature range.

*Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum ratings for extended
periods may affect device reliability.

ORDERING GUIDE

Model

Temperature Range

Package Option

AD9059BRS
AD9059/PCB

40C to +85C
25C

RS-28
Evaluation Board

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD9059 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

REV. A

AD9059
PIN FUNCTION DESCRIPTIONS
N

N+3

N+5

N+1

AIN

N+2
N+4

Pin No.

Mnemonic

1, 28

AINA, AINB Analog Inputs for ADC A and B.

VREF

Internal Voltage Reference (2.5 V


Typical); Bypass with 0.1 F to
Ground or Overdrive with External
Voltage Reference.

PWRDN

Power-Down Function Select; Logic


HIGH for Power-Down Mode
(Digital Outputs Go to HighImpedance State).

4, 25

VD

Analog 5 V Power Supply.

tA
ENCODE

tEH

tEL
tV

DIGITAL
OUTPUTS

N3

N2

N1

N+1

N+2

tPD
MIN
tA
tEH
tEL
tV
tPD

TYP

MAX

2.7ns

APERTURE DELAY
PULSEWIDTH HIGH

6.7ns

PULSEWIDTH LOW

6.7ns

OUTPUT VALID TIME

4.0ns

OUTPUT PROP DELAY

166ns

5, 24, 27

GND

Ground.

6, 23

VDD

Digital Output Power Supply.


Nominally 3 V to 5 V.

714

D7AD0A

Digital Outputs of ADC A.

2215

D7BD0B

Digital Outputs of ADC B.

26

ENCODE

Encode Clock for ADCs A and B


(ADCs Sample Simultaneously on
the Rising Edge of ENCODE).

166ns
6.6n
9.5ns

14.2ns

Figure 1. Timing Diagram


PIN CONFIGURATION

AINA 1

28 AINB

VREF 2

27 GND

AD9059

24 GND

VDD 6

23 VDD

D6A 8

21 D6B

D5A 9

20 D5B

D4A 10

19 D4B

D3A 11

18 D3B

D2A 12

17 D2B

D1A 13

16 D1B

TOP VIEW
D7A (MSB) 7 (Not to Scale) 22 D7B (MSB)

D0A (LSB) 14

Analog Input (V)

Voltage Level

Digital Output

3.0
2.502
2.498
2.0

Positive Full Scale


Midscale + 1/2 LSB
Midscale 1/2 LSB
Negative Full Scale

1111 1111
1000 0000
0111 1111
0000 0000

25 VD

VD 4
GND 5

Table I. Digital Coding (VREF = 2.5 V)

26 ENCODE

PWRDN 3

Function

15 D0B (LSB)

REV. A

Typical Performance CharacteristicsAD9059


30

0
ENCODE = 60MSPS
ANALOG IN = 10.3MHz, 0.5dBFS
SINAD = 43.9dB
ENOB = 7.0 BITS
SNR = 45.1dB

10
20
30

ENCODE = 60MSPS
AIN = 0.5dBFS

35
40
45

SECOND HARMONIC
dB

dB

40
50

50
55
60
60

70

THIRD HARMONIC
65

80
90
0

70

30

FREQUENCY (MHz)

20

60

80

100

120

140

160

TPC 4. Harmonic Distortion vs. AIN Frequency

0
ENCODE = 60MSPS
10
ANALOG IN = 76MHz, 0.5dBFS
20 SINAD = 43.0dB
ENOB = 6.85 BITS
30 SNR = 44.1dB

10

40

40

ENCODE = 60MSPS
F1 IN = 9.5MHz @ 7.0dBFS
F2 IN = 9.9MHz @ 7.0dBFS
2F1 - F2 = 52.0dBc
2F2 - F1 = 53.0dBc

20

dB

30

50

50

60

60

70

70

80

80

90

90

30

FREQUENCY (MHz)

10

TPC 2. Spectral Plot 60 MSPS, 76 MHz

30

54
SNR

AIN = 10.3MHz, 0.5dBFS

44

SNR

48

42

42

SINAD

SINAD

40

36
dB

38
ENCODE = 60MSPS
AIN = 0.5dBFS

36

30
24

34

18

32

12

30
0

20

40
60
80
100
120
140
ANALOG INPUT FREQUENCY (MHz)

160

TPC 3. SINAD/SNR vs. AIN Frequency

REV. A

20
FREQUENCY (MHz)

TPC 5. Two-Tone IMD

46

dB

40

ANALOG INPUT FREQUENCY (MHz)

TPC 1. FFT Spectral Plot 60 MSPS, 10.3 MHz

dB

10

20

30
40
50
60
ENCODE RATE (MSPS)

70

80

TPC 6. SINAD/SNR vs. Encode Rate

90

AD9059
600

12

AIN = 10.3MHz, 0.5dBFS

11

550

10

VDD = 3V

9.5

450

9.0

VDD = 5V

tPD (ns)

POWER (mW)

500

400

8.5
8.0
7.5

350
VDD = 3V

300

VDD = 5V

7.0
6.5

250

10

20

30
40
50
60
ENCODE RATE (MSPS)

70

80

6.0
45

90

TPC 7. Power Dissipation vs. Encode Rate

25
TEMPERATURE (C)

70

90

TPC 10. tPD vs. Temperature/Supply (3 V/5 V)

45.5

46.0

SNR

45.5

45.0

SNR

45.0
44.5
44.5

SINAD

44.0

43.5

43.5

dB

dB

44.0

SINAD

43.0

43.0

42.5
ENCODE = 60MSPS
AIN = 10.3MHz, 0.5dBFS

42.5

42.0

ENCODE = 60MSPS
AIN = 10.3MHz, 0.5dBFS

41.5

42.0

41.0
41.5
45

25
70
TEMPERATURE (C)

40.5
5.8

90

6.7

7.5

8.4

9.2

10

10.9

ENCODE HIGH PULSEWIDTH (ns)

TPC 8. SINAD/SNR vs. Temperature

TPC 11. SINAD/SNR vs. Encode Pulsewidth


0

0.2

0.4

ADC GAIN (dB)

GAIN ERROR (%)

0.6
0.8
1.0
1.2
1.4

5
6
ENCODE = 60MSPS
AIN = 0.5dBFS

7
8
9

1.6
1.8
45

10

25
70
TEMPERATURE (C)

90

10

20

50

100

200

500

ANALOG FREQUENCY (MHz)

TPC 12. ADC Frequency Response

TPC 9. ADC Gain vs. Temperature (With External


2.5 V Reference)

REV. A

AD9059
Figure 3 shows typical connections for high performance dc
biasing using the ADCs internal voltage reference. All components may be powered from a single 5 V supply (analog input
signals are referenced to ground).

THEORY OF OPERATION

The AD9059 combines Analog Devices proprietary MagAmp


gray code conversion circuitry with flash converter technology to
provide dual high performance 8-bit ADCs in a single low cost
monolithic device. The design architecture ensures low power,
high speed, and 8-bit accuracy.

1k

The AD9059 provides two linked ADC channels that are clocked
from a single ENCODE input (see Functional Block Diagram).
The two ADC channels simultaneously sample the analog inputs
(AINA and AINB) and provide noninterleaved parallel digital
outputs (D0AD7A and D0BD7B). The voltage reference
(VREF) is internally connected to both ADCs so channel gains
and offsets will track if external reference control is desired.

1k

1 AINA
10k
3 VREF
10k

AD9059
AD8041
VINB
(0.5V TO +0.5V)

Figure 3. DC-Coupled AD9059 (VIN Inverted)

A stable and accurate 2.5 V voltage reference is built into the


AD9059 (VREF). The reference output is used to set the ADC
gain/offset and can provide dc bias for the analog input signals.
The internal reference is tied to the ADC circuitry through an
800 internal impedance and is capable of providing 300 A
external drive current (for dc biasing the analog input or other
user circuitry).
Some applications may require greater accuracy, improved
temperature performance, or gain adjustments that cannot be
obtained using the internal reference. An external voltage may
be applied to the VREF pin to overdrive the internal voltage
reference for gain adjustment of up to 10% (the VREF pin is
internally tied directly to the ADC circuitry). ADC gain and
offset will vary simultaneously with external reference adjustment with a 1:1 ratio (a 2% or 50 mV adjustment to the 2.5 V
reference varies ADC gain by 2% and ADC offset by 50 mV).
Theoretical input voltage range versus reference input voltage
may be calculated using the following equations.

VRANGE ( p p ) = VREF 2.5


VMIDSCALE = VREF
VTOP OF RANGE = VREF + VRANGE 2
VBOTTOM OF RANGE = VREF VRANGE 2

0.1F
1 AINA

AD9059
3 VREF

The external reference should have a 1 mA minimum sink/


source current capability to ensure complete overdrive of the
internal voltage reference.

0.1F
1k
28 AINB
0.1F

Figure 2. Capacity Coupled AD9059

REV. A

1k

Voltage Reference

5V

VINB
(1V p-p)

28 AINB

1k

The AD9059 provides independent single-ended high impedance


(150 k) analog inputs for the dual ADCs. Each input requires a
dc bias current of 6 A (typical) centered near 2.5 V (10%). The
dc bias may be provided by the user or may be derived from the
ADCs internal voltage reference. Figure 2 shows a low cost dc
bias implementation that allows the user to capacitively couple
ac signals directly into the ADC without additional active circuitry. For best dynamic performance, the VREF pin should
be decoupled to ground with a 0.1 F capacitor (to minimize
modulation of the reference voltage), and the bias resistor should
be approximately 1 k.

EXTERNAL VREF
(OPTIONAL)

0.1F

5V

USING THE AD9059


Analog Inputs

1k

AD8041

VIN A

The analog input signal is buffered at the input of each ADC


channel and applied to a high speed track-and-hold. The trackand-hold circuit holds the analog input value during the
conversion process (beginning with the rising edge of the
ENCODE command). The track-and-holds output signal passes
through the gray code and flash conversion stages to generate
coarse and fine digital representations of the held analog input
level. Decode logic combines the multistage data and aligns the
8-bit word for strobed outputs on the rising edge of the ENCODE
command. The MagAmp/Flash architecture of the AD9059
results in three pipeline delays for the output data.

VINA
(1V p-p)

+5V

+5V

AD9059
Digital Logic (5 V/3 V Systems)

Applications

The digital inputs and outputs of the AD9059 can easily be


configured to interface directly with 3 V or 5 V logic systems.
The encode and power-down (PWRDN) inputs are CMOS
stages with TTL thresholds of 1.5 V, making the inputs compatible with TTL, 5 V CMOS, and 3 V CMOS logic families. As
with all high speed data converters, the encode signal should be
clean and jitter free to prevent degradation of ADC dynamic
performance.

The wide analog bandwidth of the AD9059 makes it attractive for


a variety of high performance receiver and encoder applications.
Figure 4 shows the dual ADC in a typical low cost I and Q
demodulator implementation for cable, satellite, or wireless
LAN modem receivers. The excellent dynamic performance of
the ADC at higher analog input frequencies and encode rates
empowers users to employ direct IF sampling techniques (see
TPC 2). IF sampling eliminates or simplifies analog mixer and
filter stages to reduce total system cost and power.

The AD9059s digital outputs will also interface directly with 5 V


or 3 V CMOS logic systems. The voltage supply pins (VDD) for
these CMOS stages are isolated from the analog VD voltage
supply. By varying the voltage on these supply pins, the digital
output high levels will change for 5 V or 3 V systems. The VDD
pins are internally connected on the AD9059 die. Care should
be taken to isolate the VDD supply voltages from the 5 V analog
supply to minimize noise coupling into the ADCs.

AD9059
ADC

BPF

ADC

90

IF IN

The AD9059 provides high impedance digital output operation


when the ADC is driven into power-down mode (PWRDN,
logic high). A 200 ns (minimum) power-down time should be
provided before a high impedance characteristic is required. A
200 ns power-up period should be provided to ensure accurate
ADC output data after reactivation (valid output data is available three clock cycles after the 200 ns delay).

BPF

VCO

VCO

Figure 4. I and Q Digital Receiver

The high sampling rate and analog bandwidth of the AD9059


are ideal for computer RGB video digitizer applications. With a
full-power analog bandwidth of 2 the maximum sampling rate,
the ADC provides sufficient pixel-to-pixel transient settling time
to ensure accurate 60 MSPS video digitization. Figure 5 shows
a typical RGB video digitizer implementation for the AD9059.

Timing

The AD9059 is guaranteed to operate with conversion rates


from 5 MSPS to 60 MSPS. At 60 MSPS, the ADC is designed
to operate with an encode duty cycle of 50%, but performance
is insensitive to moderate variations. Pulsewidth variations of up
to 10% (allowing the encode signal to meet the minimum/
maximum high/low specifications) will cause no degradation in
ADC performance (see Figure 1).

AD9059
RED

ADC

GREEN

ADC

8
PIXEL CLOCK

Due to the linked ENCODE architecture of the ADCs, the


AD9059 cannot be operated in a 2-channel ping-pong mode.

H-SYNC

Power Dissipation

BLUE

The power dissipation of the AD9059 is specified to reflect a


typical application setup under the following conditions: encode
is 60 MSPS, analog input is 0.5 dBFS at 10.3 MHz, VD is 5 V,
VDD is 3 V, and digital outputs are loaded with 7 pF typical
(10 pF maximum). The actual dissipation will vary as these
conditions are modified in user applications. TPC 7 shows typical power consumption for the AD9059 versus ADC encode
frequency and VDD supply voltage.

PLL

ADC

ADC

AD9059

Figure 5. RGB Video Encoder

A power-down function allows users to reduce power dissipation


when ADC data is not required. A TTL/CMOS high signal
(PWRDN) shuts down portions of the dual ADC and brings total
power dissipation to less than 10 mW. The internal band gap
voltage reference remains active during power-down mode to
minimize ADC reactivation time. If the power-down function is
not desired, Pin 3 should be tied to ground. Both ADC channels
are controlled simultaneously by the PWRDN pin; they cannot
be shut down or turned on independently.

REV. A

AD9059
+VD

800

+VD

3k
VREF

2.5V

+VDD
3V TO 5V

+VD

500

ENCODE
PWRDN

D0D7

AIN

VREF

2.5k

VOLTAGE REFERENCE

DIGITAL INPUTS

DIGITAL OUTPUTS

ANALOG INPUTS

Figure 6. Equivalent Circuits

Analog input signals to the board should be 1 V p-p into 50


for full-scale ADC drive. For ac-coupled operation, connect E7
to E8 (analog input A to C12 feedthrough capacitor), E13 to
E15 (C12 to R15 termination resistor for Channel A), E4 to E6
(analog input B to C11 feedthrough capacitor), and E10 to E12
(C11 to R14 termination resistor for Channel B) using the
board jumper connectors.

Evaluation Board

The AD9059/PCB evaluation board provides an easy-to-use


analog/digital interface for the dual 8-bit, 60 MSPS ADC. The
board includes typical hardware configurations for a variety of high
speed digitization evaluations. On-board components include the
AD9059 (in the 28-lead SSOP package), optional analog input
buffer amplifiers, digital output latches, board timing drivers, and
configurable jumpers for ac coupling, dc coupling, and powerdown function testing. The board is configured at shipment for
dc coupling using the AD9059s internal reference.

The on-board reference voltage may be used to drive the ADC or


an external reference may be applied. The standard configuration
employs the internal voltage reference without any external
connection requirements. An external voltage reference may be
applied at board connector input REF to overdrive the limited
current output of the AD9059s internal voltage reference. The
external voltage reference should be 2.5 V typical.

For dc-coupled analog input applications, amplifiers U3 and U4


are configured to operate as unity gain inverters with adjustable
offset for the analog input signals. For full-scale ADC drive,
each analog input signal should be 1 V p-p into 50 referenced
to ground. Each amplifier offsets its analog signal by +VREF
(2.5 V typical) to center the voltage for proper ADC input drive.
For dc-coupled operation, connect E7 to E9 (analog input A to
R11), E14 to E13 (amplifier output to analog input A of
AD9059), E4 to E5 (analog input B to R10), and E11 to E10
(amplifier output to analog input B of AD9059) using the board
jumper connectors.

The power-down function of the AD9059 can be exercised


through a board jumper connection. Connect E2 to E1 (5 V to
PWRDN) for power-down mode operation. For normal operation,
connect E3 to E1 (ground to PWRDN).
The encode signal source should be TTL/CMOS compatible
and capable of driving a 50 termination. The digital outputs
of the AD9059 are buffered through latches on the evaluation
board (U5 and U6) and are available for the user at connector
Pins 3037 and Pins 2229. Latch timing is derived from the
ADC ENCODE clock and a digital clocking signal is provided
for the board user at connector Pins 2 and 21.

For ac-coupled analog input applications, amplifiers U3 and U4


are removed from the analog signal paths. The analog signals
are coupled through Capacitors C11 and C12, each terminated
to the VREF voltage through separate 1 k resistors (providing
bias current for the AD9059 analog inputs, AINA and AINB).

REV. A

AD9059
J9, VDD

ANALOG INA
BNC
J5

U4
AD8041Q

E8
E7
R13
50

E9

R11
1k

C12
0.1F

8
DIS
7
+VS
5V
6
5
NC

1
NC
2
3
4
VS

C16
10F

R5
10

E14
E13
E15

R15
1k

R7
1k
R8
10k

5V
C10
0.1F

C17
10F

R9
10k

C8
0.1F

J1, REF

E2

5V

R14
1k

C9

0.1F
U1
AD9059RS

E1
E3
PWRDN

D7A
D6A
D5A
D4A
D3A
D2A
D1A
D0A

1
2
3
4
5
6
7
8
9
10
11
12
13
14

AINA
VREF
PWRDN
VD
GND
VDD
D7A
D6A
D5A
D4A
D3A
D2A
D1A
D0A

P2
C37DRPF

28
AINB
27
GND
26
ENC
VD 25 5V
24
GND
23
VDD
22
D7B
D7B
21
D6B
D6B
20
D5B
D5B
19
D4B
D4B
18
D3B
D3B
17
D2B
D2B
16
D1B
D1B
15
D0B
D0B

U5
74ACQ574
D0B
D1B
D2B
D3B
D4B
D5B
D6B
D7B

9
8
7
6
5
4
3
2

E12
R8
1k

BNC
J4

E5

R10
1k

E4
E6
R12
50

1
NC
2
3
4 V
S

8
DIS
7 5V
+VS
6
5
NC

D7A
D6A
D5A
D4A
D3A
D2A
D1A

U7
74AC00

C6
0.1F

C7
0.1F

C4
0.1F

C5
0.1F

ENCODE

C14
0.1F
C13
0.1F

U7
74AC00

R15
50
4
5

C15
10F

U7
74AC00

DECOUPLING CAPS

12
13

J12, GND

9
8
7
6
5
4

8D
7D
6D
5D
4D
3D
3
2D
2
1D
D0A
CK

C11
0.1F

5V
C3
0.1F

DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7

U6
74ACQ574

R4
10

BNC
J10
J11, VD

12
13
14
15
16
17
18
19

E10
E11

U3
AD8041Q

ANALOG INB

8D
8Q
7Q
7D
6Q
6D
5D
5Q
4Q
4D
3Q
3D
2Q
2D
1Q
1D
CK OE
11 1

11

8Q
7Q
6Q
5Q
4Q
3Q
2Q
1Q
OE
1

12
13
14
15
16
17

DA7
DA6
DA5
DA4
DA3
DA2
18
DA1
19
DA0

DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37

11

Figure 7. AD9059 Dual Evaluation Board Schematic

10

REV. A

AD9059

Figure 8. Evaluation Board Layout (Top)

Figure 9. Evaluation Board Layout (Bottom)

REV. A

11

AD9059
OUTLINE DIMENSIONS
28-Lead Shrink Small Outline Package [SSOP]
(RS-28)
C0056304/03(A)

Dimensions shown in millimeters


10.50
10.20
9.90

28

15

5.60
5.30
5.00

8.20
7.80
7.40

14

1.85
1.75
1.65

2.00 MAX

0.10
COPLANARITY
0.25
0.09

0.05
MIN

0.38
0.22

0.65
BSC

SEATING
PLANE

8
4
0

0.95
0.75
0.55

COMPLIANT TO JEDEC STANDARDS MO-150AH

Revision History
Location

Page

4/03Data Sheet changed from REV. 0 to REV. A.

Renumbered Figures and TPCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal


Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

12

REV. A