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3.

7 TIMER/COUNTER 8253/8254:
The 8086 does not posses in-built timer or counter for various applications. The IC8253/8254
serves as Timer/counter device and it can be interfaced with 8086. It has three counter operations
such as counter1, counter2 and counter3 with different sizes. The address lines A0 and A1 are
used to select the required counter operation. The 8086 can program the timer/counter IC using
the control word register. It has 8 data pins(D0-D7) to communicate with 8086. The pin diagram
and architecture of timer/counter is shown in the figure.

RD: read signal


WR: write signal
CS: chip select signal
A0, A1: address lines
Clock: This is the clock input for the counter. The counter is 16 bits.
Out: This single output line is the signal that is the final programmed output of the device.
Gate: This input can act as a gate for the clock input line, or it can act as a start pulse,

Functional description:
The block diagram of 8253/8254 Timer is shown in the figure below.

Each of the three counters has 3 pins associated

CLK: input clock frequency


A square wave of 33% duty cycle 8253: 0 ~ 2 MHz, 8254: 0 ~ 8 MHz
OUT: can be square wave, or one shot
GATE: Enable (high) or disable (low) the counter
Data Pins: (D0 ~ D7) Allow the CPU to access various registers inside the 8253/54 for
both read and write operations. RD and WR are connected to IOR and IOW of control
bus.
Data Bus buffer:
The data bus buffer is bidirectional, 8-bit buffer and is used to interface the 8253 to the system
data bus. The operation of this buffer is controlled by the chip select line ( ) which tells the 8253
that the is trying to transfer information to or from it even though is part of the

READ/WRITE logic. Data is transmitted or received by the buffer upon execution of INPUT
instruction from CPU. The data bus buffer has three basic functions,
(i). Programming the modes of 8253.
(ii). Loading the count value in times
(iii).Reading the count value from timers.
The data bus buffer is connected to using D7-D0 pins which are also bidirectional. The data
transfer is through these pins. These pins will be in high-impedance (or this state) condition until
the 8253 is selected by a LOW or

CS

. And either the read operation requested by a LOW on

the input or a write operation requested by

WR

RD

the input going LOW.

Read/ Write Logic:


It accepts inputs for the system control bus and in turn generation the control signals for overall

CS
device operation. It is enabled or disabled by
so that no operation can occur to change the
function unless the device has been selected as the system logic.
The read (
the

RD

When

RD

) and write (

WR

) pins central the direction of data transfer on the 8-bit bus. When

input pin is low. Then CPU is inputting data from 8253 in the form of counter value.

WR

pins is low, then CPU is sending data to 8253 in the form of mode information or

RD WR
RD WR
loading counters. The
&
should not both be low simultaneously. When
&
pins
are HIGH, the data bus buffer is disabled.

A0 & A1:
These two input lines allow the 8086 to specify which one of the internal register in the 8253 is
going to be used for the data transfer. Fig shows how these two lines are used to select either the
control word register or one of the 16-bit counters. Eg, if there is a 1 on both A0 & A1, and a

WR

0 an
, then the is writing a control word to the control word register. These two pins are
usually connected to the address bus lines of the same name (A0 & A1).

Control word register:


It is selected when A0 and A1 re 11. It the accepts information from the data bus buffer and
stores it in a register. The information stored in then register controls the operation mode of each
counter, selection of binary or BCD counting and the loading of each counting and the loading of
each count register. This register can be written into, no read operation of this content is
available.
Counters:
Each of the times has three pins associated with it. These are CLK (CLK) the gate (GATE) and
the output (OUT).
CLK: This clock input pin provides 16-bit times with the signal to causes the times to decrement
maximum clock input is 2.6MHz. Note that the counters operate at the negative edge (H1 to L0)
of this clock input. If the signal on this pin is generated by a fixed fq oscillator then the user has
implemented a standard timer. If the input signal is a string of randomly occurring pulses, then it
is called implementation of a counter.
GATE: The gate input pin is used to initiate or enable counting. The exact effect of the gate
signal depends on which of the six modes of operation is chosen.
OUTPUT: The output pin provides an output from the timer. It actual use depends on the mode
of operation of the timer. The counter can be read in the fly without inhibiting gate pulse or
clock input.
8254 Modes:
MODE 0: INTERRUPT ON TERMINAL COUNT
Mode 0 is typically used for event counting. After the Control Word is written, OUT is initially
low, and will remain low until the Counter reaches zero. OUT then goes high and remains high
until a new count or a new Mode 0 Control Word is written into the Counter.

MODE 1: HARDWARE RETRIGGERABLE ONE-SHOT


OUT will be initially high. OUT will go low on the CLK pulse following a trigger to begin the
one-shot pulse, and will remain low until the Counter reaches zero. OUT will then go high and
remain high until the CLK pulse after the next trigger.

MODE 2: RATE GENERATOR


This Mode functions like a divide-by-N counter. It is typically used to generate a Real Time
Clock interrupt. OUT will initially be high. When the initial count has decremented to 1, OUT
goes low for one CLK pulse. OUT then goes high again, the Counter reloads the initial count and
the process is repeated.

MODE 3: SQUARE WAVE MODE


Mode 3 is typically used for Baud rate generation. Mode 3 is similar to Mode 2 except for the
duty cycle of OUT. OUT will initially be high. When half the initial count has expired, OUT
goes low for the remainder of the count.

MODE 4: SOFTWARE TRIGGERED STROBE

OUT will be initially high. When the initial count expires, OUT will go low for one CLK pulse
and then go high again. The counting sequence is triggered by writing the initial count. GATE
e 1 enables counting; GATE e 0 disables counting. GATE has no effect on OUT.

MODE 5: HARDWARE TRIGGERED STROBE (RETRIGGERABLE)


OUT will initially be high. Counting is triggered by a rising edge of GATE. When the initial
count has expired, OUT will go low for one CLK pulse and then go high again

3.7 TRAFFIC LIGHT CONTROL:

Traffic lights, which may also be known as stoplights, traffic lamps, traffic signals, signal lights,
robots or semaphore, are signaling devices positioned at road intersections, pedestrian crossings
and other locations to control competing flows of traffic.

INTERFACING TRAFFIC LIGHT WITH 8086:


The Traffic light controller section consists of 12 Nos. point leds arranged by 4Lanes in Traffic
light interface card. Each lane has Go(Green), Listen(Yellow) and Stop(Red) LED is being
placed.

Circuit Diagram to Interface:

8086 ALP:

3. 8 LED DISPLAY:

Light Emitting Diodes (LED) is the most commonly used components, usually for displaying
pins digital states. Typical uses of LEDs include alarm devices, timers and confirmation of user
input such as a mouse click or keystroke.
INTERFACING LED
Anode is connected through a resistor to GND & the Cathode is connected to the
Microprocessor pin. So when the Port Pin is HIGH the LED is OFF & when the Port Pin is
LOW the LED is turned ON.

PIN Assignment:

8086 ALP:

3.9 LCD DISPLAY:


Liquid Crystal displays are created by sandwiching a thin 10-12 m layer of a liquidcrystal fluid between two glass plates.
A transparent, electrically conductive film or backplane is put on the rear glass sheet.
Transparent sections of conductive film in the shape of the desired characters are coated
on the front glass plate
When a voltage is applied between a segment and the backplane, an electric field is
created in the region under the segment. This electric field changes the transmission of
light through the region under the segment film.
There are two commonly available types of LCD: dynamic scattering and field- effect.
The Dynamic scattering types of LCD: It scrambles the molecules where the field is

present. This produces an etched-glass-looking light character on a dark background.


Field-effect types use polarization to absorb light where the electric field is present. This

produces dark characters on a silver- gray background.


Most LCDs require a voltage of 2 or 3 V between the backplane and a segment to turn

on the segment.
We cannot just connect the backplane to ground and drive the segment with the outputs of
a TTL decoder. The reason for this is a steady dc voltage of more than about 50mV is

applied between a segment and the backplane.


To prevent a dc buildup on the segments, the segment drive signals for LCD must be
square waves with a frequency of 30 to 150 Hz.

Hardware connection with 8086/8051 kit:

Interfacing:

3.10 ALARM CONTROLLER:


Hardware Description of Alarm and Buzzer:

8086 ALP: