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with the analog world

Zainal Arief


Analog-to-digital converter (ADC) and digital-to-

analog converter (DAC) are used to interface a
computer to the analog world


Process of taking value represented in digital code,

and conver@ng it into a voltage or current which is
propor@onal to the digital value.

1. A ve-bit DAC has a current output. For a digital input of 10100, an
output current of 10 mA is produced. What will Iout be for a digital
input of 11101 ?
2. What is the largest value of output voltage from an 8-bit DAC that
produces 1.0 V for a digital input 00110010 ?
3. A 5-bit D/A converter produces Vout=0.2 V for a digital input 00001.
Find the value of Vout for an input of 11111.

Resolu@on (step size)

Step size
Full-scale output
Percentage resolu@on

step size
% resolution =
full scale (FS)

Resolu@on (step size)

1. What is the resolu@on (step size) of the DAC
in example no.3. Describe the staircase signal
out of this DAC.
2. Using same DAC, determine Vout for a digital
input of 10001.
3. A 10-bit DAC has a step size of 10mV.
Determine the full-scale output voltage and
the percentage resolu@on

Resolu@on (step size)

1. The 0 to 2 mA analog current from the DAC is amplied to produce
motor speeds from 0 to 1000 rpm. How many bits should be used if
the computer is to be able to produce a motor speed that is within
2 rpm of the desired speed ?
2. Using 9-bits, how close to326 rpm can the motor speed be
adjusted ?

D/A converter circuitry

1. Binary weight DAC
2. R-2R ladder DAC

Binary weight DAC

D/A converter
1. Determine the weight of each input bit of gure above.
2. Change Rf to 250 and determine the full-scale output

Binary weight DAC

Binary weight DAC

Binary weight DAC

1. Assume VREF = 10 V and R = 10 k. Determine
the resolu@on and full scale output for this
DAC. Assume that RL is much smaller than R.

R-2R Ladder DAC

R-2R Ladder DAC



D0 D1 D2 D3
+ +
16 8

R-2R Ladder DAC

DAC specica@on
Resolu@on specify using number of bits

Full-scale error (%FS)maximum devia@on of the

DACs output from its expected (ideal) value, e.g.
0.01% FS
Linearity error maximum devia@on in step size
from the ideal step size

Oset error DAC output voltage when the

binary input is all 0s
Sealing @me

DAC specica@on
Sealing @me the opera@ng speed of DAC,
the @me required for the DAC output to go from
zero to FS as the binary input to change from all
0s to all 1s
Typical sealing @me range from 50 ns to 10 s

Monotonicity output increases as the

binary output is incremented.

General diagram of ADC


1. Start command
2. Control unit con@nually modies
the binary value in register
3. Binary number in register is
converted to analog value Vax by
4. Comparator compares Vax with
analog input Va
5. Control unit produce EOC when
conversion complete

Digital Ramp ADC




Successive approxima@on register

Illustra@on 4-bit ADC


Flash ADC