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Basic Interview Questions on DFT.

What is the significance of scan-compression/EDT during ATPG?
To decrease the TDV and TAT
What is the reason for increase in pattern count for compressed mode?
Because the chain lenght is small,more number of chains exist.More number of control bits to
identify faults in EDT.

The actual compression achieved will be less than the specified compression factor.
Because of extra cycles(initialization cycles) in EDT.
Deciding factors of scan design?
Number of channels on tester, memory available on channel and number of scan pins.

Scan length, Scan chains, hierarchical scan concept?

How scan chains are handled from a 3rd party IP in the chip?
By using "add subchain command"
Use of LOCKUP latch?
a) When two clock domains exist , b) When one domain with different edges trigger the flops
c) When clock skew is more than half cycle of hold time.
Difference between LOS and LOC?
Look for the basic differences in the guide.Other difference is that in LOS,there is a chance of
testing unrequired functional paths because of last shift is done when SE=1.
Scan considerations required for At-speed test?
a) OCC that supports and generate 2 pulses for capture cycle.
b) Free running functional clocks.

What are advantages of LOS and disadvantages when compared to LOC?

How do you avoid limitations of LOS?

a) Consider SE as clock, b) Pipeline scan enable.

How do we manage chain balancing and what is the requirement?

Timing issues specific to scan chain clock domain mixing?

Hold issues.Use lockup latch to avoid them.Clock skew to be decreased.

How to avoid hold issues when scan chain is stitched from +ve edge to ve edge flop?

Use lockup latch.

How asynchronous and synchronous resets are handled for scan?
Bypassing those resets with top reset.
How tri-states are handled during scan?
That results in contention issues.Only one enable has to be activated at a time.
Configure the direction of a pad in scan mode.
How bidirectional ports are handled during scan?
Configure bidi pads to a particular direction.Make it as output.

Type of faults in memory to be detected?
SAF, AF, Couplinf faults,Bridging faults.
How does a stuck @ fault is tested in memory cell location?
In memories, for example 8x1 RAM, write all 0's in 8 locations,then read 0's from bottom.
If it does not read 0 in that location we can say it is stuck at 1 and there is a failure.

What is the consideration for at-speed faults to be detected for memory?

Considerations for membist logic to be shared with multiple memories?

Ram size, type of memory, clock frequency, placement of memory.

Sequence of 13N algorithm?

Basic blocks present in BIST logic?

Data generator, address generator, bypass logic, scrambler and descrambler.

Why BIST is preferred than a logic scan test?Why memories are not considered while in

Diagnostics criteria for memories?

What is the concept of repairable memories and how it is done?

What are the faults specific to Multi-port memories?Port-Isolation Algorithm?

How repairable information is fed out to repair the memory?

How sharing of multiple memories is decided?

Do we need to do a STA separately for MBIST mode? If so why?

Yes, because the controllers doesn't come into picture when STA is done in functional mode.

What is the criterion for clock controllability for Memories during BIST?
Memory clock should be top clock, controller clock and memory clock should be same.

How do you avoid setup time violations for at-speed MBIST?

How hold violations are fixed for MBIST mode?

How the placement considerations are determined with respect to memories?


Concept of controllability and observability?

What is the need for fault testing?

To check the testability of the design.
Why functional tests are not sufficient for fault tests?
Functional tests are done to test the logic whereas DFT is done for testing manufacturing

How a logical stuck-at fault is detected?

Basic sequence of fault detection?

Difference between combinational and sequential ATPG?

Combinational ATPG -> Single capture clock.
Sequential ATPG
-> Multiple capture clock.
Classes of fault types?
For at-speed :- 0-1 transition, 1-0 transition faults.

How to improve fault coverage or how do you analyze the fault coverage in the initial
By checking controllability and observability in the design and clearin the DRC's.
What is the timing fixes that we need to do first (shift or capture)?
Shift. If there is any failure in capture we can mask but if shift sims fail we can do nothing.

How a transition fault is detected in ATPG? Explain how launch and capture of a fault is
done and detected?

** Why at-speed coverage is less compared to stuck-at?

Inter-clock domain testing is not possible in at-speed. In-to-Reg and Reg-to-Out paths are not
** Why scan shift testing cannot be done at higher frequency?
Because of Pads may not support high frequency and power consumption is more.

Special considerations required for OCC type of transition fault detection?

Why do we need path delay though sufficient transition coverage is achieved?

What is the significance of SDD patterns over transition delay patterns?

What is the concept of on-path and off-path during detection of paths?

What is concept of reconvergence of paths during path-delay testing?

How bridging faults are detected?

Considerations for bridging faults?

Special controllability requirements for IDDQ faults?

How do we decide IDDQ strobe?

Numbers of IDDQ strobes generally require?

Why does an IDDQ pattern take lot of time for test, though pattern count is very small?

How CGC faults are tested?

What kind of simulations do we generally need to do?
Chain serial and serial capture.
Why do zero-delay/Unit delay simulations fail though timing simulations are passing?
Simulator issues.
Problems generally encountered during ATPG simulations?
Hold issues.

What is the need of simulations though STA is clean?

How does synchronizing paths are handled using