DIGITAL
K. F.
CATHEY
R. D.
MITCHELL
R.
W.
D. A.
TINNELL
YEAGER
INC.
12205
DELMAR PUBLISHERS
Division of Litton Educational Publishing, Inc.
Copyright
1972
Copyright
all
will
is
portions of this
be
in
Inc.
1977. Thereafter
1,
work covered by
this copyright
No
part of this
work covered by
may be reproduced
or used in
graphic, electronic, or
taping,
mechanical, including photocopying, recording,
systems
or information storage and retrieval
without
Research
written permission of Technical Education
Centers.
Number:
70170793
PRINTED
IN
Published simultaneously
in
Canada by
The
of
Ltd.
formed pursuant to
a grant
Education, Department of
Welfare.
herein, however,
do
the
not necessarily reflect the position or policy of
endorsement
U.S. Office of Education, and no official
inferred.
Foreword
The marriage of
electronics
and technology
New
with combination
devices of
optical
many
must
new demands
for
who work
Increasingly, technicians
kinds
many
be competent also
in
who
is
combination
technology.
in industrial
This manual
for students
is
one of
who want
The most
pations.
creating
skill
technical specialists.
is
manuals
is
as
combination textbook
in electronics,
mechanics, physics,
in this series is
topic
is
modern
Each
industrial applica
has been
make
School administrators
manuals to support a
programs
in
such
fields as:
or quality assurance.
will
common
be interested
firstyear
in
the potential
of these
in
(TERC),
in
the series,
is
It
has undergone a
number of
revisions
community
and
Maurice W. Roney
Hi
TERC
is
engaged
cal Technology.
in
The following
titles
in
Electromechani
INTRODUCTORY
ELECTROMECHAN ISMS/ MOTOR CONTROLS
ELECTROMECHAN ISMS/DEVICES
ELECTRONICS/AMPLIFIERS
ELECTRONICS/ELECTRICITY
MECHANISMS/DRIVES
MECHANISMS/LINKAGES
UNIFIED PHYSICS/FLUIDS
UNIFIED PHYSICS/OPTICS
ADVANCED
ELECTROMECHAN ISMS/AUTOMATIC CONTROLS
ELECTROMECHAN ISM S/SERVOMECH AN ISMS
ELECTROMECHAN ISMS/FABRICATION
ELECTROMECHAN ISMS/TRANSDUCERS
ELECTRONICS/COMMUNICATIONS
ELECTRONICS/DIGITAL
MECHANISMS/MACHINES
MECHANISMS/MATERIALS
For further information regarding the
its
EMT
in
implementation, contact:
Technical Education Research Centers, Inc.
44
Brattle Street
iv
Preface
Technology, by
its
very nature,
a laboratoryoriented activity.
is
is
vitally important.
in digital circuit
and other
The sequence
is
intended to
modern technology.
to:
of presentation chosen
may choose
by no means
is
Some
exercises or to supplement
some of them to
in
instructors
better
meet
inflexible.
expected that
It is
The
Electronics/Digital
individual instructors
The
may wish
in a
of the
many
of the
for
some
to omit
An INTRODUCTION which
A DISCUSSION
A MATERIALS
experiment.
list
which
A PROCEDURE
experiment.
that
all
identifies
all
in
the laboratory
(Items usually supplied by the student such as pencil and paper are
In
in
which
the
lists.)
presents
stepbystep
for
instructions
performing the
of the students can at least finish making the measurements before the
offers suggestions as to
PROBLEMS
covered
in
in
how
it.
are included for the purpose of reviewing and reinforcing the points
the exercise.
Students should be encouraged to study the text material, perform the experiment,
a technical report
These materials on
technical
skill
topic.
Following this
on the job.
digital electronics
students by the
and
on each
TERC EMT
comprise one of a
staff at
The
Oklahoma
series of
were
An
Instructor's
Data Guide
Kenneth
F.
Cathey
is
TERC
staff
and suggestions.
hoped that this volume as well as the other volumes in this series, the
of
instructor's data books, and the other supplementary materials will make the study
technology interesting and rewarding for both students and teachers.
It
is
sincerely
vi
Contents
experiment 00001
experiment 00010
BOOLEAN ALGEBRA
experiment 0001
OSCI LLOSCOPE
experiment 00100
WAVEFORM MEASUREMENTS
BASIC WAVEFORMS
19
26
experiment 01011
TRANSISTOR SWITCHING
DESIGN OF THE TRANSISTOR SWITCH
DIODE CLIPPERS
TRANSISTOR CLIPPERS AND CLAMPS
DIODE LOGIC GATES
RESISTORTRANSISTOR LOGIC (RTL) CI RCUITS ....
Dl RECT COUPLED TRANSISTOR LOGIC (DCTL) GATES
experiment 01 100
INHIBITORS
106
experiment 01 101
FUNDAMENTALS OF MULTIVIBRATORS
115
experiment 01 110
BISTABLE MULTIVIBRATORS
121
experiment 01
127
experiment 00101
experiment 00110
experiment 001
1 1
experiment 01000
experiment 01001
experiment 01010
1 1 1
experiment 10000
experiment 10001
experiment 10010
experiment 10011
experiment 10100
experiment 10101
experiment 10110
experiment 10111
experiment 11000
experiment 11001
experiment 11010
experiment 11011
experiment 11100
experiment 11101
experiment 11110
37
47
59
67
76
85
95
133
140
148
156
RING COUNTER
SHIFT REGISTERS
165
184
172
vii
192
.
199
203
210
215
221
230
233
editorial staff at
Delmar Publishers
are interested in
and questions.
will
Send comments
EditorinChief
Box 5087
Albany,
Responses
be
to:
experiment
III! III/
00001
I
N UM B E R
BINA R Y
YS TEM
The number 524 can be read five huntwo tens, and four units. It could also
chine
dreds,
be expressed:
speeds.
It
524=
5 X 10 2 +
(10 =
are
the
System.
binary numbers,
used inside
into binary
this
puter operations.
in
think
465
of
as
being
It
We
don't usually
made up of four
NOT
In
sys
is
tem),
number
is
said
4X
10
1)
(1.1)
524=5X 100+2X
10 +
4X
524 = 500+20 + 4
524 = 524
The base of the number system is the
number which, when raised to the zeroth
power gives the lowest position value, and
when raised to the first power, it is the
second
position,
N=
R n dn +
+ R1
d.,
We
etc.
can
the
write
+ R3d
as:
R2 d2
3+
+ Rd
Q
(1.2)
made up of com
10 1 +
So
2X
two conditions,
to
have position.
where:
N=
the
number
d n = the digit
in
that position
position of
5654 = 5 X 10 3 +
6X
10 2 +
5654 = 5654
5X
10 1
+4X10
EXPERIMENT 0000 1
The
1.
N = 27
see
that
we
0 system probably
base
N=
binary then
1
X8 + 0X4+ X2+
in
decimal
X 2 3 + OX 2 2 +
8+OX 4+
16 + 8 + 0+2+
X 16+
X2 +
1
X 2+
X 2
N = 27
can
isn't
Figure
system too
If
1.
X 24 +
N=
N=
1
= 0 as
very useful because 0 = 1 and 0
is
system
does 0 to any power. The base 1
similar to a base zero system. It has only one
digit since multiplying one by itself any
number of times produces only one. Thus,
this
or,
2)
N= 16+8 + 0+2+
if
base be 0?
0 or
N = 11011 in
N= 1 X 16+
digits,
(base
digits in this
are either
0 and
ELECTRONICS/DIGITAL
is
expressed
binary
in
digits
code.
base
two
digits.
N=
2d.
+ 1d 0
X 2 3 + 0 X 22 +
^
(1.3)
Base 2
2 =
10 1 = 10
Tens
21 = 2
Twos
102 = 100
Hundreds
22 = 4
Fours
103 = 1000
Thousands
23 = 8
Eights
Base Ten
Units
2 4 = 16Sixteens
Units
is
Base 10
10 =
X 2 +
1
You
+ 8d + 4d 2 +
3
which
N=
X 24 +
Base
Two Comparison
is
filled in
the binary
ELECTRONICS/DIGITAL
EXPERIMENT 00001
Decimal
Binary
(1
11 (1
Fig.
appear
it
other
2)
words,
X 2 +
OX
2)
2)
+0X
0X
21
X 22 +
0X
21 +
(1
2)
2)
+0X
2)
110(1 X 2 2 +
X 21
X 21 +
111
(1
X 22 +
1000
(1
X 23 + 0 X 22 + 0 X 2 + 0 X
2)
1001
(1
X 23 + 0 X 2 2 + 0 X 2 1 +
2)
2)
1
12
100(1 X 2 2 +
101
In
10(1 X 2
system.
is
filled for
left
this
to right
we
of (25)
l0 is(11001) 2
from bottom to
top,
from
the
last
Now we
the
quite easy
will.
They
one.
we
at
numbers?
the
if
first.
forth
For instance,
remainder to the
form of (25)
iq (which
base 10), first divide the
is
read as twentyfive,
N = d 1 XR 1 +d 2 X R 2 + d 3 X
number by two:
Remainder
ntMMd
12+11
25 divided by 2== 12+
Then divide 12 by 2 = 6 + 0
Then divide 6 by 2 = 3 + 0
Then divide 3 by 2 = 1 + 1
Then divide 1 by 2 = 0 + 1
R
+ d X R" n
n
t
For binary, we have
f
N =
Up
3
2" 1
+ d X 2"2 + d X
2
3
2"
ELECTRONICS/DIGITAL
EXPERIMENT 00001
3
=1 X2 + 0X2" 2 + 0X21
(0.10010) 2
6X
0.621 =
10" 1 +
2X
10 2 +
10" 3
2" 4
(0.1
0010) 2 = (0.5625) 10
0.621 = 0.621
Similarly, a fractional binary
may be
number
(0.1
001 ) 2
written as
(0.1001)2=1 X2+
is
0X2 2 +0X2"
carried out to
accuracy
1X2" 4
Now
=1
achieved.
we
that
are
familiar
with
X^ + OX^ + OX^
(0.1001)2=1
learn
how
dition,
(0.1001) 2 = (0.5625) 10
sion.
Then
Then
Then
Then
multiply
multiply
multiply
multiply
3062
0.26124
0.52248
0.04496
X 2
X 2 =
X 2 =
X 2 =
X 2 =
1.1
3062
0.261 24
the
0.52248
1.04496
0.8992
0+0=0
(1.4)
1+0=1
(1.5)
0+1
(1.6)
= 10
or
Read
Etc.
how
to binary.
this
0.
in
multiply 0.56531
makes computations
0+ 0+0.0625
First,
it
In
we must
number system.
Xl+Oxl+OX1+1
(0.1001) 2 = 0.5 +
the
from
Binary Number System and how to get
investo
one system to another, it is time
or
(0.1001) 2
is
more places
0+
carry
(1.7)
Down
Collecting the whole
top
down we
Since
would
the binary
be written in two
be
2,
must
be
So
method.
= 10.
An example might
help.
ELECTRONICS/DIGITAL
EXPERIMENT 00001
(2)iq.
001101
+ 100101
110010
example:
11011001
10101011
00101110
1 1
1
1
nothing to carry.
1
00101110
digit 0,
plus
to carry.
1
0=10,
to carry.
subtraction
0+0=1,
1,
plus
here.
nothing to carry.
0+1
1,
1,
plus nothing
to carry.
Putting
all
Binary subtraction
is
The only
as in decimal.
we
get
10010.
simple operation.
is
zero
let's
= 0
0=
101110011
1
or (53)
10
But
01
111
110101
110101
110101
0 0 = 0

the computer
110101
is
a quite
We
is
Actually,
It
1+borrow
(1.11)
There
of a
(Because the
action again,
and
after borrowing,
(7)
is
10 =(371) 10
an easy
few simple
way
to add.
It
consists
rules.
is in
1.
21 =1).
A.
the
10=(2) 1Q
B.
01 = <1>1Q
If
the
01 = (1)
10
sum
is
zero.
the resulting
sum
Count the
is
number
is
odd,
one.
ones to determine
how many ones are to be carried to
the next higher position.
Be sure
to count the carried ones in the
the binary 10 or
(2)
pairs.
1Q
2.
Subtracting a binary
pairs of
Binary division
By
simple as binary
as
is
multiplication.
ELECTRONICS/DIGITAL
EXPERIMENT 00001
that binary
110=
and (1100) 2 =
(6)
1
2)
you
will find
000) 2
10 (1001
,
q.
It is
(72) , 0
easy to see that
,
10
1100
1001000
110
00110
110
MATERIALS
Pencil
00000
and paper
PROCEDURE
1.
Develop the positive integers of the Binary Number System through 100 and record them
in figure
2.
13A.
Convert the following binary numbers to their decimal equivalents and record them
in
figure 13B.
Convert the following decimal numbers to binary and check by converting binary back
to decimal and record in figure 13C.
Add
Record
in figure
13D.
(a)
5.
1011011
10 1101Q
(b)
(c)
6.
110111011
100111011
10110
Q1010
(b)
in figure
0000000110110111
0000001101101110
0011011011100000
1101101110000000
13D.
100110001101
010101110010
Multiply the following binary number. Convert the multiplier and multiplicand and check
in figure
13E.
110110111
10111
X
7.
answer.
Record
Check the
in figure 13E.
1001 11010001
ANALYSIS GUIDE.
In this exercise
multiplication problem.
EXPERIMENT 00001
ELECTRONICS/DIGITAL
Decimal
Binary
Decimal
Binary
Decimal
Binary
Decimal
26
51
76
27
52
77
28
53
78
29
54
79
30
55
80
31
56
81
32
57
82
33
58
83
34
59
84
10
35
60
85
11
36
61
86
12
37
62
87
13
38
63
88
14
39
64
89
15
40
65
90
16
41
66
91
17
42
67
92
18
43
68
93
19
44
69
94
20
45
70
95
21
46
71
96
22
47
72
97
23
48
73
98
24
49
74
99
25
50
75
100
(A)
Binary
Decimal
Decimal
111011101
353
11101101
557
10110.1101
632
.11011
0.725
.10001
0.5625
(B)
Binary
(C)
Fig. 13
Binary
EXPERIMENT 00001
ELECTRONICS/DIGITAL
Decimal
Binary
4.(a)
4.(b)
4.(c)
5.(a)
5.(b)
(D)
Decimal
Binary
6.
7.
(E)
Fig. 13
PROBLEMS
1.
What
is
the answer
in
binary numerals?
2.
in
1572
964
decimal.
001101
+ 100101
3.
110101 X 111587 =
experiment
00010
of
experiment we will
few Boolean theorems.
this
by
Many were
He
Aristotle.
said
principles
first set
forth
1
(2.4)
0X0=0
1X0=0
0X1=0
(2.6)
1X1
(2.8)
Equation 2.4
may look
Remember that it is
a little suspicious to
you.
a law; also
that
statements.
value
In 1847,
false and never partly true or false.
George Boole, an English mathematician,
developed a shorthand notation for these
single
(2.3)
certain
1+0=1
of
possible
(2.5)
(2.7)
discrete states.
0 and
to
simple
the
switch,
1.
When
applied
is
For
usually labelled
Boolean algebra is
similar to ordinary algebra and arithmetic.
The distributive law applies and factoring and
expansion are permitted.
It
is
different
in
that
it is
state, 1.
mathematics
"closed,"
0 or
in
which variables
A statement
is
either
the
is
maximum
value
What
"all"
still
nothing
this
in
finding a
circuit.
number of
It
provides a means of
perform
AND
OR
and
tiplication.
The
the laws.
AND
multiplication
sign
OR
while
become
0 or 0 = 0
=
or 0 =
or
0 or
Oand 0 = 0
are
and 0 = 0
0+0
= 0
(2.1)
Oand
= 0
0+1
(2.2)
and
can be sub
the system.
nothing.
drawing the
in
is still
The words
stituted
is
remember
can
The
be sublaws then
ELECTRONICS/DIGITAL
BOOLEAN ALGEBRA
EXPERIMENT 00010
+ 1=1 read
1X1 = reads
is
(1,0)=
Functions
may
be evaluated
in
the usual
and
B,
we
all
of the possible
0,
B = 0
A=
0,
B =
A=
1,
B = 0
A=
1,
B=
this
is
true,
the
(A, B) =
(2.10)
The
real
that
Boolean
A + AB
For our
it
manifests
as switching logic.
are closed.
A o
In figure 22
cf
Two Switches in
Series
C/To
clfc
22
purposes,
Fig.
(2.9)
Fig. 2 1
is
follows the
it
systems.
function
itself
A+ AB = A
This theorem
Since
combinations:
A=
B= 0
+(1) (0) = 1
1,
can write
A=
way.
as follows:
"1
the
previously
Two Switches in
10
Parallel
an output
is
available
ELECTRONICS/DIGITAL
PARALLEL SWITCHES
SERIES SWITCHES
Output
Open
Open
No
Open
Open
No
Closed
Closed
Yes
Closed
Closed
Yes
Open
Closed
No
Closed
Open
Yes
Closed
Open
No
Open
Closed
Yes
Fig.
if
Output
either
figure 23
or B
lists all
is
23
The
table in
closed.
do these
switches or transistors.
Substituting 0 for open (or on)
two
in
the
The dual of an
tables which
algebraic equation
correspond
addition.
changing
certain
pairs
of
symbols.
is
that
inter
This
in our study of
Boolean algebra in that the dual of each law is
also a law, and each theorem based on the law
For
has a dual.
This saves much time.
=
example, the law 0 + 0
0 has as its dual
1X1 = 1, when 1 is substituted for 0 and X is
becomes important to us
switches
multiplication
can
and
be
to
used
parallel
represent
switches can be
This
is
a very
substituted
because
it
or transistor
multiplication
for +.
Boolean algebra
is
proven,
its
dual
is
in
auto
matically accepted.
logic
circuits.
BOOLEAN ADDITION
BOOLEAN MULTIPLICATION
(Series Switches)
(Parallel
Switches)
AB
A+
Fig.
24
11
0 and 1,
itself which
to
number of variables
method of proof presents
sible
a
is
is
consists
substitution
direct
of
the
theorems can
quick
the
The use
A X A
can be proven
but actually
000
100
010
needs no
theorem.
AX A
0+1
1X1
0X0 = 0
A+0 = A
(b)
AX
A
1
1+0=1
0+1
5 (Distributive Law)
(A + B) + C = A+(B + C);
+
AX(B + C) =
(2.15)
AXB AXC
(AXB)XC = AX(BXC)
(A + B) + C =
0 + 0= 0
001
0+1
110
1+0=1
101
011
1
1
+
+
+
1
1
=
=
=
(b)
(B
1+0=1
0+1
0+1
=
=
1
1
0+1
6 (DeMorgan's Law)
(A + B) X (A + C) =
(AX B) + (AXC) =
(a)
(2.12)
+ C) =
0+ 0= 0
A+
1+0=1
1+0=1
111
2 (Identity Law)
(a)
0+ 0= 0
THEOREM NUMBER
THEOREM NUMBER
B +
1+0=1
(b)
(2.14)
A+ B = ?
0+0=0
(a)
ABC
shown
A+ B= B+A
AX B=BXA
it is
(Commutative and
THEOREM NUMBER
0+0=0
proof since
below,
0+1
(A or A is A) (2.11)
(A and A are A)
A+A
as
similarly,
(b)
we can
(a)
Associative Laws)
many complex
of
reduction
THEOREM NUMBER
(a)
A+A=A
AX A=A
Its dual (b)
list all
of theorems
this
A+ =?
THEOREM NUMBER
To prove
This can
be demonstrated
indeed
allows
1.
all
(213)
method and
of
Law)
to
related
directly
be
This method of
to the variables.
assigned
ELECTRONICS/DIGITAL
BOOLEAN ALGEBRA
EXPERIMENT 00010
A+
AX
(B
C)
(B + C)
(2.16)
+ 0=
The proof
1+0=1
0 + 0=0
It
is
is
work equivalent
12
for
theorem
six
(a).
It will
ELECTRONICS/DIGITAL
(A + B)
A +
(A + C)
Fig.
25
(B X
C)
Theorem Six
"not zero."
indicates
closed for
possibility
is
equal to
we have
1.
in
binary
0,
or "not one"
is 1,
THEOREM NUMBER
(a)
(b)
A+(AXB)
AX(A+B)
(Absorption
A
A
=
=
The
illustration
electrical
(2.17)
of
may
Fig.
26
is
how
difficult
To
zero.
= Not A.
= 0.
of
this
is
When one
set
an elec
trical
is
contacts
made.
be proven by exhaustion
A
A
Law)
This theorem
"not zero"
shows
THEOREM NUMBER
8 (Double Negation)
simple networks
(A) =
Now we
reach
ordinary algebra.
function.
(2.18)
This concept
is
is
the "not"
usually
26
Theorem Seven
13
^0
Fig.
in
ELECTRONICS/DIGITAL
BOOLEAN ALGEBRA
EXPERIMENT 00010
Example:
now been
illustrates this
Reduce
THEOREM NUMBER 9
A + A=
(a)
(b)
A X A= 0
(2.19)
A+A=
0+1 =
1+0=1
AB + C
Given:
theorem.
AB X
this
(A + B) C + AC + B =
Theorem 8 & 10 (b)
AC
Theorem 6
(b)
AC +
AC
C+
Theorem
+ B =
B) = ?
(BC +
Theorem
(2.20)
(a)
AC + BC
(a)
B =
1 1
(b)
C + B = Answer,Theorem
'Writing the next to last step
like 7 (a).
look
one
this
+ B =
to a simpler
work
AC
expression
to
C)
Theorem 10
form
THEOREM NUMBER 10
A + B + C) = A_ _ C_
(a)
(AX BXC) = A+B + C
(b)
AC+B =
(or
A X C + C + B
(a)'
makes
it
mce
the
THEOREM NUMBER
A+
AX(A+B) = AXB
A+(AXB) = A+B
(a)
(b)
THEOREM NUMBER
(A X
(b)
B) +
AC
(2.21)
12
(A+B) X (A + C) X
= (A+ B) X (A + C)
(a)
B +
11
(AX
C)
(B
+ C)
(2.22)
+ (B X C)
<>
= (A X B) + (A X C)
Now
that
we have
These
time to examine their usage.
factor
terms,
expand
to
used
be
can
theorems
simpler
to
polynomials
and reduce complex
forms. When we remember that all Boolean
it
is
Fig.
27
expressions can really be switching combinations, the real worth of the system is realized.
Simplify algebraically:
gives us a tool
design
standpoint,
ability to
tems.
A + B + AC =
Rearranging terms
Theorem 7 (a)
A + AC + B =
A + B = Answer
may
14
by
EXPERIMENT 00010
ELECTRONICS/DIGITAL
mathematical manipulation
largely a matter
is
ulating the
Remember,
in
our
field
OR
AND
(+)
repre
(X) repre
28
Many times
Many more examples could be
in
given, but
relay,
AND
is
referred to as an
OR
the stage
at
This
is
MATERIALS
1
because
0 SPST switches
3 SPDT switches
1
VOM
or
FEM
OR CIRCUIT o
+ B
AND CIRCUIT O
A
Fig.
29
X B
OR A
OR AB
AND  OR Switch
15
Circuits
circuit.
EXPERIMENT 00010
ELECTRONICS/DIGITAL
BOOLEAN ALGEBRA
PROCEDURE
SPST switches may be wired to aid
Prove theorem 3(b) using the truth table method.
draw the equivalent circuit.
you in understanding the theorem. Record the Proof and
2.
3.
Fig. 2
10
First
in figure
results.
210.
Fig. 2
Experimental Circuit
Record your
1 1
4.
5.
circuit
Using a truth table, verify the output of the experimental
6.
7.
8.
9.
in figure 26.
in figure 21 1.
Record
it
in
results.
10.
Develop
11.
12.
compare the
analyzing the data from this experiment, you should
approach. Do they agree?
Boolean algebra method of circuit description with the hardwire
ANALYSIS GUIDE.
Which method
In
easier?
is
Why?
PROBLEMS
1.
Simplify
2.
Draw
(AB + A)
C = output
wx + wz + wy +
3.
Check the
(a)
A+
Do
not simplify.
x'y'
table,
identity of each of the following expressions with a truth
A' =
(b)
A' = 0
(c)
16
(A')
ELECTRONICS/DIGITAL
THEOREM
A X 0= 0
AX0=0
3(b)
THEOREM
A
6(b)
I
TRUTH TABLE FOR
A
B
Fig.
(A X B) + (A X C) =
AX
(B + C)
(A X
+ (A X C) =
AX
(B + C)
B)
BOOLEAN EXPRESSION
210
0
1
Fig.
210
SIMPLIFIED EXPRESSION
x
Fig. 2
12
Fig.
210
EXPERIMENT 00010
ELECTRONICS/DIGITAL
BOOLEAN ALGEBRA
Fig. 211
Fig. 211
THEOREM
BOOLEAN EXPRESSION
A

Fig.
212
OSCILLOSCOPE WAVEFORM
ME AS UREMENTS
00011
experiment
will set
DISCUSSION. An
oscilloscope
more than
a special
of a meter
movement with
a pointer,
we
confine
will
has a
it
all
ray tube
cathode
really little
is
for analyzing a
wave shape.
much
to deflect in
deflects
cases
its
the same
The
pointer.
way
What are the parameters which are important when considering waveforms? AC am
voltmeter
deflection in both
DC
plitude and
is
level
Another
scope
able
is
applied voltage.
rapid
is
oscillo
changes
By thinking of the
in
trace as a twodimensional
and
In
vertical voltages
regard
the
beam
follow very
to
special
adopts a moreorless
following
is
require
will
instruments.
of the trace.)
2.
The
special
off.
plugin unit.
laboratorytype instrument
often
is
DC
3.
wave
inputs,
4. Set the
Among
voltage,
name
AC
quency, period,
rise
5.
DC
its
settings.
internal
generator to
few items.
calibrated position.
fre
tion
shape.
controls
to
and
vertical posi
their
midrange
positions.
7.
8.
it is
plug to insure
in.
19
line
properly plugged
approximately one
Allow
9.
ELECTRONICS/DIGITAL
WAVEFORM MEASUREMENTS
EXPERIMENT 00011
minute
17.
Make any
AC
tism
be
until
screen.
damaging the
CRT
19.
screen.
intensity control,
it
is
intensity
should
turned
every
down
brightness.
sation
sweep oscilloscopes,
mode
automatic position.
is
may be
required.
screen.
control to the
the
produce a variation
the
position
sweep
magnifier
to
sometimes convenient
it
clean
in
X1
The amplitude of
viewing.
ance.
24.
triggered
14. For
horizontal deflec
welldefined spot.
12.
two cm of
tion.
1 1
amp. attenuator to
probably be
etc.
and
(including calibra
and calibration
intensity setting
should
probe should
The lowest
When
line.
line
starts
on the zero
set
It is
this
axis (centerline) of
the screen.
uation.
a zero reference.
20
to
EXPERIMENT 0001 1
ELECTRONICS/DIGITAL
Fig. 31
WA VEFORM MEASUREMENTS
One Volt
Calibration
(A)
(B)
Fig.
32
Undercompensated Probe
21
list
take
in fact,
time to
little
actually perform.
ELECTRONICS/DIGITAL
WA VEFORM MEASUREMENTS
EXPERIMENT 0001 1
it
to be
ment with
a calibrated
desirable.
First
we
is
for measurement.
signal
input
an
accept
to
ready
The
CRT
instruments
atory
the
trace.
vertical
quency.)
steps in
1.
amplitude measurement
voltage
(in
2.
In labor
most
5.
is
is
be measured to
number
of divisions be
Due
to
it is
recommended
that
be used. Normally, the fastest reasonable sweep rate will be best for easy
calculations.
6.
may be
waveform
7.
controlled by a front
calibrated in frequency
time base
signal to
knob
Apply the
of the sweep,
is
without overdriving
panel
signal
All
units.
operation
that of
is
in
Set the vertical attenuator to a deflection factor which will display the
a convenient
tively.
This
fre
4. Set the
and
to measure
cases,
CRT
It is
expected
3.
graduations
work
is
By counting the
measurement).
how
consider
will
voltage
amplifier
most
is
tant in digital
oscilloscope
sweep control
duration.
instru
In pulse or digital
quickly without
directions.
work, an
duration.
In
as
vertical position
Make
is
in
any oscilloscope,
if
the reading.
is
This
is
8.
possible
3.1.
22
WA VEFORM MEASUREMENTS
EXPERIMENT 0001 1
ELECTRONICS/DIGITAL
cm
*
Fig.
Time Duration
33
setting
(3.1)
magnification
cm
Horizontal distance = 5
For example:
This
(figure 33)
sider
is
= 0.1 ms/cm
instantaneous
Sweep normal
a finite
(magnification
last
rise times.
In practice,
amount of time
is
and have
however,
1)
rise
Substituting in 3.1,
maximum.
TD
In theory, square
= 
give a
= 0.5 milliseconds
To
its
more constant
is
defined
Rise time
is
quency.
Frequency =
Time Duration
90%
(3.2)
=
0.5
ms
for
frequency.
measuring time
duration
and
10%
should be considered
MICROSECOND
= 2000 Hz
in
work.
Fig.
23
34
Rise Time
With
sweep,
rise
ELECTRONICS/DIGITAL
WA VEFORM MEASUREMENTS
EXPERIMENT 0001 1
scope
a calibrated
is
time of
It
rise
much
As
rise
time of an
amplifier
points.
is
relative to rise
measurements that are worth remembering. The instrument used to measure rise
time
1/3
MATERIALS
1
Function generator
DC power
VOM
supply (040V)
or
FEM
PROCEDURE
1
in
the discussion.
2.
discussion.
Calibrate the probe using the procedure outlined in the
3.
Set the
4.
Measure the
5.
6.
Apply
7.
8.
9.
Apply
DC power
DC
30 Hz
sine
in
signal
vertical amplifier.
IV steps up to five
volts.
input.
cycle.
10.
11.
Repeat steps 9 and 10 for 60, 100, 200, 500, 1000 Hz.
12.
13.
Apply
4.
15.
Determine the
rise
time of the
signal.
kHz.
24
EXPERIMENT 0001 1
ELECTRONICS/DIGITAL
ANALYSIS GUIDE.
In
WA VEFORM MEASUREMENTS
analyzing these data you should compare the accuracy obtained using the
frequency.
DC
10
Volts
11
12
13
14
60
100
200
500
15
Audio Generator Hz
30
1000
AC
Volts
Multimeter Reading
Oscilloscope Reading
100 Hz
Frequency
Rise
500 Hz
kHz
Time
Fig.
35
PROBLEMS
1.
Why
is it
rise
If
this
is
rise
time measured
correspond to?
2.
What
3.
is
the period of a
certain
kHz waveform?
waveform has
What
is
a horizontal deflection of
is
25
is
cm
BASIC WAVEF0R
QQIOO
ent
INTRODUCTION. Waveforms
,ogic devices.
characteristics considered.
DISCUSSION. Logic
dous importance to
us.
in space
puters of this age allow us to travel
as
as
like
is
principles,
basic
all
logic
all
electronic.
spans the
enters the
realm of physical science and even
in human
mind
area of philosophy and the
Logic
encounter.
mediums.
variety of
to
Logic,
mind the
vehicle for our study, keeping in
to a
applicable
fact that the principles are
a tool
is
used by the
the study
code or
tell
what to do by changing
which
the magnitude, shape, frequency, etc.,
the
circuits
logic
includes the
changing of direction or
level
of a current or voltage.
first
human mind.
They
of waveforms.
is
Fortunately,
highly
and
sophisticated
for the
very useful tools have been developed
some
to
areas
specific
of
study
narrow the
common
of the
of these
physical sciences.
true that
(in fact, at
of light which,
seen
rapid
development
in
sentation of a voltage
of
the
changes
parameters of the
field
is
will
etc.
been
methods,
in
this
area,
the
language,
at
given
rate.
in
it
one
a given time period (usually
itself
defined as a cycle.
second)
water, copper,
repeat
this
cycles
passage of information.
oil,
repre
most cases of
to
air,
When
of application
will
calibrated as to
produce
its
In
in
oscil
are also
the mechanical strip chart recorders
the same.
used, but the basic principle is
the non
Logic
when properly
the
in
present time, the application of logic) is
few years
the electronic field, but the past
have
is
loscope.
The most
waveforms.
electrical
is
the
26
The
The
relationship
EXPERIMENT 00100
ELECTRONICS/DIGITAL
form
wave
is
BASIC WA VEFORMS
we
For the
will
periodic waveforms.
'=4
(4.1)
where
= frequency
T=
the time
in
in
Hertz
wave pattern
familiar
which
result
complete cycle.
sine function. Sinusoidal
here
in
we examine wave
particularly useful when an
various forms as
analysis.
It
is
is
as a
generally speaking, of
We
the
laboratory type
pattern
positioned
is
and
traced repeatedly,
is
two complete
shown, there
while
the
returned to
electron
its
beam
can be
is
is
danger
the
lost
scope
is
starting point.
little
are,
interest in digital
with
largely
nonsinusoidal waves.
of voltage or current
whose changes
are not
sine functions.
The
waves.
first
is
math
number of pure
sine
phase.
sinusoidal
component
sine
cycles.
due to time
in
it
time base
a horizontal
it
Normally
measured.
Since
oscilloscope.
They
be dealing
will
DC component and
on
point only.
starting
circuits.
"sine waves"
called
sine
its
These component
waves.
The
frequency
is
sine
the harmonic.
For instance,
if
fundamental
at a cyclic rate.
Fourier Analysis.
frequency
harmonic
do not occur
They must be displayed on
is
monic
Variations of this
Sometimes we
first har
is
of
is
all
of the advantages
of a mathematical representation.
Equations
are
form.
27
a square
wave
is
J
+
+
[sin cot
sin
cot
+^
sin
5 cot +
7T
(2i^T)
1)wt
sin
cot
3
sin
cot cos
cot cos
sin
cot
cot
(4.4)
where d =
(ff)
(duty cycle)
All
is
always odd
go
cot cos
N = term number
1) = harmonic number which
(2N 
'
time
(4 2)
where
+
sin(2N
sin
e =
for a rectangular
The
ELECTRONICS/DIGITAL
BASIC WA VE FORMS
EXPERIMENT 00100
fundamental
maximum
wave
is
at
its
value.
have
All of these equations theoretically
Several
be
can
things
determined by
a wave.
observing the general equation for
square
From equation 4.2 we can tell that this
(the 1, 3,
wave contains only odd harmonics
component
DC
no
Also there is
5, etc.).
is
symmetrical about
value for
the horizontal axis (the average
the amplitude,
e,
zero).
is
infinitely
more than 10 to 20
sine
describe a waveform.
application,
in
ligible
require
waveforms may
Pulse
that.
a
Observe the following equation for
This rule
is
only.
sawtooth wave:
covered
=
[sin cot 
sin
From equation
sin
cot
+ ^
sin
3 cot +
is
in
AC
circuit
courses,
is
is
normally
the
most
square waves
Let's continue our discussion of
using a second
(4.3)
cot
4.3
we can determine
that
of as
segments themselves can be thought
shapes
These
being one of four basic shapes.
all
are
harmonics
the harmonics are present (odd
). The
have + signs and even harmonics have
wave
no
symmetrical
the
sine,
waveforms.
and exponential
truly square wave is made up
step,
ramp,
sudden
axis.
28
change from
step voltage
is
to another.
level
we
Theoretically,
to
like
Any
some
finite
change
however,
does,
require
length of time.
BASIC WA VEFORMS
EXPERIMENT 00100
ELECTRONICS/DIGITAL
is
usually
very short
preceding constant
be
can
from
of
amplitude
the
shows
or
positive
constant
the
difference of the
41
the
either
in
direction
step
negative
defined
is
The
level.
two constant
the
as
Figure
levels.
waveform.
a square
Square Waveform
Fig. 4 1
in
figure 41.
voltage
constant
(at
the time
is
for
level)
time
duration
which
period.
tangular
pulse
equal
is
pulse
the
onehalf
to
+
o
Duty
Cycle io/\
X 100
(%) i
pulse
waveform
that
it
the
made up
The only
segments.
relationship
of
the
made up
equal
time
to
maximum
in
is
the "off"
as a
50%
in
special
to
duty cycle.
con
the
50%
When
ratio,
the waveform
rectangular wave.
its
defined as a
is
rectangular
step function
amplitude) that
wave
is
any
less
(4.5)
is
pulse duration.
is
duration
(4.4)
suddenly moves to
wave
Pu se period
function
If
sidered to be
is
of step
practical difference
the period.
have an
rectangular
similar to a square
is
also
is
waveform.
is
Period
a special
form.
The duty
^PERIOD
PULSE
OFF
DURATION
TIME
This relationship
is
PULSE
DURATION
Fig.
42
Pulse
29
demonstrated
in figure 42.
From
ELECTRONICS/DIGITAL
BASIC WA VEFORMS
EXPERIMENT 00100
figure 42
it
is
important to learn
zero
equal to the
The
is
This
can be expressed as
maximum
edge
is
amplitude.
level.
T = T d + T0
p
(4.6)
43
Figure
represents
where
= pulse period
Td =
TQ
more
pulse
reveals
edges
are
some
require
and
Pulse
will
examine them
in
some
detail.
We
we
wave shape
is
much
you
The
fall
time
is
to
figure 43,
rise
tangular
length
that
shorter than
curve
but
fall.
to
changes,
of time to
have
amount
trailing
instantaneous
small
and
leading
that the
not
theoretically
Examination of this
practical pulse.
pulse duration
Referring to
contains
the
fall
some
is
not actually
variations.
EDGE
LEADING
EDGE
43
Pulse
30
rise
Waveform
but
time and
TRAILING
Fig.
The
flat,
BASIC WA VEFORMS
EXPERIMENT 00100
ELECTRONICS/DIGITAL
AVERAGE
AMPLITUDE
FALL TIME
RISE TIME
Fig.
Two
44
Practical Pulse
The
is
rate.
frequency)
is
in
The
lies
in
question are
(pulse repetition
*
o
Cycle =
% Duty
o/ r>
The
relationship of the
is
given
PRF
in
(or
Pulse Duration
 rr
=.
Pulse Period
In cases
PRR)
*
Duty
y Cyc
y
/>
in
Pu
is
se off
In
in
Q
4.9
making measurements.
approaching the
discussion
of
tri
pulses/sec
basic
in
time
especially
pulse period
50 times
This equation
(4.6)
Tp =
at least
can be written
PRF =
is
equation 4.6.
o/
where
i
(4.8)
v
X inn
100
by
the
time.
(4.7)
seconds
31
EXPERIMENT 00100
straight
line
any
(or
that
is
ELECTRONICS/DIGITAL
BASIC WA VE FORMS
It
When
it
sequence
result
is
is
shown
is
a triangular wave.
triangular
wave
usually
(the
fall
for the
desirable
negative
sawtooth waveform.
in figure 45.
are
cases
In
finite fall
sawtooth
Practical
is
over 10
to com
plete
ramp
Thus
fall
our
This basic
rise
time that
time.
of
discussion
waveform
is
basic
waveforms.
called an exponential
waveform.
its
An example
of an exponential function
is
the
voltage equation
RISE TIME
Fig.
The
45
rise
Triangular
Wave
fall
e=
Ee
t/T
time of a
The graph of
triangular
this equation
decreasing curve of
waves can
is
a constantly
negative slope.
from a
Expo
resistance
nential
equal to zero.
Fig.
46
Sawtooth Wave
32
result
ELECTRONICS/DIGITAL
Fig.
47
wave made up of
and
is
wave
is
form
in
an amplifier
circuit
Such
a case
is
Some
circuit.
coupling
shown
49.
They
are
shown
trapezoidal
Staricase
many
and
in
figure
staircase
(B)
49
in
waveforms.
in figure 48.
Fig.
Wave
this
signal.
part these
frequency harmonics
Differentiated Square
This type
The reverse of
48
Many
an example
Fig.
(A)
Trapezoidal Wave
(B)
Staircase
33
Wave
ELECTRONICS/DIGITAL
BASIC WA VEFORMS
EXPERIMENT 00100
MATERIALS
Oscilloscope
1
1
mF capacitor
1H inductor
0.1
PROCEDURE
Set up the oscilloscope for waveform viewing.
1.
a properly calibrated
probe.
2.
with a
Adjust the function generator to produce a waveform
3.
4.
5.
6.
your
rise
50% duty
cycle.
results.)
7.
8.
Identify the
fall
trailing edge.
time of the
it.
signal generator to
ground as shown
410.
'"
J_
SIGNAL
GENERATOR
O
Fig.
410
10.
1 1
rise
2.
fall
time of the
3.
4.
Replace the
5.
16.
1
7.
dentif y the
Identify the
fif capacitor
its
with a
its
trailing edge.
appearance.
H inductor.
shape.
inductor.
34
ELECTRONICS/DIGITAL
18.
Compare
by the function
generator.
19.
Waveform
Period
Freq
Period
Freq
Set
Set
Read
Read
Td
50% DC
0.1 ixF
CAP
Parallel
Inductor
Parallel
10 KC Pulse
Td = 10 /usee
Sketch of
First
Waveform
Sketch of
Second Waveform
Fig.
411
35
% DC
Tr
TF
Identity
of
Wave
ELECTRONICS/DIGITAL
Sketch of
Third Waveform
Sketch of
Fourth Waveform
Fig.
411
ANALYSIS GUIDE.
PROBLEMS
1.
A certain
2.
What kind
3.
waveform has
of
What
is its
frequency?
ms and
What
is its
duty cycle?
4.
the
% duty cycle
in this case?
36
What
is
experiment
INTRODUCTION. With
circuits
TRANSISTOR SWITCHING
00101
In this
experiment we
will investigate
highspeed logic
the characteristics of a
DISCUSSION.
of bipolar transistors.
They
two types
are the
PNP and
type transistors.
NPN
types.
is
The
NPN
reversed
That
PNP
E current
current directions.
In the
NPN
type, Iq and
current flows
In a transistor the
by
both
'e'c
(5.1]
in.
tion of flow
,
and
Iq.
Equation 5.1
Transistor
Symbol
t'.
52
Transistor Current
37
There are
JFig.
the
valid for
<6
PNP and NPN
is
must be appropriate.
lg
Fig. 5 1
is,
PNP
or
ELECTRONICS/DIGITAL
TRANSISTOR SWITCHING
EXPERIMENT 00101
OOUT
CEO
IN
Fig.
53
PNP Common
Emitter Configuration
from collector to
is
to emitter, called
is
is
base.
the device
junction.
PN
'CEO
amount

characteristics of this
larger than Iq B q by an
usually
IcEO
collector
may
point from
54
PN Junction
Diode Characteristics
38
is
not
Base bias
prevent the
changing significantly
E
Fig.
condition
be destroyed.
changes.
in figure 54.
this
frequently added to
junction, as indicated
If
is
operating
when
Iq
Bq
EXPERIMENT 00101
ELECTRONICS/DIGITAL
TRANSISTOR SWITCHING
IN
'cc
Fig.
55
Common
Base Configuration
The value
the
55.
of a^
is
The
type of transistor.
first
of these
The
shown in
is
transistor
commonemitter
figure 56
is
configuration
second frequently
encountered arrangement.
polarities.
The
can be determined
plification factor
by the expression
a = 7TT
(j3
is
determined by divid
(5.2)
CO
'c
(5.4)
is
given by
(5.3)
(5.5)
OOUT
IN
o
V B8
'cc
1
Fig.
56
39
ELECTRONICS/DIGITAL
TRANSISTOR SWITCHING
EXPERIMENT 00101
O OUT
O
IN
'cc
BB
57
Fig.
handy relationship
(3f e
This relationship
Common
The
Co/lector Configuration
Characteristic curves can be determined
between a fe and
exists
for
is
The curves
figurations.
for the
common
The CB input
(5.6)
versus
characteristic
with
having a
gain, 0,
is
usually higher,
when
power gain to be
is
l^
known.
third configuration
is
the
common
The current
arrangement.
from
ampli
both
in
in finding
is
value
its
is
determined by
and
known.
when
(5.7)
the
V^g
when V^g
Ijr
cases,
shown
V EB
finding
Vq B
The
The
figure 58.
in
projected
perpendicularly
Al.
Al
In
method used
known
collector
known, or
is
The
is
a plot of
The value of
fixed.
The current
is
give
value
for
value
is
is
V EB
(Points
V EB when
given.)
the
common
1,
collector
configuration
is
allows the
common emitter
common collector
to have a
responding
common
factor of a
since
afe
<
j3
fe
the
circuit.
configuration
emitter circuit.
common
This
<
i
And
collector con
At the same
three configurations.
has the
configuration
because of
its
atively lower
low
power
lowest
voltage
resistance gain
gain.
Its
time, this
and
gain
rel
voltage gain
V EB VOLTS
is
Fig.
40
58
CB
EXPERIMENT 00101
ELECTRONICS/DIGITAL
TRANSISTOR SWITCHING
<
<
on
V EB VOLTS
V CB VOLTS
Fig.
base
is
59
V^g
are
VQg
is
given as
volts
V CB
and lg
most
useful.
given as A'
a line perpendicular to
locates point Q.
is
CE
appear as a family),
Input Characteristics of
lg.
10
Characteristics
plotted with
of
CB Output
Fig. 5
= A'
E
mA
line
Projecting perpendicularly
U3
K
_l
O
>
LU
m
>
V CE VOLTS
Fig. 5 1 1
41
CE
ELECTRONICS/DIGITAL
TRANSISTOR SWITCHING
EXPERIMENT 00101
<
E
=
B
0mA
V CE VOLTS
Fig. 5
shown
figure 512,
in
CE
Output Characteristics of
12
suitable
is
chosen,
it
can be used to
V
_cc_
i
Cmax
the
in
The DC load
circuits.
the normal
of
design
manner.
constructed
line is
If
switching
logic
in
certain parameters
V cc
becomes the
resistance
is
intercept.
When
the load
intercept
predetermined, the
Ycc
'C
The
max
intercept
satisfies this
R,
is
the value of
equation.
R L can be
c which
selected by
of
using the assigned (or chosen) value
load
of
family
a
for
as the end point
Figure 513 demonstrates this
V cc
lines.
method. When
Fig. 5
42
13
EXPERIMENT 00101
ELECTRONICS/DIGITAL
TRANSISTOR SWITCHING
"OFF" REGION
514
Fig.
Load
lines for
ON and OFF
contains
class
spends most of
its
time
in
the
ON
regions.
This
transistor
and
while
OFF
this
in figure
This region
is
flowing,
past cutoff.
transistor
The
the
develops
if
Because
in this
it
region,
our load
is
DC power supplies
VOMsor FEMs
PNP
Transistor socket
transistor,
kft,
33
2W
kft,
no problem usually
off).
active region
(040V)
resistor
1/4W
resistor
PROCEDURE
1.
Connect the
circuit
shown
in
fall.
figure 515.
43
only operating
line crosses
MATERIALS
2
curves
where a
very briefly
current
where
area
to the other.
is
base
the
operate.
The
514.
(no
The
amplifier operation.
Regions of a Transistor
polarities.
the
maximum
ELECTRONICS/DIGITAL
TRANSISTOR SWITCHING
EXPERIMENT 00101
DC POWER
SUPPLY
Fig. 5
2.
3.
First
Experimental Circuit
zero.
20
4.
B to
The
15
volts for
V CE
5.
On
6.
Disassemble the
7.
Assemble the
a single sheet of
circuit.
circuit
shown
in
figure 516.
VARIABLE DC
POWER SUPPLY
Fig.
516
8.
Apply 1 .0
9.
V CE
V BE
CE ).
values for
10.
11.
On
V CE
of the device.
a sheet of graph paper, plot the input characteristics
44
160Mamps,
EXPERIMENT 00101
ELECTRONICS/DIGITAL
40
60
80
100
120
140
'c
'c
'c
'c
'c
B /xA
Vqe
volts
TRANSISTOR SWITCHING
o
2
4
6
8
10
12
14
16
18
20
VCE
l
B Ma
1.0V
5.0V
10.0V
20.0V
V BE
V BE
vBe
V BE
0
10
20
30
40
60
80
120
160
Fig.
517
45
ANALYSIS GUIDE.
drawn regarding
The graphs should show the saturation region and
that can be
discussion?
If
yes,
ELECTRONICS/DIGITAL
TRANSISTOR SWITCHING
EXPERIMENT 00101
how?
If
no,
cutoff.
in
why?
PROBLEMS
1.
Select a suitable
V cc
and draw
DC
3.
Given
V cc = 12V
RL
in
problem
1.
46
in
the
experiment
INTRODUCTION.
00110
application.
is
DISCUSSION.
In
operating point
is
Care
point for
maximum
is
the
regardless of
less)
operation.
In this
experiment we
shall
the
amplifier
tion
class
(more or
to be used as a switch,
This
is
Iqq
biased.
taken to choose
linearity.
It
is
must be canceled by
not
which
is
a reverse bias lg
OFF'
plications.
When
In a
normal switching
circuit,
the operat
operating
must approach
transistor
fall at one
The upper extreme
nearly
operating point to
of Iq
is
line.
lower limit of Iq
as
region,
The
logic circuits.
operating
saturation
first
is
in
these regions
When
defined
ON
given
it
in
is
is
is
ing
point that
To
said to
resistance
actually
the
is
to
input
signal;
ON
is
is
discussion
must be
is
resistance
application and
is
is
The
ON
ratio of the
very important
when
eval
It
ON
OFF
two
OFF
by
normally conducting
to
switch
OFF
have
minimum
beyond
mechanical contacter.
may be
saturation
high resistance
is in
edge of the
so
conditions.
is
just at the
the
short circuit as
the
is
conducting as hard as
the
What
or "normally on."
happens physically
when
the device
condition, the
discussions of
fall
ON
region.
increased
We
possible.
saturation
is
in its
when no
is
input signal
(6.1)
applied.
much
To achieve
like
this,
should
(6.2)
47
ELECTRONICS/DIGITAL
TRANSISTOR SWITCH
EXPERIMENT 00110
INPUT
Fig. 6 1
Circuit
Fixed Bias Transistor
to many things
These changes are due
temperature. Fixed
cluding shifts in ambient
demonstrate and easy to
bias is easy to
is a good
For these reasons, it
calculate.
discussion. The value of
starting point for our
in
Ohm's Law
value
the
of the point
coordinates
determined by the
the saturation
where the load line crosses
corresponds
The OFF resistance
boundary.
0
the point where B =
to the coordinates of
This is the
intersect.
and the load line
boundary of the cutoff region.
ON
The
resistance
is
is
(6.3)
the transistor as a
In order to operate
switch,
we must
Figure 61
learn to bias
shows
transistor switch.
it
appropriately.
fixed bias
a circuit for a
The
least effective.
simplest and often the
is
the
It .s
Its mam
seldom used.
compensate for changes in
that it does not
which will cause a
transistor parameters
fault
actually very
is
the
corresponding shift
in
In this
caseV BE and B
l
point.
zero signal base operating
operating
the
The problem of holding
overcome by
point fixed is somewhat
ing
some
apply
in figure 62.
selfbias, as illustrated
'cc
Fig. 6 2
Cirucit
Self Biased Transistor
48
ELECTRONICS/DIGITAL
EXPERIMENT 001 10
Rg
&3
Fig.
Qpoint
resistor
Rg
lector
operating
signal
Of Stabilized Bias
bias
the
some
stability.
equal to the
point.
sum
of
This
stabilized bias.
name
an unfortunate
In
transistor
we
applications,
no
is
bias.
different.
Rg2
bias resistor
is
at
probably
usually
in
is
previous systems
(transistor
as well as to
In the saturation
are
and
is
this
Actually, this
junction.
The baseemitter
chosen by
Figure 64 represents the principal current flow paths associated with the transistor,
Rg2
Vgg
is
signal
(6.5)
point,
and
is
a value
chosen to be
cc
_
p
"B1
V CE V RB2
i
(6.6)
Fig.
'z
49
64 Current
Flow in
ELECTRONICS/DIGITAL
TRANSISTOR SWITCH
EXPERIMENT 001 10
STORAGE TIME
DELAY TIME
FALL TIME
RISE TIME
&5
Fig.
remembering
that
any
in
time.
The B
pulse
Thus,
The
is
It is
transistor.
resulting
B Vqe Waveforms
the device
is
happens
beginning of the
V CE wave
time (between
10%
and the
(between
is
for
trailing
the
90%
delay
curve
point.
edge and
to
This
when the
fall
is
The
is
storage time
100%
When
is
base material.
on to off
ment
carriers to
is
start
in
the transistor
storage time
the
is
is
time
is
method of
to use
reducing
In
tor
rise
region.
may
be operated only
tech
in
However,
any waveform.
to the
operated
it
is
from
devices,
reproduce
transistor
saturation region.
all
needs explanation.
period
on the
time
fall
not nor
is
the rise
internal
caused by the
from
removed
the loadline.
complex and
gives the
given value of
fulldriven operation.
50
is
quite
called
EXPERIMENT 001 10
ELECTRONICS/DIGITAL
Fig.
A
is
66
shown
in figure 66.
Vg^
known.
figure
TRANSISTOR SWITCH
67.
determine
Once Vg^
is
in
known we can
Rg by
rise time.
This seems a
values for
One method
is
RB
V BE
required for lg
the
it
AV
on can be determined
(6.7,
The
if'B on
Ig
on
is
will
maximum
Vg E
if
Vqq
AV
is
V inmax V BEon
V EB V0LTS
Fig.
&7
Determining
51
Vgg
<*8)
Since
desired
the
capacitor
overdrive current,
through
CB
will
ELECTRONICS/DIGITAL
EXPERIMENT 00110
to
is
supply the
the current
equal the
B on
equation for
It
'CB
_l Bon
is
also
is
possible
At
Solving this
(6 10)

to
When Rg
experimentally.
(6.9)
determine
is
in
the
Cg
circuit,
placed
different values of capacitance can be
across
At
yields
'Bon At
cB =
"av
CB
current.
C B AV
Cg
until
it
the
required
rise
time
is
obtained.
MATERIALS
 10 meg)
2 Resistance substitution boxes (15ft
equivalent
or
Transistor type 2N 1 305
1
1
Transistor socket
DC power
2N1305
supplies (040V)
transistor
Function generator
PROCEDURE
1.
required R L for
Using the transistor curves, calculate the
2.
V cC
6V and c = 4 mA.
l
in figure 68.
2N1305
R,
=?
OSCILLO
SCOPE
6 VDC
rum
IV
Fig.
Apply
2V
68
The
5.
Draw
52
rise
time, pulse
EXPERIMENT 001 10
ELECTRONICS/DIGITAL
6.
7.
Calculate
8.
Wire the
Rg
Rg
step 5.
Fig.
9.
in
TRANSISTOR SWITCH
&9
shown
in figure 69.
Record the
rise
time,
fall
10.
Observe point
and
fall
11.
Calculate
12.
Install
13.
Cg
in
the circuit of figure 69 with the oscilloscope. Measure and record
rise
ANALYSIS GUIDE.
the
The
in
53
EXPERIMENT 001 10
TRANSISTOR SWITCH
CALCULATIONS R L
Waveform
RB
CALCULATIONS
Fig.
610
54
ELECTRONICS/DIGITAL
ELECTRONICS/DIGITAL
FIRST
EXPERIMENT 001 10
DELAY
RISE
PULSE
STORAGE
FALL
TIME
TIME
DURATION
TIME
TIME
CKT
OUTPUT Rg
POINT X Rg
m
rUIT
UUITPI
1
R P
r>gL.g
POINT X
R BCB
OUTPUT
Steps
(Three
Above
CB )
POINT X
(Three Steps
Above Cg)
OUTPUT
Steps
CB
(Three
Below
POINTX
(Three Steps
Below C)
Output Waveform
with
Rg
in
TRANSISTOR SWITCH
the
circuit
Fig.
&10
55
EXPERIMENT 001 10
Waveform
Point
TRANSISTOR SWITCH
at
with
Rfj in the
Circuit
C R CALCULATIONS
Output Waveform
with
CB
in
the
Circuit
Fig. 6
10
56
ELECTRONICS/DIGITAL
EXPERIMENT 001 10
ELECTRONICS/DIGITAL
Waveform
Point
Cg
the
in
at
with
Circuit
Output Waveform
C Three
Steps Above Cg
with
Waveform
Point
at
with
Three Steps
Above Cg
Fig.
& 10
57
TRANSISTOR SWITCH
EXPERIMENT 00110
ELECTRONICS/DIGITAL
Output Waveform
With C Three
Steps Below
Waveform
Point
Cg
at
With
C Three Steps
Below Cg
Fig.
610
PROBLEMS
1.
Calculate saturation
V cc
= 180CK2.
2.
Draw the
Draw the
it
is
in
Explain your
to be reasonable.
in
reasonable.
58
Explain
why you
experiment
INTRODUCTION. The
we
diode
(fill
frequently encountered
is
will
DIODE CLIPPERS
I I
this device
is
In this
logic circuits.
in
experiment
positioned as
in
dif
and
They can
also
circuits.
set
E jn =
first
to
circuit
we
you as a halfwave
series clipper
going
circuit
passed
if
will
look at
is
is
rectifier.
shown
the diode
in
is
(7.1)
the
simple
reverse
diode be
Using
diode.
is
(R
(7.2)
resistance
of the
diode.
It
is
is
is
It
is
where
ratio
figure 71.
Dj.
jn
reversed) will be
+R f
much
circuit
(R L
transients.
series clipper.
is
equation can
similar
The
shown
the peak
much
larger
(R r
R L R
).
is
the forward
diode current,
The equation
Rf
is
The
the
is
the load
for the
positive
circuit
in figure 71
some other
in
Fig. 7 1
shown
Series
Diode Clipper
59
clipping level
is
is
used
level.
If
EXPERIMENT 00111
ELECTRONICS/DIGITAL
DIODE CLIPPERS
2V
Fig.
is
72
necessary.
By
input voltage
The twovolt
original
5V
With
7V
is
is
greater than
2V and
until
it
this
volts
clipped.
adds to the
clipped output.
effect
is
We
volts clipped.
parallel with
In the case of figure 72, the negative
2V
circuit.
R L?
series currentlimiting
resistor
w6
10V
out
O
2V
Fig.
3V
73
60
ov
L__r
is
exces
DIODE CL IPPERS
EXPERIMENT 00111
ELECTRONICS/DIGITAL
rAA/\r
OV
Fig.
sive
74
During
smallest of
R_.
If
much
R_ will
the
resistance
of
produce E Q as
As with the
clipper
half cycle to
biased
resistance
rr
is
are
of ohms.
to
series
both
be
the shunt
clipper,
forward and
reverse
levels.
the series
during the
a negative pulse.
diode should be
In
alters the
75
The reverse
resistance of the diode should be by far the
The load
highest resistance in the circuit.
The series
resistance is the next largest.
relationships
can
design
many thousands
in
the
greater than
The
this
ground.
reverse
all.
values should be
effectively
TTTJ
important.
R[_,
it
shows
action
this
shunt clipper.
in
The output
reverse
will
input.
and the
will
The
be the
full
be equal
to
the
61
waveform
E.
75
biased
,0V
Fig.
Figure
ELECTRONICS/DIGITAL
DIODE CLIPPERS
EXPERIMENT 001 1 1
AAAr
 ov
in
li_t
<
^" V Bias
Bias
76
Fig.
bias voltage.
is
greater
forward
conduction
E
in"
Rs
(7.3)
It
the
action,
useful.
It is
This circuit
used
is
clipping action.
in
many
The
sine
wave
bias to the
is
diodes.
is
as
is
is
R_.
input
is
which
Rf
this
clipper that
in
Ej
is
diode clipper.
if
appear across
There
V Bias
V jn
will
then
is
'f
where the
bias.
current
cycle.
These biases
are equal
when
When
D\
is
symmetric.
will rise
V B . When D2
conducts, the output voltage will go negative,
to the bias voltage value of
Forward biasing of
cuit
is
shown
a shunt clipper
in figure 76.
This configuration
ward
bias
the
diode,
we
cir
When we
to the value of
half cycle of
for
allow conduction
AW
T
77
half cycle of Ej
Ik
'B1
Fig.
Vg2 So
E jn
62
Dj clips
and D2
the positive
EXPERIMENT 00111
ELECTRONICS/DIGITAL
DIODE CL IPPERS
MATERIALS
Diode,
1N645
or equivalent
DC power
supply (040V)
Oscilloscope
Function generator
PROCEDURE
1.
Assemble the
circuit
shown
in
figure 78.
INPUT
10V
100
11
pp
Fig.
The
78
First
kn
Experimental Circuit
2.
Apply
3.
Connect the oscilloscope across R_ and sketch the output waveform.
the amplitude, period, and zero reference level.
4.
Add
10V
the
2V
bias as
shown
in
Be sure to record
figure 79.
= 100
kn
in
2V
Fig.
5.
As
79
2V
bias supply.
63
p p
kHz input
EXPERIMENT 001 1 1
DIODE CLIPPERS
ELECTRONICS/DIGITAL
7.
8.
in
figure 710.
tookn
710
Fig.
Apply
9.
a 5
Vp_p,
10.
11.
Add
the
2V
bias
shown
in
figure 711.
3.3
12.
1
R[_.
kn
Fig.
711
kHz
waveform across
R_.
3.
Repeat step
14.
ANALYSIS GUIDE.
2.
In analyzing
your
results,
The
levels of clipping in
PROBLEMS
1.
2.
in
Draw
total voltage
megohms.
Its
forward resistance
is
10
V Bjas
=
1
swing of E QUt ?
64
will
be the
ELECTRONICS/DIGITAL
EXPERIMENT 00111
DIODE CL IPPERS
First Circuit
Amplitude
=
1
Period
till
1
1
Hit
MM
Mil'
HM
M M Mil
MM
Output Waveform
(Show zero reference level)
Second Circuit
Amplitude
MM
MM MM MM
III!
Ml
Ml MM' MM MM
Ppriod
Output Waveform
(Show zero
reference level)
Third Circuit
Amplitude
Period
nn MM MM MM
II
III!
Mil
MM MM MM
Output Waveform
(Show zero reference level)
Fig. 7
12
65
EXPERIMENT 001 1 1
DIODE CL IPPERS
ELECTRONICS/DIGITAL
I
Fourth Circuit
Amplitude
HH
Period
MM
III
ii
1
I
MM MM MM
Output Waveform
(Show zero reference level)
Fig.
712
66
HH
01000
experiment
we
is
a transistor
is
is
selection.
In this
The
experiment
it
achieved.
A method
DISCUSSION.
many
waves
in
a sine
wave.
practical systems
is
experiment
we
will
look at
overdriving.
to "square"
in several
with
is
ways
of
In this
how
can
this
The
the
large
sinewave
reaches
its
in
first circuit
we
shall
consider
schematic
is
shown
is
(but not
load
resistance
and the
in
the transistor
almost
Actually
The
called
maximum
"clipped."
is
if
be
will
figure 81.
the
In this case
sufficiently
quite) perpendicular,
be done.
in
examine how
will
TRANSISTOR CLIPPERS
AND CLAMPS
saturation
class
design
due to
V CC
L=i C max
AAAr
6
Q
'cc
Fig. 8 1
67
(8.1)
This equation
Vqq
line.
\q
rent.
This
load line
voltage
drawn from
is
Vqq
load
is
DC
is
maximum
the
is
is
ELECTRONICS/DIGITAL
EXPERIMENT 01000
to Iq
where the
The
maximum.
lg
gAT
The input
can be found by
E in
SAT"
line.
R b'b SAT
(8.2)
standpoint
is
Rg which
Ig
Fig.
82
Clipper
Load Line
line
is
drawn.
The
The
from cutoff to
saturation.
The transposition
form for
rise
resistance
selecting Rg.
usually
will
The base
level.
be
emitter
negligible
when
in
b"
(8.3)
this
circuit
across
is
is,
same frequency.
At the
collector
is
at
its
fall
start
is
for saturation
(equation 8.3).
The
is
the voltage
rise
time (and
pression
with no
supply voltage.
Rg
(8.4)
rB
E in
After
SAT
V max
sin
2 *
(8.5)
fx
the
resistor
input
is
mains
off.
When
fall
have an
the
rise
times.
saturation
re
resistor
influence on
is
of
Ej
input
voltage
required
68
for
and
to
level
produce the
EXPERIMENT 01000
ELECTRONICS/DIGITAL
Bias
'CC
BE
Fig.
The
and
increase in frequency.
The end
trend
fall
in transistor
may seem
how
with
However,
long
when you
The
is
short
when the
junction
is
to
carriers
the turnoff
best
way
is
transistor
In
order to do this
diode clamp.
we can
This clamp
up the base
to
region.
will
With few
OFF
once the
is
signal
is
is
re
considerably
will
more
clearly
idea.
In
Vqq
the
is
base
in
This con
Vqq q N
voltage will
driven further
its
own
bias voltage.
to prevent the
The object is to
vent the basecollector from becoming
ward biased.
This means that the
into saturation.
lector
The
never become
majority
In other words,
It is
to prevent this
operating
region.
reduced.
degree of saturation.
fill
carriers
collector
must be removed
will
ON
into
active
of time,
biased,
pass
pre
allowed to go
is
Anytime the
forward
are allowed
These
device
the
junction
ready to switch
indeed required.
region.
majority
increased
carriers
periods
inside
not tend to
relatively
in
just
so con
make
beyond
drop
to
By
level.
collectorbase
takes to switch.
it
will
point
fre
switching
base
we
switch applications.
we would be
voltage
determined
is
collector
to
limit of this
quently arises
cerned
is
times with an
is
time.
It
83
use
will
what
is
clamp
voltage.
called
larger
69
is
prefor
bias
always much
The
ELECTRONICS/DIGITAL
EXPERIMENT 01000
o _v cc
xr
'1<
84
Fig.
diode
is
Practical
At
level.
point
that
the
C1
at cutoff
diode
limiting factor.
The
circuit can
diode
Eq E q N
than E BE
larger
is
much
Then
still
at
portion
V CE ON
V Bias
(8 7)
v DiodeFD" V CE ON
(88)
V Diode FD
lector
shown
is
in figure
is
This
Ri and
84.
level
is
VC 1
When no
output
signal
rises
to
is
Rl
circuit.
1
(8.9)
as
potential
it
R s ).
is
go
70
our
simple
collector
Vq E
is
the signaldiode
to
is
Th
back
This circuit
figure 85.
when employing
base over
The diode
change
Vq<j.
in
To improve
drive.
the clamp
in
particularly useful
the value
+ R2
\q
the extra
to accomplish this
used
is
saturation,
V CC R
value and
clamp shown
by the voltage
set
approach
The
of
One way
clamp.
clamping
transistor.
is
control
A more
maximum
its
disadvantages
the
V Bias
that
'
or
is
circuit
the
circuit recovery.
is
in
will
the bias.
around
the
conduct because of
This will
overdrive
let
the
part of \q
circuit
and
the
EXPERIMENT 01000
ELECTRONICS/DIGITAL
85
Fig.
transistor (a sort of
bypass
This
equal to the
bypass,
in
put,
3flg.
across
V clamp
V CE
we
resistor
is
has
can use
o
has
slightly
all
been
placed with
86
characteristic
silicon
diode.
A/NAr
Fig.
not seriously
(desired)
V forward
does
silicon
time
/3f
the
is
recovery
its
will
to
is
of
Back Clamp
Single Diode
relief valve).
voltage
drop
(from
A
its
0.5V to
EXPERIMENT 01000
0.7V)
in
circuit
forward
the
the diode
The diode
type and
In
always forward
is
at the collector
Dj
is
direction.
is
ELECTRONICS/DIGITAL
this
is
biased.
germanium
^BE
(8.13)
At that
excess
This
opposes
current
V CE
Iq
and
Vg^
greater than
volts.
we can observe
can be determined
at the time.
by
Substituting,
must always
be
V CE
= Forward Dr P
D 1 + Clamp
D2
Voltage
plus the
clamp voltage.
The
trick here
is
VgQ
off,
= Forward Drop
V Bq
V D1
is
has
D2 + Voltage Across Di
VD
voltage.
we
its
both
V D2
and
Since
insured that
we chose D 2
its
as a silicon diode,
V BC
= Forward Dr P
D 2 + Forward Dro P D 1
makes the
always
conducting value
this
Vq^
> V BC
(8.12)
MATERIALS
1
Oscilloscope
VOM
Function generator
germanium type
1 kft resistor 1/2W
DC power
Transistor type
Output
supply (040V)
2N 1 305
or equivalent
FEM
or
Transistor socket
Breadboard
1/2W
PROCEDURE
1.
Calculate
V cc
2.
R B and R L
in figure 87.
72
2N1305
transistor operating
at
EXPERIMENT 01000
ELECTRONICS/DIGITAL
2N1305
e
out
O
'CC
Fig.
87
3.
From
4.
5.
6.
7.
Calculate the rise time for the leading and trailing edges.
8.
9.
10.
Assemble the
ej
circuit
rise
10V peak
sine
wave
at
kHz.
trailing edges.
n and lg.
shown
R2
in figure 88.
OUTPUT
11
0 v cc
AA/V
10V
J2N1305
ru
C1
6.8
kn
GND
Fig.
88
73
EXPERIMENT 01000
RB
V CC
RL
ELECTRONICS/DIGITAL
E in
tTE
tLE
Calculated
Measure
Output
Resistor
Clipper
r2
Ri
v cc
Calculated
Measure
Output
Diode
Emitter
Clamp
Fig.
89
74
V C1
E in
EXPERIMENT 01000
ELECTRONICS/DIGITAL
V
11.
Apply
12.
.
p p
in
wave input?
PROBLEMS
1.
a bias
voltage of 3 volts,
what
is
the
3.
Given a single diode back clamp with an \q required at 6 mA and the current through
the load resistor 3 mA, how much current will pass through the diode?
We
transistor conducting
drop of 0.2V.
We
is
1.5 volts.
The
The diode Di
is
your answer.
75
Is
this possible?
forward
Explain
experiment
QJ^QQJ
DISCUSSION. Logic
normally operate
input
levels.
with two
logic cir
cuits,
possible
signals that
in
OFF or ON, or
number system. The
two signal levels could be represented by any
two voltage levels. When the more positive
series
with each.
types.
operations,
system
level
0 or "no".
is
termed negative
different
logic.
The
levels
is
types of systems
(+)
and times
(X).)
Figure 91
gates.
In
OR
gate,
duces an output.
is
can be of
exists
same polarity so
more negative or more positive
two Boolean
In
when any or
present
polarities or the
long as one
them plus
to the
two
or "yes", the
logic.
OR
sents
termed positive
is
call
They correspond
logic
experiment
level
In this
at
A,
That
all
is,
an output pulse
The Boolean
or B, or C.
is
use today.
Some
A+
of the
B + C = Output
(9.1)
0,
6 and
0,
OR
and 5 and 0
volts.
AO
gates will
more
positive
BO
+4
bO
CO
+4
OR
cO
GATE
AND GATE
6 V BIAS
Fig.
91
Diode
6 V BIAS
lower
truth
table
the
for
AO
The
shown in
figure 91.
in
OR
EXPERIMENT 01001
ELECTRONICS/DIGITAL
gate
is
figure 92.
BO
INPUT
OUTPUT
>r
C O
6v Bias
summary, the
In
an output
C, or
OR
there
if
is
OR
Gate
Positive
"You
circuit says,
Circuit for
Going Pulses
get
the
In
an input at A, or B, or
electronics
N."
An OR
94
Fig.
92
Fig.
0 E c
case
of
almost
is
the
OR
circuit,
the
Pulses which
trivial.
The
AND
circuit,
and
C and
The
Boolean
circuit
in
and B
equation
for
AND
the
Reversing the
diode
the
positive pulses.
is
times larger
ABC
= Output
of
pulses
polarity.
gate
select
will
As long
opposite
OR
gate for
as the R_
many
is
(9.2)
AND
circuit
is
shown
to the
figure 93.
to
the
losses
across the
diodes,
it
is
not
INPUT
OUTPUT
Fig.
electronics
may
require
circuit
93
AND
AND
are
total
is
all
Be
the diodes
signal.
The
dropped across
R L or
(The voltage drop across
Circuit
R_)
V RL
V Bias
(9.3)
77
EXPERIMENT 01001
ao
ELECTRONICS/DIGITAL
+4
bO
co
+4
Bias
95
Fig.
Positive
AND
Gate
dropped
inputs,
turned
off;
Since
all
as
is
OV
be an output will
(9.4)
Figure
positive
pulses.
pulses can be
shows an
made by
AND
when
for
zero,
drop goes
to
and
These are the most basic and perhaps
at an
AND
still
Rj_ voltage
off.
In figure
and the
gate
will
the bias
E0 =
all
inappropriate
pulses appear
(INPUTS)
at
gate and
Many
practical
If
any of the
in
other
logic
logic
Fig.
96
78
circuits.
in
gates
are
OR
gate.
used
in
Resistorcapacitor
many types
(OUTPUT)
of transistor
EXPERIMENT 01001
ELECTRONICS/DIGITAL
A
(INPUTS)
(OUTPUT)
Fig.
The
gates.
97
Three input
when
important
is
Gate Symbol
diode
particularly
will
a sort of
zero output
normal
is
shown
backward
when
AND
ative
In
Vpj_
is
at
because
V^
is
v RL
with a
off but
C and
A and B,
negative
the diodes
when
at
least
at the
positive pulse
equal
to V
will
will
I
6 +v.
98
is
not change
level.
"0 E r
Fig.
a neg
still
A o
voltage
magnitude
applied to
cut off.
=o
the
and
When
B.
this case,
pulse
v 1 +
while
input
all
table
AND
to V2.
This
in figure 98.
voltage
voltage.
truth
V2
diode inhibitor,
Its
will also
it
is
be clamped to the
employed.
With
resistor.
OR
Inhibitor Gate
79
EXPERIMENT 01001
ELECTRONICS/DIGITAL
MATERIALS
2 Resistance substitution boxes
(15ft 10megS2)
DC power
Oscilloscope
supply (040V)
Function generator
PROCEDURE
1
Connect the
circuit
shown
in figure 99.
OUTPUT
+5V =
V(1)
+4
AO
2.4
^^V
0=
V(0)
BO
Fig.
2.
0+4V
99
The
Experimental Circuit
First
at
kHz
to input A.
Apply approximately +5
volt pulses at
kHz
to input B while
is
at zero volts.
Measure
5.
B.
in figure
910.
O OUTPUT
+5V =
V(1)
>r
INPUT A O
30 kn
O +4 VOLTS
0=
V(0)
INPUT B O
Fig.
6.
Apply +5
volt,
910
kHz
pulses at
with B at zero
waveform.
80
volts.
EXPERIMENT 01001
ELECTRONICS/DIGITAL
7.
Apply +5
volt,
kHz
pulses at B with
kHz
pulses at
at zero volts.
waveform.
8.
Apply +5
type of
9.
and
B.
(Positive Logic)
+3V
10.
volts,
gate.
at
will
kHz.
ANALYSIS GUIDE.
In this
circuit,
and
give
its
Boolean equation.
In
operation of each of the experimental gates using your waveforms to illustrate their operation.
Output
Input
A = +5
B=
Output Waveform
Input
A=
Output
B = +5
Output Waveform
Fig.
911
81
EXPERIMENT 01001
ELECTRONICS/DIGITAL
Output
Input
= +5
B = +5
Type
Circuit
Output Waveform
Output
Input
= +5
B=
Output Waveform
Input
A=
Output
B = +3
Output Waveform
Fig.
911
82
EXPERIMENT 01001
ELECTRONICS/DIGITAL
Output
Input
A = +3
B = +3
Circuit
Type
Output Waveform
Fig.
911
Two
83
EXPERIMENT 01001
ELECTRONICS/DIGITAL
INPUTS
OUTPUT
Fig.
911
BOOLEAN EQUATION
PROBLEMS
1.
2.
Will
AND
AND
will
the output
level
two inputs
be?
diode
if
silicon diodes
germanium? Why?
what
will
84
A?
experiment
INTRODUCTION.
this experiment we
gates are
RESISTORTRANSISTOR LOGIC
01010
(RTL) CIRCUITS
may
examine transistorized
They
In
These
RTL
circuits.
DISCUSSION.
of
shown
the circuit
transistor
supply
ative
Qi
Vgg.
Let's
is
If
figure
in
simply, a
The
101.
pulse
we apply
If
the
However,
circuit
since
if
that
acts
driving
is
inverted.
is
called
As
possible.
OR
like
an
the
base
where E 0
(10.1)
is
gate.
negative
often
+ B + C = E,
a single input
result,
is
completely into
transistor
saturation,
a sufficiently neg
drives the
gate.
transistor
NOR
cuit
output
resistances
can
cir
be readily determined
acteristics.
curves
shown
For example,
let's
consider the
in figure 102.
INPUTS
'"LTLTLT
:
o o
b
i_n_r
u
Fig.
10
An
85
_rLn_rr:
EXPERIMENT 01010
I
ELECTRONICS/DIGITAL
(RTL) CIRCUITS
'B
(iA)
0.05
V CE (VOLTS)
Fig.
102
Transistor Characteristics
60
the
mA
The
would be reasonable.
would then be
things.
First,
resistance
V cc
20
5
CSAT
observe
0.15V 0.13V
80 juA  40 juA
Al g
0.02V
= 500fi
40 /nA
On
not a standard
is
size,
is
we would
from
Vqq
transistor
C max
20
5.1
saturation.
line
plotted
is
this
mA
we observe
60 mA or more
j = 60 (x A)
g
base current of
off.
10R in
In
our example,
would be
R B = 10 R jn = 5
With the load
R B=
to
3.9k
must not be so
col
is
V CC
it
will
the
value of
the nearest
size.
two
be approximately
approximately
AV BE
= 4kfi
mA
is
on
will
/xA) with
col
'in
RC =
Vgg
And
0.15 volts.
lector resistor
0.20
V BE (VOLTS)
about 5
0.15
0.10
kft
that a
and
required for
4.7
86
we would probably
k2
resistor.
decide
to
use
EXPERIMENT 01010
ELECTRONICS/DIGITAL
The input
R2,
resistors (Rj,
R3)
are
cases,
Vg on
input
pulse
R 1 = R2 = R3
lg
chosen
are
and
applied,
if
assure
that
VA
To turn
satisfy
VB
V c = 10 volts
we must
we have
100.15
= 164
60 /xA
kl
inverted
size,
size.
more
103
figure 101
is
cir
In
the value of
Rg
to a
is
applied,
and saturate
AND
gate.
Such
a gate
if
it
we
have an
is
called a
gate.
most
conditions are
practical
inputs.
in
we would
(A)
shown
we merely change
all
NAND
not a standard
circuit
when
than
use 150 k2
is
our example. In
If
Since this
in
cuits available.
BSAT
R,
bsat
we would probably
The RTL
V A V BEon
VA
the relationship
_
R1 =
use simply
we can
is
either case,
height that
sufficient
will
g^y
to
compared to the
so small
is
R
"1 ~
(RTL) CIRCUITS
(b)
87
NAND
Gate (with
ALL INPUTS
N inputs)
EXPERIMENT 01010
ELECTRONICS/DIGITAL
(RTL) CIRCUITS
Fig.
104
An
Inversion /AND
(NAND) Gate
urated.
If
we apply two
s
\^
Oand s \\ = lg
\
Vgg
Vgg on we
this
much
are both
V BB
q
andR
.
(N1)l BSAT
We
acts as an
happens,
pulse.
But
we
now
we apply
inverting
Rq
all
AND
circuit
NAND
or a
circuit resistances
be
Choosing the
S
1!^
if
SAT
RB =
B),
circuits are
inputs (A and
is
NOR
gate.
somegate.
as
as
before.
The base
ABC
= E
Q
(10.2)
resistor
If
we
transistor
We
sistor
Q.
is
If
one input
sat
still
we apply
it is
too deeply
cutoff.
must,
satisfy
therefore,
lg
is
than
SAT
That
Vg^ on
Secondly,
sat
88
First,
be saturated.
greater
from saturation to
ditions simultaneously.
switch the
is,
Vg E
must
still
be
when
all
must be cut
inputs
off.
are
That
EXPERIMENT 01010
ELECTRONICS/DIGITAL
105
Fig.
is,
Vgg must
approximately
be
perhaps even a
little
we choose
cutoff.
We
circuit
shown
R3 =
= R =
2
From
zero
(or
From
to have
Vg^
this circuit
is
shown
we have
figure
in
106.
the equation
Let's suppose
equal to zero at
'bb
's
'bsat
in
.
105 (assuming
figure
or
= R ).
N
this circuit
we
V BB
see that
V BEon
5
ES +
Kg
V BB
(RTL) CIRCUITS
N Es
where E5
is
Similarly,
Fig.
106
all
V BEon
ffc
(N 
1X
1)
K
'bsat
but
89
Vgg
EXPERIMENT 01010
V BE
on
AND
ELECTRONICS/DIGITAL
(RTL) CIRCUITS
BE on
9 ives us
circuit
component
the circuit
values.
Rg
If
is
such that
is
BB
B
(1/N)
SAT
=
RR
B
off.
values of
and
R 1 ~\
it
V BB
i
'BSAT
and Ri =
1
SAT
SAT
And
A+
RB
B + C = E,
55.5 kQ,
NOR
operation.
and
Using
Rj
= R =
2
R3=
166 kft
AND
we would probably
use values of
always be
INVERTED
As was the
function
case before
we can change
by selecting another
the
set
or
of
NOR
gate,
we can convert
OUTPUT
INPUT
jj
OE,
. . 
WV
+v
BB'
Fig.
107
Logic Inverter
90
Figure
By
to the output of a
logic.
INVERTER
a gate can
necessary.
logic
if
_TL
to
coup
NAND
AND and OR
EXPERIMENT 01010
ELECTRONICS/DIGITAL
Fig.
In
Rl =
an inverter
Rg = 10
Rj
Rq
is
108
NPN Logic
chosen as before,
for
The
have
used
PNP
transistors
up to
this point
only.
Similar
Gates
(RTL) CIRCUITS
NPN
transistors.
and
NOR
gate
You should be
NAND
and
be constructed using
employing
NPN
NOR
NAND
devices
which
is
the
gate by yourself.
MATERIALS
2
DC power supplies
or FEM
(040V)
VOM
2 Transistors, type
by student)
or equivalent
Breadboard
2 Transistor sockets
PROCEDURE
1.
2.
Using your transistor curves, determine an appropriate value of collector resistor to use
= 10 volts.
V
with
3.
transistors
cc
Vgg
of 10 volts and a
Eg of 10
Rj
volts.
circuit
NAND
shown
in
figure 104.
4.
5.
When your
present.
circuit
is
NAND
91
Vq^
with no input
EXPERIMENT 01010
A
Connect input
6.
ELECTRONICS/DIGITAL
(RTL) CIRCUITS
(B input should be
grounded.)
Vq^
7.
and
8.
polarity.
its
(A should be
grounded.)
9.
10.
11.
Vq^
polarity.
its
and input B to
and
polarity.
its
2.
3.
V BB
proper polarity.
1 1
2.
14.
15.
your
R
it
to the output of
16.
17.
V BB
this
Vq^
Vq E
of
Draw
18.
complete
transistor type,
ANALYSIS GUIDE.
circuit
it
how your
how you
an
can
tell if
this experiment,
you should
RTL
V CE
No
from
Discuss
values,
polarities.
what
circuit
is
NAND
V CE
Input A Only
Input
or a
Input B Only
Circuit
Second
Circuit
Third
Circuit
Fourth
Circuit
Measured Data
109
92
gate.
V CE
First
Fig.
NOR
V CE
Input
A&
tell
EXPERIMENT 01010
ELECTRONICS/DIGITAL
(RTL) CIRCUITS
Circuit Diagram
109
Fig.
PROBLEMS
1.
JTTI
TL
JIT!
component values
for
1010.
in figure
oWVi
WV
n.
JUTJl
in
o
D
OUTPUT
oWV"
__n_TL
ALL INPUTS 5V_pp
Fig.
1010
Circuit for
93
Problem
EXPERIMENT 01010
2.
3.
Make
(RTL) CIRCUITS
ELECTRONICS/DIGITAL
output of the
figure 1010?
4.
What
5.
Explain
is
94
in
in figure
1O10?
circuit in
INTRODUCTION. There
(DCTL)
experiment we
three
state
a negative pulse
on.
off,
is
voltage
would
applied to input
inputs
to
come
the
and
on.
B,
both
equal
be
0_i
all
pulses to
all
approximately
The
to
get
Vqq.
Q 2 would
and
However, since
Q3
is still
pulse only
an output
negative
direct
zero.
neously.
If
then
output
inputs,
come on and
common
we apply simultaneous
If
cut off.
circuits.
figure 111.
zero.
will
DISCUSSION.
in
own
experiment
inputs to
all
This circuit
three
then
is
that
we
will
when we apply
is
bases
a
simulta
NAND
gate
want
cut off
ABC =
(11.1)
E,
OUTPUT
'cc
INPUT
i_n_n_r
0
E c
UTJ
i_r
oAA/V
^f^(fc^)
Fig.
111
Series
DCTL NAND
95
Gate
EXPERIMENT 0101 1
(DCTL) GA TES
Fig.
The DCTL
ELECTRONICS/DIGITAL
12
Series
DCTL NOR
sistors,
of
of
Rq need
safe
(Figure
was such
11
RC =
a circuit.)
is
If
NOR
its
Iq
max
and
(11.3)
Some
tran
max
sistors
be biased individually.
shows
Figure 113
The
Vqq.
gate and
it
value of
V cc
'C
Q3 are
value
computing Rq.
ative voltage.
by choosing
all
Vqq, and
In building series
112.
Suppose that
Gate
circuit
Such
is,
a circuit
may be
either a
NAND
or
NOR
Boolean expres
bias.
is
A+
Series
B + C = E,
DCTL
(11.2)
bias polarity.
DCTL
NPN
or
PNP
tran
parallel
96
transistors.
made
using
EXPERIMENT 01011
ELECTRONICS/DIGITAL
Fig.
14
Parallel
97
DCTL NOR
Gate
(DCTL)
GATES
EXPERIMENT 0101 1
(DCTL) GA TES
ELECTRONICS/DIGITAL
v ccQ
cc
_n_n_TL
j~ltl
BO
n
115
Fig.
such
In this circuit
circuit.
sistors
are
voltage
is
all
A DCTL NAND
three tran
Figure
transistors,
rises to
fore, of the
it
near zero.
NOR
is
DCTL
parallel
circuit.
dual
parallel
near zero.
The gate
is
sistors,
there
case.
all
three transistors
output
If
we
normally
we
two
transistors are
tran
still
on.
Sim
is still
(11.4)
level is
are
the other
B + C = E,
circuit
this
applied to
ilarly, if
A+
the
shows the
115
In
If
of
dual
logic
normally at V cc
Gate
But
if
we
turn off
all
for
its
Boolean expression.
as a
We can
NAND
gate.
is
consequently
If
which
normally
produce positive
have a negative
signal
pulses
level
we have
and
ABC =
the
98
E,
(11.5)
EXPERIMENT 0101 1
ELECTRONICS/DIGITAL
(DCTL) GA TES
+v ccO
Oe.
AO
AAAr
AAAr
v bbO
A/W
AAAr
v bbO
CO
AAAr
B
AAAr
v bbO
Fig. 1 16
we need only
build
parallel
series circuits,
'c
max
anc
'
sistors
DCTL
116
gate.
cir
to
gate
bias
V cc
line
u
'C max
them
is
almost
to build parallel
shows
Rq
com P ute
separately
DCTL
we simply choose
=
Rr
C
We
series
if
of
Rq and
a separately biased
NPN
is
then calculated
using
Rg
Figure
R B~
circuit.
99
V BB

SAT
(11.6)
EXPERIMENT 0101 1
ELECTRONICS/DIGITAL
(DCTL) GA TES
NAND
current to
base
limit
to
NOR
twice lg SAT'
chosen
n1
or
safe
value, say
gates.
E
Similarly, the input resistors are
2lgg A j
MATERIALS
3 Transistors type 2N 1304 or
Breadboard
3 Transistor sockets
VOM
DC power
FEM
or
supplies (040V)
by student
PROCEDURE
1.
Choose
10
a value of
Rq which
is
V cc
of
volts.
which
2.
Compute
3.
4.
Apply
5.
6.
a value of R]
a voltage of correct
is
polarity to input
volts.
signal.
voltage.
out
put voltage.
and C.
7.
8.
Now
9.
Use
zero output.
all
8.
Vqq.
10.
11.
in
your truth
signal to all three inputs so that the three transistors are on.
2.
Remove
3.
Repeat step
table.
100
only.
Record
EXPERIMENT 0101 1
ELECTRONICS/DIGITAL
(DCTL) GA TES
14.
15.
and
16.
17.
and output
Vqq. Use
all
C.
18.
19.
20.
Draw
ities
gate
In analyzing
gates to parallel
NAND
your
gates.
results
zero.
all
18.
circuit values.
series
NOR
First Circuit
Inputs 0 or
4 through
ANALYSIS GUIDE.
NAND
gates in the
Data
Output
Oor
Boolean Expression
Fig. 1 17
volts
NAND
EXPERIMENT 0101 1
(DCTL)
ELECTRONICS/DIGITAL
GA TES
Inputs 0 or
Output
0 or
volts
Boolean Expression
Inputs 0 or
Output
Boolean Expression
Fig.
117
102
Oor
volts
EXPERIMENT 0101 1
ELECTRONICS/DIGITAL
(DCTL) GA TES
Output
Oor
volts
Boolean Expression
Fig. 1 17
PROBLEMS
1.
Design a series
E
= 5
S
I
NAND
gate using
Repeat problem
3.
Repeat problem
using a
4.
5.
15
volts,
volts.
2.
figure
2N 1304s
2N1305.
shown
in figure
18.
How
is it
different
from
11?
6.
Draw
7.
figure
in
18.
shown
in figure
8.
in figure
9.
waveform.
shown
in figure
19.
waveform.
10.
103
in
figure 1110.
(DCTL) GA TES
EXPERIMENT 0101 1
v cc
INPUT
AO
LT
"LTLTLT
+E
i
Fig.
18
VW
Circuit for
Problem Five
INPUT
ruu
~U
VW
ao
LT
LT
uuu
Fig.
VW
19
Circuit for
104
Problem Seven
EXPERIMENT 01011
ELECTRONICS/DIGITAL
(DCTL) GA TES
+v cc
GATE
OUTPUT
?
INPUT
"0
AO
VW
i_n_r
+E C
~LTLT
Fig.
1 1
105
Er
experiment
INTRODUCTION.
experiment we
NOR
Inputs A,
other
which prevent
it is
shown
gate
B,
in
figure
negative
is
reference
is
voltage.
(12.1)
used,
all
the
When
c~
VCC
I
i
'C
max
any of the
a pulse
device.
transistors,
is
at zero volts.
s
+ B + C = E 0 (lnvertedOutput)
arrangement
of the gate
gate
In
can be inhibited.
from
this
DCTL NOR
NAND
a logic gate
121.
pulses
When
shall
circuits
logic
logic operations
DISCUSSION.
the series
some
Circuits
at certain times.
this
In
/f///f/t INHIBITORS
By
Vqq.
NPN
transistors.
"LTLTLr:
nji_n_
n_n_
J~L
Fig. 12 1
Vqq and
Series
106
NOR
Gate
'cc
EXPERIMENT 0 1 100
ELECTRONICS/DIGITAL
WV
WV
ao
o
io
'1
WNr
^Afc~
Fig.
As we have
said,
any time
122
positive
A, B, or C which
any of the
that
Q3),
output
some
cut
will
switch
or
and the
off
Suppose for
drop to Vqq.
reason we wish to exclude certain
For
inhibitor.
diode and
122
this
we
need to
possible
Inhibitors are
transistor
is
devise
logic.
transistor
The
in
inhibitor
B
or
C.
many ways
We
cutoff.
by applying
can
signals at A,
in
bias
and
in
gate.
allow us to use
to
an
both
circuit
the
will
transistor
will
pulses.
figure
transistor
INHIBI TORS
gates,
NPN
or
PNP
transistors
and
for the
ways.
The
is
Many
They
be constructed.
107
The
EXPERIMENT 01 100
INHIBITORS
applied
to
circuits,
and
NAND
one.
Its
Boolean expression
is
it
gate,
due
to
incoming
the
ELECTRONICS/DIGITAL
pulse.
in
output
The
inputs
AB
Its
truth table
is
= E,
shown
(12.5)
in figure 124.
no effect
(it
inhibited).
is
on which gate
series
NOR
will
shown
gate
Boolean expression
A+
is
B +
vary depending
AB=E Q
10= 0
00= 0
01
11 =
inhibited.
is
The Boolean
in
figure
121, the
equation 12.1.
C = E rt
=0
1
Fig.
A+
B + C = E,
(12.3)
The output of
A+
when the other
signal at
B +
Ai
C = E,
(12.4)
The
in figure
123.
is
inverted
from
= E,
that
(12.6)
logic
is
is
is
AB
NAND
AND
inhibited
gate
can be seen
AND,
of an
With an inhibitor
NAND
shown
NAND
in figure 125.
circuit
The output
is
The
is
The
series
NOR
in figure
126.
logic
is
shown
alteration
strates
inputs.
Agate inhibited.
V^V
Figure
Its
inhibitor's,
truth
is
When A and B
or B
inhibitor signal
B
O
Fig.
*^YV
123
Inhibited
NAND
at cutoff.
108
transistor
is
That
diodes
will
conduct
if
the
v RL  Vl
Gate
the
negative voltage at
of the
like
table,
to say,
= o
(12.7)
EXPERIMENT 01 100
ELECTRONICS/DIGITAL
Fig.
125
Logic
Fig.
Symbol
126
Fig.
127
for inhibited
Three Input
Inhibited
NOR
NAND
Gate
NOR Gate
+v i
Fig.
128
Gate
EXPERIMENT 01 100
where Vp_
The equation
voltage
(negative value)
in
with
re
is
to R_.
opposite
ELECTRONICS/DIGITAL
is
sistor
INHIBITORS
conducting.
to both
across R_.
off.
With diodes
D3
clamp diode
output
voltage
will
to
the
V2
Inhibition occurs
is
When
value.
A and
remain clamped to
will
at
will
will
the
nullify
cause
load and E
when
at the
applied to
and B
and B
a positive pulse
same time
C will conduct
inputs.
and
The diode C
0 cannot change.
MATERIALS
3 Transistors type 2N 1 304 or
2N1305
1
or equivalent
by students
Breadboard
3 Transistor sockets
(1512 10 megft)
1
VOM
Oscilloscope
or
supplies (040V)
DC power
FEM
N305
or equivalent
Function generator
PROCEDURE
1.
Choose
10
a value of
Rq which
is
2.
Compute
3.
4.
Vqq
of
volts.
VOM
Apply
a value of
R 1 which
is
volts.
and oscilloscope.
kHz
reading.
5.
6.
Now try
7.
8.
9.
Apply pulses to A,
all
and
C.
results.
circuit.
R2 and modify
B,
Record the
At the same
B<,
and
C.
70
Record the
results.
EXPERIMENT 01 100
ELECTRONICS/DIGITAL
10.
Remove the
pulses
from
Aj.
Record the
results.
11.
Remove the
pulses
from
B<.
Record the
results.
12.
Remove
C.
Record the
results.
13.
14.
15.
circuit.
16.
INHIBITORS
in figure
128.
Record
a gate can be
in
which
is
The results of the diode inhibitor should be compared with those of the
what conditions.
transistor inhibitor. The uninhibited transistor gate should be compared with the inhibited gate.
PROBLEMS
1.
Draw
2.
Show
the
3.
input which
is
NAN D
NOR
gate.
Show
inhibited.
111
NAND
gate at
EXPERIMENT 01 100
INHIBITORS
ELECTRONICS/DIGITAL
E
o
3
a.
<D
E
o
~o
u E
fQ.
'
mm' "ill!
</>
in
co
<D
CO
CD
d,
u
c
c S
QJ
tt
k.
=^
^ CO
I CD
O
>
.2
i_
</5c5 S.
ctj
05
MM
m r
)
MM
Mil
MM
M'l'
MM
MM
MM
7/2
MM
HH
ELECTRONICS/DIGITAL
EXPERIMENT 01 100
INHIBITORS
E
o
M
0)
T3
ave
>
03
"5. x:
ea
03
Q.
out
mm
HH
MM
ac
O0
03
C
"qj
00
lev
CO
03
00
i_
03
be td
um
a
<D
/an
0)
o
c
0)
L.
0)
03
i_
_03
01
i_
*>
T3
c
03
00
"to
o 03
>
CO
X3
rio
03
CL
i
a
res
Q
03
C3
III)
mi
il
il
113
il
MM
II
Mil"
MM MM
EXPERIMENT 01100
INHIBI TORS
ELECTRONICS/DIGITAL
E
L.
o
4
CD
>
Q.
+>
>
ZJ
to
C
o
it
3
to
(0
SJS.c
og
+++*
OC
MM MM
tO
(13
1)
s
L.
tO U
CD
"D
!
gj
00
03
3 >
<"
Q)
c
<D
L.
0)
CD
i_
"a
ro
V)
"D
O S
0)
c/3
U a
I
6
0)
++++
mm" Mil
III!
Imi' Mil
114
IMI
MM mm'
II
MM
FUNDAMENTALS OF
experiment
INTRODUCTION.
bistable.
stable
01101 MULTIVIBRATORS
The introduction
stable
astable multi
or freerunning oscillator,
vibrator,
shot,
refers
back.
has no
Selection of the
131
figure
be
will
procedure.
Characteristic
those shown
in
'b
vs
^BE^
w '"
curves
such
Vq^
as
and
b e necessary.
Step
Astable multivibrators, because of their
output waveforms, are used as square wave
generators, as
1.
multivibrators
where
amplifiers
feedback
with
loop.
is
the addition
Figure 131
of
shows
positive
a
basic
For symetrical
=
operation, R 2
Rg4 while R B i = Rg3,
B
and R_ = R[_2 This allows each transistor
astable multivibrator circuit.
ON
R=
is
'cMAX
'
line
is
intersect
V CC^'CMAX'
Since
RT = R E + R L
Normally R
E
less of Rj.
is
Thus
(13.1)
L1
'B2
5
Fig.
131
115
the
The
curve.
1
^Bl
timing of frequency.
to be
and
mono
multivibrator circuits.
astable, monostable,
Fig.
Step
The
2.
it
should be kept
near the
point
be
portion of the
linear
bleeder
thus
3.
V CCr Tney
anc
'BQ' 'CQ'
'
re
<
13 4

>
line.
Step
most
the
Vreq^eq^e^Ccq+'bq)
mind
criteria so
should
in
we
the
of
Transistor Characteristics
selected
that
load
132
point
center
ELECTRONICS/DIGITAL
MULTIVIBRATORS
EXPERIMENT 01101
current
resulting
sistance.
indicates
in
smaller
reduction of
Rg2,
input
is
re
limited.
of.
As
a rule of
thumb,
let
in figure 132.
(13.5)
'RB2Q 'BQ
Iqq
to
the lg
be
read
directly
Step
By
4.
Step
To determine Rg2
5.
on the base of
Vg^Q
Also
base of T^
step).
is
is
is
provided by
in
calculation of
R B2 ~
Vpg2.
the above
a reverse bias,
enough to offset
VggQ. The
requirement
Now
Rg2 may
be found from
132B).
V RB2Q
J
RB2Q
V REQ
V BEQ
(13.6)
RB2Q
Vg^Q
large
equal
Tj
figure
Since
must be
still
Z on
(point
Step
Vpg2
V R g2Q
6.
To determine R B1
it
is
seen that
and
previously, then
is
V,RB2Q 
REQ + V BEQ
(13.2)
116
(13.7)
EXPERIMENT 01101
ELECTRONICS/DIGITAL
passing
Current
+
!rB2Q
through
Rgj
equals
IgQ
definite frequency
Therefore,
f~
~
where C
R B1 ~
RB1Q
RB1Q
may
This
(13.9)
RB2Q
<
desired.
1Q6
1310
UAiui
0.025C + 2.5
oscillate for a
V RB2Q
Rqi
SI"
(13.8)
is
is
MULTIVIBRATORS
is
making
Cj
and C2
different values.
Rg^ = Rg3,
=
R L1
R L2' 3ut c ue to
of components, the value of Rg2
and
Rg4 may
be adjusted to bring
In the case of a
multivibrator there
'
'
Vq
determined
in
one transistor
of both
ON
is
monostable, oneshot,
step 3.
ON
required.
lations
itors
the
affect
empirically
either
lations,
an
tran
RC
derived
time
constant,
formula
may
be
thus
An
used
or to
When
ON
frequency of oscillations.
affecting the
sistor
ON.
OFF.
transistor should
is
state,
Fig.
133
if
let's
again do a
117
MULTIVIBRATORS
EXPERIMENT 01101
Fig.
The
multivibrator.
will
be helpful
Step
1.
in
this effort.
R E (Again R E
<
10% R T
figure 134
R^
and
must be drawn).
was presented
(13.13)
R B3"
B.
= R_2
s,
(this
Again,
is
(13.27)
)
be adjusted due to
separate
The same
is
pro
C
is
time
Vq
The value of
desired amount of
The larger the Cj
chosen so as to get
in
V CC/'CMAX
d3.11)
R T = R L1 + R E = R L2 +
(13.12)
RT =
Oscilloscope
Variable
circuits.
DC power
2 Transistors, type
(15ft 10 megft)
supply (040V)
2N1305
or equivalent
(1W)
transistor used
2 Transistor sockets
1
0.01
nF
capacitor
Function generator
118
in
circuit
MATERIALS
1
Monostable
R L2 = Rj
transistor characteristics
Here we chose
lines
R[_1 =
Transistor Characteristics
characteristic
points given
in
one
134
ELECTRONICS/DIGITAL
Breadboard
PROCEDURE.
1.
R_i
= R
=
L2 2.5
kfi,
Do
not connect
Cj
and C2
Rg2 = ^B4 =
R B1 = R B3 = 100
in figure 131
until
Step
kfi,
R E = 200ft
3.
and
J2
are
2.
Start with
3.
4.
Double
5.
Slightly vary
6.
7.
Cj
9.
Connect
Rg2 and
=
Rfj4
2V.
= Vq2
'
a sketch of
it.
Fig.
8.
EXPERIMENT 01101
ELECTRONICS/DIGITAL
a 5
p p
135
1000 Hz
in
it.
in figure
35.
in
output.
ANALYSIS GUIDE.
in
and
10.
119
EXPERIMENT 01101
MULTIVIBRATORS
ELECTRONICS/DIGITAL
PROBLEMS
1.
Calculate the frequency of oscillation of the circuit of the astable multivibrator and
compare
it
during step
6.
2.
Explain
3.
4.
in
step 5?
If so,
how do you
II
MM
till
Mil
mm" MM MM MM'
Output Waveform of
MM MM MM
Mil
11
1
1
First Circuit
j
'mm Mil
120
Mil
II
MM
experiment
INTRODUCTION.
Some
BISTABLE MULTIVIBRATORS
01110
In this
is
last
T2
saturated and
T
T2
Ti cutoff and
will
two
saturated.
cutoff, or
The
state.
multivibrator
inventors.
its
is
also
is
state.
commonly
let's
also
used.
stable circuit
starts
is
it is
used
in
This
OFF
The
T
is
initially in
resistance of the
ON
tran
potential
computer
Sometimes the bi
potential
(zero).
will
be close to ground
the
it
because
transistor.
Bistable
other
the
sistor will
electronic counting.
than
conduction.
"flip
forces the
trigger circuit,
The name
one
current
Either condition
bistable
active devices.
Vqq
for
be examined.
basic design criteria for the bistable or "flipflop" multivibrator will be presented.
there are
for
will
collector
potential
relative values of
Rgand
of
T2 depends on
Tj
and on the
R2.
shows
multivibrator circuit.
a typical
PNP
zero potential,
bistable
R4,
Bistable Multivibrator
121
will
be cut off.
Vq2 w '"
Rgand R^ form a
INPUT PULSE
Fig. 14 1
T2
With T2
approach Vqq.
voltagedivider network
EXPERIMENT 01 1 10
Vqq
across
even
which
in
ON
the
When
condition.
in
is
will
keep
its
and
Tj,
T2 ON.
the
If
through T^ to
Tj
and
Vqq
in
is
This
value.
If
J2
Two
to
is
Tj.
Fig.
positive
will
Now
citors
and
consider
to conduct
142
negative
pulses
or
and
positive
This
is
sometimes not
signal
This reduction of
T
applied to
OFF,
Tj
will
This
is
the appli
(zero) potential.
saturation
this will
change
in
toward the
cumulative,
T2
cause conduction
start decreasing,
will
conducting
is
through
Tj
its
T2
less
base
happen as
the stable state of the circuit
The
cut off.
then reached
stable
To change
this action of
it
these conditions
one of
and
less
ELECTRONICS/DIGITAL
let's
relabel
some
in
in figure 142.
capa
order to
122
the resistors
circuit.
Vqq
After
If
in
load line
construction,
ON and T2
OFF
is
let's
assume thatTj
'
not,
is
Since
compute the unknown resistances.
R L V BE (J^ ON) a f and V cc were
In this condition
treated
V cc
C1
EXPERIMENT 01 1 10
ELECTRONICS/DIGITAL
<L1
[ci
T2
V BE
may
OFF) =
(T 2
being
transistor often
(14.2)
'B1
by use of the
plotted
be
R B ^.
equation for
For
the variation of R B3
constants,
R B 4 may
and
(14.1)
as
(l
of this
not be neglected.
b eeder
l
co )R B2
(14.9)
Substituting,
B1
V CC
= (V cc /R L )ap =
H a
L F
_V CE
(14.3)
(T
'RB1
is

ON)V BE
!
(T 2
B1
OFF)
 'co
(14.10)
From the
we
notice that
So
'rB3~
B1
V BE
(14.4)
RB4
OFF)
(T 2
R B2
=
'C2
since
^2
cut
V CC V BE< T 1 0N
RB3
'
V CE
(T!
ON) V BE
(T 2
OFF)

R B1
CO
(14.11)
>
(14.5)
R B3 + R L2
or
R B2 =
and
V BE
(Tt
V BE
ON)
v CE
(14.6)
'RB4
R B4
(T 2
OFF) R B1
on)v be
(Tt
(t 2
off)i co r b1
(14.12)
from the
Remember
above equations,
V CC
figure 141?
V BE T 0N_>
<
^CC_
V BE< T 0N
R L1 a F
R B3 + R_2
tors
were

can be plotted.
the capacitors
C
and C2
in
capaci
to;
>
1.
R B4
2.
(14.7)
That
capacitors
is,
C
in
From
this
we
R B4
ing time.
R L1 V BE (T 1 ON)a F (R L2 + R B3
VqqRl"<>:pV be (Ti ON)  V CC R L2  V CC R B3
)
Rd/1
B4 "
123
(14.8)
ELECTRONICS/DIGITAL
MATERIALS
Oscilloscope
2 Variable
DC power
Multimeter
2 0.01
juF capacitors
2 Transistor sockets
Function generator
SPDT
supplies (040V)
Breadboard
switch
PROCEDURE
1.
in figure 143.
Have your
(47 kft).
2.5 kft
V CC =15V
TRIGGER
PULSE INPUT
Fig.
143
2.
3.
4.
is
OFF.
Apply
a positive
this.
124
ON
and C3.
BISTABLE MULTIVIBRATORS
EXPERIMENT 01 1 10
ELECTRONICS/DIGITAL
VC 1 =
V C2 =
II
MH
MM
MM MM
till
II
V C 1' =
VC2 =
1
nil
MM MM
HH
1lH
Mil
It
144
II
\[
MM
nil
Mil
MM MM
Mil
till
H+H H+H
125
HHHH
M MH
Fig.
Mil" "mm
Mil
ttIt
++++
EXPERIMENT 01 1 10
5.
If
V C1
'
V C2
and
the answer
is
'
ELECTRONICS/DIGITAL
4 using
a fivevolt positive
signal.
6.
C3
to the base of
T.
T2
V C2
and put
a pulse signal of
C 4 shown
in figure 141) to
at
V c2
Then
ANALYSIS GUIDE.
reset
criteria,
resistance
Be able
and with
PROBLEMS
2.
How many
How
stable states
were there
in
when the
Explain
how the
126
basic
1.
to
resis
MULTI VIBRATOR
experiment
INTRODUCTION.
We
will also
In this
operation the
ON
a transistor
OFF
is
transistor
is
trig
trig
normally
OFF
less
transistor
= Q B + Q BS
(15.3)
than
ON.
urated transistor.
The trigger circuit must furnish a sufficient amount of power to dependably turn
the transistor.
off
gered
turn
will
experiment we
If
the transistor
is
not
for switching.
saturated,
be supplied
sat
time required
is
capac
itively
can be approximated by
If
size
This reduction
used.
(15.1)
that
may
Wn
also be approx
QB
v trig
(15.4)
(15.5)
or
(15.2)
OB
If
is
'mm
(0.159) h FE
is
then
imated.
OFF ~
capacitor value
Q =V trig C
in
is
'mm
required, then a
Q BS
V trig
(Saturated Case)
(15.6)
Emitter triggering
is
the
name
applied to
and
is
used
saturation,
is
in
circuit.
127
EXPERIMENT 01 1 1 1
TRIGGER CIRCUITS
Fig. 151
pulse
is
is
Emitter Triggering
very
at their
should
all
trigger
ON
constants and
constants
in
PNP
transistors
is
constructed using
and positive
used.
applied.
be
ELECTRONICS/DIGITAL
OFF
Let
us
now
to a
which
common
is
Schmitt
computer
in
The
trigger.
circuitry, the
trigger are:
is
as for
(1)
To
(2)
To
rectangular waveforms
signal.
quency.
Consequently,
multivibrators
Figure
are
152
is
is
a basic
its
Schmitt
trigger
associated waveforms.
However, the
The
is
will
=
R L1 = R L2 R B1 = R B2 R
B3 R B4
;
remain
until
T 2 ON
input
designed so
and
When
this signal
(15.7)
725
T.j
OFF
of pre
signal
= C
2
an
is
is
applied
is
applied
EXPERIMENT 01 1 1 1
ELECTRONICS/DIGITAL
TRIGGER CIRCUITS
10V
Fig.
Fig.
stable
state
opposite
152
153
will
polarity
and
sufficiently
large
is
We
values
can
for
following
transistors
determine
the
Schmitt
process.
The
value
change state
circuit
trigger
stable state of
at
which the
component
using
Ej,
circuit
(T 2
must
ON)
<
flip.
15 8 >

and
the
T2
i,
129
min
V BE, min
(Tj)
+ V,
V RE,Q
(15.9)
ELECTRONICS/DIGITAL
TRIGGER CIRCUITS
EXPERIMENT 01 1 1 1
2V and
Vg^ q
transistor
= 0.2 V
This implies that
We
can
V B E,
(T
for
solve
VR
q = 1.8V
p_
V RB2
we know
if
be computed
VRB2,Q =
2
1V
'C2,
ON
'RE,
_ h
FE
_I C2,
(15.10)
0" 4
1
of the
ON
'b2,
(15.13)
ON
B2,
(15
ON
4)
V RE, Q
(15.15)
amps,
R_2
then
hp^
known.
is
RE,
we
the
Therefore,
Therefore,
If
if
and
=  3V
ON)
may
Rp_
VrB2 Q
'
B2"l bleeder
may
V RL2
= 21 kfl
be determined by
V CC
V CE,
(15.11)
(T 2
ON)
V RE,
q]
V RL2
l
and
R bl + r Ll
By choosing
V CCVr B 2,Q
'bleeder
value of Rjj.
'b2,
L2"i C2, ON
=
(1512)
V CC "[ V CE,
ON
'C2,
we may compute
With this
the circuit
Rg.
ON) + V RE, q]
(T 2
ON
in
in
figure 152
is
values,
MATERIALS
1
Oscilloscope
2 Transistors type
2N 305
1
(15ft to 10 megft)
or equivalent
2 Transistor sockets
Function generator
DC
2 k2 potentiometer
Breadboard
transistor
PROCEDURE
1.
Use
2.
a collector voltage of
Apply
in
Vqq
a sinusoidal input of
figure 154 using your computed values of R_ 2 and Rg= 10V. Record your values on the diagram.
circuit.
130
trigger the
TRIGGER CIRCUITS
EXPERIMENT 011 1 1
Fig.
3.
When
the input
154
triggering,
is
ELECTRONICS/DIGITAL
Slowly increase the input frequency to 10,000 Hz and observe the output waveform.
5.
resistor.
it
ANALYSIS GUIDE.
In
Schmitt
Input
+++ till
""
I
limitations.
trigger circuit.
Output
II
lilt
l)
ll
Fig.
155
H+4
EXPERIMENT 01 11 1
ELECTRONICS/DIGITAL
TRIGGER CIRCUITS
Output
Output
MM MM MM MM* MM MM
Fig.
155
HH H++.
PROBLEMS
1.
In step
3 of the procedure, was the frequency out onehalf the input frequency?
Explain.
2.
What
3.
132
"
'""
INTEGRATED
10000
CAE
CIRCUIT
FLIP FLOPS
INTRODUCTION. Computers
computations.
how
consider
will
In this
is
component
flipflop
circuit.
DISCUSSION.
its
by turning
calculations
OFF.
types
of
counters,
circuits,
including
shift
in
many
registers,
These
circuits
The
Counting
design.
and
ers,
circuits
of multivibrators fed
strings
are
made up of
by
gates, invert
routed
triggers.
devices (card
storage)
by these buildingblock
circuits.
Each integrated
blocks were
same
the
vacuum
be
to
effort
tubes.
The
idea
requirements for
was
and
machine.
directed
of the
AND
several
stable
gates
and some
multivibrators).
representation appears
may
contain
flipflop
typical
(bi
schematic
in figure 161.
This
is
many
this
symbol
same
Actually,
circuit.
representation
the logic
usually the
is
useful.
is
most
drawn
ation
circuit.
It
is
circuit operates as
With the advent of the transistor, designers were able to greatly decrease the size,
weight,
given
multivibrators,
The
etc.
size reduction
given
area
flipflop.
The
is
commonly
is
is
dependent on the
The
called
bistable multivibrator
circuit
computer
in
some of
carries
used
of
circuit
can
ing
integrated
We do know
fast switch
ure
in saturation.
stable multivibrator.
133
is
is in
Figbi
EXPERIMENT
10000
AC FLIPFLOPS
ELECTRONICS/DIGITAL
EXPERIMENT 10000
ELECTRONICS/DIGITAL
AC.
FLIPFLOPS
'CC
0 0 0 0 0
Ly rjLL T d
J
KEY
'
O 0 0 0
GND
CP
762
F/y.
Aoflr/'c
Y1
'L2
WAr
OUT
nouT2
3r
'C2
'C1
GNDQ
O GND
7 6
F/fli
If
then
Vg
is
1
in
saturation and
Q2
is
,4
Bistable Multivibrator
C3
at cutoff,
are
sition
135
Capacitor C
2
constant during the tran
speedup capacitors.
serves to keep
from one
VE
EXPERIMENT 10000
ELECTRONICS/DIGITAL
FLIPFLOPS
I.C.
Ov cc
O GND
When
Ql
a trigger pulse
is
164
Fig.
Any
applied so that
is
Q2
cutoff and
these
^C1
Vg.
remains
remains
conditions,
^CC' ^C2
Another
in saturation.
^E'
anc
^B1
'
added.
input
ess tnan
other
'
trigger pulse
or
less
logic
are
will
The
first
input
multiple
directly
a logic circuit
is
into
for a
figure 165.
NPN
The
or Q.
resetset flipflop
The
gates.
first is
through
is
becomes
flipflop
Under
unchanged,
'
basic
when
flipflop
clock input
logic symbol
illustrated
is
is
labeled
in
usually present
the second
frequency.
is
general circuit
is
is
The operation
same as that
essentially the
In
An
sistor terminals.
is,
the
ON
and
to
urating type
go
is
slow operation
many
into
NPN
flipflop, neg
when the
is
flipflop
is
in
initial
condition.
or
may
further classify
flip
may
saturation.
The
makes
output.
in its
times
allowed
161
When
OFF
We may
not be equal.
in figure
may be
astable flipflop
symmetrical or nonsymmetrical
That
labeled Cp.
of this circuit
Another
first.
it
less
desirable
is
to
sat
T2
0.
Qi
is
desired, the
will flip
it
from
set of
its
in
practical applications.
136
will
flip
it
EXPERIMENT 10000
ELECTRONICS/DIGITAL
OUT
(Q)
IN (ONE)
SET (ONE)
OUT(Q)
LOGIC
RESET (ZERO)
1&5
Fig.
Before
we go
further
it
is
Logic Symbol
worthwhile to
the
to
vious
casual
Unlike basic
and
When
is
is
may
open
actually
in
of a millisecond. Therefore,
circuits,
integrated
mechanical switch
bounce
only the set
(ZERO)
triggering circuit
observer.
DTL
in a fraction
due to the
IN
can be
of the
reset
triggered
which
circuits
(ZERO)
times
FLIPFLOPS
(ONE)
LOGIC
AC.
and
close
is
circuit
closed,
(bounce)
it
several
MATERIALS
2 Integrated circuits type
2
1
SN 15845
or equivalent
sockets
DC power
Oscilloscope
DPDT
switch
supply (040V)
PROCEDURE
1.
in figures
2.
Using figure 162 as a guide, hook up the power supply to provide Vqq.
Do
3.
Vqq
= 5V.
Connect the
DPDT
when
desired.
137
OV = ground may be
applied to
EXPERIMENT 10000
I.C.
ELECTRONICS/DIGITAL
FLIPFLOPS
G)G)G)G)G)G)G)
KEY
Fig.
4.
When you
The IC Socket
166
and the polarity of the Vqq are right, turn on the power
supply and record the output of this "triggering circuit" when a low input is applied to
are sure the circuit
which
will
logic.
we can examine
We now
have
cir
is
The
neutral position).
V cc
6.
change
7.
triggering circuit
common ground
and
= 5V.
it
Connect
If
is in
the
state
and Q, the outputs of the IC (not the "trig(high state at 5V) use the "triggering circuit" to
to the 0 state.
a
"high"
level
input to
Sj
and
"low"
level
input to
C^ Now,
using the
"triggering circuit", apply a pulse to the clock pulse input of the IC and observe
and Q.
8.
Reverse the inputs of step 7 and apply another clock pulse while observing the outputs.
9.
Fill in
0.
Repeat steps
6,
11.
Short inputs
S
2.
13.
as
much
of the RS
Mode Truth
2 and C1 to
C 2 and
repeat steps
1 1
7,
8 and
to 6.
9.
The
IC
is
now in
Figure 167.
138
EXPERIMENT 10000
ELECTRONICS/DIGITAL
RS
Outputs
Inputs
c2
c1
s2
S1
FLIPFLOPS
I.C.
Q
t
bit
time before
clock pulse
bit
time after
J
clock pulse
= no input, terminal
left floating
Indeterminate
Outputs
Inputs
Si
Cl
Outputs
Inputs
s1
Fig.
167
PROBLEMS
1.
What
2.
3.
Would
it
between PNP
logic
and
Cp
NPN
logic?
139
experiment
INTRODUCTION.
circuits.
In this
BLOCKING OSCILLATORS
10001
experiment we
We
will
generator usually
of blocking oscillators.
DISCUSSION. A blocking
the
itself
polarity
These
off after a
indicate connection
When
the base.
is
monostable.
The
may be
circuit.
either astable or
astable circuit
is
lator
is
development of
a favorite for
the
will
the circuit
180
will
induce a voltage
will
logic
energized,
in
in
the
base winding
Forward
oscil
is first
leakage.
of the transformer.
used as a
tooth waves.
that a
In a block
Blocking oscillators
so
of the
bias
increase
Iq,
baseemitter junction
Vgg
times with
some more.
tinue until a
is
pulses.
Very
fast rise
and
fall
reached.
into saturation.
mon emitter
will
field
That
is,
momentarily there
be no further change
in
the magnetic
O v cc
TR
Fig.
171
Common
140
EXPERIMENT
ELECTRONICS/DIGITAL
BLOCKING OSCILLATORS
10001
*3
*1
w
I_l
o
>
111
CO
>
TIME
'CC
TIME
Fig.
the
sistor
in
will
Therefore,
drop
in
the flux at
itself.
no
longer
collector
be
forward
current
lector
biased.
EMF
in
col
phase relationship.
to
The
circuits
This
drops.
in
then repeats
no voltage will be
the base winding; and the tranwinding,
collector
induced
172
With no change
transformer.
These
cutoff,
is
driven into
is
much
cutoff.
is
the
transistor
stops,
was conducting,
was charged.
C
When
ing
base
The
maintain
current
Vqq
to
and
the'
EMF
(Iq)
(Vq^)
is
is
attempt
The
the sum of
flow.
cycle
141
may
EXPERIMENT
10001
ELECTRONICS/DIGITAL
O Ycc
CLAMP
Fig.
173
lector
There
junction.
col
one other
is
across
The
circuit.
The
negative excursions.
is
it
shown
in
figure
third
winding
is
74.
and
there
usually
to
Diode
figure 173.
shown in
a voltage clamp which
collector from going
the
Dj is
Diode D2
placed
winding to
transformer
the
field.
quickly
transistor
When
is
while
the
the transistor
reverse biased
D2 becomes forward
D2
in
the previous
transformer core or
cir
tran
cutoff.
and
is
Cj,
bias
biased
and
sistor
cutoff.
conducting, diode
At the
circuit.
is
in
base config
is
V^^
common
also be
tion.
is
requires
circuit
Voltage
circuit
The
is
This circuit
may
in
at
zero.
Often
a third
winding
is
provided on the
circuit
in
is
its
flexibility
this
of design.
source
V^^
will
type
The
transformer
142
bias
new
cycle.
prevents
transistor
the
breakdown.
EXPERIMENT
ELECTRONICS/DIGITAL
10001
BLOCKING OSCILLATORS
OUTPUT
CLAMP
Fig.
174
A Common
175
Fig.
Common
of
base and
Common
both
the
source
of
the
trigger
conducts.
creases
Regenerative feedback
the forward
bias
on the
the astable.
For
reverse
bias
core saturates.
monostable types,
sistor
mono
application
is
applied.
pulse,
Then the
transformer
transistor will
drop
in
Upon
applied.
the tran
143
in
transistor
is
EXPERIMENT
1000 1
ELECTRONICS/DIGITAL
Ov cc
_TL
'CLAMP
Fig.
176
monostable
stable
blocking
the
state,
Vgg.
Common
common
emitter
For the
oscillator.
voltage
basetoemitter
The
instant of cutoff
collector
Just as
in
V Reverse
The base
'1
rate
is
when
No
voltage
With the
winding.
is
induced
in
the base
collapse,
and
V BB
maximum
The
trigger
of collector current,
fall
this
induces an
is
is
low,
opposite
sensitivity
the
Vgg
trigger
Vgg
If
point
so
great
where the
to
discharges through
Cj
(17.1)
(
bias returns to
a safe value
v BB + v
Bias
voltage.
given by
drops.
transistor at the
is
Vq^
is
on the
will
on
is
on noise alone.
make
the circuit
is
reached
that the
Increasing
less
likely to
induced into
winding
oscillator
When
the
transistor
is
in
the
a forward bias
active
increase
Vgg. The
in
corresponding
until
Cj.
144
An
increase
in
emitter
current
EXPERIMENT
ELECTRONICS/DIGITAL
10001
TRIGGER
JL
T~
'EE
Fig.
177
saturates,
R^Cj
is
The dropping
induces an
EMF
the
drives
ductance
in
magnetic
cuit are
not so
and the
common
emitter circuit.
negative,
Ci then discharges
and the transformer secondary.
is,
through
source
R
EMF)
cutoff.
are
(Cj
in
(L).
emitter
collector current
The decrease
primary.
field
no feedback to the
dropping.
the
Common
CC
in
fact,
critical
paralleled
The same
Vgg.
this cir
sensitivity
bias
and
circuit
The
were
as
for
the
common
emitter
circuit.
MATERIALS
2N 1 304 or equivalent
sheets, 2N 1 304
Transistor type
Set of data
DC power supplies
Oscilloscope
(15fi to 10 megft)
drop)
(040V)
Function generator
Breadboard
PROCEDURE
1.
2.
Assemble a
common
in figure 171.
3.
4.
Vqq
Rj
V cl_.
Be sure to
some adjustment.
Start high.
at
Rj
and
C
andCj.
145
will
require
EXPERIMENT
5.
BLOCKING OSCILLATORS
10001
Observe the
Vg^ waveform on
values, frequency,
6.
7.
rise
Observe the
waveform on the
and
time on
rise
Record
the oscilloscope.
its
values, frequency,
Record
oscilloscope.
a sketch of the
its
waveform.
8.
and the
ELECTRONICS/DIGITAL
in
one step above and one step below the present value and
the Vgg and Vq^ waveforms.
common
record
and
trigger pulse
10.
Mqq
bias (V^
E voltage to prevent transistor breakdown (see the data
compatible with values of Rj and Ci for oscillation with a 3V input
)
(low frequency).
rise
Rj'
and Cy.
time on
Record the
maximum
voltage,
minimum
a sketch of the
voltage,
collector to
ground.
11.
resulting change.
12.
effect.
ANALYSIS GUIDE.
oscillator.
The
well as the effects of varying the amplitude and frequency of the input pulses.
PROBLEMS
1.
A common
3.
What
is
is
50V. What
is
Vqq
of 10V.
The
voltage induced
Vq^?
Vg B
in a
'common
emitter blocking
oscillator?
4.
List the
146
common
trigger rate of a
common
EXPERIMENT
ELECTRONICS/DIGITAL
10001
BLOCKING OSCILLATORS
R1
C1
MM
Common
Effects of
MM MM MM MM MM MM MM MM
il
Emitter
Vg^
varying
R,
Effects of
varying
MM MM MM MM MM MM MM MM
Cl
Common
Emitter
Vq^
R 1
Mil
Common
Effect of
1
1
Emitter
MM
Mil"
Vqq
amplitude
Fig. 178
147
II
Mil
II
MM
II
experiment
10010
INTRODUCTION. As we
is
TWODIODE STORAGE
COUNTER
generator.
We
will
DISCUSSION.
select
name
This
Staircase generator
is
on
effect of pulses
predetermined count
its
level.
The
rate
let's
at
which
charge
will
C
is
RC
determined by the
time constant of C
1
and the sum of the diode resistance plus the
generator
(around
resistance
many
generators).
very
small
duration,
it
When
compared
the V
to
500
kft
for
time constant
this
the
input
is
pulse
value will
charge to the
(V^j = E).
consider
While
C is
charging,
D2
is
will
will
not conduct
remain
zero.
Cj is left with a
= E across D1 and in
Because the polarity
past,
charged voltage of
cannot conduct. C
1
wants to discharge, however, and does so
through the source, D and into C
2
2 C 2 will
charge to equal the voltage at C1 (V
=
C1
Ci
is
zero as
is
The
initial
the charge on
C^ to charge through
first
C2
charge on
When we
one
V
C2
1
series
is
D 2 and
with
it
will
cause
V C2>
Dj.
"1
f+
l\
nr
~c
VOLTAGE
OPERATED
DISCHARGE
E0
SWITCH
>
O
Fig. 181
182
Fig.
EXPERIMENT 10010
ELECTRONICS/DIGITAL
To complete
time
stabilize.
ordinarily
is
change
the
in
C2
voltage across
will
quite
be
charge leaves
be small
original
its
state
compared to Vqj.
During
of
the
next
more charge
first
input
pulse
slightly
first
pulse.
will
will
The output,
as
shown
Among them
are blocking
cause
Let's
in figure
examine what
plest circuit
purpose.
pulse, the
be
will
bulbs.
Because C2 has
in
this
A number
oscillators,
This stores
a little
less
input
pulse,
of
time
the
182,
staircase generator
put
amplitude asymptotically.
149
is
staircase action.
183.
rent) at
is shown in
The bulb fires (conducts curabout 70V. The input pulse must be
neon bulb
figure
is
approximately
equal
maximum
to
the
out
pulse
EXPERIMENT 10010
A Neon Staircase
183
Fig.
Generator
amplitude.
maximum
will give
stage
on the
firing
trailing
scribed
circuit
with the
is
is
more
about
ten.
Because
of
in
of steps, counters
trigger point
number of
practical
of storage
decrease
this
exactly as de
70V
ELECTRONICS/DIGITAL
may be cascaded
to obtain
steps.
We
level at Q,2
and
The number of
may
be increased by
in
Decreasing
capacity of
the
increasing
steps
circuit
the mathematics.
The equivalent
when diode D2
conducting,
the capacity of
circuit state
of
steps.
comparator (bulb)
practical
because
Q>2
value
the
is
soon
reliability
reached,
of
voltage across
A maximum
responds.
the
that
noise
and
across
Fig.
become
fluctuations
184
j),
however,
level
small
as
we have
vn
closer
The
C2
is
in
vn
<
V V n
>
cTTc:
so
the
where n
Normally, the
is
the
number
of the step.
150
(18.1)
proportional to
in
Vn
EXPERIMENT 10010
ELECTRONICS/DIGITAL
Vn
V [A(V n 
V, then
it
will
V)]
can
be calculated using
vary
Thus,
Vn
= Ae an
V n V
is
V(VV
(18.9)
l)5T
(18.2)
The
step
total
and the n +
step
is
components
V n+1V n
involved.
M
(v
v n v n+1
(V n V)
+ C2
D =
f_J_^ Aean
c i + c2
(18.10)
An example might
we have
a(n +
c7Tc 2
(18.3)
Ae
184 )
mv
C2
is
9 times
V
Suppose that
help.
larger
than
My = (110
10) =
100V
which renders
but
a =
n
c
C2
Tn
+c
2
(18.5)
C 2 =9C 1
or
C2
c7Tc^
9
= 10"
or
So
V n V
A laTrc1
2
'
= 10V
(100)
(18.11)
So
The
Vn
c2
+ A[ ^
)n
first
(18.7)
100
Now,
and
is
for n = 0,
Vn
The tenth
1:
^)(to")
(
10=1v
(18 12)

defined as
= VjV
pulses
(18.8)
757
which are
all
the same.
This
is
true
EXPERIMENT 10010
because the step
determined
by
charge
leak
will
(and dependability)
level
the
on
charge
off through
is
is
This
the
load
ELECTRONICS/DIGITAL
D2 and
no
used as a discharge
is
charging
Cj
C2
will
first
One
positive
through
difference
switch.
binary
this
is
will
also be
reversed.
counters.
MATERIALS
2 Capacitor substitution boxes
Oscilloscope
Breadboard
(15010
meg)
4 Diodes type
N34
or equivalent
Function generator
PROCEDURE
one shown
1.
Connect
2.
3.
4.
Record the number of steps and sketch the waveform, (each cycle)
5.
6.
Calculate the amplitude of each step using the circuit values measured
7.
in
figure 183.
resistor,
at a rate of
results
on your sketch.
in
equation
18.9.
its values.
Cj
boxes.
9.
7.
10.
11.
12.
13.
Assemble
14.
fig.
Record the
effect.
185).
first
and feed
it
staircase.
152
ELECTRONICS/DIGITAL
Fig.
ANALYSIS GUIDE.
In
EXPERIMENT 10010
185
two waveforms
in step
comment on
operation. Discuss how
Mil
Mil
MM
MM MM MM MM
Fig.
186
\'
MM
MM MM
The Results
153
Mil
MM
III!
the
the
EXPERIMENT 10010
lilt
II
II
MM
MM
It
ttir
III!
Mil
MM MM
MM
il
till
Fig.
186
II
'
1^
MM
till
ELECTRONICS/DIGITAL
Mil
II
M MM MM
till
Mil Ml)
II
MM
MM
il
EXPERIMENT 10010
ELECTRONICS/DIGITAL
MM MM
Mil
MM
llll
MM
II II
llll
MM
lilt
mi
Mil] JIM
llll
till
F/flr.
II
MM MM
till
MM
PROBLEMS
1.
five,
It is
and four
steps, respectively.
How many
four?
2.
3.
C1 =
0.01/zF
C2 =
0.02/iF
AV C2 for step
A.
What
B.
Step six?
It is
is
one?
desired to have a storage counter that will trigger on every twelve input pulses.
may
use.
Any type
be used.
755
experiment
INTRODUCTION.
multivibrator,
11
BASIC COUNTERS
1 1 I I
in
The
bistable
especially useful
is
logical
DISCUSSION. The
two
cuit has
In this
where
This makes
es
is
is
stable states.
it
pecially useful
system.
The
saturated types
build.
They
in
have
less susceptibility
power supplies
more reliable and
causes
the
to noise.
switch
action
to
be
where N
the
is still
transistor while
of 15.
is
region.
useful in
quire
it
highspeed
switch
action
2N 
(19.2)
Saturation,
a fourflipflop
saturated
predic
is
Maximum count =
tion
counted.
require fewer
and,
however,
number of bistables.
the decimal number to be
the
and
in
a bi
and
first
Thus,
maximum
The input
can be fed to
rapid
flipflops.
binary counter.
the
number of
all
calculations.
powers of two
in
set
(flipflops) represent
the binary
number
system.
more complicated
circuitry.
in
digital
storage
FF 0 =
computers.
delay time
1
FFj = 2
re
FF 2 = 2 2
The
FF 3 = 2 3
in
the counter
is
3
very easy to determine that 2 + 2 1 + 2
= 15.
This can be
When
calculated using
from 0 to
the
1,
first
to switch FF.
0,
156
then FF.
When FFq
is
will
inappropriate
switches from
which
to
will
EXPERIMENT
ELECTRONICS/DIGITAL
ii
0
m
C
COUNT INO
BASIC COUNTERS
FF
FFo
FF,
1001
m
R
Tf
IT
RESET O
Fig. 191
switch
FFq
This pulse
FF
1.
tive
it
will
not switch
FF2
with
NPN
transistors)
will
pulse.
like
from 0 to
it
coupled to the
By proper
arrange
ment
because,
is
J
which
polarity,
receives
its
will
When two
FFq
back to
FF
original state.
first
As
go to cutoff,
the transistor
So we
see, in
of flipflops can
sired
like
lector.
decimalbinary conversion.
It
made
the
like
true
is
first
pulse
down
the
chain.
to
We
What happens
multivibrator
is
in
electronically?
When
will
the
to
V cC with
the
first
positive pulses,
transistor
is
in saturation.
Application of the
change
in
At
that
PNP
transistors
and
the
and
switch (0 to
1),
and
it
switches from
is
this will
happen
to 0.
at the
collector
in
in
near 0.
The counter
posi
157
is
15th
EXPERIMENT
pulse,
and
all
pulse.
The
pears
in figure
revealing
1001
BASIC COUNTERS
by the 16th
therefore, the
This table
193.
the actual
ELECTRONICS/DIGITAL
useful in
is
FF
state of each
the binary
FF corresponds
and,
10
11
number
12
13
14
15
16
UJJJJJJJJJJJXLL
^WLjWLTLrir:
ov
Fig.
192
10
11
12
13
14
15
16
FF 1
FF 2
FF 3
Fig.
193
Count
(or pulse)
FF
158
to
EXPERIMENT
ELECTRONICS/DIGITAL
1001
BASIC COUNTERS
Ov,
OUTPUT
Two
Fig. 194
When
Probably the most important consideration for designing a counter after choosing the
FFs is the manner in which they are to be
bistable pair with diode steering
The diodes
and base
tive pulses,
and the
this,
both
state.
is
To
them
When
a reset pulse
is
Q2 and Q 4
Q2
by D 2 and
,
go to FFj
Q3
or
This
Q3
will
diode (D 3 and D 4 )
quently, this bistable does not change
to near 0
is
at the base of
When Q 4
cuts off,
its
base.
Q 4 will cause
Q 3 must go to
it
to
sat
uration.
output.
state.
The
out through
pability
is
count.
its state.
755
it
will
remain at
all
first
the
is
bi
carried
maximum
all
count beyond
The
1.
This
11.
to 0 by the
Conse
FFq to
now becomes
nary count
not
Q 4 because of the
steering circuits.
pulse).
cause
will
at the col
The
will con
which
The output
A count pulse is
Q 2 will cut off,
level.
its
applied to
positive
cut off.
off.
does change
it
is
to posi
do
(a
trig
goes to saturation.
lector of
coupled.
gering.
FF Q
Q2
ca
are returned
its
maximum
EXPERIMENT
Fig.
A common
ling
BASIC COUNTERS
1001 1
195
Binary with
There
is
195.
ELECTRONICS/DIGITAL
still
shown
in figure
first
in
is
to the
FF
ON
AND
will shift
off.
pulse
When
is
desired,
it
is
applied, the
are 1s
(if
AND
for
rating type.
proceeds as
Collector triggering
is
often used
gates clarification).
in
creased speed
Clamping
is
Any
shown
in figure 196.
AND
to switch
in
is
counter
its
change.
AND
gate,
must be
in
AND
The
is
normally only
will
160
its
delay
AND
on
Such an arrangement
The
in
before the
gates to
sequence.
is
The counting
The in
lar
The FF
few microseconds,
still
EXPERIMENT
ELECTRONICS/DIGITAL
t
0
FF 0
R
t
0
FF
FF
C:
1001 1
R
i
F =3
(:
BASIC COUNTERS
<
RESET IN
COUNT
IN
F/g.
196
Gated Binary
FFs
(All
in
JK Mode)
MATERIALS
4 Integrated
1
flip flops,
type
SN1584N
or equivalent
1
DC power supply (0 40V)
4 IC sockets appropriate for the ICs

Oscilloscope
Function generator
1
1
DPDT
switch
SPST momentarilyclosed
switch
PROCEDURE
1.
maximum count
of seven.
Show
all
of your
work.
2.
Draw
for a
maximum count
Show your
in
the JK
mode
(SPST) and supply voltages. Have the instructor check the drawing before proceeding.
3.
Remember, these
in
0 0 0 0 0 0 0
O 0 0 0
Fig.
197
The IC Socket
161
EXPERIMENT
4.
1001 1
Connect
BASIC COUNTERS
ELECTRONICS/DIGITAL
be applied to the clock pulse terminal of FFq. The counting circuit and triggering
must have a common ground and Vqq = 5V.
5.
circuit
7.
Apply
8.
9.
Now
Vqq
use the "triggering circuit" to apply pulses to the binary counter and complete the
data table.
10.
if
is
is
a state other
in
than 000.
1 1
triggering circuit
circuit.
12.
Now
connect the function generator (pulse output) with the amplitude off to the clock
pulse of FFq.
13.
set to
Vqq
= 5V.
generator so
that a pulse train of about 7 positive, 41/2V pulses being applied to the clock pulse input
of
FFq can
in
14.
Now make
in
15.
16.
For your
own
is
multivibrator
the system to
work
the output of
momentarily closed.
ANALYSIS GUIDE.
FFq and
when
Do not exceed
in
amplitude
Also discuss
properly.
162
ELECTRONICS/DIGITAL
Fig.
198
163
EXPERIMENT
1001
BASIC COUNTERS
ELECTRONICS/DIGITAL
Clock
Pulse
FF,
FF
FF
Time
= 0
Counting Data
Decimal
Equivalent
0
1
CP
FF 2
FF 1
FF
4
5
6
7
PROBLEMS
1
2.
3.
4.
What type
of pulse triggers the FFs used (negative going or positive going)? Explain.
164
experiment
INTRODUCTION. Counting
applications. Many different
a
computing system.
the several
ways
DISCUSSION.
the first
is
is
which
in
of
bers to
will
examine
other logic
in
This circuit
a ring counter.
output of
state;
last
last
is
one of
used
as
and places
back to one.
it
in
it
FF
the one
is
when
indicated
we
the
a binary counter.
state.
first bistable
returns to one.
Before
reaches the
of the register
scale
The
binary
numdecoding
makes
a "ring"
decimal easy. When the ring counter is
from
bistable
first
be
other
all
will
can
count pulse
state.
arrangement
a series of
etc.
decimal readout
use
is
the
"1"
time is allowed in the
"0" state.
bistables are in the
This
computers and
in
In a ring counter,
first.
experiment we
the third,
binary
important operation
a very
ring counter
counters
binary
to
in
In this
is
RING COUNTER
10100
let
us examine
make
this counter.
is
to decimal zero
state; all
KEY
number
reset,
is
the
As you
to be
omitted.
is
FF correspond
turned on to the
16
puts,
states.
1Q
1Q
GND
2K
2Q
2Q
15
14
13
12
11
10
CLEAR
PRESET
PRESET
CLEAR
K
CLOCK K
Fig.
20
1J
in
V CC
CLOCK
2J
opposite
EXPERIMENT
10100
RING COUNTER
ELECTRONICS/DIGITAL
flipflop)
*n
Qn
t
t
clear
the
logic
20
The
independently of
Fig.
The
clock,
and
may be
operation
The
follows:
This
system.
is
of
counter
the
move
first
is
to
is
as
reset the
done by momentarily
closing
The
The
201.
in figure
terminal.
FF5
is
of
the
ring
flops, so
of 5
if
to
be
used
in
first flipflop is
count pulse
first
devices
it
will
is
the
The
applied.
in
first pulse,
Kg of FFq
this
will
used to represent 0
Jo
1
is 1,
is
the
due
to
FFq
0, so
to 0 and remain
FF1
is
due to
from the 0
its
coupling to
state to the
count
sixth
initial
is
is
the
state.
pulse shifts
1.
In this
(preset) condition.
back
FFj
manner, the
pulse,
of FFq,
0 due to
to 0 and sets
At
there.
will remain
logical 0.
is
flip
is
all
feedback loop.
Now
the 0 state.
the
in
ready to count.
time of this
it
the
counter
them
experiment.
is
The
often
Figure
putting
system
is
This pulse
is
in the
it
state.
until
ring
The system
to
the
its
can be
166
RING COUNTER
EXPERIMENT 10100
ELECTRONICS/DIGITAL
PR.
ST.
FF
CLR.
PR.
ST.
FF 5
PR.
ST.
FF
CLR.
COUNT
INPUT
PR.
ST.
FF 3
Q CLR. K
RESET
Each
of
are
like
flipflop
about 50
flipflop
ns.
202
Fig.
This
is
the time
it
Tt
If
in
there
step.
the one
imum time
shown
is
minimum
each pulse
in figure
period
is
N X Tt
is
NTt
the time
system
takes the
make
fanout
limitation
of
the
Therefore, the
is
regard
ICs
to the
being used.
Any type
T^
point with
counter.
where
each
circuits
gating
is
in
applications
required.
transistor
The
binary device
may be
used as a
unijunction transistors,
167
EXPERIMENT
RING COUNTER
10100
ELECTRONICS/DIGITAL
o v cc
4e
V,
INPUT
O
203
Fig.
Ring Counter
SCR
ring counter in
counting pulse
at
SCR
voltage occurs
anode.
its
in
will
be
coupled
transmitted through
C2
its
maintenance
is
positive.
SCR.
S]
is
is
and
and turns
all
same
by
Vqc
The
is
S2
will
D2
to the gate of
in
the on
is
When S2
in
or gates
proper condition
for change.
S2 and
The diodes
first.
in
Vqq
is
which
as
first
voltage
much the
the JK FF counter.
off.
to
with
fluidic flipflops.
MATERIALS
1
DC power
supply (040V)
SN7476N
or equivalent
1
SN15845N
or equivalent
Inline IC sockets
SN15845N
(SN7476Ns have 16
Oscilloscope
Function generator
SPST
DPDT
switch
(centeroff) switch
pins;
has 14 pins)
PROCEDURE
Examine your
ICs.
SN15845N
168
set or
EXPERIMENT 10100
ELECTRONICS/DIGITAL
2.
RING COUNTER
Connect the output of your "triggering circuit" to the clock terminal of one of the other
ICs.
Use Vqc = 5V Experimentally determine the truth table for the ICFF. Record

3.
your
Now
Record the
0s,
states of
all
Vqc
shown
in figure
to be very sure
when
202.
it is
not over 5
volts.
is
tripped.
Use 1s and
levels.
5.
6.
7.
Disconnect the supply voltage and the "triggering circuit" from the counter.
8.
Connect the function generator (pulse output) to the counter so that +4.5 volt pulses
will
all
1, 2, 3, 4, 5,
if
is
circuit.
9.
may
10.
least
form of
11.
of
is
2 FFs.
FF.
if
is
being applied.
ANALYSIS GUIDE.
its
construction.
Truth Table
tp
Fig.
169
EXPERIMENT 10100
RING COUNTER
ELECTRONICS/DIGITAL
Reset
FF 0
FF1
FF 2
FF 3
FF 4
FF 5
Effect of reset
when count
MM!
< 5 was
MM
nil
Nil
mm'
MM MM HM
Mil
Mil' llll
lilt
Fig.
MM MM MM
M MM nil
170
HI
Mil
II
RING COUNTER
EXPERIMENT 10100
ELECTRONICS/DIGITAL
MM
HH
Mil
Fig.
MM'
II
lilt'
1111
mm'
MM
II
Mil' HH
Mil
MM
PROBLEMS
the scale of count for the circuit
1.
What
2.
From the
3.
What
is
4.
What
is
used
is
in
is
the
in figure
maximum
202?
maximum
the experiment?
171
experiment
INTRODUCTION. The
ing of binary
numbers.
number
It fill
10101
HIF T R E
GIS TER S
this
experiment
we
will
DISCUSSION. Data
is
in
few microseconds.
output
Therefore,
sively.
made up
most
shift
are
registers
figure 211.
lines are
The
sistor.
choosing the
The
condition.
series,
in
first
is
chosen
side to
put
is
andO
input
tran
After
the
is
go to the one
con
arbitrarily.
a flipflop
the
side
symbol for
The T or
trigger
in
The
next FF
circuit.
first
first
FF and
first
The
causes
down
are pieces
see,
is
every
first.
Many bits can be
way (depending on the number
of flipflops)
until
on command or
for
after
is
will
If
called
the binary
will
shift the
left
is,
number
in effect,
to the right
in effect, division
in
is
is
The
simply the
state of the
FF
at T.
1
To
comple
transistor,
ducting transistor
and compatible).
multiplication by two.
is,
ting
used to
in effect,
because the
is
is,
ment or
particular circuit of interest here
Symbol
and a pulse
some predetermined
length of time.
The term
FlipFlop
the information
21 1
Complementing
"bit"
stored in this
is
Fig.
shifted
new
the
and
Shifting
(all
In
else
remaining constant
network
by two. The
Let's
registers
172
EXPERIMENT
ELECTRONICS/DIGITAL
SHIFT REGISTERS
10101
CLOCK
PULSE
INPUT
OUTPUT
2" OUTPUT
212
Fig.
shows
ure 212
you
FFs
is
FF 0 (2)
cuits will
state
applications) the
is
logical 1,
0 volts =
is
trigger
counter.
There are 2
NPN
cir
counter.
It is
on
is
0001
0010
referred
up
to as an
be thought of as
by
where n = the number of the output
2 n+1
stage.
logical 0.
NPN
logic,
go from 0 to
1,
of the wrong
polarity.
Frequency =
with the
(21.1)
>n+1
1
)
The second
the FFq (2)
If
n pulses
complements (switches)
stage from 1 to 0. This time the switching is
stage
in the proper direction to cause the FF
pulse
input frequency
because the
slope
state
positive
will
FF
is,
corresponds to
defined as + volts =
stage to
is
the
FF would
Positive logic
That
in
is
1),
(binary 2)
With
pulse
pulse,
complemented.
is
(binary
output feeds
successive unit.
Mode
one corresponds to
pulse
pulses.
input clock
negativegoing
each
first
As
of these
OUTPUT
Fig
OUTPUT
IT
nary
n.
Then
if
n'
additional
numbers
are fed
n'
j
complement.
wrong to complement the FF2
to
Figure 213
carried out
count
is
shows how
one pulse
stage,
binary number.
is
will store as
etc.
at a time.
The binary
Two more
pulses
count to go to binary
Up
in this
addition.
173
binary 3 (11).
5 (101).
way
for
EXPERIMENT
10101
SHIFT REGISTERS
FF
ELECTRONICS/DIGITAL
FF 2
FF 1
FF 0
Output
Output
Input
Output
Output
Pulse No.
23
22
10
12
13
14
16/0
Fig.
213
FourStage
counting
down.
the difference
is
now
is
fre
It is
is
valid.
In this case
down
Fig
op
the pulse
feeds
side
Notice that
Each successive
Up Count
is
11
15
same
FF used
down count
of
174
consists
EXPERIMENT
ELECTRONICS/DIGITAL
10101
SHIFT REGISTERS
CLOCK
INPUT
6
Fig.
Four Stage
214
OUTPUT
Down Count
FF 3
FF 2
OUTPUT
Register (All
6
FFs
OUTPUT
in
OUTPUT
JK Mode)
Decimal
FF 1
2
OutDUt
Output
Output
Output
Output
Count
16 or U
lb
1 A
14
\6
4
5
Input
Pi cp imu.
Nn
rUloc
i I
o
2.
10
11
12
13
14
15
16/0
Fig.
215
175
0/16
EXPERIMENT
SHIFT REGISTERS
10101
ELECTRONICS/DIGITAL
INPUT
R
0
0
FF,
FF,
FF.
OUTPUT
OUTPUT
INPUT
SHIFT
(CLOCK) O"
INPUT
Fig.
216
methods with suitable coupling to allow shifting from one mode to the other.
By using
steering gates, the input
FF can be
controlled
ing to
binaries,
is
a circuit
Variations can be
flipflops.
one
one
bit at a
fc>e
As
it is
time (correspond
Each
shift
moves
made
on its left.
Figure 216 shows the circuit for
all
S and T
is
shifted serially,
data
Shift
accomplished by using
its
the
complement of the
a shift
INPUT
OUTPUT
f
OUTPUT
1
INPUT
SHIFT
PULSE
O
Fig.
217
176
is
EXPERIMENT
ELECTRONICS/DIGITAL
SHIFT REGISTERS
10101
Fig.
218
216 or 217.
is
shown
in either fig
which
all
is
You
and
used ex
Delay
The
lines are
through the
circuit,
count to ripple
changing one FF at a
time.
S and R inputs.
is
shift register
a multiplication broad
side shift.
will
practical
delay lines
one binary
make
is
mation
is
well as
0 and
but they
transferred before
stored.
1
The
to insure reliability.
circuits
As always,
set
new
and
infor
reset as
must remain
first
shift
pulse
gates.
One
is
gate operates
the
consistent.
The
two
first
OR
it
FF2. Through
AND
when
operation,
only those
AND
a shift pulse
gates with
is
ap
inputs
These gates
cuit
and
shift the
count. This
its
Again
we
is
beginner to understand.
it
comple
is
The
cir
in
terms
actual circuits
NAND
177
FF3
will
is
and
NOR
EXPERIMENT
SHIFT REGISTERS
10101
ELECTRONICS/DIGITAL
SHIFT PULSE
Fig.
As we have
of register
is
term implies
the
a
common
type
or shift register.
The
said the
serial
219
most
number of FFs
in
series,
the
all
the FFs.
When
to the first
FF where
it is
stored.
circuit
one
Several bits
may be
scale integrated
modules (MSI).
gram
stored
is
shown
is
Its logic
in figure
consumertype
and package
2110.
This unit
length of
medium
is
The
single
the
moved
common
Also very
chip.
ter.
diais
regis
R inputs of FF Q
The
Figure 2111
clock pulses
almost exclusively.
Whole
toward
clock pulses
registers are
The
later,
in
and
is
trend,
The clock
gate.
least
775
Nega
NOR
shift
fast as
18 MHz.
EXPERIMENT
ELECTRONICS/DIGITAL
10101
GND
12
13
14
SHIFT REGISTERS
CP
10
11
*5
R
CP
CP
CP
KEY
CP
S I
CP
CP
ri
CP
CP
'cc
Fig.
2110
CLOCK PULSES
nnnjimruuinJuT
2ND
[1ST
1
AB INPUT
Ji
h
1ST
Q OUTPUT
Fig.
2111
179
2ND
_TL
!
EXPERIMENT
SHIFT REGISTERS
10101
ELECTRONICS/DIGITAL
transistors.
cludes 4
of
35
gates.
The
total
power
is
55 %
dissipation
i
about 175
mW. The
gates.
in
MATERIALS
1
Oscilloscope
DC power
supply (0
40V)
type
SN7491AN
or equivalent
5 JK/RS
flipflop,
SN15845N
type
or equivalent
6 IC sockets
1
DPDT
VOMorFEM
Function generator
each type of IC
centeroff switch
PROCEDURE
1.
fan out.
2.
constructed by shorting either the set or reset terminal of one FF to ground through
the
3.
DPDT
switch. Use
V cC
= 5V.
Before applying power, place an accurate meter across the power supply and make
that
4.
Have the
5.
6i
lab instructor
sure
0.5 volt.
check your
circuit.
circuit.
register, especially
how many
register.
Draw
a sketch of the
output
to
trains
Then repeat
steps 3 through 6.
It is
still
on the
characteris
tics
of the shift register and IC application of the logic theory. Discuss each of the circuits
Was
Which was
easier to
180
used.
EXPERIMENT
eL ectronics/digital
MM
HM
Mil
II
MM
till
Mil] 'mi
in
lilt
Mil
MM
Mil' "mm
MM MM MM MM
Fig.
Mil'
2112
MM
II II
MM MM
10101
MM
SHIFT REGISTERS
Mil
MM
MM
MM MM MM' MM MM
The Results
181
EXPERIMENT
10101
SHIFT REGISTERS
nil HH
llll
llll
llll
1
1
III
ELECTRONICS/DIGITAL
r 'llll
1
1
MM
llll
Mil' llll
nil HH
llll
II
MM
llll
llll
mm' Mil
Fig.
2112
llll
\\
'mm
llll
llll
MM
llll
llll
llll
llll
Mil
II
MM MM'
MM MM
Mil
EXPERIMENT
ELECTRONICS/DIGITAL
10101
SHIFT REGISTERS
PROBLEMS
1.
A PNP
flipflop triggers
What
triggers a
What
is
on
NPN
flipflop?
2.
of the 2
output stage?
is
Show
a block diagram
183
and explain
fully.
the frequency
DIODE MA TRIX
experiment
INTRODUCTION.
the form of
Digital logic
level shifts
matrix
is
into
some
kind
a diode matrix.
is
In this
The
experiment we
will
examine how
relatively large.
been used
The
in dig
logic gates
in small step
As an example of
At
DECIMAL OUTPUT
BINARY OUTPUT
Consider a 64step,
000
diode
true.
011
100
false
110
101
variables.
(2")
111
<
INPUT
\y
0.
jy
>
>
yy
1
23^
+v ccFig.
22
>
y .y
.y ,y
this
010
001
first,
seem to be entirely
sixstage counter.
number considerably.
method.
is
gate
is
done.
CIR C UITS
or pulse trains.
of translational network.
this
10110
inputs
EXPERIMENT
ELECTRONICS/DIGITAL
are available.
at
and the
is
l
lines
1.
The low
These
(logical 0)
(decimal
The most
output.
scheme
line
5)
is
that
it
all
will
serious
produce a high
problem with
Looking
volts
of Diodes Required
222
back at the
in figure
221,
we
standard
diode
(22.1)
Fig.
this
requires
X N = Number
trick has
figure 222.
matrix
2N
384
101
requires
separate gates.
signals
still
1).
line
high (logical
101 10
185
EXPERIMENT
101 10
QQQQQQQQ
r
X
OUTPUT
DECIMAL
BINARY
INPUT 2^
INPUT
Y
INPUT
ELECTRONICS/DIGITAL
000
001
010
011
100
101
110
111
*
>
INPUT 2 1
2'
INPUT
<
2'
INPUT
VOLTS
Fig.
223
them would
zero.
and 2
straight matrix.
connections
for
Number
of Diodes
actuated.
(22.2)
line
is
activate the
is
method.
one
Let's
line
is
the
and decoding.
The
shift register
increases.
010
(figure 222).
clamps
network
0 and 01 activate
+ 2 2 + 2 3 + 24 + 2 5 + 2 6 or 126
diodes as compared to 384 for either a straight
increases,
translation
require 2 1
There
tree
matrix.
tree
diode
requires
2N =
practical
in a
we
much
four times as
suffice to
In
186
22
EXPERIMENT
ELECTRONICS/DIGITAL
16
output
mal
lines,
(which
is
101 10
input
AND/OR
each
decimal
gate (one
number
AND/OR
encoded or
be
to
gate for
decoded).
both
pFs
are
in
lines
This
and
When
outputs.
proper
sequence,
the binary
the
correct
in
both directions.
the
matrix will
either encode or
bit
to realize that
is
a multi
must be
numbers ending
for
all
right
in
most
bit, as
By
for the
kn
7,
9,
OR
gate.
is
the
The other
in
the same
kf2
its
VDC
1
3, 5,
output of a fiveinput
manner.
the
and
1,
the others.
bit positions
decode.
most
right
converter,
decimaltobinary
In
kn
0
O
O
2
kn
OGND
Fig.
224
EXPERIMENT
101 10
ELECTRONICS/DIGITAL
IIH
\i~<r
a9
i~<r
b?
i~~<^
t~<"
by
cs>
i~<r
c9
5V
r~<i~
d9
dO
h
CL
h
D
F/ff.
225
BinarytoDecimal Converter
188
EXPERIMENT
ELECTRONICS/DIGITAL
Just as
OR
in
101 10
this case, A, B, C, D,
ground potential by
bit position
is
All
nonenergized
in
construction of a
lines.
represented by
would be clamped to
Each binary
matrix.
in
the
check value
number of electromechanical or
any
fluid
flow devices.
lines,
MATERIALS
1 1
Diodes, type
SPDT
Oscilloscope
VOM
DC
Breadboard
N34 or
equivalent
normallyclosed switches
or
FEM
k2 resistors,
2W
PROCEDURE
1.
2.
3.
Record your
4.
With an oscilloscope or
5.
Using a
VOM
0 through
6.
in figure
circuit.
VOM
224.
level for
outputs of
and
0.
numbers
9.
type shown
in
ANALYSIS GUIDE.
work
with.
189
EXPERIMENT
Switch
That
101 10
ELECTRONICS/DIGITAL
23
is
Closed
Fig.
226
190
EXPERIMENT
ELECTRONICS/DIGITAL
101 10
PROBLEMS
1.
to reduce the
diode matrix provides 8 outputs. The treeing method is to be used
number of diodes in the matrix. The current flowing in each output line is 150 mA.
What is the current through the diode which is clamping the maximum number of
lines?
2.
Given
a twelvestage counter,
matrix?
What
is
the
number
what
using
the
be better?
3.
in place
of a diode matrix?
191
DISCUSSION.
in
It
design.
its
is
fer
Whether
this
inside
computer or spans
several miles,
transfer
designer can
used
entirely
distance of
Now we
eliminate the
among
failure
place
There are a
occur.
takes
D and
not
it is
of a
possibility
circuits have
Boolean expression of P
column
experiment
this
we
examine
will
development of a
circuit
occuring
in
which
the
in
which
check
way
occur
in
error
that an even
each
generated.
occur
If
such a
word,
is
generated
number of one
then
even
and_D =
ABCD
is
word we
will
is
A=B=C = 0
1.
listed
"Sum
the
in
Since the
literals
bits
know
Now
C D
it
is
of Products"
C were
A, B and
possible to write a
A, B,
an
C and D
terms
the
in
all
for which P =
by simply adding
transfer the B
in
This
I.
Boolean form)
(in
"Sum
Boolean
combinations of
of Products"
is
all
done
the
column.
From
this case,
ABCD
P =
fifteen.
To do
this
we
P=1,
In
will
this
in
present.
Let's
In
bits
parity
If
in a particular
is
of Products."
is
bit.
we must
in
"Sum
listed
column.
In
terms of the
errors.
gle errors
in
D.
In
C and
A, B,
literals
in a
illustrates
C D
it
words.
However,
expression.
192
P.
Therefore,
we make
this
use of the
EXPERIMENT
ELECTRONICS/DIGITAL
Input
MA
>
Binary
101
1 1
n
u
R
D
D
r
of
even
Equivalent
Decimal
Sum
Products
parity
THE
Equivalent 1
D C
WORDS
zero
one
ABCD
two
ABCD
three
four
five
six
seven
ABCD
eight
ABCD
nine
ten
eleven
twelve
thirteen
ABCD
fourteen
ABCD
fifteen
Fig.
Boolean identities
P =
in
23
ABCD
ABCD
the following:
ABCD
ABCD
ABCD
193
EXPERIMENT
We now
its
101
of P
and from
form,
reduced
1 1
shown
we
this,
in figure
ELECTRONICS/DIGITAL
When
in
can
232.
1s are
Those which
the
is
irrelevant.
the circuit
is
is
previously
trans
It
odd
be these four
will
somewhere
in
bit,
In
programmer
fact,
one "1"
bit,
Fig.
232
results.
same
would
line.
possible to use an
the transmission
INPUTS
the
if
by
operator.
or
to determine
prescribed
C
D
OUTPUTS
194
condis
EXPERIMENT
ELECTRONICS/DIGITAL
101
1 1
MATERIALS
1
Oscilloscope
DC power
supply (040V)
10 IC Sockets
10 Dual 4INPUT
SN15830N
NAND/NOR GATE,
type
or equivalent
PROCEDURE
Figure 232
1.
OR
gate.
is
composed of 2 EXCLUSIVEOR
NAND
gates,
implemented from
Have
gate circuits.
this
2.
circuits
it
is
operating
correctly.
3.
Use Vj n 1
truth table to verify that the circuit is working
(
properly.
ANALYSIS GUIDE.
In
the analysis of your results you should verify that the circuit performed
Discuss in your
error detection.
PROBLEMS
1.
2.
odd
3.
Drawa
circuit
4.
(a)
which
will
odd
change.
1.
Which would be
for the
(b)
in
231 using
in
error
if
error
if
(1)
00001
(6)
01111
(2)
01101
(7)
11111
(3)
11010
(8)
01000
(4)
01001
(9)
00010
(5)
00000
(10)
01010
755
2.
in
EXPERIMENT
101
1 1
ExclusiveOR Gate
NOT
Fig.
233
Gate
Gate Diagrams
196
ELECTRONICS/DIGITAL
ELECTRON ICS/DIGITAL
EXPERIMENT
AND
OR
Fig.
233
101
1 1
Gate
Gate
197
EXPERIMENT
10111
Truth Table
Fig.
234
198
ELECTRONICS/DIGITAL
experiment
INTRODUCTION TO DIGITAL
TEMPERATURE CONTROL
11000
INTRODUCTION. The
ment we
will
DISCUSSION.
which
may
Digital
of
the pulses.
signal
ble
tell
amplitude or position
the system
how
to
cycles
in
such a
way
is
Since this
quency
If
is
is
being used to
fre
oscillator.
determined
is
in
the
the pre
correct
CONTROLLED
DEVICE
FREQUENCY
VARIABLE
OSCILLATOR
CONTROLLER
COUNTER AND
ERROR MEASURING
DEVICE
CLOCK
oscillator
an indication of
24 1
a fixed
that
Fig.
is
re
oscillator.
frequency
the repeti
in
dant information
spond.
contain information
digital control.
Digital Control
199
System
EXPERIMENT
11000
ELECTRONICS/DIGITAL
V BB = 6V
Fig.
242
UJT
Oscillator
the error which would then produce the correct count, stopping the controller. This general description fits
in
age the
UJT
generating
circuit,
shown.
error sensing.
discharge through
ter
to this volt
the
emit
output voltage
f,
is
given
approximately by
In this
experiment we
will
be concerned
Figure 242
is
peak potential,
firing or
of the
The
UJT
is
where Rg
is
given by
R E = R 2 + R3
V p = 7?V BB
Since
where
t?
is
stant for
(a
varies
con
from
Vg B
is
is
be varied by temperature,
cally), this circuit
is
light or
mechani
in the
frequency
200
R3
oscillator.
EXPERIMENT
ELECTRON ICS/DIGITAL
1000
MATERIALS
2 Potentiometers, 10 k2, 2W, linear, or a
DC power
Oscilloscope
UJ
2N4891
Transistor, type
or equivalent
supply (0
40V)
PROCEDURE
1
2.
Connect the
circu
it
of figure 242.
Observe and record the waveshapes at the emitter and base one with
R^
set approxi
R^ (which
is
R2 + R3) shown
in
shown
5.
in
in
PPS
at the resistance
R E and
the graph.
WAVESHAPES
VF
(FIG. 242)
RE
1
Calculated Frequency
kfi
2kfi
4ki2
8kS2
10kJ2
12 kft
14kft
16 kft
18 kQ.
20kfi
Fig.
201
Measured Frequency
on
EXPERIMENT
11000
ANALYSIS GUIDE.
measured frequency
Explain
is
why
different
ELECTRONICS/DIGITAL
changing
value.
PROBLEMS
1.
resistance,
75 Hz.
2.
3.
Redraw the
resistive type)
4.
R3
ohms with
value of
If
value of
if
R3
if
a frequency of
Name two
as a photocell (photo
a frequency of
7.
R2
75 Hz was desired when the photo10k ohms? (Use information from problem 1.)
cell resistance is
5.
a desired
if
R3 were
is
in
10k ohms?
the previous question should increase so
ohms
to 5k ohms,
held constant at 5k
the out
ohms?
in
202
experiment
INTRODUCTION. An
experiment we
this
DISCUSSION.
used
will
electronic clock
examine
multivibrator
is
and as
a device to
chronizing multivibrator
very often
is
NOR
words
NOR
OR,
in
which the
output of
when input
a 3input
OR
circuit
Then
invert
is
1s.
to
is
high (a
1)
is
is
illustrates
the output
OR
the variables:
OR
B + C = Output of
+ B + C = Output of
OR
NOR
By Demorgan's Theorem we
a 1.
and change
the
all
ORs
to
ANDs and
vice versa
is
AX
B X C =
NOR
low
OR
Inverted
NOR
Output
Fig.
25 1
in
arriving at
a 1.
we
Another way of
is
This
invert them:
func
function.
the inputs
function
Remember
or input B or input
OR
function.
A+
OR
To do
be
NOT
logic blocks.
or vice versa.
verted
that the
OR
(a 0)
This syn
will
from
a clock
synchronize the
is
in
pulses,
tion
is
method of making
overall
the
///////
203
OR and NOR
Output
in
EXPERIMENT
100 1
00
252
The
shown
in
is
figure 252.
is
column of
output
AND
is
The
Function
figure
1s.
NOR
Output
operation.
NOR
Fig.
The
ELECTRONICS/DIGITAL
+ B + C = A'
B'
C = NOR
is
CONTROLLED
DEVICE
FREQUENCY
VARIABLE
OSCILLATOR
CONTROLLER
COUNTER AND
ERROR MEASURING
DEVICE
CLOCK
Fig.
253
Digital Control
204
System
function
is
shown
in
EXPERIMENT
ELECTRONICS/DIGITAL
The clock of
how
ble
Since this
oscillator.
is
the condition
of
This
is
time
is
You have
(freerunning)
may be
a fixed
number
oscilla
an indication
is
1001
frequency
a version that
NOR
other
being
system to be built
later.
The
is
the
circuit
are
the count
is
wrong,
rect count,
eral
is
actually a
The
shown
quency,
in
f, is
figure 255.
The output
by
fre
given approximately
1.4RC
error sensing.
205
is
EXPERIMENT
1001
ELECTRONICS/DIGITAL
1
Fig.
255
MATERIALS
1
Quad, 2input
MC
2 Capacitors, 10
1
NOR
integrated circuit,
724P or equivalent
DC power
(iF,
Oscilloscope
2 Potentiometers, 100
6V
supply (0
kft,
1W,
linear or a
40V)
PROCEDURE
1.
common
206
and pin
1 1
EXPERIMENT
ELECTRONICS/DIGITAL
Input B
Output
(pin 1)
(pin 2)
(pin 3)
Input
1001
3.5
o.b
n
U
3.5
3.5
(B)
(A)
256
Fig.
2.
3.
Output
NOR
Logic
Complete the data table for the NOR 1 (pins 1, 2 and 3) circuit and record the output
voltage in figure 256A. Zero voltage means to ground the input
Consider voltage
less
than
volt a zero
volt a
Connect the
connected to
5.
Vqq
1 1
and 4 are
at pins 1, 3,
5 and 7
in figure
257.
Adjust the potentiometers one at a time and observe the nonsymmetrical output wave
R.
the settings so
to get the desired results. Output can be from either pin 5 or pin 3.
8.
Carefully measure the resistance of each potentiometer and record their values in figure
258.
ANALYSIS GUIDE.
pin)
in
final desired
waveshape.
the discussion.
PROBLEMS
1.
Make
2.
Complement
AND
circuit.
1.
A, B and C.
What function
is
If
complements
NAND
circuit
may
A, B, and C.
207
OR
EXPERIMENT
11001
ELECTRONICS/DIGITAL
Pin
Pin 3
Frequency =
Pin 5
Pin 7
Fig.
257
208
Hz
EXPERIMENT
ELECTRONICS/DIGITAL
4.
Rj
11001
mF
to pro
What
and R2,
if
a frequency of 5
kHz was
with 33 k2 resistors, Ri
desired?
HIGH
0.05
0.1
SEC
SEC
Fig.
Ri =
ohms
R2 =
ohms
258
209
experiment
INTRODUCTION.
exercise
ling its
we
will
MANUAL TEMPERATURE
CONTROL
11010
employed
a simple oven,
If
digital
The clock of
is
vari
a fixed
is
error sensing.
is
being used to
quency
fre
the count
count of pulses
rily
FREQUENCY
CONTROLLER
VARIABLE
OSCILLATOR
COUNTER AND
ERROR MEASURING
DEVICE
CLOCK
Digital Control
210
System
used
is
in
prima
The
DEVICE
26 1
is
con
be an oven heated by
CONTROLLED
Fig.
wrong,
itself
tored by a thermistor.
oscillator.
is
an indication of
is
if
the
mechanism where
is
the
is
servomechanism.
in
the controller
how
In this
temperature.
DISCUSSION. A
loop
in a
moni
ELECTRONICS/DIGITAL
EXPERIMENT
1010
100,000
TYPICAL
RESISTANCE  TEMPERATURE
r.URVF
RB41L1
TC
HQ.
20500
25
10000
50
4020
100
910
125
494
10,000
1,000
o
50
25
Fig.
The thermistor
ment
is
10k
ohm
262
75
100
125
150
Thermistor Curve
(at
as
down and
visaversa.
Figure 262
is
the
this
means that
211
experiment.
re
in
EXPERIMENT
11010
Fig.
is
Experimental Setup
263
shown
ticular
in fig
resistance
lamp
is
lamp
SCR
lighted.
switch current.
is
The
circuit,
it
is
AC
line)
is
the
low
re
connected to
later for
control of the
light.
The advantage of
for half
the
blocks to be used
anodecathode
in
the
is
being directly
will
ELECTRONICS/DIGITAL
is
down
it
to half, note
this par
212
is
EXPERIMENT
ELECTRONICS/DIGITAL
1010
MATERIALS
1
Oven
box such
(use a cardboard
as a
shoe box)
1/2W
Lamp, 75W,
Line cord
VOM
DC power supply
(0 
or
or equivalent
FEM
40V)
PROCEDURE
1.
Connect the
2.
3.
Measure the
in
initial
light
comes
on.
4.
5.
light
Record
remains
ON
6.
7.
Repeat
on the data
table.
Thermistor Resistance
Room
ANALYSIS GUIDE.
Temperature
on the
results.
Also discuss
how
Thermistor
Time
Resistance
10 sec
30
sec
50
sec
60
sec
2 min
3 min
Fig.
264
213
Temperature
between the
ELECTRONICS/DIGITAL
PROBLEMS
1.
An ohmmeter
what
effect high
ohmmeter
3.
4.
is
R.
Explain
What
is
the yintercept?
the slope?
Write an equation for the line you drew in problem 2. The equation for a straight
line is Y = mx + b where m is the slope and b is the yintercept.
furnace
5.
2
is
resulting temperature.
its
What
power
in
how
your home.
Briefly explain
how
a thermistor
214
TEMPERATURE CONTROL
COUNTERS
experiment
INTRODUCTION.
experiment we
this
In
error
will
measuring device.
DISCUSSION.
is
Digital control
ter
variable
fixed
the coun
of figure 271
frequency
oscillator.
tells
Since this
is
the
ber of cycles
cillator
cation
of
device.
the
is
The clock
how
is
It
nism.
271.
is
If
is
an
os
general
is
the pulses
fits
The
concept of
is
used
in
error sensing.
the variable
description
the
indi
This
error.
frequency
In this
oscillator.
its
CONTROLLED
DEVICE
FREQUENCY
VARIABLE
OSCILLATOR
CONTROLLER
COUNTER AND
ERROR MEASURING
DEVICE
CLOCK
Fig.
27 1
Digital Control
215
System
application
in
EXPERIMENT
11011
ELECTRONICS/DIGITAL
BINARY
3
0
U
DECIMAL
o
1
10
11
12
13
14
15
2
*
BINARY
273
nary counter.
two
To
inte
To
2
a
INPUT
BINARY
1
and the 2
right
bi
digit
is
minimum
is
shown on the
which
flow
216
is
in circuit
diagrams.
the
left.
to the table
con
shown on
stage counter
Binary Counter
each one.
Fig.
We
BINARY
such a system.
BINARY
in
Fig.
left,
signal
ELECTRONICS/DIGITAL
EXPERIMENT
14
12
13
11011
10
11
_Q
Q_
+v
KEY
ra
Fig.
274
MC 790P
In
use
false
it
will
stable
on the
be necessary to
bounce.
caused
is
left side
left
in its stable
Fig.
275
left.
GROUNDED AND
ICs.
Experimental Circuit
217
NOR
circuits
the far
IS
The mono
of figure 275.
3.5V
unstable state
stable condition.
its
by switch contact
its
manual operation,
returns to
by
(in
PIN 11
EXPERIMENT
11011
ELECTRONICS/DIGITAL
MATERIALS
1
MC
790P
or equivalent
1
MC
724P
sockets
or equivalent
1
Capacitor, 10 fxF,
6V DC
DC power
supply (0
40V)
PROCEDURE
Connect the
1.
circuit
shown
275.
in figure
Apply power and momentarily connect the DC reset line, Cq, to the 3.5volt supply. All
lamps should be out. A lighted lamp is a 1 and an unlighted lamp is a 0, so the first entry
2.
line in
3.
all
zeros as shown.
Remember
the table and circuit are laid out in reverse so that a lamp lighted on the far
a
one on the
4.
5.
6.
Connect the
7.
8.
output of stage
Vqq
to the
(d) to
is
complete.
Cq
line.
is
results in the
(a).
second data
is
table.
way through.
ANALYSIS GUIDE.
second data table
from that
in
the
tell
why
in the
first.
PROBLEMS
1.
Draw
the
the block diagram of the fourstage binary counter with the trigger input to
first stage
AND.
3;
If
is
AND
grounded. What
to input
zeroed
that
left enters as
1,
gate of problem
will
is
is
initially.
218
in
binary?
Assume
is
being fed
the counter to be
ELECTRONICS/DIGITAL
4.
If
EXPERIMENT
1101
the pulse duration of problem 3 were 0.04 seconds, what would the counter have
read
in
binary?
5.
Show
6.
Show
to 8.
AND
DECIMAL
BINARY
3
(b)^
(d)2
0
1
4
5
6
7
9
10
11
12
13
14
15
Fig.
276
219
EXPERIMENT
101
DECIMAL
BINARY
(d)
23
ELECTRONICS/DIGITAL
(C)2
(b)2
(a)2
0
1
3
4
5
6
7
8
9
10
11
12
13
14
15
Fig.
276
220
(Cont.)
experimen
INTRODUCTION.
this
11100
Digital servo
experiment we
AUTOMATIC TEMPERATURE
CONTROL
will
investigate
simplified
example of
working
digital
closedloop
servomechanism.
figure 281.
is
frequency
The clock
how
in
This
being used
oscillator.
is
vari
If
is
a fixed
is
determined
correct
if
the count
CONTROLLED
DEVICE
FREQUENCY
VARIABLE
OSCILLATOR
CONTROLLER
COUNTER AND
ERROR MEASURING
DEVICE
CLOCK
28 1
the pre
is
wrong,
an indication of
Fig.
the
oscillator
is
in
Digital Control
221
System
EXPERIMENT
V gB
1 1
 6.0
100
VOLTS
2N4891
C
mF
0.5
Fig.
282
UJT Oscillator
to discharge through
shown.
A
ing a
this
UJT
will
The
is
we
f,
is
given ap
firing or
cir
will use.
peak voltage, V
of the
where Rg
is
given by
r?
is
stant for
(a
by
con
proximately by
V^BB
where
experiment.
UJT
employ
Rj
varies, the
Vgg
The
Once the capacitor charges to
age the
UJT
is
a collector
this volt
222
dia
shown
KEY
Fig.
283(A)
= 100
to
be Used
=3.5V
R_ = 100 kn
kn
c = 10 mF
C 1 = 10>jF
NOR
1
[2
/Y>J
i
11
TO GROUND
F/ff.
in
figure 283.
283(B)
An
given approximately
f,
is
lar
by
The
desired
The
is
simi
is
It is
shown
in
figure 285.
The SCR
a symmetrical wave.
223
EXPERIMENT
(1)
HIGH
(0)
LOW
1 1
100
Fig.
Fig.
285
284
Clock Waveform
224
ELECTRONICS/DIGITAL EXPERIMENT
1 1
100
100,000
10,000
in
5
I
O
UJ
o
z
<
f
00
UJ
1,000
100
50
100
75
125
150
TEMPERATURE
Fig.
286
Thermistor Curve
The
shown
is
The counter
periment
shown
286.
225
is
in figure
that
we
287.
one
EXPERIMENT
1 1
100
Binary Counter
287
Fig.
MATERIALS
Potentiometer, 10 k2, 1/2W, linear, or
UJT
transistor,
6V
Resistor,
RB41 L1
4
kS2,
type 2N4891 or
equivalent
1
box
1 15V
75W,
Lamp with socket,
Resistor, 47fi,
DC power
SCR, GE C22B
Line cord
VOM
or
or equivalent
FEM
MC
790P
or
equivalent
circuit,
10V DC
1/2W
supply (0  40V)
or equivalent
1/2W
1/2W
Oscilloscope
Resistor substitution
NPN
transistors, type
2N3709
or
linear,
Oven
(use a cardboard
box such
as a
shoe box)
PROCEDURE
1
2.
The
(c)
They
are not
shown to
of pulses
let
in
UJT
clock,
the variable frequency oscillator and (b) the
(a)
actual scale.
what
1
is
The number
oscillator.
circuit.)
226
AND
Fig.
288
Waveforms
ON
OFF
3.
Time period 3
4.
is
digital
or
5.
will
turn the
If
positive pulse
is
ferentiate the
time periods
6.
To
light will
the count of 8
8.
is
SCR
OFF.
on the Cq line will zero the counter. Thus, it will be necessary to difwaveform of figure 288(b) so that a positive spike at the beginning of
and 3 will zero the counter.
1
output of
(d)
(a).
UJT
the
of the
if
remain ON.
OFF
necting the 0 output (d) of the binary counter to the gate of the
This
go
light will
and
3, etc., to let
counter at 150F.
9.
10.
Apply power to the clock and adjust for the appropriate time
the lamp is lighted are not critical in time length.
Connect the
circuit as in figure
interval.
227
in
Intervals
where
ROLLED DEVICE^^
t
10
kn
4**I
+6.0V
0.5
mF
'150
AND
~l
INVERTER
'
284.
LAMP
LAMP
r
LAMP 2'
LAMP
I
CD
CLOCK
FIGURE
~1
C = 0.05mF
^ R=
DIFFERENTIATOR
22 kfi
283
USE
__J
WAVEFORM OF
FIGURE
288(b)
Fig.
289
Experimental Setup
228
DIFFERENTIATOR
r If
2
ELECTRONICS/DIGITAL EXPERIMENT
ANALYSIS GUIDE.
1 1
100
PROBLEMS
1.
2.
Repeat problem
229
at
200 F.
experiment
digital
We
computer.
form
11101
will
is
a calculation.
DISCUSSION.
the calculation
is
completed.
Pulse trains of
tal
at a fantastic rate.
The
actual
programming
in
acteristics
new model
has
its
own
char
to be used
structions
to solve
will
the
all
synchroni
in
in
are
also
Magnetic cores,
tapes,
the
in
is
in
memory.
amounts
of data
and instructions.
consists mostly
all
the actual
cal
culations take place in this part of the comCounters and registers are the most
puter.
common
circuits
used
in
part of the
this
computer.
The inputoutput
research, etc.
are the
Each
digital
computer
is
in this
elements
1)
in
computer.
each
digital
There
course.
combination
memory,
are:
3) the
computer.
Raw
data and
in
computer through
human commands
this
corded, then an operator could convert
language into meaningful data, but the speed
at
230
human
this
operators.
is
much
EXPERIMENT
ELECTRONICS/DIGITAL
The
size of
1 1
to
superimposed on the
is
TV
week on
demonstrated.
appli
experiment we
program the
will
during play
cations.
In this
tournament standings
golf
screen.
thousands of
larger units
TV
may be
with even
linked
101
may be
game on
written to
stant for a
known
value of R and C.
MATERIALS
IBM 1401 computer system
(or equivalent)
20 Blank
printer,
cards.
PROCEDURE
Punch the program cards to read as shown
cause the program NOT to run properly.
1.
0 U T
mistake
in
0
0
N T
0 R M A T
N D
U S
U T
T 0
G 0
Any
figure 291.
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
T +
in
T 0
Fig.
291
231
EXPERIMENT
11101
ELECTRONICS/DIGITAL
2.
3.
4.
Double the value of R and load the new program into the card readpunch
5.
Repeat step
printer.
unit.
3.
unit.
the
1.0,
and R =
2.0.
PROBLEMS
1.
and 50
2.
R =
is
Explain
1.0.
Plot the
value
3.
sec;
when
why you
232
is
correct.
values.
Which
What
INTRODUCTION.
Digital
VMM A RY OF LOGIC
experiment
OPERA TIONS
has
logic
its
own
many
we
systems
logic
In this
any language,
As with
may
or false.
thorough under
that
state
system
logic
the
all
diagram
logic
is
set
on,
and they
words True,
will
be used herein.
confuse you
information
all
the true
These
bits.
bits are
When we
off.
are talking
about
the
voltage
and
0.
"Hi" for
made
often
is
important
Lo or Off
The
12, which
as
+.
It
is
also
common
in
to
Up 32
25
16
2
8
2
4
2
presence
designations
0, etc.,
of
is
that the
may
be used
complete
and 0 to Hi and Lo
if
the
first
letter
Then
they
become
logic.
Hi
1,
In
Lo =
and
0 for positive
0.
are
would be designated
1,
will
It
the
conversion of
voltage.
Lo,
Even the
the
than
stage.
system.
It is
False,
to
zero volts).
"Positive
The choice of
more
for an
either
Hi,
Electron
levels
is
usually
will
Many
signal.
logic states,
do not have to
correspond exactly to 0 volts and one volt.
ically,
experiment
Hi and +.
current
in
or
logic functions.
will
is
the symbols
encounter a
be represented.
24
is
True
In the binary
number system
1/2
1/4
1/8
1/16
2~ 1
2" 2
2" 3
2" 4
233
Down
EXPERIMENT
Each
bit
is
11110
all
is
1/2
1/4
1/8
1/16
22
21
Decimal No.
16
decimal point
is
The
symbols
basic
called
are
shown
GATES
AND
OUTPUT
INPUTS
INPUTS
AMPLIFIERS
OUTPUT
INPUT
SWITCHING ELEMENTS
MATRIX, REGISTER,
(FLIP FLOPS,
ETC.)
ITRIGGER
SET INPUT
CLEAR INPUT
FF
(RESET)
>
INPUT
DELAY ELEMENTS
Fig.
30
called
4
23
23
to provide a
24
in
for
21
Weight
in
or
devices
10110.1000.
may
number
Truth Tables.
Binary No.
digits
for 22.5
ELECTRONICS/DIGITAL
Logic Symbols
234
OUTPUT
in
figure
These
301.
ELECTRONICS/DIGITAL
302
Fig.
One
Symbol
for the
AND
Gate
is
the
AND
Its
produce
puts
symbol
a true
are
produce
to
true.
single
a false output.
the circuit
all
is
shown
false
This
in figure
is
all
the
in
input will
analogous to
303.
none of
output
Symbol
304
Fig.
its
of
plication
be a
will
OR
The
outputs.
false.
gates
(all
Gate
false),
its
An
important ap
in
the timing of
is
on for a
true signal to one
When
equivalent
trical
removed, the
is
for
an
OR
gate.
Obviously
DC VOLTS
Fig.
Fig.
303
305
gate
shown
in figure 304.
is
the
OR
build
The
two or more inputs and one output.
output will be 1 or Hi when any one of the
inputs
is
Hi.
The
OR
OR
Gate
ments
LOAD (OUTPUT)
LOAD (OUTPUT)
DC VOLTS
is
OR
for the
in
They
logic circuitry.
up the
signal
when
it
are used to
gets too
weak to
levels.
in
active
region
amplifiers.
and function as
They
also
linear
the
pulse
When
one or more of
its
inputs
is
a true.
235
X (OR
IB)
from the
It
said to
is
is
be the com
in
when
signal
is
amplifier.
It
is
in
The
dicates an inversion.
is
the
OR
is
Conversely, of course,
or normal state.
gates
in
is
Lo
Hi
Hi
Lo
the symbol
is
is
307
possibility
is
Hi.
the
if
The
shown
The output
308.
figure
input
is
lo
OR
inversion indicator
The
in
any case
it
not
often
Fig.
Another
B.
to
indicates an inversion.
Lo
the B input
may be
symbol
inversion
if
is
Hi
Hi
occuring at
symbolically
is
Lo
only
several
Lo
inverted
inverter
306
amplifier output
input.
A)
INVERTER AMPLIFIER
Fig.
The
NONINVERTING AMPLIFIER
(A)
one output.
ELECTRONICS/DIGITAL
The
is
inverted for
Lo
Lo
Lo
Lo
Hi
Hi
Hi
Lo
Lo
Hi
Hi
Lo
236
OR
EXPERIMENT
ELECTRONICS/DIGITAL
Fig.
its
or an
output inverted.
OR
gate gives us a
308
of
a Hi at the
are
is
Lo
Hi, a
at
the
NOR
one time.
The same
If
Lo
Lo
Hi
Lo
Hi
Hi
Hi
Lo
Lo
Hi
Hi
Hi
Lo
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Lo
Hi
Hi
Lo
OR
Gate
the inverted
AND
NOR
case
gate
Inverted
This can
gate.
is
Lo output
The
function
Gate)
309
OR
(NOR
Fig.
has
11110
OR
is
shown
or
in figure
NAND
circuit.
an
logic
inverter
This
amplifier.
AND
gate
is
gate with
type of gate
the inputs
Such
be obtained by following an
to produce
all
Gate
all
of the
NAND
will result.
Fig.
30 10
Inverted
AND
237
Gate
Lo
Lo
Lo
Lo
Hi
Hi
Hi
Lo
Hi
Hi
Hi
Lo
(NAND
Gate)
ELECTRONICS/DIGITAL
X=AB=A+B=A+B
30
Fig.
implemented.
an abundance of
OR
gate
NAND
1,
This
this
with
is
Lo
Lo
ttt
Lo
Hi
Hi
and
circuit
Hi
Lo
Hi
is
NAND
Hi
Hi
Lo
outputs
the
gives
OR
an
in
configuration
associated
Gate
on hand, but an
gates
is
figure 301
OR
Phantom
1 1
but
gate
implementation.
30 13
Fig.
the other
will
is
Exclusive
OR
Truth Table
be high.
in
30 12
Fig.
Exclusive
OR
Gate
Exclusive
The symbol
OR.
Exclusive
produces
in
The
the
differently,
true
output
is
shown
that of the
OR
Exclusive
Gate
When
output
the
is
To
false.
Exclusive
OR
say
are
However,
if
low,
the
output
produces a
will
or B
is
be
3014.
arrangement
This configuration
is
is
It
all
The next
if
either input
This
gate.
followed by an
this
OR
in figure
is
compliment of the
same,
figure 3012
OR
the Exclusive
If
flop.
The
outputs.
flop
its
low.
is
last
basiclogic circuit
flip
impulse was.
capability of
238
the
storage.
until triggered to
low while
is
It
It
remains
the flipflop
in
one
The
makes
it
state
storage
a very
ELECTRONICS/DIGITAL
Fig.
important unit
digital
this
30 14
stay at
All
Q will
the
a flipflop
is
connected as shown
A's output
is
it
as
two
NAND
Gate
is
Lo
Hi
Lo
Hi
Lo
Lo
Hi
Hi
Hi
Gate
connected to one
let's
(from
Now
gate
Since
similar
Now let's
Q is fed
inputs of
two
inputs so
gate
inputs so
NAND
239
Gate
on R
at
Q goes to 1.
Q goes to 0.
will
be locked at
will
is
locked at
put a
1.
have
In a
0.
on S and
Flip Flop
0 on
R.
B has two
>
3015
two
goes to
inputs so
will
and 0 so
>
Fig.
0 on S and
feedback loop) so
has
and therefore
at the
Since
on S and 0 on R
will
is
Let's
1
put
input.
of
1.
Hi
0 and gate
gates
figure 3015.
in
Lo
same time.
Oand
approach to producing
to consider
Lo
stay at
Now
delays.
interesting
and
An
OR
Inverted Exclusive
logic systems.
in digital
and thus
goes to
has
0.
two 0
EXPERIMENT
inputs so
1
locked at
is
inputs so
11110
is
locked at
The
The
0.
by what
is
FF
state of a particular
stored in
is
and the FF
line (Q)
This output
is
line
(not Q).
stored function.
line
pulses of a given
the
that
PRF
gates will
particular
is
either
clocked
and
can be
or
Clocked
instances of time.
RS FF
limited to applications
is
will
flip
device
same time.
the
because
reset
FF in the Lo state.
R terminals must not be
simultaneously
in
on the
a signal
the
places
use of the
by
reset to zero
is
applied
may be
Flipflops
The outputs
state
device
unclocked. Clocking
lines
identified
with
available
is
is
it.
on an output
ELECTRONICS/DIGITAL
RS
FF.
unclocked FF
will
Since the
It
is
one
is
until
this
is
another pulse
is
applied.
Since
Lo's
applied to
to
both
K,
known.
3016
flip
Figure 3018
This unit
Hi input
to the Hi state.
If
Hi's
produces no change.
line
is
OUTPUT
INPUT
Fig.
The JK
the
inputs
state.
FF switches to Lo.
If J and K receive Hi's at the same time, the
FF switches to the compliment (if it was
Applying
Hi, it goes Lo and vice versa).
are
state
FF
at J switches the
The outputs
no such uncertain
for the
bistable with
another type.
arises for
flop has
change.
input
need
RS FF
Symbol
240
Before
After
Trigger
Trigger
Pulse
Pulse
Lo
Hi
Hi
Lo
Hi
Lo
Lo
Hi
for Toggle
FF
ELECTRONICS/DIGITAL
RS
OUTPUT
INPUT
RS
Lo
Lo
Will
Lo
Hi
Hi
Lo
Hi
Lo
Lo
Hi
Hi
Hi
Fig.
30
Symbol
RS FF
for an
OUTPUT
INPUT
Fig.
flipflop
(TFF);
it
normally
is
method
pling
RC
uses the
either a dual
The
AC
is
actually
The
combines two
logic
element.
All
of
it
The
is
Hi
Lo
Hi
Lo
Hi
Hi
Compliment
for the
both
not
the
FF
input
information
With
at
J.
The
a Hi input at
K, and the
The
trailing
edge
When
and
K.
The
trailing
With a Hi input
JK
Hi
type)
Lo
input
It
one for
is
Hi
trailing
to form a
this
Lo
No Change
Lo
method
Lo
trailing
time constant of
dual rank
stores
cou
Symbol
30 18
Not Change
flipflops.
operation
at
They
241
will
these
others
to
review the
on your own.
ELECTRONICS/DIGITAL
supplies
4 IC sockets
PROCEDURE
1.
The Tl SN15830N
dual 4input
is
NAND/NOR
gate.
tie
them together
shown
3019.
AB
X
30 19
Fig.
3.
4.
Now
in
Now
NAND
Gate
and
B.
Record these
NOT (INVERTER)
construct the
Fig.
5.
all
Pairing Inputs to
3020
construct the
circuit as
Construction of
AND
circuit
shown
shown
in
in figure
3.
Gate
3.
AB
Fig.
3021
Construction of
AND
242
Circuit
from
NAND
Gates
EXPERIMENT
ELECTRONICS/DIGITAL
11110
3022
Fig.
6.
7.
Now
construct the
Fig.
8.
Construct the
Construction of
circuit
NOR
3023
shown
circuit
OR
Circuit
in figure
shown
from
NAND
in figure
shown
circuit as
3.
EXCLUSIVEOR
Gates
NAND
3.
Gate
in figure
3.
Fig.
3024
Construction of
NAND
9.
DENCE
circuit as
from
Gates
shown
243
Circuit
in figure
3.
ELECTRONICS/DIGITAL
3025
Fig.
10.
Construct the
Construction of
RS
flipflop circuit as
shown
in figure
The
is
ANALYSIS GUIDE,
basic
PROBLEMS
1.
2.
It
was stated
this
in
NAND
all
basic
and can
implement
also be used to
all
is
gate
is
is
the
is
perhaps just as
NOR
gate
shown
below.
We
then B =
0.
implement
if
we want
equal to
So by
tieing
all
A1 =
can pertain.
Therefore,
NOR
if
gate to 0
B =
we can
below.
Now
in
triggering circuit of
will
logic devices
Gates
using only
NAND
circuit.
NOR
gates implement an
Be sure to
AND
circuits.
244
circuit,
each
NOR
an
OR
circuit,
and a
EXPERIMENT
Name
Date:
Instructor
Class
Decimal
Binary
Decimal
Decimal
Binary
Binary
Decimal
26
51
76
27
52
77
28
53
78
29
54
79
30
55
80
31
56
81
32
57
82
33
58
83
34
59
84
10
35
60
85
11
36
61
86
12
37
62
87
13
38
63
88
14
39
64
89
15
40
65
90
16
41
66
91
17
42
67
92
18
43
68
93
19
44
69
94
20
45
70
95
21
46
71
96
22
47
72
97
23
48
73
98
24
49
74
99
25
50
75
100
Binary
(A)
Decimal
Binary
Decimal
111011101
353
11101101
557
10110.1101
632
.11011
0.725
.10001
0.5625
(B)
Binary
(C)
Fig.
13
Decimal
Binary
4. (a)
4.(b)
4.(c)
5.(a)
5.(b)
(D)
Decimal
Binary
6.
7.
(E)
Fig.
13
EXPERIMENT
Name
Instructor
Class
Date:
THEOREM
Aa v
X
AX
3(b)
THEOREM
A
6(b)
x
TRUTH TABLE FOR
A
B
Fig.
210
(B + C)
(A X B) + (A X C)
(B
BOOLEAN EXPRESSION
210
SIMPLIFIED EXPRESSION
B
x
Fig. 2
12
+ C)
AX
= AX
(A X B) + (A X C) =
Fig.
0= 0
n
= n
0_
0
Fig.
210
Fig. 211
BOOLEAN EQUATION
A
B
C
SIMPLIFIED EQUATION
Fig. 211
THEOREM
BOOLEAN EXPRESSION
A
1
Fig.
212
EXPERIMENT
Name
Instructor
Class
Date:
DC
10
Volts
11
12
13
14
60
100
200
500
15
Audio Generator Hz
30
1000
AC
Volts
Multimeter Reading
Oscilloscope Reading
100 Hz
Frequency
Rise
500 Hz
Time
Fig.
35
kHz
EXPERIMENT
Name
Date:
Instructor
Class
Waveform
Period
Freq
Period
Freq
Set
Set
Read
Read
Td
50% DC
0.1 /nF
CAP
Parallel
Inductor
Parallel
10
KC Pulse
=10 /xsec
Sketch of
First
Waveform
Sketch of
Second Waveform
Fig. 4 1 1
% DC
tr
Identity
of
Wave
Sketch of
Third Waveform
Sketch of
Fourth Waveform
Fig.
411
EXPERIMENT
Name
Instructor
Class
Date:
maA
. .
Vq
volts
4U
bU
on
oU
"c
'c
'c
1
I
nn
uu
on
0
2
4
6
8
10
12
14
16
18
20
VC E
l
B Ma
1.0V
5.0V
10.0V
20.0V
V BE
V BE
v BE
V BE
0
10
20
30
40
60
80
120
160
Fig.
517
/in
'c
EXPERIMENT
Date:
Name
Instructor
Class
CALCULATIONS R L
Waveform
RB
CALCULATIONS
Fig. 6
10
rl
no
OI\
OUTPUT
DELAY
K lob
DillLot
CL
CTflD
ARC
o UnAot
P ALL
A
P
TIME
TIME
DURATION
TIME
TIME
rU
RB
POINT X Rg
OUTPUT RgCg
pni
NT X
R BC B
OUTPUT
(Three
^fpn<5 Ahnv/p
cB
POINT X
/
\
~T"
1
hrQQ
Mf cc Q+ar*e
OLcpS
Above Cg)
OUTPUT (Three
Steps Below
Cg)
POINT X
(Three Steps
Below C)
Output Waveform
with
Rg
in
the
circuit
Fig.
610
EXPERIMENT
Name
Date:
Class
Waveform
Point
Rg
the
in
Instructor
at
with
Circuit
C B CALCULATIONS
Output Waveform
with
Cg
in
the
Circuit
Fig.
&70
Waveform
Point
Cg
the
in
at
with
Circuit
Output Waveform
with C Three
Steps Above
Waveform
Point
Cg
at
with
Three Steps
Above Cg
Fig.
&10
EXPERIMENT
Name
Date:
Class
Instructor
Output Waveform
With C Three
Steps Below
Waveform
Point
Cg
at
With
C Three Steps
Below Cg
Fig.
610
EXPERIMENT
Date:
Name
_____
Instructor
Class
First Circuit
Amplitude
=
II
1
1
Mil
Mil" 'llll
mi
Output Waveform
(Show zero reference level)
Second Circuit
Amplitude
MM MM
lilt
MM
II
ll
il
MM MM
II
Period
Output Waveform
(Show zero reference level)
Third Circuit
Amplitude
Period
=
llll
llll
Mill
1^
'llll
MM
till
Output Waveform
(Show zero reference level)
Fig.
712
till
llll
Fourth Circuit
MM
till
MM
nil"
MM
lilt
Output Waveform
(Show zero reference level)
Fig.
712
II
MM
EXPERIMENT
Name
Date:
Instructor
Class
RB
RL
V CC
E IIin
v cc
V C1
tTE
tl_E
Calculated
Measure
Output
Resistor
Clipper
r2
Ri
Calculated
Measure
Output
Diode
Emitter
Clamp
Fig.
89
E in
EXPERIMENT
Name
Instructor
Class
Date:
Output
Input
A = +5
B=
Output Waveform
Input
A=
Output
B = +5
Output Waveform
Fig.
911
Output
Input
A = +5
B = +5
Circuit
Type
Output Waveform
Output
Input
A = +5
B=
Output Waveform
Input
A=
Output
B = +3
Output Waveform
Fig.
911
EXPERIMENT
Name
Date:
Instructor
Class
Input
Output
A = +3
B = +3
Circuit
Type
Output Waveform
Fig.
911
Two
INPUTS
OUTPUT
Fig.
911
BOOLEAN EQUATION
EXPERIMENT
10
Name
Date:
Class
V CE
No Input
V CE
Input A Only
Instructor
V CE
Input B Only
First
Circuit
Second
Circuit
Third
If
\J
1
Circuit
Fourth
Circuit
Measured Data
Fig.
109
Circuit Diagram
Fig.
109
V CE
A&
Input
EXPERIMENT
Name
11
Date:
Class
First Circuit
Data
Instructor
Inputs 0 or
Output
Oor
volts
Boolean Expression
Output
Oor
Boolean Expression
Fig. 1 17
volts
Inputs 0 or
AA
Output
D
D
r>
Li
flnr
u or
\/nlt<;
Boolean Expression
Inputs 0 or
Output
Boolean Expression
Fig.
17
Oor
volts
EXPERIMENT
Name
12
Date:
Class
Instructor
E
o
E
U
o
a? 9
+>
ca
>
<
5 !
E
_ "
CD
3 m
8 o
Ml)
till' "llll
MM
3 >
C 03
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CD
<n
.
03
CD
CO
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ic
1
J
tO
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c 5
CD
03
4>
L.
CO
03
g >
0)
T.
CD
>
C
CD
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L.
8.
III!
II
MM MM
'
tin
Mil HH
MM
Mil" M
II
HH
E
i_
C/5
4
QJ
a
0)
ZJ
>
tO
>
(0
D >
>
f
~3 E
S
CD
II
MM
il
055
2
c "
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c
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C
(D
4<
"to
5 u
"O
.2
0)
co CD Q.
MM
lilt
MM
Mil
II
MM
MM
MM MM
EXPERIMENT
12
Name
Date:
Class
Instructor
L_
Cl
+*
CD
>
>
"D
CO
+*
CD
CD
03
~~El
ch
ea
CO
Q.
w
O
1
MM
</i
or
CO
C
CJ
>
CD
CO
cn
ata
i
CD
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E c
c
eva
DO
Cl
CD
en
w
ice
i_
CD
t_
CD
H
CD
Dc
CO
T3
1.1 i
CD
CO (J Cl
CO
CD
HH
tilt
Mil
Mil'
II
MM
MM mm" MM
Mil
EXPERIMENT
13
Name
Date:
Class
II
Mil
llll
Instructor
mm' MM
llll
MM' MM
Mil
Output Waveform of
MM MM
llll
First Circuit
MM
Mil
MM
EXPERIMENT
Name
14
Date:
VC
Class
Instructor
=
1
VC2
V C 1'
'C2
MM MM MM MM
MM MM
MM
MM MM mi MM
Mil" 'mm
MM
MM MM
Fig.
144
II
il
Mil
MM
II
II
MM MM
lilt
III)
II
il
II
MM
If
HH
EXPERIMENT
Name
15
Date:
Class
Instructor
ln P ut
Hit
MM mi'
't
Output
1
llll
llll
0ut P ut
Output
Fig.
155
EXPERIMENT
16
Name
Date:
Class
RS
Instructor
Inputs
Outputs
e
b1
C1
c2
Q
t
0
0
bit
J
= no input, terminal
left
JK
time after
clock pulse
floating
Indeterminate
Inputs
n+
Outputs
S1
Cl
Inputs
Si
Fig.
1&7
Outputs
EXPERIMENT
Name
17
Date:
Class
Instructor
C1 =
it
MM MM MM MM MM MM MM M il MM
Common
Emitter
V BE
Effects of varying
R1
Effects of varying
MM MM
MM MM MM MM
HH
MM
'1
Common
Emitter
Vq^
*1
MM
Common
Emitter
MM
Mil] "mm
V^g
Fig. 178
mi MM MM MM
EXPERIMENT
Date:
Name
18
______
Instructor
Class
lilt
il
MM MM
Mil
MM MM MM
MM
lilt
II
MIM MM
Fig.
HH
III
MM MM
mi
Mil
Mil
llll
Mil' 'till
MM
Mil'
MM
llll
Mil'
MM MM MM MM MM
186
The Results
MM
Mil
MM MM MM MM MM MM
till
MM
Mil'
HH
HH
H"++"
till
till. 4
MM MM' MM
Mil
MM
It
MH
MM MM
F/gr.
756 777e
ti
MM
ll II
/?esi//fs
II
HH
till
+W
till
Mil
MM
HH
(Cont'd)
EXPERIMENT
Dat e:
19
Name
Class
Fig. 198
Instructor
FF 0
FF
FF
Time
t
= 0
Counting Data
Decimal
CP
Equivalent
FF 2
FF 1
3
4
5
6
7
FF 0
EXPERIMENT
Name
20
Date:
Class
Instructor
Truth Table
tp
*n
Reset
FF,
FF 2
FF 4
FF5
Effect of reset
when count
< 5 was
Fig.
MM
Ml)
II
MM' M
1
MM MM M MM
1
<
MM MM MM MM
MM
nil M M
Fig.
Hit"
II
MM MM
(II)
MM MM MM
MM MM
Mil;
MM MM
Mil
mm'
MM
MM MM' MM
II
EXPERIMENT
Name
21
Date:
Instructor
Class
tilt
til)
mi
1)11
lilt*
tin Mill
MM MM MM
MM MM
HII Mil
MM MM
Mill
MM
Fig.
Mil
mm' jlll
Mil'
2112
1
1
till
MM MM
MM MM MM
The Results
MM
II
II
MM
II
MM
till
Mil
MM
III!
MM MM
MM
Mil
MM MM HIT
MM MM
nil
Fig.
Mil'
MM MM
till
MM
ntt'
MM MM
MM mm' MM MM MM
2112
MM
Mil
II
MM
MM
MM
EXPERIMENT
Name
22
Instructor
Class
Date:
Switch
That
23
is
Closed
Fig.
226
EXPERIMENT
Name
23
Date:
Instructor
Class
AND
OR
Fig.
233
Gate
Gate
Gate Diagrams
Fig.
233
AND
Gate
OR
Gate
EXPERIMENT
Name
23
Date:
Instructor
Class
Truth Table
Fig.
234
EXPERIMENT 24
Name
Date:
Class
WAVESHAPES
Instructor
(FIG. 242)
RE
1
Calculated Frequency
kfi
2kl
8 kfi
10
kn
12 kft
14
kn
16 kfi
18 k2
20 kft
Fig.
Measured Frequency
EXPERIMENT
25
Name
Date:
Class
Input
Input B
Output
(pin 1)
(pin 2)
(pin 3)
3.5
3.5
3.5
3.5
Instructor
(A)
(B)
Fig.
256
NOR
Logic
in
in
Frequency =
in
OJ
in
Fig.
257
Hz
EXPERIMENT
26
Name
Date:
Class
Instructor
Thermistor
Time
RlCglolal
P Q <l1"3 nIL<C
r*P
10 sec
30
sec
50
sec
60
sec
2 min
3 min
Fig.
264
Temperature
EXPERIMENT
Name
27
Date:
Class
Instructor
BINARY
(d)
DECIMAL
23
(b)2
(a)2
0
1
2
3
4
5
6
7
9
10
11
12
13
14
15
Fig.
276
DECIMAL
BINARY
3
(d)2
(C)2
(b)2
(a)
n
0
2
0
1
2
3
4
5
6
7
8
9
10
11
12
To
14
15
F/flr.
27 6 The Data
Tables (Cont.)
378000