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ISSN 2319-8885

Vol.03,Issue.28
September-2014,
Pages:5674-5677
www.ijsetr.com

An Efficient Avoidance of On-Chip Codeword Generation to Cope with Crosstalk


P.MAHESWARI DEVI 1, Y.PENCHALAIAH2, N.PUSHPALATHA3
1

PG Scholar, Dept of DECS, AITS, Tirupati, Andhrapradesh, India, Email: maheshswari425@gmail.com.


2
Asst Prof, Dept of ECE, AITS, Tirupati, Andhrapradesh, India, Email: penchu.yadla@gmail.com.
3
Asst Prof, Dept of ECE, AITS, Tirupati, Andhrapradesh, India, Email: pushpalatha_nainaru@rediff.com.
Abstract: An inductive and capacitive coupling is the responsible for slowing down signals between bus lines results in
crosstalk induced delays. Existing bus encoding techniques tackle the issue by avoiding certain types of transitions of this work
we can proposes a codeword generation method for such techniques are scalable to very wide buses. As the crosstalk in an onchip bus on the data patterns transmitted and it is highly dependent on the bus, different crosstalk avoidance coding schemes
have been implemented to boost the bus speed and/or overall energy consumption is reduced. Despite the availability of the
codes, of data words to code words for no systematic mapping CODEC design has been proposed and this is mainly used to the
nonlinear nature of the crosstalk avoidance codes (CAC). The lack of practical CODEC construction schemes has hampered the
use of such codes in practical designs of this work can be presents guidelines for the CODEC design of the (FPF-CAC)
forbidden pattern free crosstalk avoidance code. We can analyze the properties of the FPF-CAC and show that mathematically,
exists a mapping schemes based on the numbers Fibonacci numeral system in the representation. This is our first proposed
CODEC design offers a near-optimal area overhead performance. An improved version of the CODEC is presented, which can
achieves theoretical optimal performance and we can also investigate the CODECs implementation details and including design
complexity and the speed of the optimization schemes are provided to reduce the size of the CODEC and improve its speed.
Keywords: Codeword Generation, Crosstalk, Encoding.
I. INTRODUCTION
Every line in a bus suffers from parasitic coupling with its
neighbors that impacts speed of transitions. There are many
techniques that can be used to cope with the presence of
crosstalk. Repeater insertion which speeds up the transitions
on a line however gives rise to complicated layouts and
routing issues. Another technique is to use bus encoding to
avoid certain types of transitions on neighboring lines present
theoretical approach to encoding. Temporal shielding will
result in reduced throughput. One widely recognized way to
avoid crosstalk induced delays is to avoid all opposing
transitions on every pair of lines in a bus. This problem was
studied] with detail presents a quick mathematical method to
generate code words of given length. Code book so formed as
random logic is implemented from the scalability issues. The
encoding technique proposed in works by avoiding all sorts
of simultaneous transitions on neighboring bus lines,
assisting and opposing, thereby avoiding speedup or
slowdown is designed as a transition code where every
transition (rising or falling) is represented by a 1 while a
steady state is represented by a 0. For example, a codeword
101 indicates that in a three bit bus, edge lines are
undergoing transitions while the middle one is in a steady
state. As a result, eliminating code words with consecutive
1s eliminates all simultaneous transitions on neighboring bus
lines. Although the code proposed in relies on code words
from two consecutive time frames, it can be considered as a

memory less code because a simple XOR array can be used


to translate the transitions to 1s and 0s. It also is possible to
have more efficient code that allows some of the opposing
transitions if they are compensated by an assisting transition.
The code proposed it will achieves this goal by eliminating
any data word that contains pattern bbb, b{0, 1}, on
neighboring bus lines during any given time frame. In order
to maintain simpler code book and encoder logic, the authors
rely on bus partitioning and group complement bits which
results in significant overhead. The encoding technique
proposed by every bus line involves duplicating. In these
kinds of effects are encoding removes slowdown caused by
crosstalk and error detection provides certain degree. It is a
scalable method and can easily be implemented on-chip.
Redundancy is huge however and the cost in terms of area is
prohibitive. All encoding techniques with acceptable
redundancy rely on maintaining a code book. Exponential
size of the code books makes these methods non-scalable
using conventional random logic implementation. None of
the on-chip codeword generation avoidance is the very
essential problem on the existing work addresses. In this
paper, we offer a systematic CODEC construction solution
for the forbidden-pattern-free crosstalk avoidance code (FPFCAC). The mapping scheme we propose is based on the
representation of numbers in the Fibonacci numeral system.

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P.MAHESWARI DEVI, Y.PENCHALAIAH, N.PUSHPALATHA


We Show that all data words can be represented in the
studied as part of the effort to improve the power and speed
Fibonacci-based numeral system with FPF vectors. We
characteristics of the on-chip bus interconnects. Fig. 1
propose several different coding schemes that allow the
illustrates a simplified on-chip bus model with crosstalk. CL
CODECs to be constructed for any arbitrary bus size. With
denotes the load capacitance which includes by the driver,
such a systematic mapping, the CODEC for a wider bus is
the receiver gate capacitance and also the wire-to-parasitic
constructed by a simple extension for a smaller bus in the
substrate parasitic capacitance inter-wire coupling
first CODEC is proposed in this paper is proven to have nearcapacitance is the CI between
optimal area overhead performance.
We further offer an improved coding scheme that achieves
optimal overhead performance. We also propose
modifications to our near-optimal CODEC that will reduce
the complexity and improve the delay performance of the
CODEC. The key contributions of this paper include the
following.
If we can define a deterministic mapping scheme for the
FPF-CAC-based on the Fibonacci-based binary numeral
system.
It is based on the mapping scheme; we propose coding
algorithms that allow systematic CODEC constructions
so that the CODEC for a wider bus is obtained as an
extension of the CODEC for smaller bus.
We can show that the CODEC gate count grows quadratic
ally with bus size as opposed to the exponential growth for
the existing approaches.
The goal of the proposed method is to provide with a
generalized strategy for scalable codeword generation for
encoding techniques that allow recursive codeword
generation. Most of the coupling aware encoding techniques
in the literature fall in this category. In deep sub micrometer,
the performance of interconnects is critical. As on-chip
interconnects are placed closer and closer together, the
coupling induced delays become more and more important.
As the use of tightly coupled and wider buses become more
common, a scalable codec implementations strategy becomes
increasingly important. This paper provides details of the
application of the proposed framework for effective real-time
codeword generation to existing encoding techniques, such as
[6]. Due to the recursive nature of codes discussed in this
paper the Fibonacci sequence is a common occurrence in all
three. Even though the proposed strategy utilizes Fibonacci
numbers for convenience of explanation, it is not limited to
encoding techniques based strictly on Fibonacci sequence. As
an example, the correlation graph of the weight limited
version of the code proposed has been explained.
II. ON-CHIP BUS MODEL WITH CROSSTALK
As a VLSI technology has marched into the deep submicrometer (DSM) regime, new challenges have been
presented to circuit designers. As one of the key challenges,
performance of a bus based interconnects has become a
bottleneck to the overall system performance. In large
designs e.g., systems-on-chip (SoCs) where wide global
busses are used, long and interconnect delays often dominate
logic delays. Once negligible, crosstalk has become a major
determinant of the total power consumption and on-chip bus
delay for the impact of crosstalk in on-chip busses has been

Fig.1. On-chip bus model with crosstalk


adjacent signal lines of the bus. In practice, this bus structure
is electrically modeled using a distributed (RC) resistancecapacitance network, after parasitic resistance including the
wire as well (not shown in Fig. 1). For DSM processes, CI is
much greater than CL. Based on the energy consumption and
delay models given in, the energy consumption is a function
of the total crosstalk over the entire bus. The delay, which
determines the maximum crosstalk and the maximum speed
of the bus, is limited by any wire in the bus it has been shown
that reducing the crosstalk can boost the bus performance
significantly.
Different approaches have been proposed for reducing
crosstalk by eliminating specific data transition patterns.
Some schemes focus on reducing the energy consumption,
while others focus on minimizing the delay. Certain schemes
offer improvements in both. In this paper, we focus on
crosstalk avoidance for delay reduction. As the crosstalk is
dependent on the data on the bus transition patterns, can be
classified based on the severity of the crosstalk they impose
on the bus more detailed explanation of pattern classification.
The general idea behind techniques that improve on-chip bus
speed is to remove undesirable patterns that are associated
with certain classes of crosstalk. Among the proposed
schemes, some are more aggressive than others (they remove
more patterns and achieve higher speed improvements).
Different schemes incur different area overheads since they
require spacing between wires or both additional wires. As
one of the simplest techniques to eliminate the crosstalk
induced delay penalty, passive shielding inserts passive (e.g.,
grounded) shield wires between adjacent active data lines.
This technique can reduce the bus delay by nearly 50%.
However, it requires doubling the number of wires and hence
incurs an area overhead 100%. Crosstalk can also be
exploited to speed up the bus. Techniques such as active
shielding can reduce the bus delay by up to 75% at the price
of 200% or more area overhead.

International Journal of Scientific Engineering and Technology Research


Volume.03, IssueNo.28, September-2014, Pages: 5674-5677

An Efficient Avoidance of On-Chip Codeword Generation to Cope with Crosstalk


It has been discovered relatively recently that encoding the
permutations also grows rapidly. For example, to encode the
bus can eliminate some classes of data patterns with much
8-bit data to an 11-bit CAC bus, there are over 6 106
lower area overhead compared to the shielding techniques.
possible mapping permutations.
These codes are commonly referred to as crosstalk avoidance
codes (CACs). CACs can be further divided into two
In addition, the CAC codes are non-linear and therefore it
categories: memory-less and memory-based. The memoryis difficult to extend a mapping scheme for smaller busses to
based coding approaches generate a codeword based on the
larger busses. Several different schemes have been proposed
previously transmitted code and the current word data to be
for CODEC construction for FPF-CAC or other memory-less
transmitted on the data is recovered based on the receiver
CAC. These schemes are bus partitioning, which breaks up
side, and the received code words from the previous and
all based on wide bus into smaller groups or lanes (typically
current cycles. The memory-less coding approaches use a
3 to 5 bits) and exhaustively searches for the optimal
fixed code book to generate a transmit codeword to, solely
mapping that yields for the groups most efficient CODEC it
based on the input data. The corresponding receiver decoder
is unfortunately, in order to handle the group boundaries,
uses the current received codeword as the only input to
crosstalk across, these schemes all inevitably suffer from
recover the data. The theoretical lower bound of the area
additional area overhead. In this section, we propose two
overhead for memory-based codes is lower compared to
coding schemes that allow us to encode data to the FPF-CAC
memory-less codes. However, the memory-based CODECs
without partitioning the bus. These coding schemes allow us
are much more complex and the only known codeword
to systematically construct the FPF-CAC CODECs for busses
generation method is an exhaustive search and pruning-based
of arbitrary size. Bysystematically, we mean that the
method.
CODEC for a larger size bus is extended from the CODEC of
a smaller bus. The gate counts of the proposed CODEC
Several different types of memory-less CACs have been
implementation roughly grow quadratic ally with respect to
proposed. The code designs are discussed. These codes offer
the bus size, instead of exponentially for previous
the same degree of delay reduction as the passive shielding
approaches. Both our schemes are based on the Fibonacci
technique, with much less area overhead (ranging from 44%
numeral system.
to 62.5%). Unfortunately, none of the referred papers
addresses the mapping between data words and code words
IV. SIMULATION RESULTS
for the CODECs. So far, all the CODEC design approaches
are based on bus partitioning (which breaks a big bus into a
number of small groups (lanes) and applies CAC coding on
each group independently). Such an approach has to deal
with the crosstalk across the group boundaries. Several
different schemes are proposed to handle this inter-group
crosstalk, such as group inversion and bit overlapping. In all
cases, more wires are needed and therefore the overall area
overhead is higher than the theoretical lower bound.
III. FPF-CAC CODEC DESIGN
As discussed in the previous section, the 3C and 4C
crosstalk classes can be avoided if the bus is encoded using
the FPF code. We provided the recursive procedure for
generating the code words and showed how to compute the
total number of code words and the lower bound for the area
overhead. However, the mapping scheme between the input
data words and the output code words was not discussed, nor
was it shown how a CODEC for the FPF-CAC can be
constructed. Conceptually, the mapping between the data
words and the code words is flexible, provided it can be
reversed by the decoder. In the case of the code book is not a
power of two, a 1-to-1 mapping is not required when the size.
A 1-to-many mapping for certain data words may reduce the
CODEC complexity further. mWhen the data bus width is
small, the CODEC can be implemented and the mapping
flexibility can be exploited to optimize the speed and/or the
area of the CODEC. However, as the data bus width
increases, the CODEC size grows exponentially the number
of 2-input gates required for CODECs of data bus widths
varying from 3 to 121 the total number of mapping

Fig.2. Mapping 4-Bit Nat Code to 3-Bit Data.

Fig.3. Mapping 4-Bit OTEE Code to 3 Bit Data

International Journal of Scientific Engineering and Technology Research


Volume.03, IssueNo.28, September-2014, Pages: 5674-5677

P.MAHESWARI DEVI, Y.PENCHALAIAH, N.PUSHPALATHA


[6] C. Duan, A. Tirumala, and S. P. Khatri, Analysis and
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V. CONCLUSION
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The conventional implementation strategy is based on
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explicit enumeration of code words. In case of very wide
buses, such codeword enumeration results in exponential
hardware overhead. Maintaining a codebook is not a practical
approach. Proposed implementation strategy takes advantage
of the iterative structure of the encoding technique. The
encoder/decoder is described as structural HDL models that
use multi-bit adders, comparators, and multiplexers as
building blocks. This makes the strategy scalable for very
wide buses. The proposed strategy has been applied to a
variety of encoding techniques. The properties an encoding
technique must possess to be implementable using the
proposed strategy are described in this paper. Three of the
existing encoding techniques that fit the criteria were
implemented using proposed strategy with encouraging
outcomes. All three encoding techniques exhibit similar
scalable trends in areas such as hardware overhead, power
consumption, memory requirements and time complexity.
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International Journal of Scientific Engineering and Technology Research
Volume.03, IssueNo.28, September-2014, Pages: 5674-5677