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Ladder Logic
Learning objectives
E l i the
Explain
th operation
ti off TON,
TON TOF,
TOF and
d RTO timers
ti
Explain
p
the use of CTU and CTD timers
Timers
Overview
Ti
Timers
are used
d to
t delay
d l actions
ti
Block-Type Timer
E
Example
l
TON
I:2
TIMER ON DELAY
Timer
Time Base
Preset
Accum
EN
T4:0
0.1
50
0
DN
Time Base:
Timers are typically
yp
yp
programmed
g
with several different time bases
Block-Type Timer
Example
TON
I:2
TIMER ON DELAY
Timer
Time Base
Preset
Accum
EN
T4:0
0.1
50
0
DN
Preset Attribute:
Preset value is the number of time increments timer must count
before changing the state of the output
Block-Type Timer
Example
TON
I:2
TIMER ON DELAY
Timer
Time Base
Preset
Accum
EN
T4:0
0.1
50
0
DN
Accum Attribute:
[Rockwell] Timers have one input. When the input transits from low
to high, the timer will begin timing (Accum value)
Timers that do not lose their accumulated time when the enable input line
transitions to low again are known as Retentive Timers
Retentive Timers continue to maintain accumulated time and increment
the time when the input line goes to high again
Non-retentive Timers lose the accumulated time whenever the enable
input transitions to low
Timer Block
Numbering System
TON
I:2
TIMER ON DELAY
Timer
Time Base
Preset
Accum
EN
T4:0
0.1
50
0
DN
Timer
T4:0
T
4
:
0
File Type
Fil
T
(Timer)
(Ti
)
File Number of the Timer
Delimiter
Element (The actual timer number)
Block-Type Timer
E
Example
l
TON
I:2
TIMER ON DELAY
Timer
Time Base
Preset
Accum
EN
T4:0
0.1
50
0
DN
Timer On Delay
y Instruction:
Turns an output on after a Timer has been on for a preset time
interval
Block-Type Timer
Status Bits (EN, DN, TT)
Bit
S t When
Set
Wh
R
Remains
i Set
S t Till
Accumulated value is
equal to or greater than the
preset value
The Timer Enable (EN) bit is set immediately when the rung
goes true. It stays set until the rung goes false
10
C
Consider
id timer
ti
T4
T4:0
0 from
f
the
th example:
l
The Timer Timing (TT) bit is set when the rung goes true. It stays
set until the rung goes false or the Timer Done (DN) bit is set (i
(i.e.,
e
when accumulated value equals preset value)
11
The Timer Done (DN) bit is not set until the accumulated value is
equal to the preset value. It stays set until the rung goes false
12
Time Base
1 Second
0 01 Second
0.01
To 32,767
32 767 intervals (up to
5.5 minutes)
0.001 Second
13
Memory Storage
Timers
15
14
13
EN
TT
DN
12
11
10
Internal Use
Bits
0 T4:0
Preset Value
1 T4:0.PRE
Accumulated Value
2 T4:0
T4:0.ACC
ACC
Current status of timer bits (EN, TT and DN) stored in first 16 bits
14
TON Timer
Ladder Diagram
TON
I:2
3
T4:0
EN
T4:0
1.0
180
0
DN
O:5
TT
T4:0
DN
1
O:5
2
When input I:2/3 is true timer begins to increment the accumulated value of TON Timer
T4:0 in 1 second intervals
The TT bit is used in rung 2 to turn on Output O:5/1, while the timer is timing (ACC <PRE)
The DN bit of timer 4:0 is used in rung 3 to turn an output O:5/2 when the timer is done
timing (ACC = PRE)
Note: the Preset for this timer is 180 The timer will have to accumulate 180 1-second intervals to time
out
Note: This is a non-retentive timer: If Input I:2/3 goes low before 180 is reached, the accumulated value
is reset to zero
15
1.
2.
3.
4.
16
Bit
S t When
Set
Wh
R
Remains
i Set
S t Till
17
Ladder Logic
TOF Timer
TOF
I:2
3
EN
T4:0
1.0
180
0
T4:0
This output is energized while the timer is timing
DN
O:5
TT
T4:0
DN
When input I:2/3 transitions from true to false The ACC value is incremented
as long as the input stays false and ACC PRE
The TT bit for timer T4:0 (T4:0/TT) is used to turn output O:5/1 on while timer is
timing
The DN bit of timer 4:0 (T4:0/DN) is used to turn on output O:5/2 when the timer
has completed the timing (ACC = PRE)
18
Retentive Timer On
RTO
RTO Instruction:
1.
2.
To zero the ACC value, use a reset (RES) instruction in another rung with
the same address as the RTO
19
Retentive Timer On
Status Bits
Bit
Set When
Accumulated value
preset value
20
Ladder Logic
RTO Timer
RTO
I0:2
3
I0:2
EN
T4:0
10
1.0
180
0
DN
T4:0
RES
TT bit is set when rung becomes true and remains set until ACC value equals
the preset value or RES instruction resets the timer
DN bit is set when the timers ACC value is equal to the preset value
21
Cascading Timers
Cascading Timers
TON
O
I:2.0
1
TIMER ON DELAY
Timer
Time Base
Preset
Accum
EN
T4:0
1.0
32,767
0
DN
TON
T4:0
DN
TIMER ON DELAY
Timer
Time Base
Preset
Accum
EN
T4:1
1.0
7233
0
DN
T4:1/DN turns on
What is the delay?
23
Counters
Primaryy Counter
C
Types
yp
UP Counters
Down Counters
Up/Down Counters
many are coming and how many are leaving to determine total number in stock
Counters
A ib
Attributes
Counters (CTU)
Edge-Triggered
Edge
Triggered
CTU
I:2
Count Up
Counter
Preset
Accum
EN
C5:0
10
0
DN
C5:0
O:5
Input I:2/3
Status
On
Of
Output O:5/1 On
Of
Status
0
10
11
Each time there is an Of to On transition, the Counter increments its count by 1 (CTU)
When the Accumulate count equals the preset value, the counter turns on
26
Counters
Numbering System
How counters are addressed:
C5:0
C
5
:
0
File Type
File Number of the counter
Delimiter
Element (The actual counter number)
27
C5 4 DN
C5:4.DN
C5:4.PRE
C5:4.ACC
28
Memory Storage
CTU Counter Bits
15
Bits
CU
13
12
DN
OV
11
10
Internal Use
Element
0 C5:0
Preset Value
1 C5:0.PRE
Accumulated Value
2 C5:0
C5:0.ACC
ACC
Count Up
p ((CU),
), Done ((DN)) and Overflow ((OV)) bits are stored in first 16 bits
The CPU sets the OV bit when the counter exceeds upper limit +32,767
14
ACC wraps around to -32,767 and continues from there towards zero
29
Bit
S t When
Set
Wh
R
Remains
i Set
S t Till
Done bit
(bit 13 or DN)
Count-Up Counter
Ladder Diagram
CTU
I:2
3
COUNT UP
Counter
Preset
Accum
EN
C5:0
4
0
C5:0
Energized
g
when the Accumulated Preset
DN
O:5
DN
C5:0
Energized
g
when the counter overflows
O:5
OV
The DN bit is set when the ACC value the Preset value
The DN bit of C5:0 (C5:0/DN) is used to turn on O:5/1 when ACC Preset value
The OV bit of C5:0 (C5:0/OV) is used to set O:5/2 when <What happens?>
31
Count-Up Counter
Ladder Diagram
CTU
I:2
3
COUNT UP
Counter
Preset
Accum
EN
C5:0
4
0
C5:0
Energized
g
when the Accumulated >= Preset
DN
O:5
DN
C5:0
Energized
g
when the counter overflows
O:5
OV
I:2
Reset
ese cou
counter
e to
o zero
eo
C5:0
RES
32
Count-Down Counter
Ladder Diagram
CTD
I:2
3
COUNT DOWN
Counter
Preset
Accum
CD
C5:0
4
0
C5:0
Energized
g
when the Accumulated Preset
DN
O:3
DN
C5:0
Energized
g
when the counter underflows
O:3
UN
I:2
Resets
ese s cou
counter
e to
o zero
eo
C5:0
RES
Each time input I:2/3 makes a 01 transition, the counter ACC value gets decremented by1
The DN bit is set when the ACC value the Preset value
The DN bit of C5:0 (C5:0/DN) is used to turn output O:3/1 on when Accum Preset value
The UN bit of C5:0 (C5:0/UN) is used to set OUTPUT O:3/2 ON when the ACC value
underflows (-32,768)
Input I:2/1 is used to reset the C5:0s ACC value to zero
33
Bit
S t When
Set
Wh
R
Remains
i Set
S t Till
Done bit
(bit 13 or DN)
Memory Storage
CTU and CTD Counter Bits
Bits
15
14
13
12
11
CU
CD
DN
OV
UN
Internal Use
Element
0 C5:0
Preset Value
1 C5:0.PRE
Accumulated Value
2 C5:0
C5:0.ACC
ACC
ACC wraps around to -32,767 and continues incrementing from there towards
zero to +32,767
The CPU sets the UN bit when the counter exceeds lower limit -32,767
Count Up (CU), Count Down (CD), Done (DN), Overflow (OV) and
Underflow (UN) bits are stored in first 16 bits
The CPU sets the OV bit when the counter exceeds upper limit +32
+32,767
767
10
35
Cascading Counters
CTU
I:2.0
1
COUNT UP
Counter
Preset
Accum
EN
C5:0
24
0
DN
CTU
C5:0
DN
COUNT UP
Counter
Preset
Accum
EN
C5:1
5000
257
DN
C5:0
RES