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Chapter 9: Inverters

THREE-PHASE BRIDGE INVERTER WITH


INPUT-CIRCUIT COMMUTATION

Instead of commutating each inverter thyristor individually, it is possible to


employa method known as input-circuit commutation or d.c.-side commutation,
in which the inverter circuit is commutated as a whole. The next set of thyristors
in sequence is gated when all conducting thyristors have been turned-off. This
commutation technique is also used to extinguish simultaneously all thyristors
connected to one rail of the d.c. supply. Commutation alternate between the
positive and negative rails. A typical commutating circuit for this purpose is
shown in Fig. 9.1, where it is connected at the input terminals of the three-phase
bridge inverter. The commutating circuit consists of four thyristors TA , T B, TC
and T D, in a bridge connection with a commutating capacitor C. There are two
identical commutating inductors, L 1 and L 2, in the positive and negative supply
rails, and these are shunted by freewheeling diodes DA and DB . It should be noted
that the inverter feedback diodes D1 to D6 are connected directly to the input d.c.
terminals.

Fig. 9.1

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Three-phase bridge inverter with input-circuit commutation

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The operation of the commutating circuit proceeds as follows. Assume that


thyristors T 1, T 2 and T 3 are conducting, so that load terminals A and B are
connected to the positive d.c. rail and terminal C is connected to the negative rail.
A d.c. supply current, Id, is established in the upper and lower commutating
inductors, and capacitor C is charged to the d.c. supply voltage, Ed.c., with the
right-hand plate negative, from previous operation. Suppose that it is desired to
commutate SCR T1 prior to gating T 4. The gating pulses to the upper thyristors,
T 1 and T 3, are removed but the gating of T 2 continues. Commutation is initiated
by simultaneously gating the two auxiliary thyristors, T B and T C, thereby
connecting the negative terminal of the charged capacitor to the upper rail of the
inverter and diverting the d.c. current, Id, through L 1, TB , capacitor C, and T C. A
voltage of 2Edc is impressed across the upper inductor, L 1, and the upper
thyristors, T 1 and T 3, are subjected to a reverse voltage of Edc because the inductive
load current transfers to the feedback diodes, D4 and D6, thereby clamping
terminals A and B to the negative d.c. supply terminal. Thyristor T2 continues to
conduct the freewheeling load currents which circulate through T 2, inductor L 2,
and feedback diodes D4 and D6. Thus, all line-to-line voltages are reduced to zero
during this interval.
As explained above, the inverter d.c. current is diverted into the commutating
capacitor C, when thyristor TB and TC are triggered. This current gradually reduces
the capacitor voltage to zero and then charges it up with the opposite polarity,
leaving it ready for the next commutation of the lower group thyristors. The
circuit designer must ensure that the negative voltage on capacitor C is maintained
for a time toff that exceeds the thyristor turn-off time tq.
During the oscillatory charging of capacitor C, the current in inductor L 1
increases from its initial value of Id to a final value of Imax when the capacitor is
charged to a voltage Edc with a right-hand plate positive. There is no overshoot of
capacitor voltage because the inductor current Imax which was flowing in L 1, TB ,
C and T C now circulates in inductor L 1 and freewheeling diode D1, thereby
allowingthyristors T B and T C to turn-off. The surplus magnetic field energy in
L 1, due to its excess current, represents trapped energy that is dissipated in
circuit resistance by the circulating current. The commutating circuit is usually
designed to reduce this trapped energy to a minimum to maximizing the
commutation efficiency. On this basis, the circuit components required to
commutate a maximum d.c. current of Id(max) are
L = 1.82
and

C = 1.47

Edc t q

(9.1)

I d (max)
I d (max) t q

(9.2)

Edc

Following successful commutation of the upper group of thyristors, the next


inverter conduction sequence is initiated by gating T 3 and T 4, to leave T 2, T3 and
T 4 as the three-gated thyristors.

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The major advantage of input-circuit commutation is that multiple thyristor


turn-off is possible with a reduced number of commutating components but the
trapped energy may be appreciable.

1 Single-phase Auto-sequential Commutated


Inverter (Single Phase ASCI)
Figure 9.2 shows the single-phase version of the common auto sequentially
commutated inverter circuit. It should be noted that the forced commutating
circuit components are included. The two capacitors store the energy necessary
for commutation. The four series diodes effectively prevent the capacitors from
discharging through the load in the interval between inverter commutations.
Thyristor pair T 1, T2 and T 3, T 4 are alternatively switched to obtain a nearly
square-wave load current. As usual, the triggering frequency of the thyristors
determines the output frequency. The circuit behaviour during the commutation
interval is highly load dependent. If the inverter feeds a passive RL load, the
voltage and current waveforms are as shown in Fig. 9.3. The circuit operation
proceeds as follows:

Fig. 9.2

ASCI with series RL load

In this mode between commutations, the constant source current I


is flowing in the load, and hence the load voltage is RI. Thyristors T1 and T2 are
conducting, and the current I is established in the circuit consisting of T1, D1, the
load, D2 and T2. The capacitors C1 and C2 are charged to a voltage V c = +EL
from the previous half-cycle. Note that EL is greater than the load voltage RI, as
shown in Fig. 9.3.
Mode 1:

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Fig. 9.3

Voltage and current waveforms

When thyristors T 3 and T 4 are gated-on, the capacitors C1 and C2


apply a reverse-bias to thyristors T1 and T 2, respectively, causing them to turnoff. However, the load current I continues to flow in the same direction as before,
through T 3, C1 D1 the load, D2, C2 and T 4. The capacitors are in series with the
load and are discharged by the constant current I. When the capacitor voltages
have fallen from EL to R 1, diodes D4 and D3 conduct and Mode 2 is terminated.
Mode 2:

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Thyristors T 3 and T 4, and all four-diodes are now conducting so that


the load is effectively connected in parallel with both commutating capacitors.
This RLC circuit undergoes a transient response during which the load current
falls to zero and reverse. When a load current attains a value I, diodes D1 and
D2 become reverse biased. This terminates Mode 3 and completes the commutation
process.
Mode 4: For the next half-cycle, the source current I is flowing through T 3,
D3, the load, D4, and R 4. Note that the capacitor voltage is now EL , as shown in
Fig.9.3(d), and the capacitor hold this voltage until the next commutation.
The d.c. current source delivers a unidirectional current I to the inverter, and
when the inverter feeds a reactive or regenerative load, the d.c. supply current
cannot reverse as it did in the case of a VSI. However, the feedback diodes of
VSI have been removed, allowing the d.c. link voltage to change polarity and
permitting a return of energy to the d.c. link by virtue of a reversal of d.c. link
voltage rather than a reversal of d.c. link current. When T 3 and T4 are gated to
initiate Mode 2, the inverter input voltage, Edc, goes negative, as shown in Fig.
9.3(e), and remains negative throughout this interval. Hence, the input power
Edc. I is also negative, indicating that power is being returned to the d.c. current
source.
Mode 3:

Three-phase Current Source Inverter

The three-phase bridge current source is formed by adding a third leg, or half
bridge, to the single-phase circuit of Fig. 9.2. The resulting autosequentially
commutated inverter is used to deliver adjustable frequency a.c. power to a
cage-rotor induction motor or synchronous motor, giving a rugged a.c. motor
drive. In a synchronous motor drive, the auxiliary commutating circuits may be
employed for starting the motor, but when the motor runs at more than 10 per
cent of rated synchronous speed, the generated emfs of the synchronous machine
are adequate for load commutation of the inverter thyristors, and the commutating
circuit is rendered inoperative.
The d.c. link converter is given the characteristics of a controlled current
source by removing the shunt capacitor in the d.c. link and employing a current
regulation loop to control the output d.c. current from the phase controlled rectifier,
as shown in Fig. 9.4 signal representing the desired current is compared with the
actual current, as measured on the d.c. or a.c. side of the rectifier. The difference
is amplified and used to control the rectifier delay angle so that the required
current value is obtained. A large series inductor in the d.c. link circuit filters the
output current from the controlled rectifier. If the polarity of the d.c. link voltage
reverses, the phase controlled converter can function as an inverter, returning
power to the a.c. supply network. Consequently, this converter configuration, in
which a thyristor rectifier feeds a current source inverter, has an inherent
regenerative capability that is advantageous in many drive applications. A drive
rectifier bridge, followed by a current regulated d.c. chopper, is sometimes used
as a non-regenerative current source for the CSI.

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Fig. 9.4

Phase-controlled thyristor rectifier operating as a


controlled current source for a CSI

Figure 9.5 shows the three-phase autosequentially commutated inverter feeding


a balanced star-connected RL load. The path of the regulated input current, I,
through the inverter and load phases is governed by the particular inverter thyristors
that are gated into conduction. In Fig. 9.6, the six thyristors, T1 to T6, are numbered
in the sequence in which they are gated, and each thyristor conducts for 120 of
the output period. The gating of one thyristor cause an adjacent conducting
thyristor of another phase to turn-off, and so establishes the 1 2 0 conduction
pattern. The two banks of delta-connected capacitors store the energy necessary
for commutation, and the six blocking diodes, D1 to D6, isolate the capacitors
from the load.
The inverter conduction sequence is such that the regulated source current, I,
is directed through a pair of conducting thyristors, one connected to the positive
d.c. rail and the other connected to the negative rail. There is a 60 interval in
each half-cycle during which both thyristors in the same half-bridge are turnedoff, and the corresponding a.c. line current is zero. Assuming instantaneous
commutation, the line current has the quasi-square waveform as shown in Fig.
9.5, which is identical to the line-to-line output voltage waveform of a six-step
VSI. Fourier-analysis of the current waveform gives the expression

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iA =

2 3
1
1
I sin w t sin 5w t sin 7w t
p
5
7

1
1

sin 11w t + sin 13w t L


11
13

(9.3)

Thus, the fundamental component of a.c. line current has an amplitude of

2 3I p , and RMS value of 6 I /p or 0.78I.


The unique relationship between input and output voltage magnitudes for the
six-step VSI has its counterpart in the unique relationship between input and
output current magnitudes for the current-fed inverter. If the CSI feeds the
balanced delta-connected load of Fig. 9.6(a), the phase current has the six-step
waveform of Fig. 9.6(b), which is characteristic of the line-to-neutral voltage
for a balanced star-connected load fed by a six-step VSI. By Fourier analysis:
iR =

2
1
1
I sin w t + sin 5w t + sin 7w t
p
5
7
1
1

+ sin 11w t + sin 13w t + L


11
13

(9.4)

Clearly, the current waveforms delivered by the six-step CSI have pronounced
low order harmonics. In an a.c. motor drive, these harmonics give rise to pulsating
torques and irregular shaft rotation at low speeds, as in the case of six-step VSI
drive.
When an electrical load is fed from an a.c. current source, the terminal voltage
waveform is determined by the response of the load to the applied current. The
di
di
is the rate of change of current.
voltage across the inductor L is L , where
dt
dt
Consequently, the idealised current waveforms of Figs 9.5 and 9.6 cannot be
realized with practical inductive loads because the instantaneous step changes in
current would develop voltage spikes of infinite amplitude. In practical circuits,
the rate of change of load current must be limited to keep the terminal voltage
within the peak voltage capability of the inverter thyristors. The commutation
interval, during which load current is transferred from phase-to-phase, must be
sufficiently long to reduce the rate of change of current to an acceptable value.
This constraint does not drive in a VSI because the feedback diodes provide a
path for inductive load currents to charge the d.c. link capacitor. This arrangement
prevents rapid interruption of load current and clamps the inverter output voltage.
In a CSI, however, there are no reverse current paths because the feedback
diodesare removed, and the commutation interval can only be shortened at the
expense of increased voltage stresses on the inverter devices.

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Fig. 9.5 ASCI (a) Circuit diagram: (b), (c), (d) idealized a.c. line current
waveform; and (e) thyristor gating sequence

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Fig. 9.6

Idealized current-waveforms in a balanced delta-connected


load fed by a six-step current source inverter
(a) line-current (b) phase-current

For an induction motor load, the terminal


voltage waveform is determined by the impedance presented to the fundamental
and harmonic components of the inverter output current. At harmonic frequencies,
the input impedance of the motor is effectively the sum of the stators and rotor
leakage reactances. The reactances are large at harmonic frequencies but are
relatively small at fundamental frequency. Consequently, fundamental and harmonic
effects can be separated and the induction motor represented by the approximate
equivalent circuit of Fig. 9.7(a), in which the total leakage inductance per phase,
L, is placed in series with each of the fundamental phase voltage sources, Ea, Eb ,
and Ec. When the induction motor is fed from a current source, the terminal
voltages are obtained by superposition of the fundamental voltages, Ea, Eb and
di
voltages developed across the leakage inductances.
Ec, and the L
dt
Induction Motor Voltage Waveforms:

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Fig. 9.7

An induction motor fed by a six-step CSI. (a) Approximate


induction motor equivalent circuit; and (b), (c),
(d) voltage and current waveforms

di
is zero except when a step
dt
change in current occurs. Consequently, the terminal voltage is a fundamental
sine-wave with superimposed voltage spikes, as shown in the phase and line
voltage waveforms of Fig. 9.7. The position of the voltage spikes on the motor
voltage waveform clearly depends on the fundamental power factor. These
commutation voltage spikes must not cause the blocking voltage capability of the
inverter thyristors to be exceeded. This voltage restraint is ensured by employing
an induction motor with a small leakage reactance and extending the commutation
interval so that the rate of change of current is not excessive.
In the case of a six-step current supply, L

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Commutating circuit analysis The ASCI has a relatively simple circuit, but an
analysis of the commutating action is complicated due to the fact that the
commutating phase interacts with the other two phases and the motor load.
Figure9.8 shows the CSI feeding a star-connected induction motor. Inverter
operation is assumed to be in a steady state condition with motor speed constant.
The commutating cycle proceeds as follows:
Mode 1: In this mode, the inverter is in the normal operating mode between
commutations. Assume thyristors T 1 and T2 have been conducting for sometime,
so that phases A and C carry current but phase B does not. The resulting current
path is shown in Fig. 9.8(a). Capacitors C1, C3 and C5 are assumed to be charged
with the voltages EL , zero, and EL , respectively. When the inverter is first
switched ON, the capacitors must be precharged with a voltage distribution of
this nature, but the auxiliary precharging circuit is not needed subsequently.

When thyristor T 3 is triggered, T 1 is reverse-biased by the voltage on


capacitor C1, and turn-off. As shown in Fig. 9.8(b), the current I, which was
flowing in T1, is now flowing through T3, the capacitor bank formed by C1 in
parallel with C3 and C5, and diode D1. During this charging interval, the constant
source current, I, linearly charges the capacitor bank. The outgoing thyristor, T 1,
is reverse-biased until the motor phase currents have the same values as existed
during Mode 1. This charging mode ends when diode D3 starts to conduct.
Mode 2:

This is the current transfer mode during which motor current transfers
from phase A to phase B, as shown in Fig. 9.8(c). When diode D3 conducts, the
upper capacitor bank is connected in parallel with the motor through diodes D1
and D3. The resulting LC circuit resonates, and in one quarter of the resonant
period the oscillatory current reduces the phase A current from I to zero, and
increase the phase B current from zero to I. Diode D1 then blocks, and the
commutation cycle is complete.
Mode 3:

The source current I is now feeding phases B and C through thyristors


T 3 and T 2, as shown in Fig. 9.8(d). This condition lasts until T 4 is gated to initiate
the next commutation. Because D3 is the only conducting diode in the upper
group, the upper capacitor group retains its charge until the next upper group
commutation.
The duration of transfer Mode 3 determines the rate of change of motor phase
di
current and the magnitudes of the resulting L voltage transients developed across
dt
the motor leakage inductances. These voltage spikes appear in the output voltage
waveform, as discussed previously and shown in Fig. 9.7. A large value of
commutating capacitance prolongs transfer Mode 3 and thereby limits the voltage
stresses on the inverter devices. The increased commutating time is, therefore, of
adequate duration to permit the use of low-cost, converter-grade thyristors rather
than expensive, inverter-grade devices with fast turn-off characteristics.
Mode 4:

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Fig. 9.8 (Continued)

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Fig. 9.8

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Commutation process in three-phase ASCI

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The commutation cycle described above is applicable at low-output frequencies,


when commutations in the upper and lower groups do not overlap. As the output
frequency of the inverter is increased, partial overlap occurs when the charging
Mode 2 commences in the upper (lower) group before the current transfer Mode
3 is completed in the lower (upper) group. As the inverter frequency is increased
further, the current transfer mode may occur simultaneously in both upper and
lower groups. This so-called multiple commutation effect, or full commutation
overlap, results in a current by-pass effect in which a portion of the source
current, I, is diverted from the motor by two conducting diodes in the same
inverter leg. This diversion of current causes a reduction in the power input to
the motor for a given source current and adversely affects the output torque
capability, efficiency, and stability of the drive.
Large commutating capacitors have a beneficial effect in reducing inverter
voltage stresses but they also lower the operating frequency at which the current
by-pass effect occurs, and so limit the useful frequency range of the inverter.
Consequently, it may be desirable to reduce the commutating capacitance and
limit voltage stresses by means of a voltage clamping circuit. This may consist of
three-phase diode bridge rectifier connected in parallel with the CSI across the
motor terminals and feeding a series string of zener diodes that determine the
clamping voltage level.

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