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Unlike bipolar transistors, JFETs are exclusively voltagecontrolled in that they do not need a biasing current.
Electric charge ows through a semiconducting channel between source and drain terminals. By applying
a reverse bias voltage to a gate terminal, the channel
is pinched, so that the electric current is impeded or
switched o completely. A JFET is usually on when there
is no potential dierence between its gate and source terminals. If a potential dierence of the proper polarity is
applied between its gate and source terminals, the JFET
will be more resistive to current ow, which means less
current would ow in the channel between the source and
drain terminals. Thus, JFETs are sometimes referred to
as depletion-mode devices.
3 Function
I DS
VDS
SAT
VGS - VP
Saturation region
VGS0 = 0
VGS1 < VGS0
VGS2 < VGS1
Saturation
region
Channel
V o
GS
VP
Linear
region
VDS
JFETs can have an n-type or p-type channel. In the ntype, if the voltage applied to the gate is less than that
applied to the source, the current will be reduced (similarly in the p-type, if the voltage applied to the gate is
greater than that applied to the source). A JFET has a
large input impedance (sometimes on the order of 1010
ohms), which means that it has a negligible eect on external components or circuits connected to its gate.
I DS
Linear region
History
6 MATHEMATICAL MODEL
In normal operation, the electric eld developed by the symbol is usually drawn without the circle when drawgate blocks source-drain conduction to some extent.
ing schematics of integrated circuits. More recently, the
Some JFET devices are symmetrical with respect to the symbol is often drawn without its circle even for discrete
devices.
source and drain.
Schematic symbols
D
G
S
6 Mathematical model
D
G
ID =
bW
qNd n VDS
L
where
ID = drainsource current
S
Circuit symbol for a p-Channel JFET
In every case the arrow head shows the polarity of the PN junction formed between the channel and the gate. As
with an ordinary diode, the arrow points from P to N, the
direction of conventional current when forward-biased.
An English mnemonic is that the arrow of an N-channel
device points in".
3
In terms of IDSS , the drain current can also be:
ID
6.2
2IDSS
=
VP2
(
)
VDS
VGS VP
VDS
2
Saturation region
The drain current in the saturation region is often approximated in terms of gate bias as:[3]
IDS
(
)2
VGS
= IDSS 1
VP
9 External links
Physics 111 Laboratory -- JFET Circuits I pdf
Interactive Explanation of n-channel JFET
where
IDSS is the saturation current at zero gate
source voltage, i.e. the maximum current
which can ow through the FET from drain
to source at any (permissible) drain-to-source
voltage (see, e. g., the I-V characteristics diagram above).
In the saturation region, the JFET drain current is most
signicantly aected by the gatesource voltage and
barely aected by the drainsource voltage.
If the channel doping is uniform, such that the depletion
region thickness will grow in proportion to the square root
of the absolute value of the gatesource voltage, then the
channel thickness b can be expressed in terms of the zerobias channel thickness a as:
b=a 1
VGS
VP
where
VP is the pinch-o voltage, the gatesource
voltage at which the channel thickness goes to
zero
a is the channel thickness at zero gatesource
voltage.
8 References
See also
Constant-current diode
Fetron
10
10
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