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Code No: V3108 / R07


Set No. 1

III B.Tech I Semester Regular Examinations Nov2009

COMPUTER SYSTEM ORGANIZATION


(Electrical & Electronics Engineering)

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Time: 3 hours Max. Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
*****
1. (a) Write the algorithm for multiplying two floating point numbers.
(b) Multiply 0.45x1049 and 0.50x1049
(c) Add 0.147x103 and 0.789x103[6+5+5]

2. (a) Construct a common bus system with multiplexers for four registers.
(b) Discuss the type of instruction formats with examples.[7+9]

3. (a) Write the micro-operation for the following instructions


(i) BSA (ii) BUN (iii) LDA
(b) What is interrupt cycle? Draw the flow chart which shows how computer
Handles the interrupt.[6+10]

4. (a) how is an instruction mapped to a microinstruction address.


(b) Give the implementation of conditional branching with multiplexers.[8+8]

5. (a) Explain briefly about dynamic random access memory with a neat diagram.
(b) What is the difference between static memory cell and a dynamic memory cell?

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Which of these can be none destructively read out?[8+8]

6. (a) in how many ways data can be transferred from I/O units to or from memory?
Explain.
(b) Explain Daisy chaining method. [10+6]

7. (a) what is meant by pipeline hazard? Explain delay due to data dependency with
An example.
(b) Compare different types of parallel computers.[10+6]

8. (a) Discuss the difference between tightly coupled and loosely coupled
Multi processors.
(b) What is the purpose of system bus controller? Explain how the system can be
Designed to distinguish between references to local memory and references to
Common shared memory?[6+10]
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Code No: V3108 / R07


Set No. 2

III B.Tech I Semester Regular Examinations Nov2009

COMPUTER SYSTEM ORGANIZATION

www.andhracolleges.com
(Electrical & Electronics Engineering)
Time: 3 hours Max.Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
*****
1. (a) Write the steps in subtraction of unsigned numbers.
(b) Illustrate the layered view of a computer system with a diagram.[7+9]

2. How are register reference instructions recognized by the program control? Illustrate
With a flow chart. Give some example for register reference instructions.[16]

3. (a) how is a 64-word stack implemented. Write the micro operations of PUSH and
POP operations.
(b) Convert ABCDE+*-/ into reverse polish notation.
(c) Convert A+B*(C*D+E*(F+G)) into reverse polish notation.[6+5+5]

4. Give the detailed design of micro programmed control unit. Explain.[16]

5. (a) Write the types of ROM? Give Applications of ROM.


(b) Illustrate fully associative mapping with a neat diagram.[8+8]

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6. (a) what is meant by Software Polling?
(b) Illustrate asynchronous read with the help of Timing Diagram[7+9].

7. (a) what are the operations in a three segmented pipeline? Give an example that uses
Delayed load with the three segment pipeline.
(b) Consider the multiplication of two 40 x 40 matrices using a vector processor. How
many product terms are there in each inner product?[8+8]

8. (a) Draw the diagram of a three dimensional hypercube. List all the paths available
from node 2 to 7.
(b) How can the cache coherence problem be solved using cache write back policy?[8+8]
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Code No: V3108 / R07


Set No. 3

III B.Tech I Semester Regular Examinations Nov2009

COMPUTER SYSTEM ORGANIZATION

www.andhracolleges.com
(Electrical & Electronics Engineering)
Time: 3 hours Max. Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
*****
1. (a) Multiply the following numbers represented in two’s complement form
(i) 0011011 x 1011011
(ii) 101101 x 110011
(b) Represent – (0.625) decimal in binary floating point form
(c) Illustrate the long hand division of binary integers 1011 by 11.[6+4+6]

2. (a) Draw the diagram of a bus system for four registers. Use three state buffers and
a decoder instead of multiplexers.
(b) Illustrate logic micro operations with examples.[8+8]

3. (a) What are the characteristics of RISC processor? Discuss briefly.


(b) What is a subroutine? Write the differences between subroutine and program.[8+8]

4. (a) Give the format of micro instruction. Explain the use of each field in it.
(b) Explain the difference between hardwired control and micro programmed
Control[8+8]

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5. (a) What are the design decisions made in the design of cache memory system?
(b) Compare and contrast the methods of mapping memory to a cache. [8+8]

6. (a) Give the configuration of the DMA interface and its connection to the CPU
Through buses? Explain how the DMA interface functions. [16]

7. (a) Show how instruction cycle in a CPU can be processed with a four segment Pipeline.
(b)Write the pipeline conflicts that cause the instruction pipeline to deviate from
its normal operation. [8+8]

8. (a) Describe the following terminology associated with multiprocessors


i) Mutual exclusion ii) critical section iii) hardware lock
iv) Semaphore
(b) Construct the diagram for an 8x8 omega switching network. Show the switch
setting required to connect input 3 to output 1. [8+8]
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Code No: V3108 / R07


Set No. 4

III B.Tech I Semester Regular Examinations Nov2009

COMPUTER SYSTEM ORGANIZATION


(Electrical & Electronics Engineering)

www.andhracolleges.com
Time: 3 hours Max. Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
*****
1. (a) Represent decimal number 8620 in
i) Self complementary code ii) weighted code iii) EBCDIC
(b)Perform the arithmetic operation (+42) + (-13) and (-42)-(-13) in binary using signed
Two’s complement representation for negative numbers.
(c) Represent the number (+46.5)10 as floating point binary number with 24-bits. The
Normalized fraction mantissa has 16-bits.[6+4+6]

2. (a) Draw the diagram of 4-bit adder sub tractor circuit. Explain Briefly.
(b) What is the difference between a direct and indirect address instruction? How many
References to memory are needed for each type of instruction to bring the operand
Into a processor register. [8+8]

3. Briefly explain the use of overlapped register widows in RISC processor with an
Example.[16]

4. (a) Explain how the mapping from an instruction address can be done by means of read
Only memory?

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(b) Write briefly about symbolic micro instruction with examples. [8+8]

5. (a) How can the virtual address translation be made faster? Illustrate with a block
Diagram.
(b) Define Hit Ratio. How are the hit ratio and cache size related? Doe the hit ration
Increases with cache bits. [8+8]

6. (a) Write the steps for data transfer in program control data transfer.
(b) Describe the types of bus arbitration techniques. [8+8]

7. (a) Write Flynn’s classification of parallel computer.


(b) Write the classification of parallel computers based on mode of accessing memory. [8+8]

8. What is cache coherence? Why is it important in shared memory multi- processor?


Systems? How can the problem be resolved with a snoopy cache controller? [16]
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