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Code No: X0224 II B.Tech I Semester (R07) Regular Examinations, Nov- 2009 SWITCHING THEORY AND LOGIC DESIGN (Com to EEE, EIE, BME, E.CON.E, ECC, ICE) Time: 3 hours Answer any FIVE Questions All Questions carry equal marks Max Marks: 80

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1. a)Convert the following numbers to base 6 ii) to base 10 i) b) Explain error correction and error detection codes with examples. (4+4) (8) 3.

2. a) Reduce the following Boolean expression to the minimum number of literals(2+3+ 3) i) x(x’+Y) ii) xy+x’z+yz iii) (x+y)(x+y’) b) Draw the logic diagrams to implement the following Boolean expressions: (8) i) Y= A + B + B’ (A + C’) ii) Y= iii) Y= A + CD + ABC iv) Y= (A ’+B Simplify the following functions using three variables map? a) F (x, y, z ) = ¦ (0,1,5,7 ) b) A′B + BC ′ + B′C ′ Write short notes on 3 to 8 line decoder? (16)

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4. (16) 5. a) Tabulate the PLA programming table for the four boolean functions listed below: [8]

¦ m(1,2,4,6) m(0,1,6,7) B(x,y,z) = ¦ m(2,6) C(x,y,z) = ¦ m(1,2,3,5,7) D(x,y,z) = ¦

A(x,y,z) =

b) Realize XOR gate using three threshold gates. 1 of 2

[8]

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Code No: X0224

6.

7.

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b) Compare merits and demerits of ripple and synchronous counters. [6] PS A B C D E F G H NS,Z X=0 B,0 E,0 D,1 C,1 B,0 C,1 C,1 C,1 X=1 E,0 D,0 A,0 E,0 D,0 C,1 D,1 A,1

a) Define the following terms in connection with a flip-flop: i) Setup time (ii) Hold time (iii) Propagation Delay (iv) Preset [

[2+2+4+2]

Find the equivalence partition and a corresponding reduced machine in standard form (16)

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8.

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Construct an ASM block that has 3 input variables (A,B,C), 4 output variables (W,X,Y,Z) and 2 exit paths. For this block, output Z is always 1 and W is 1 if A & B are both 1. If C=1 & A=0,Y=1 and exit path 1 is taken. If C=0 or A=1, X=1 and exit path 2 is taken. (16)

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Code No: X0224 II B.Tech I Semester (R07) Regular Examinations, Nov- 2009 SWITCHING THEORY AND LOGIC DESIGN (Com to EEE, EIE, BME, E.CON.E, ECC, ICE) Time: 3 hours Answer any FIVE Questions All Questions carry equal marks Max Marks: 80

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1. 2. 3. 4. 5. Simplify the following Boolean expression using three- variable map.(8+8) a) F ( A, B, C ) = ¦ (0,2,3,4,6) b) xy + x ′y ′z ′ + x ′yz ′ Explain the operation of priority Encoder?

a) What is self complementary code? Explain with two examples. ( 8 ) b) Given that ( 4+4) i) ii) determine the value of the b a) List the truth table of the function ( 9) i)F= xy + xy’+ y’z ii) F= x’z + yz iii) F= x’z+xy b) given AB’+A’B=C show that AC’+A’C=B. (7)

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6. 7. Obtain the equivalent classes using partition method and give proper assignment PS NS,Z X=0 F,0 D,0 F,0 G,1 D,0 F,1 G,0 G,1 1 of 2 (16) A B C D E F G H X=1 B,0 C,0 E,0 A,0 C,0 B,1 H,1 A,0

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a) Realize the following Boolean function using Threshold gate. F(x1,x2,x3,x4) = ¦ m(0,1,3,4,5,6,7,12,13) [12] b) What is a Programmable logic array? [4] a) Design a modulo-12 up synchronous counter using T-flip flops and draw the circuit diagram. [10] b) Compare synchronous and asynchronous sequential circuits. [6]

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Code No: X0224

8.

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Construct an ASM block that has 3 input variables (D,E,F) and 4 output variables (P,Q,R,S) and 2 exit paths. For this block, output P is always 1 and Q is 1 if D=1. If D and F are 1 or if D and E are 0, R=1 and exit path 2 is taken. If (D=0 and E=1) or (D=1 and F=0), S=1 and exit path 1 is taken. Realize it with PLA and 2 D flip flops. Draw the block diagram and give the PLA table. (16)

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Code No: X0224 II B.Tech I Semester (R07) Regular Examinations, Nov- 2009 SWITCHING THEORY AND LOGIC DESIGN (Com to EEE, EIE, BME, E.CON.E, ECC, ICE) Time: 3 hours Answer any FIVE Questions All Questions carry equal marks 1. a) What is Hamming code? Explain with an example. b) Find the 9’s and 10’s complement of the following decimal numbers i) 52,784,630 ii) 63,325,600 iii) 00,000,000 2. Max Marks: 80

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3. 4. Write a short notes on 4-to-1-multiplexer? 5. a) Implement the following Boolean functions using PROM. m(0,2,6,7,8,9,12,13) W (A,B,C,D) = ¦ m(0,2,6,7,8,9,12,13,14) X (A,B,C,D) = ¦ m(2,3,8,9,10,12,13) Y (A,B,C,D) = ¦ m(1,3,4,6,9,12,14) Z (A,B,C,D) = ¦ b)Write short notes on Multigate synthesis.

(8)

( 8 )

a) Express the Boolean function F = A + B’C as a sum of minterms. (8) b) Show that a positive logic NAND gate is a negative logic NOR gate and vice versa (8) Simplify the following Boolean function by first finding the essential prime implicants

[10]

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6. 7. PS A B C D E F G NS,Z X=0 E,0 C,0 B,0 G,0 F,1 E,0 D,0 1 of 2 X=1 C,0 A,0 G,0 A,0 B,0 D,0 G,0

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[6]

a) Draw and explain the working of Master-Slave JK Flip-Flop. [8] b) Design a sequence detector that detects 110010. Implement the Sequence detector by using D-type flip-flops. [8]

Find the equivalence partition and a corresponding reduced machine in standard form for the machine given below. (16)

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Code No: X0224

8.

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2 of 2

Construct an ASM block that has 3 input variables (A,B,C), 4 output variables (W,X,Y,Z) and 2 exit paths. For this block, output Z is always 1, and W is 1 if A and B both are 1. If C=1 and A=0,Y=1 and exit path 1 is taken. If C=0 or A=1, X=1 and exit path 2 is taken. Realize the above using multiplexer and register. (16)

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Code No: X0224 II B.Tech I Semester (R07) Regular Examinations, Nov- 2009 SWITCHING THEORY AND LOGIC DESIGN (Com to EEE, EIE, BME, E.CON.E, ECC, ICE) Time: 3 hours Answer any FIVE Questions All Questions carry equal marks Max Marks: 80

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1. 2. a) Show that the dual of the exclusive-or is equal to its complement b) Express the complement of the following function in sum of minterms forms i) F(x,y,z)= xy+xz ii) F(A,B,C) = (2, 4, 5, 7) 3. b) d ( x, y, z ) = ¦ (3,6,7 )

a) Represent the unsigned decimal numbers 842 and 537 in BCD, and then show the steps necessary to form their sum. (8) b)Represent the decimal number 5,137 in i)BCD ii) excess-3 code, iii) 2421 code ,and vi) a 6311 code. (8)

(8) (8)

Simplify the following Boolean function F together with the don’t care condition d; then expressed the simplified Boolean function in sum of minterms. (8+8) a) F ( x, y, z ) = ¦ (0,1,2,4,5)

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5.Implement the following function with a multiplexer, with an 8 × 1 multiplexer?(16) F ( A, B, C , D ) = ¦ (0,3,5,6,8,9,14,15,) f2 (A,B,C,D,E,F) =

6. Realize the given functions using a PLA with 6 inputs, 4 outputs and 10 AND gates: [16] f1 (A,B,C,D,E,F) = ¦ m(0,1,2,3,7,8,9,10,11,15,32,33,34,35,39,40,41,42,43,45,47)

¦ m(8,9,10,11,12,14,21,25,27,40,41,42,43,44,46,57,59)

6. a) Design a Mod-6 synchronous counter using JK flip-flops. b) Compare combinational and sequential circuits.

[10] [6]

7. a)Find the equivalence partition for the given machine and a standard form of the corresponding reduced machine. (8+8) 1 of 2

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Code No: X0224

PS A B C D E

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b) Convert the following Mealy machine into a corresponding Moore machine. PS A B C D E NS,Z X=0 B,0 E,0 D,1 C,1 B,0 X=1 E,0 D,0 A,0 E,0 D,0 8.

NS,Z X=0 B,0 E,0 D,1 C,1 B,0

X=1 E,0 D,0 A,0 E,0 D,0

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a) Explain in detail the Mealy state diagram and ASM chart for it with an example. (8) b) Show that 8 exit paths in an ASM block emanating from the decision boxes that check the eight possible binary values of three control variables X,Y,Z. (8)

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JNTU previous papers old papers supplementary regular papers ist year 2-1 2-2 3-1 3-2 4-1 4-2 first year second year third year fourth year semester cse ece it eee mechanical civil

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