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Lecture-2

Design Flow

R.SAKTHIVEL., Asst.prof(Senior)
IC Design Group, VITU
Email:circuitsakthi.yahoo.co.in
EEE588 – Digital IC Design -VLSI
DIVISION-2010 FALL

VLSI DESIGN FLOW
VLSI Design Flow
Verification

Specification
Hardware description
languages (VHDL)

Simulation. Timing analysis, formal
verification

Implementation
Full custom, standard cell,
gate arrays

Testing
Automatic test equipment
(ATE), structural scan
testing
Built-in Self-Test

Manufacturing
CMOS

EEE588 – Digital IC Design -VLSI
DIVISION-2010 FALL

Design Flow System Specification S L V n g i s e D I Functional Design Behavioral Representation S L V Functional Verification Logic Design Logical (Gate level) Verification Logic Verification n g i s e D I Circuit Design S L V Circuit Representation Circuit Verification EEE588 – Digital IC Design -VLSI DIVISION-2010 FALL n g i s e D I .

Design Flow Cont’d n g i s e D I Physical Design S L V Layout Representation Layout Verification Fabrication and Testing S L V n g i s e D I Packaging S L V Testing EEE588 – Digital IC Design -VLSI DIVISION-2010 FALL n g i s e D I .

Floor planning and placement 3. Logic Partitioning 2.Physical Design n g i s e D I 9 A Physical design converts a circuit description into a geometric description 9 This is the description used to manufacture a chip 9 Physical design cycle S L V S L V n g i s e D I 1. Routing 4. Post layout optimization S L V n g i s e D I EEE588 – Digital IC Design -VLSI DIVISION-2010 FALL back .

Physical Design Cycle S L V n g i s e D I S L V S L V n g i s e D I n g i s e D I Back EEE588 – Digital IC Design -VLSI DIVISION-2010 FALL .

S L V n g i s e D I n g i s Lecture-3 SI De L V Design Issues and Challenges S L V n g i s e D I EEE588 – Digital IC Design -VLSI DIVISION-2010 FALL .

Design Abstraction Levels S L V n g i s e D I SYSTEM n g i s e D I Architectural Abstraction MODULE Level S L V + GATE Logical Abstraction Level CIRCUIT Vin S L V Vout n g i s e D I S n + G DEVICE Physical Abstraction D n+ EEE588 – Digital IC Design -VLSI DIVISION-2010 FALL Level .

manufacturability S L V – clock distribution n g i s e D I – reuse and IP. portability n g i s e D I – systems on a chip (SoC) – tool interoperability EEE588 – Digital IC Design -VLSI DIVISION-2010 FALL .Major Design Challenges • Microscopic issues n g i s e D I • Macroscopic issues – ultra-high speeds – time-to-market – power dissipation and – design complexity S L V supply rail drop S L V (millions of gates) – growing importance of – high levels of interconnect abstractions – noise. crosstalk – reliability.

Quality Measures • • • • • • • • Functionality Area Speed Power Consumption Testability Manufacturability Reliability Time-to-market EEE588 – Digital IC Design -VLSI DIVISION-2010 FALL .

™ Ease of test generation and Testability. S L V n g i s e D I Hence design is a continuous trade off to achieve adequate results for all of the above parameters. ™ Time to design. S L V n g i s e D I EEE588 – Digital IC Design -VLSI DIVISION-2010 FALL . Flexibility. Power. Function. The tools and methodologies used for a particular chip will be a function of these parameters.The main design parameters are … n g i s e D I ™ Performance – Speed. S L V ™ Size of the die.

Why worry about power? -. De Intel® .Chip Power Density Sun’s Surface Power Density (W/cm2) 10000 Rocket Nozzle 1000 …chips might become hot… Nuclear Reactor 100 8086 Hot Plate 10 4004 P6 8008 8085 Pentium® 386 286 486 8080 1 1970 1980 1990 Year 2000 EEE588 – Digital IC Design -VLSI DIVISION-2010 FALL 2010 Source: Borkar.

1995 . Rabaey.Why worry about power ? -.Battery Size/Weight 50 Battery (40+ lbs) Nominal Capacity (W-hr/lb) Rechargable Lithium 40 Ni-Metal Hydride 30 20 Nickel-Cadmium 10 0 65 70 75 80 85 90 95 Year Expected battery lifetime increase over the next 5 years: 30 to 40% EEE588 – Digital IC Design -VLSI DIVISION-2010 FALL From Rabaey.

7KW 400W 88W 12W 10% 0% 2000 2002 2004 2006 2008 EEE588 – Digital IC Design -VLSI DIVISION-2010 FALL Source: Borkar.35 0.9 0.3 0.Why worry about power? -.7 0. De Intel® .4 0.4 0.2 0.6 Threshold VT (V) 0.Standby Power Year 2002 2005 2008 2011 2014 Power supply Vdd (V) 1.25 8KW 50% Standby Power 40% 30% 20% …and phones leaky! 1.5 1.

CMOS Power Dissipation EEE588 – Digital IC Design -VLSI DIVISION-2010 FALL .

ƒ at the packaged level. Average Quality Level is equal to one minus the defect level. ƒ at the system level. EEE588 – Digital IC Design -VLSI DIVISION-2010 FALL . Testing a die can occur ƒ at the wafer level. It is the aim of the test procedure to determine which die are good and should be used in the end systems. Testing a VLSI circuit is very expensive and time consuming because of its complexity. ƒ at the board level.Testing • Need for testing? One measure of product quality is the defect level.

Testing Digital Systems Initial description Correct Correctdesign? design? Is Isititreally reallythe thething thing you youwant wantto tobuild? build? Does Doesititwork? work? The Thegoal goalof oftesting testingis isto to determine determineififthe thepart partwas was manufactured manufacturedcorrectly correctly— — assuming assumingthe thedesign designwas was correct correct logic synthesis simulation place & route Is Isthe thedesign designcorrect? correct? Fab Line AAgoal goalof ofthe theCAD CADtools toolsis isto to make the design correct. i. make the design correct. EEE588 – Digital IC Design -VLSI DIVISION-2010 FALL . i.e.itit correctly correctlyimplements implementsthe thespec..e.. spec.

Some Important terms in Testing Faults – What are they and where do they come from? Any problem during manufacturing may introduce a defect that in turn may introduce a fault. Defects often occur in metallization in the fabrication process and may occur after fabrication during wafer saw or die attach etc. Fault Models – Physical faults – Open circuit faults. PODEM Algorithm. bridging faults Logical faults – Stuck at faults. Algorithms for fault detection – D Algorithm. EEE588 – Digital IC Design -VLSI DIVISION-2010 FALL .

• Observability – It is the ease with which one can observe the internal node at the output of a integrated circuit. EEE588 – Digital IC Design -VLSI DIVISION-2010 FALL . • ATPG – Automatic Test Pattern Generation. • Controllability – It is the ease with which one can set or reset a particular internal node via input pad.Design for Testability. The ratio of total number of internal nodes that can be tested using the test program to the total number of internal nodes is called the percentage – fault coverage. • DFT . • Fault Coverage – It is the measure of goodness of a test program.

5 296 40 9% $417 EEE588 – Digital IC Design -VLSI DIVISION-2010 FALL Die cost .80 $1300 1.90 486DX2 3 PowerPC 601 Wafer cost Defects/ cm2 Area (mm2) Dies/ wafer Yield $900 1.70 $1700 1.80 $1200 1.6 256 48 13% $272 Pentium 3 0.0 81 181 54% $12 4 0.2 234 53 19% $149 Super SPARC 3 0.0 43 360 71% $4 0.80 $1700 1.0 196 66 27% $73 DEC Alpha 3 0.80 $1500 1.3 121 115 28% $53 HP PA 7100 3 0.What is YIELD? Yield –The ratio of number of good die to the total number of die on the wafer Chip Metal layers Line width 386DX 2 0.70 $1500 1.

Built In Self Test EEE588 – Digital IC Design -VLSI DIVISION-2010 FALL .Test Techniques • Adhoc Testing • Scan Based Testing • BIST .