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™ Few diagrams which can convey both layer
information and topology. They are,






metal contacts: all the four above layers are
deliberately joined together where the contacts are
some cases the second metal and second polysilicon
layers are used.

Thinox region includes n-diffusion .† How the transistor is formed? When thinox and polysilicon cross each othr the transistor is formed. P o l y s Diffusion il i c o n Transistor formed . p-diffusion & transistor channel.

™ Types of metal contacts are. 9 Butting contacts 9 Buried contacts SYMBOL .where we need metal contacts by etching the oxide.METAL CONTACTS ™ After the layouts are designed need for interconnecting appropriate layer is required.

Butting contacts ‰ It is used to make when connecting diffusion to polysilicon ‰ Disadvantage: ‰ * Suffers with reliablity problem ‰ *It requires metal cap ‰ So. not widely used .

™ It is widely used ™ It is more reliable ™ It does not require metal cap .Buried contacts ™ It is used to connect poly to metal contacts then metal to diffusion.

It contains sufficient information to layout the circuit .STICK DIAGRAM † It conveys information that reflects the actual layout topology of a circuit to the designer.

STICK CODING N-type enhancement N-diffusion D Polysilicon G S L:W L:W S D G Metal 1 N-type depletion contact D Implant S Buried contact L:W L:W G S D G .

STICK CODING P-diffusion S Demarcation line Vdd or Vss contact D L:W G P-type transistor D L:W G p-type D-line D L:W S N-type npn S G .

Vias and Contacts 2 4 Via 1 1 5 Metal to 1 Active Contact Metal to Poly Contact 3 2 2 2 .

VDD 3 In 1 •Dimensionless layout entities Out • Only topology is important • Final layout generated by “compaction” program GND Stick diagram of inverter .

Stick Diagram for inverter V DD Out In GND .

Stick Diagram for NAND2 V DD Out A GND B .

S D G N-type enh S D G P-type enh S D G N-type dep npn .SYMBOLIC DIAGRAM ‰ It is the attempt to abstract the layout in some manner in order to to reduce the complexity of the task.

LAYOUT DIAGRAM ™ It is the diagram which can stressing the ready translation into mask Layout form. ™ The rules will produce layouts which will work in practice. ™ A set of design rules are setout for layouts. ™ This mask layout produced during design will be compatible with fabrication process. .

♠ ¾ ¾ ¾ More specifically Layout rules for. to prevent short circuiting to prevent opening to prevent contacts from slipping outside the area to be contacted ♠ GOAL is. ™ Simple ™ constant in time applicable to many process ™ standardized among many institution .

Layers in 0.25 mm CMOS process .

Intra-Layer Design Rules Same Potential 0 or 6 Well Different Potential 2 9 Polysilicon 2 10 3 Contact or Via Hole 3 2 Select 3 Metal1 Active 2 2 3 .

¾ Design rules are often dependent upon both process equipment and process design.DESIGN RULES ¾ Due to the complexity of modern VLSI circuitry designing for testability is mandatory ¾ Designers want design rules to improve the performance and chip area. .

e. to allow an engineer to layout VLSI circuit with reasonable assurance that it will work.PURPOSE OF DESIGN RULES ‰ To prevent unworkable constructs ‰ to prevent the unreliable constructs ‰ to prevent hard to implement constructs ‰ i. .

Meta design rules Mead.conway design rule ™ Meta design rule: very first design rules Disadvantage: not much helpful unless one knows the process intimately ™ Mead-conway rule: characterize the process with a single scalable parameter called Lambda .™ Design rules are.


† Then what is lambda based rules? It is process dependent it is defined as the maximum distance by which a geometrical feature on any one layer can stay from another feature due to overetching. .† What is lamdba? It is the parameter defined as the half width of a max-width line (or) as a multiple of standard deviation of process. misalignment distortion etc.


6 microns.† Advantage of Mead-conway lambda based rules: allows future scaling and makes the layout portable. † Unit dimension: Minimum line width „ scalable design rules: lambda parameter „ absolute dimensions (micron rules) . It is suitable for 3 microns to 0.


DESIGN CHECKS † Design performs two major checks before fabrication 1) Design rule check(DRC) 2) Layout Vs schematic(LVS) .

† DRC at two levels.Design rule check (DRC) † It is to ensure that nothing has wrong in the process of assembling the logic cells and routing. @ check of the detailed router @ check of correctness of the library cells .

Check of the detailed router ™ This is the first level of check in DRC ™ Principally it is a check of the detailed router ™ It checks for rule problem between logic cells. violation. .

Check of correctness of the library cells ™ This is the second level of check in DRC ™ This check is at the transistor level ™ Principally it is a check of correctness of the library cells ™ Usually the ASIC vendor performs the check with their own software .

what happens? closes a loop between the logical and physical design process and ensure that both are same. † How do you do? An electrical schematic is extracted from the layout and compare to the netlist.Layout Vs schematic (LVS) † What do you mean by LVS? It is the check to ensure that what is about to be committed to silicon is what is really wanted. . † So.

Problems of LVS ™ Transistor level netlist for a large ASIC forms an enormous graph ™ Creating a true reference is diffcult .