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Minimization of Redundant Internal Voltage Swing in Cmos Full-Adder

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Minimization of Redundant Internal Voltage Swing in Cmos Full-Adder

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Minimization of Redundant Internal Voltage Swing in Cmos Full-Adder

Minimization of Redundant Internal Voltage Swing in Cmos Full-Adder

© All Rights Reserved

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ISSN: 2319-1163

CMOS FULL-ADDER

Citharthan Durairaj1, Vasanth Rajendran2

1, 2

VLSI, Electronics and Communication Engineering, Kapagam University, Tamil Nadu, India,

sidharth.durairaj@gmail.com, vasanthrajendran1@gmail.com

Abstract

We proposed a CMOS full-adder cell for low-power applications. The proposed logic structure of CMOS full-adder is used to

minimize unnecessary internal voltage swing taken place in the prior CMOS full-adder by adding four nMOS transistors to the logic

structure of SUM circuit and three nMOS transistors to the logic structure of CARRY circuit. These nMOS transistors are used to

minimize the internal voltage swing from (0 VDD) to ((0 - Vtp)VDD) during redundant internal voltage transitions. For area

constrain applications, we can use these extra nMOS transistors either to the SUM or CARRY circuit depending upon our need. The

proposed full-adder has maximum of 36ps longer data to output delay as compared to the prior CMOS full-adder. The full adder was

designed with a 0.18m CMOS technology.

----------------------------------------------------------------------***-----------------------------------------------------------------------1. INTRODUCTION

used in many VLSI systems, such as application-specific digital

signal processing (DSP) architectures and microprocessors.

This module is the core of many arithmetic operations such as

addition/subtraction, multiplication, division and address

generation. Thus a full-adder having low-power consumption

and low propagation delay results of great interest for the

implementation of modern digital systems.

ADDER

depends on 1) dynamic power, 2) short-circuit power, 3)

leakage power and 4) static power. The dynamic power

dissipation is the dominant factor compared with the other

components of power dissipation in digital CMOS circuits. As

technology scales down, i.e. for submicron technologies, the

contribution of dynamic power dissipation also increases

because of increased functionality requirements and clock

frequencies [1]. The dynamic power P = CV2f equation

consists of three terms: voltage, capacitance and frequency.

Frequency reduction is the best applied to signals with larger

capacitance. One effective method of reducing switching

frequency is to eliminate logic transitions that are not necessary

for computation [2].

In this paper, the inputs to the nMOS transistors are blocked

during redundant internal logic transitions taken place in

existing CMOS full-adder structure by adding extra nMOS

transistors serially and thereby reducing the redundant internal

voltage swing.

The logic scheme is shown in Fig.1 [4]. The true-table for a 1bit full-adder is given in Table 1. Examining the true-table and

by referring the logic scheme, it can be seen that for producing

the SUM output, MUX 1 select the output of

value when

C = 0 whereas it select the output of

value when C = 1.

Similarly for producing the CARRY output, MUX 2 select the

output of A B value when C = 0 whereas it select the output

of A + B value when C = 1.

The features and advantages of this logic structure listed in [5]

are as follows.

There are not signals generated internally that control the

selection of the output multiplexers. Instead the C input

signal, exhibiting a full voltage swing and no extra delay,

is used to drive the multiplexers, reducing so the overall

propagation delays.

The capacitive load for the C input has been reduced, as it

is connected only to some transistor gates and no longer to

some drain or source terminals, where the diffusion

capacitance is becoming very large for sub-micrometer

technologies. Thus the overall delay for larger modules

where the C signal falls on the critical path can be reduced.

The propagation delay for the SUM and CARRY outputs

can be tuned up individually by adjusting the XOR/XNOR

and the AND/OR gates; this features is advantageous for

applications where the skew between arriving signals is

critical for a proper operation, and for having well

__________________________________________________________________________________________

Volume: 02 Issue: 04 | Apr-2013, Available @ http://www.ijret.org

559

chance of glitches in cascaded applications.

The inclusion of buffers at the full-adder outputs can be

implemented by interchanging the XOR/XNOR signals,

and the AND/OR gates to NAND/NOR gates at the input

of the multiplexers, improving in this way the performance

for load-sensitive applications.

found about the logic structure is explained below:

ISSN: 2319-1163

complementary pass transistor logic style (SR-CPL) [5].

However both logic styles suffer from redundant internal

voltage transitions. Since net 1 and net 2 have higher

capacitances (approximately half the oxide capacitances of pass

transistors in XOR and XNOR logic, wire capacitances, and

half the oxide capacitances of transmission gates) it causes

higher power dissipation. It also follows for net 3 and net 4

(denoted in Fig.1) due to continuous operations done by AND

and OR circuit. So we need to avoid this unwanted internal

logic transitions without much degradation in performance.

select the

value when C = 0 whereas it select the

value when C = 1. But the logic structure of XOR continuously

produces the output to net 1 (denoted in Fig.1) even when the

input C = 1. Similarly logic structure XNOR produces the

output to net 2 (denoted in Fig. 1) even when the input C = 0. It

causes redundant logic transitions on net 1 and net 2. The logic

structure of XOR/XNOR in the full-adder was implemented

using double

REDUNDANT INTERNAL VOLTAGE SWING

The modified DPL logic of XOR and XNOR to produce the

SUM output is shown in Fig.2. Here we added four nMOS

transistors to the existing XOR and XNOR logic structure. The

gate control of added nMOS transistors in XOR logic structure

is

whereas in XNOR logic structure is input C. So that

inputs to the nMOS transistors are blocked in XOR logic when

the input C = 1 and in XNOR logic when the input C = 0. Thus

switching transitions are taken place from (0 - Vtp)VDD

instead of 0VDD during redundant operations (XOR output

when C = 1 and XNOR output when C = 0). This minimizes the

redundant voltage swing in net 1 and net 2. However this will

increase the load for input C due to the increased gate voltages.

But due to the smaller size of transistors the capacitive load will

be smaller compared to the net 1 and net 2. In addition, the

input transition

TABLE I

TRUE-TABLE FOR A 1-BIT FULL-ADDER: A, B, AND C

ARE INPUTS; SUM AND CARRY ARE OUTPUTS

SUM output.

__________________________________________________________________________________________

Volume: 02 Issue: 04 | Apr-2013, Available @ http://www.ijret.org

560

ISSN: 2319-1163

output.

probability of input C is lesser when compared to the input

transition probability of A and B. Similar actions are taken for

net 3 and net 4. Three nMOS transistors are added to the

existing AND and OR logic structure such that inputs to the

nMOS transistors are blocked in AND logic when the input C =

1 and in OR logic when the input C = 0. The modified pass

transistor logic structure to produce the CARRY output is

shown in Fig.3.

c) modified XOR logic output to net 1 d) existing XNOR logic

output to net 2 e) modified XNOR logic output to net 2.

Pdynamic = CL.VDD2.N (0VDD).f

(2)

4.1Dynamic Power

transitions at the output or equivalently the number of times CL

is charged to VDD. Fig.4 shows the existing and modified

output voltages of net 1 and net 2 with respect to the input

voltage C. Fig.5 shows the existing and modified output

voltages of net3 and net4 with respect to the input voltage C.

The inputs C, B and A are as per the true-table (i.e. 000111).

VDD for the operation is 1.8 V. For redundant operations

(XOR and AND logic output on net 1 and net 3 when C = 1,

XNOR and OR logic output on net 2 and net 4 when C = 0) in

the modified logic structure the equation (2) is modified as

(1)

The capacitances on the net 1, net 2, net 3 and net 4 are charged

to VDD from (0 - Vtp) instead of 0 during redundant

operations. This reduces the voltage swing which can be clearly

seen from Fig.4 and Fig.5.

and to minimize area. However if we control the inputs of

pMOS transistors the peak voltage on the nets will be reduced

to (VDD-Vtn) during redundant operations.

4. PERFORMANCE COMPARISONS

transistors. Pdynamic is caused by the charging and discharging

of capacitances in the circuit.

(3)

__________________________________________________________________________________________

Volume: 02 Issue: 04 | Apr-2013, Available @ http://www.ijret.org

561

ISSN: 2319-1163

proper functionality.

REFERENCES

3 c) modified AND logic output to net 3 d) existing OR logic

output to net 4 e) modified OR logic output to net 4.

The proposed full-adder can operate properly with voltage

supply as low as 0.6 V. Since these realization have neither

static consumption, nor internal direct paths from VDD to Gnd

(except for the inverters at the inputs, which could be avoided if

the inputs come from Flip-Flops with complementary outputs),

they are good candidates for battery-operated applications

where low consumption modules with standby modes are

required. The transistors in the proposed full-adder are minimal

and not larger than 1 m (except for the symmetrical response

inverters at the input).

4.2. Delay

Due to the extra nMOS transistors the proposed logic structure

of full-adder introduces a falling delay compared to the existing

logic structure of full-adder. The maximum output delay

associated with proposed full adder structure compared to the

existing is only 36ps.

Designing CMOS Circuits for Low Power, Kluwer academic

publishers, pp. 10-12

[2] Gary Yeap, Practical Low Power Digital VLSI Design,

Kluwer academic publishers, pp. 1-3

[3] A. M. Shams and M. Bayoumi, Performance evaluation of

1-bit CMOS adder cells, in Proc. IEEE ISCAS, Orlando, FL,

May 1999, vol. 1, pp.27-30.

[4] M. Aguirre and M. Linare, An alternative logic approach

to implement high speed low power full adder cells,. in Proc.

SBCCI, Florianopolis, Brazil, Sep.2005, pp. 166-171.

[5]. Mariano Aguirre-Hernandez and Monico Linares-Aranda,

CMOS

full-adders

for

energy-efficient

arithmetic

applications, IEEE Trans. Very Large Scale Integr (VLSI)

Syst. vol. 19, no.4, pp.718-721, Apr. 2011.

[6] R.Zimmerman and W. Fichtner, Low power logic

styles:CMOS versus pass-transistor logic, IEEE J.Solid-State

Circuits, vol.32, no.7, pp. 1079-1090, Jul. 1997.

[7] A.M. Shams, T.K. Darwish, and M.Bayoumi, Performance

analysis of low-power 1-bit CMOS full adder cells, in

Proc.SBCCI, Florianopolis, Brazil, Sep.2005, pp. 166-171.

BIOGRAPHIES:

D. Citharthan was born in Kumbakonam, 6th

Sep 1987. He was completed B.E Electrical

and Electronics Engineering in Panimalar

Engineering College, Chennai, Tamil Nadu,

India. He is pursuing Master degree in VLSI in

Karpagam University, Coimbatore, Tamil

Nadu, India. His research area includes CMOS

Design and Low power VLSI.

R. Vasanth was born in Dharapuram, 20th

Nov 1986. He was completed M.Sc.,M.Phil in

Applied Electronics in RVS College of Arts

and Science, Sulur, Coimbatore, Tamil Nadu,

India. He is pursuing Master degree in VLSI in

Karpagam University, Coimbatore, Tamil

Nadu, India. His research area includes Low power VLSI and

Industrial Electronics.

CONCLUSIONS

A modified logic structure to reduce redundant internal voltage

swing in CMOS full-adder cell was proposed. The proposed

logic is used to minimize the voltage swing from (0VDD) to

((0 - Vtp)VDD) during redundant internal logic transitions.

The outputs are simulated using Cadence virtuoso. The

simulations showed that the proposed logic structure of fulladder is well suitable to low-power applications, and the power

Volume: 02 Issue: 04 | Apr-2013, Available @ http://www.ijret.org

562

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