VLSU Lecture on device characteristics

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VLSU Lecture on device characteristics

© All Rights Reserved

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You are on page 1of 13

Payman Zarkesh-Ha

Office: ECE Bldg. 230B

Office hours: Tuesday 2:00-3:00PM or by appointment

E-mail: payman@ece.unm.edu

ECE520 - Lecture 5

Slide: 1

Short Channel Effects

Source-Drain resistance

Subthreshold conduction

Velocity saturation

Mobility degradation

Threshold voltage rolloff

DIBL effect

Punch through

Hot electron

Narrow channel effect

ECE520 - Lecture 5

Slide: 2

Todays Lecture

Overview of T-SPICE

BASIC CMOS Inverter

Resistive load inverter

VTC curves

Power dissipation estimation

Switching threshold

Noise margin

CMOS Voltage-Transfer Characteristic (VTC)

Device variations

Vdd scaling (minimum supply voltage)

ECE520 - Lecture 5

Slide: 3

* Test Circuit for VLSI Class

Vdd Vp gnd DC 5V

RL

Vp Vout 10K

M1

.DC Vin 0 5 0.05

.plot Vout

.include 'device_model.modlib'

.end

ECE520 - Lecture 5

Slide: 4

ECE520 - Lecture 5

Slide: 5

A resistive load inverter consists of a pull down NMOS and a

pull up resistor

Voltage Transfer Characteristic (VTC) is a function of transistor size and

resistor value

A good inverter provide a fast transition in VTC curve

ECE520 - Lecture 5

Slide: 6

The pull up resistor must be calculated to maintain a specific

low level voltage (VOL) at the output

Example:

RL

Kn = 100 uA/V2

VT0 = 0.7 V

VOL = 0.25 V

How much is RL for (W/L)=5 ?

ECE520 - Lecture 5

Slide: 7

When the output is high, there is no current drawn from VDD

When the output is low, a DC current is drawn from VDD

Assuming probability is 50% for logic high and logic low

How to compute Power in the previous example?

RL

How much is the power for a design with 100K similar resistive

load logic gate?

ECE520 - Lecture 5

Slide: 8

Example:

VOH = 5.0 V

Kn = 100 uA/V2

VT0 = 0.7 V

VOL = 0.25 V

(W/L) = 5

RL = 9.1 K

V(out)

RL

VOL = 0.25 V

0

VIL = 0.9 V

VIH = 2.2 V

V(in)

ECE520 - Lecture 5

Slide: 9

Noise Margin

Noise Margin

NM L VIL VOL

It is better to have:

ECE520 - Lecture 5

VOH = VDD

VOL = VSS

Large NMH

Large NML

Slide: 10

V(out)

RL

Example:

Kn = 100 uA/V2

VT0 = 0.7 V

VOL = 0.25 V

(W/L) = 5

RL = 9.1 K

V(in) = V(out)

VM = 1.9 V

VM = 1.9 V

V(in)

ECE520 - Lecture 5

Slide: 11

How to compute VM

Find out MOS operating region

Write the equations for current

Calculate VM

Example:

VM in resistive load inverter

ECE520 - Lecture 5

Slide: 12

How to compute Noise Margin

Use approximation (gain factor)

Determine gain at VM

Extrapolate VIL and VIH

VOL and VOH are easy to compute

Example:

Vout

V OH

VM

V in

V OL

ECE520 - Lecture 5

V IL

VIH

Slide: 13

NMOS Inverter

Large pull up resistor was a problem for resistive load inverter

Depletion mode NMOS was an efficient way to implement a

resistive pull up

Depletion device has an implant in the channel to give it a negative VT and

so it is always on it was a very effective non-linear load device

This solved the area, but not the noise margin or power problems

ECE520 - Lecture 5

Slide: 14

Since a resistor is so big, its better to use a single PMOS

transistor that is always on:

PMOS pull up

NMOS pull down

ECE520 - Lecture 5

Slide: 15

CMOS Inverter

CMOS inverter is comprised of

PMOS pull up

NMOS pull down

Advantages

No direct path from VDD to GND (zero static power - except for leakage)

Better noise margin (Rail-to-rail output swing)

Ratio-less logic (output level not depend on gate size)

Always finite resistance to VDD or GND

Very high input impedance

ECE520 - Lecture 5

Slide: 16

Treat each transistor as either on or

off

Each transistor has an on

resistance

This isnt a bad model as long as the

input transition is quite a bit faster than

the output transition and its very

intuitive

effective transistor resistant and

load capacitance

ECE520 - Lecture 5

Slide: 17

ECE520 - Lecture 5

Slide: 18

How to compute VM in CMOS logic gate?

Use the previous method to compute VM

Assume velocity saturation model

ECE520 - Lecture 5

Slide: 19

How to compute noise margin in CMOS logic gate?

Use the previous method to approximate Noise Margin

Vout

V OH

VM

where

V in

V OL

V IL

ECE520 - Lecture 5

V IH

Slide: 20

10

For typical CMOS processes, n = 2 to 3 times p

To get maximum noise margin we can make Wp = 2.5Wn

We dont actually implement this ideal case

This means NMs are not seriously compromised by (wp/wn) ratios not equal

to 1

1.8

1.7

1.6

1.5

V (V)

1.4

1.3

1.2

1.1

1

0.9

0.8

10

10

W /W

p

ECE520 - Lecture 5

Slide: 21

We really want the best speed/power ratio

At Wp = 2.5 Wn the rise and fall times for the gate (assuming that

they are equal at the input) will be equal

Each gate is a load for a preceding gate

As we widen the PMOS we slow down the previous gate

Every increment of width adds C

C is important term in power (the one we can control!)

It turns out that its best to use a ratio of about 1.5 rather than

2.5-3 that would give us equal rise and fall times

In this case, NMOS are faster and PMOS slower, but the faster

falling input helps make up for the slower rising output and the

overall C

ECE520 - Lecture 5

Slide: 22

11

Impact of process variation

2.5

Good PMOS

Bad NMOS

Vout(V)

1.5

Nominal

1

Good NMOS

Bad PMOS

0.5

0

0

0.5

1.5

2.5

Vin (V)

ECE520 - Lecture 5

Slide: 23

2.5

0.2

2

0.15

V out (V)

V out (V)

1.5

0.1

1

0.05

0.5

Gain=-1

0

0

0.5

1.5

2.5

0

0

V (V)

0.1

V (V)

0.15

0.2

in

in

ECE520 - Lecture 5

0.05

Slide: 24

12

Once VDD drops below threshold voltage, the transistors operate

in the subthreshold region.

Using equation for subthreshold region we can prove:

1

g e VDD

n

ECE520 - Lecture 5

2 T

Slide: 25

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