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You are on page 1of 9

01.

Logic 0

A

x

y

C

(a) Binary to Gray code converter

(c) Binary to EXCESS-3 converter

(d) EXCESS-3 To Gray code converter

Ans: (a)

02.

0

24 1

decoder 2

3

x

y

0

4:1

1

MUX

2

3 S1 (MSB) S0

y

(a) X NOR Y

Ans: (d)

03.

(b) X NAND Y

x

(c) X XOR Y

(d) X XNOR Y

0

1

1

0

0

1 4:1

2 MUX

3 S1 S0

f0

0

1 4:1

2 MUX

3 S1 S0

y0

x0

x1

f1

y1

(a) sum output of 2 bit addition

(b) carry output of 2 bit addition

(c) borrow output 2 bit subtraction

(d) none of the above

Ans: (a)

04.

T

Q

T-FF

Q

Clk

x=0

x=1

(a)

0

x=1

x=0

(b)

x=0

x=1

x=0

x=0

x=1

x=1

(c)

x=1

x=0

x=1

(d)

x=0

x=1

x=0

1

Ans: (a)

05.

What is the output voltage of the D/A converter after applying 4 clock pulses. Assume the

Johnson counter is initialized to 000. The input-output table of digital to analog converter is

given below.

3 bit

Johnson

counter

D/A

converter

V0 = ?

Clk

D/A Converter

Digital Input

Analog Output

000

0V

001

1V

010

2V

011

3V

100

4V

101

5V

110

6V

111

7V

(a) 2 V

(b) 3 V

(c) 5 V

(d) 7 V

Ans: (b)

06.

T

T

Q

Clk

(a) up counter if X = 1

(c) down counter if X = 1

Ans: (a)

07.

(b) up counter if X = 0

(d) down counter if X = 0

TTL

Totempole

NAND

A

B

(a) Decoder

Ans: (b)

(b) Multiplexer

TTL

Totempole

NAND

TTL

Totempole

NAND

TTL

Totempole

NAND

(c) Demultiplexer

(d) None

08.

Minimum number of 2 input NAND gates required to implement the Boolean Expression

X Y A B C

(a) 7

(b) 8

(c) 9

(d) none

Ans: (d)

09.

For a TTL circuit IOH = 400 A, IIH = 40 A, IOL = 16 mA, IIL = 2 mA. The Fanout is

8 10

(a) 10

(b) 8

(c)

(d) None

2

Ans: (b)

10.

Va

Successive

Approximation

ADC

Digital

Output

Analog

Input

Clk

The 4 bit successive approximation ADC has full scale value of 15V. the sequence of states is

shown below. The analog input lies in the range.

1010

Start

1100

1000

1001

1000

END

(a) 8 V 9 V

Ans: (a)

11.

(b) 9 V 10 V

(c) 10 V 11 V

For the 4 bit DAC shown below, the Analog output voltage is (Assume ideal OP-Amp)

10 k

10 k

10 k

10V

20 k 20 k

20 k

20 k

20 k

20 k

+25V

_

+

V0

-25V

(a) 1.875 V

Ans: (b)

12.

(b) 3.75 V

(c) 5 V

(d) 15 V

Integrated output waveform for the dual scope ADC is shown in the figure. The time T for on 8

bit counter with 4 MHz clock will be

V

0

T

(a) 0.032 ms

Ans: (b)

13.

(b) 0.064 ms

(c) 0.64 ms

(d) 0.024 ms

What is the equivalent Boolean Expression in product of sums form for the K-Map in the

figure.

AB

00 01

CD

00

01

1

1

10

11

10 11

1

1

(a) B C D B C D

(c) B D B D

Ans: (c)

14.

(b) B D B D

(d) None

(a) 011000

(b) 100111

(c) 101000

(d) 101001

Ans: (c)

15.

0 00

b3 b2 b1 b0

4 bit

Binary

Adder

d4

d 3 d2 d1 b0

Consider the above circuit. It has 4 bit binary input b3 b2 b1b0 and has the five bit output

d4d3d2d1d0. The circuit implements.

(a) Binary to Hex conversion

(c) Binary to excess-3 conversion

Ans: (d)

(d) Binary to radix 12 conversion

16.

1.

Taking twos complement is equivalent to sign change

2.

For a 4 bit number A, A+ ones complement A is equal to 24 1.

3.

Fan in of a gate is always equal to Fan out of the same gate.

4.

Master Slave Flip Flop stores 2 bits of data.

Which of the following is true.

(a) 1 only

Ans: (b)

(b) 1 and 2

(c) 1, 2, 3 only

(d) 1, 2, 3, 4 only

representation of 8 * P is where * represents multiplication

(a) (C3D8)16

(b) (187B)16

(c) (F878)16

(d) None of the above

Ans: (a)

17.

18.

Assertion: It is not desirable to drive transistor into hard saturation for high speed switching

circuits.

Reason: It is difficult to bring back transistor to cutoff from hard saturation.

Ans: (a)

19.

Q QC

C

CLK

D QB

D QA

A

fout

CLR

CLR

CLR

0

4:1 1

MUX 2

S1(MSB)S0 3

QA

(a) 125 KHz

Ans: (c)

20.

0

0

QC

0

QB

Reason: Bit is stored as charge in DRAM.

Ans: (d)

(d) None

21.

X+Y+Z=1

XY = 0

W X Z 0

XY Z W 0

The value of W, X, Y, Z are

(a) 0000

Ans:

22.

(b) 1101

(c) 1100

(d) none

Match List I with List II & select the correct answer using the code given below.

List I

P

.

List - II

1.

X

Y

0

Y

0 2: 1

MUX

1

S

X

X

Y

X

1

0 2: 1

MUX

1

S

Y

X

Y

Y

Y

0 2: 1

MUX

1

S

X

Code:

(a)

(b)

(c)

(d)

Ans: (b)

P

1

3

2

2

Q

2

2

1

3

R

3

1

3

1

23.

Reason: Transistors with high storage times are used in ECL logic family.

Ans: (c)

24.

An 8 bit digital to analog converter has full scale output voltage of 10V and an accuracy of

0.1%. The maximum error for any output voltage will be

(a) 1 mv

(b) 10 mv

(c) 10/255 mv

(d) None

Ans: (d)

25.

Assertion: Carry look ahead adder is faster than ripple carry adder.

Reason: Carry look ahead adder generates carry bits directly from input.

Ans: (a)

26.

01.

PROM contains programmable AND array and programmable OR array.

02.

PLA contains fixed AND array and programmable OR array.

03.

Minimum number of MOSFETs required for 1 bit DRAM cell is 8.

04.

BCD, 2421 & EXCESS 3 are self complementing codes.

Which of the following is correct

(a) 2 and 4 only

(b) 3 and 4 only

(c) 1, 2, 3, 4

(d) none of the above

Ans: (d)

27.

Reason: Noise margin of MOS logic family is higher compared to RTL.

Ans: (b)

28.

01.

Registers are made of edge triggered flops where as latches are made from level

triggered flip flops.

02.

Latch employs cross coupled feed back connections.

03.

Noise immunity is the amount of noise which can be applied at the input of the gate

without causing the gate to change state.

04.

Propagation delay is the time required for a gate to change its state.

Which of the following statements are NOT correct.

(a) 1 and 2

(b) 3 and 4

(c) 1, 2, 3, 4 (d) none

Ans: (d)

29.

VCC = 5V

1.4 k

4k

100 k

Q4

Q2

Vi = 2.7V

D

V0

Q1

Q3

1k

1k

List I

P. Q1

Q. Q2

R. Q3

S. Q4

List - II

1. Active

2. Saturation

3. Cutoff

4. Reverse Active

Codes:

(a)

(b)

(c)

(d)

Ans: (a)

30.

P

4

3

3

4

Q

2

2

1

1

R

2

2

2

2

S

1

2

1

3

Assertion: The Dual slope integrating type ADC is slow compared to other converters.

Reason: The conversion time is different for different analog input voltages.

Ans: (b)

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