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Optimal Body Bias to Control
Stability, Leakage and Speed in
Article in Journal of Circuits System and Computers · April 2016
Impact Factor: 0.25 · DOI: 10.1142/S0218126616500961


2 authors:
Rohit Lorenzo
National Institute of Technolog…

Saurabh Chaudhury
National Institute of Technolog…

Available from: Saurabh Chaudhury
Retrieved on: 03 July 2016

a controller circuit is introduced which is separately controlling the ‡ saurabh1971@gmail. body bias control.5% and 89. India † rohit. No.2% over conventional 6T SRAM cell. leakage and speed in SRAM cell. leakage power and speed of Static random access memory (SRAM) have become an important issue with CMOS technology scaling. The proposed cell is implemented with 65 nm CMOS technology and exhibits higher hold and write margins with an improvement of 26. leakage and speed are con¯rmed under process. 25.6% improvement in write margin as compared to conventional 6T SRAM cell. about 62.lorenzo@gmail. and Computers Vol. Based on word line signal value. National Institute of Technology.29% in hold margin and 16. channel length and gate oxide thickness in MOSFET devices.c World Scienti¯c Publishing Company DOI: 10. 1650096-1 . Keywords: Low leakage. Continued device scaling reduces threshold voltage (Vt ). optimal body bias voltage is generated through control circuitry to control stability. The proposed cell gives faster read and writes with an improvement of 68. Static random access memory (SRAM) has been widely used in system on chip (SOC) because of its high speed and compatibility with standard processors. voltage and temperature variations. SRAM. 1. Leakage and Speed in SRAM Cell¤ Rohit Lorenzo† and Saurabh Chaudhury‡ Department of Electrical Engineering. 8 (2016) 1650096 (15 pages) # . In standby mode. driver and access transistors of SRAM cell. Received 7 February 2015 Accepted 25 February 2016 Published 20 April 2016 The stability. In this paper.Journal of Circuits.2% leakage power reduction is observed in 8  16 array architecture of SRAM. stability. process variation. Introduction Now-a-days design of low power memory has become an important and essential requirement because it occupies a large portion of the chip area. Assam 788010. Robustness of the proposed SRAM cell with respect to stability. *This paper was recommended by Regional Editor Piero Malcovati.1142/S0218126616500961 Optimal Body Bias to Control Stability. Systems.1 which consequently leads to excessive leakage power consumption. Low-power SRAM cell designs without compromising speed and stability are very much important in very large scale integrated systems.

we propose.7 In standby mode. band to band tunneling. a particular row of the cell is in active mode or in standby mode. the static power dissipation can be reduced by controlling the body biasing. we have applied FBB only to the access transistors in the SRAM cell. Lorenzo & S.2 All these techniques reduce leakage power dissipation in SRAM cell. However. With down scaling.10 So optimal body bias leads to minimum leakage current and improved yield. A number of techniques have been developed to tune the Vt using body biasing methodology to enhance the performance of SRAM cell. 9 that a correctly applied body bias reduces the parameter variations. FBB is found to be the most e®ective technique to minimize active leakage. however. Researchers have come out with a di®erent idea to control the Vt . low sub-threshold leakage in idle state and high speed in active mode can be achieved by a suitable body-bias controlling scheme. Di®erent requirements of Vt of NMOS and PMOS transistor in idle and active mode can be adjusted by an appropriate control of bulk voltages. We have also adopted the same idea and applied partial FBB. speed can also be improved by decreasing the Vt during active mode and sub-threshold leakage current can be reduced by increasing the Vt during idle mode. both transistors are reverse body-biased (RBB) while in active mode both transistors are forward body-biased (FBB). The word line signal decides 1650096-2 . a word line based controller circuit to operate the SRAM cell in active and idle modes. Drain induced barrier lowering (DIBL). It must be applied partially as veri¯ed in Ref. gate leakage. In the proposed cell. it should be applied judiciously looking into circuit's path-criticality. Similarly. Many researchers have proposed di®erent schemes to reduce power consumption such as voltage scaling. In standby mode. Reverse body-bias may slightly improve the sub-threshold leakage conduction by increasing the Vt .4 A typical memory organization consists of individual cells arranged in an array of horizontal rows and vertical columns. 8. 1.R. etc.3 Moreover. power density is a growing concern in today's high-performance chip which even demands for thermal-aware design. it will a®ect the circuit's timing.5. body biasing and power gating. Vt is one of the important parameter to control leakage current and speed. These leakage reduction techniques are more e®ective when devices are scaled down to deep submicron regime because leakage current sharply increases for down-scaled devices. the leakage power will increase due to short channel e®ects. It is also possible to have Vt modulation even at 32 nm technology. while keeping the load and driver transistors Vt unaltered with no body bias. Chaudhury E±ciency and reliability can be signi¯cantly improved by reducing the power consumption.11 In this paper. The variation in Vt can dramatically a®ect the static noise margin (SNM).6 In SRAM cell. It has been shown in Ref. Based on word line signal. Minimization in sub-threshold leakage can be achieved by an over-driven body bias scheme whereas speed can be enhanced by an under-driven body bias scheme as shown in Fig.

there are three main components of current which are considered to be the major contributors to leakage power dissipation in SRAM cell. Another important performance matrix is read/write speed and SNM. 2. 1650096-3 . In Sec. The remainder of the paper is organized as follows. 2. Sec. NMOS access and driver transistors in active and idle mode. di®erent body voltages for PMOS load transistor. Conventional 6T SRAM Cell In the structure of conventional 6T SRAM cell as shown in Fig. Leakage and Speed in SRAM Cell Vdd+∆ Vdd Standby In Active Out Active Standby Vss.Optimal Body Bias to Control Stability. we brie°y review conventional 6T SRAM cell. Finally. 2. 5 concludes this paper. gate and junction leakage. Transistor leakage current is mainly dependent upon the type of transistor. 1. Section 4 analyzes the results of the proposed cell. Reading and writing speed can be enhanced by decreasing the Vt of access transistor (N3 and N4) but decrease in Vt has a strong impact (negative) on the SNM. Section 3 discusses the proposed SRAM cell. logic level of the word line and type of operation.12 as indicated by the legends in the ¯gure of 6T SRAM cell. whatever the value stored in SRAM cell.12 Sweeping the Vt values of one transistor causes a mismatch between the two halves of voltage. There will be always some leaky transistors in symmetric structure of SRAM cell.∆ Fig. These are sub-threshold. Over-driven body bias in standby mode.

However. 3. driver and access transistors of SRAM cell. it has two input signals. Lorenzo & S. Conventional 6T SRAM cell. Similarly. reduces power during standby mode and controls the stability during both active and standby mode. 3(c) and 3(d) transfers Vb ¼ Vss –V to the bulk of NMOS driver and access transistors.R. due to this high Vt sub-threshold leakage current will be reduced in SRAM cell. di®erent voltage levels must be provided during active and standby mode through a body-bias control circuit. The proposed control circuit provides three di®erent body-bias signals to load. Chaudhury WL BL BLB P1 P2 N3 N4 (Low) Q QB (High) N1 N2 Isub Igate Ijunction Fig. if it is applied at word level (row-based style) in SRAM cell architecture then it works e±ciently in maintaining the timing constraints and minimizing the power dissipation. So to control the body bias voltage of these transistors.8 The body-bias controller circuit with the proposed SRAM cell architecture is shown in Fig. Node A (red node) in Fig. During standby mode. while the architectural level implementation is ine±cient and has too much power overhead. WL = 0 and WL = 1. driver and access transistors. 1650096-4 . Vt of both PMOS and NMOS transistors become high. Proposed Architecture Body bias has been widely used in digital circuits and systems to control leakage current and timing performances. This controller circuit improves the speed during active mode. 3(b) of the body bias controller circuit transfers Va ¼ Vdd þ V voltage to the bulk (body) of PMOS load transistor. word line signal is used to control the body bias of the load. node B (blue node) and C (black node) in Figs. 2. Gate level implementation of it has too much area overhead. Applying appropriate body bias while improving the stability and delay is extremely challenging at deep nanometer level. 3. In the array of SRAM cell. In this way.

the load and driver transistors Vt is kept unaltered.12 Whereas. This means the bulk of load transistors (P2 and P1) are supplied with Vdd whereas. This is 1650096-5 . In active mode. We have not supplied bulk with Vdd þ V in active mode just to avoid stability degradation. both the access transistor N3 and N4 are FBB to enhance the speed. (d) Proposed SRAM cell with controller circuit (color online).Optimal Body Bias to Control Stability. 3. when a small positive voltage Vc ¼ ðþV Þ is applied to the bulk of both the NMOS transistor N3 and N4. the bulk of driver transistors (N2 and N1) are tied to Gnd. Leakage and Speed in SRAM Cell WL BL BLB Vdd + ∆V N3 P2 P1 N4 WL PMOS-bulkload Q QB N2 A N1 Va WL Vdd (a) (b) Small(+ ∆V) = Vc Vss WL NMOS-bulkdriver Vb B NMOS-bulkaccess WL C Vc WL Vss-∆V Vss-∆V (c) Fig.

Based on word line signal. voltage transfer to NMOS bulk access through C node is Vc ¼ 0:8 V and 0. The control lines as indicated by the legends (red. 4. Chaudhury because. the body bias control signals for standby and active mode are shown in Fig. 1650096-6 .12 V. The advantage of such controller circuit is that by FBB the access transistor (N3. Vt variation of load and driver transistors during active mode has the largest impact on the voltage transfer characteristic and hence the stability of SRAM is a®ected. These control lines are for PMOS-bulk-load-transistor. by applying RBB to all transistors in idle modes. leads to speed-up the read and write operation. voltage transfer to NMOS bulk driver through B node which is Vb ¼ 0:12 V and Vss . Similarly. the leakage currents of the entire transistor will decrease. With this stimulus in the control circuit. the voltage transfer to PMOS bulk load through A node is Va ¼ 1:12 V and Vdd . The array of proposed design is shown in Fig. we have provided no body bias to load and driver transistors in active mode and so their Vt remained unaltered. Fig. Lorenzo & S. 4. Control circuit signals.13 So to avoid the stability problem.R. N4) in active mode. 5. blue and black lines) from controller circuit are shared by the row of cells.

Standby power dissipation In standby mode. Based on word line signal.8 Simulation and analysis for our proposed architecture are presented in subsequent sections. Again. Array structure of proposed design (color online). 4. These voltages 1650096-7 . 4.8. NMOS-bulk-driver-transistor and NMOS-bulk-access-transistor. gate and junction leakage current.Optimal Body Bias to Control Stability. in standby mode all the transistors are overdriven by applying a voltage of Vdd þ V for PMOS transistors and Vss – V for NMOS transistors.1. 5. The result of simulation using 65 nm predictive technology model is then compared with the conventional SRAM cell with a supply voltage of 1 V and cell beta ratio of 1. Leakage and Speed in SRAM Cell Fig. De¯nitely the body bias voltages modulate the Vt even in deep nanometer. we perform circuit simulation using Tanner EDA tool. particular row is selected for active or standby mode. There are library of cells as provided by ARM in 32 nm technology with di®erent body bias voltages having di®erent power and timing characteristics with a power supply of 1. the access transistors of both conventional 6T and proposed SRAM cell are cut-OFF and the bit-line pairs are charged to Vdd .1 V. Each row of array architecture requires separate controllers because word line signal is di®erent for di®erent row. Results To evaluate the performance of the proposed SRAM cell. The total leakage current is the sum of the sub threshold. We have taken a wide range of body bias voltages for simulation purposes just to see the e®ect of body bias on performance metric.

The static power dissipation of the proposed cell is measured in a wide range of overdriven voltage of Va .19 1. we can see that the proposed design reduces more leakage current as compared to conventional 6T SRAM cell. Chaudhury Table 1. Comparison of conventional 6T SRAM cell with proposed cell at di®erent temperature is shown in Fig.45% 55.60% 51.12 1.10% 44.70% 59. 6. which is about 62.31 1. Static power dissipation at di®erent temperatures.35 1.000907 (27  C) 36. Static power dissipation is a function of temperature because leakage current is dependent on the temperature.7% in 8  16 array. 1650096-8 . The static power consumption has been drastically decreased by the reduction of leakage current in all six transistors.26 1.R.001341 0. SRAM 6T Proposed Va (V) 1.001078 0.000999 0.34% 62. Lorenzo & S.001182 0. Static power dissipation (Standby mode at WL ¼ 0).001554 0. The Vt can be increased up Fig.70% Design at Vb & Vc (V) 0:12 0:19 0:26 0:31 0:35 0:4 Array will increase the Vt of all six (PMOS and NMOS) transistors. Vb and Vc . Vb ¼ 0:4 V and Vc ¼ 0:4 V it gives the best reduction of static power. From Table 1. 6.4 8  16 Static power (W) % saving 0.002435 — 0. At a voltage of Va ¼ 1:4 V.

FF. Read and write delay Read and write access time (Read/write delay) is measured. 7. Static power consumption is also tested and compared at a di®erent process corner of TT. 4. From Table 2. and consequently results in better read and write performance. 7. in proposed cell. Finally. load and driver transistors are actually with no body bias.Optimal Body Bias to Control Stability.2% at Vc ¼ 0:8 V and write delay is reduced by 89.2. SS. From results we can observe that as overdriving voltage increases. However. SF and FS as shown in Fig. too much of RBB in order to raise Vt will cause tunneling and other leakage problems. In the architecture of proposed cell as shown in Fig. Leakage and Speed in SRAM Cell Fig. the word line signal controls the Vt of transistors and maintains the performance by transferring the appropriate body bias signal to the substrate of all the transistors of SRAM cell. Read and write performance of the proposed design is compared with conventional 6T SRAM cell. Static power dissipation of conventional and proposed cell. and are shown in Table 2. better leakage reduction is achieved in the proposed design. Performance 1650096-9 . 3. So the proposed cell provides good access time. control circuit transfers a voltage Va ¼ Vdd through node A (red). In this way. during active mode. we can say that the proposed design achieves better read delay over conventional design by 68.2% at Vc ¼ 0:8 V. to certain limit. to load PMOS transistor and Vb ¼ Vss (ground) to the driver NMOS transistor through node B (blue). while Vt of access transistors in active mode are reduced because the bulk of access transistors forward body. when word line is activated. in order to minimize leakage current.biased by voltage ¼ þV through node C (black).

31E-12 2. 4. SRAM 6T Proposed Read-delay (s) % reduction Write-delay (s) % reduction 5.13E-11 2.20% 1. The plotted curves are obtained at room temperature using a supply voltage of 1 V.29E-11 5. Comparison of read/write performance at 27  C.05E-11 — 3. Read delay at di®erent corner conditions. Therefore. W /L ratio of driver transistor is large compared to other transistors in 1650096-10 .02E-11 — 2. We can see from the results that the proposed design shows better read/write performance at Vc ¼ 0:8 V. SF and FS and are shown in Figs. Overall SNM is determined by the side length of smaller square as illustrated in Fig.13E-11 1.8.59E-11 37.4 V 0. SS. improvement of proposed design with conventional 6T SRAM is also observed at di®erent process corners of TT.3. 8 and 9.40% 68.25E-12 37.20% design Va Vb Vc Vdd Vdd Vdd Vss Vss Vss 0. The beta ratios of proposed and conventional 6T SRAM cell are taken as 1.60% 57.20% 74. FF. 10.R. Chaudhury Table 2.30% 89. 8.2 V 0. Lorenzo & S. SNM and stability Figure 10 shows the butter°y curve for conventional 6T and proposed SRAM cell as obtained during read operation.8 V Fig.

Butter°y curve of conventional -6T and proposed SRAM during read operation.Optimal Body Bias to Control Stability. Fig. 9. 1650096-11 . Write delay at di®erent corner conditions. 10. Leakage and Speed in SRAM Cell Fig.

1650096-12 . body terminal of PMOS load transistors are ¯xed to Vdd . In active mode. this reduction in Vt of access transistor has a negative impact on read SNM. On the other hand. in order to reduce the read and write delay. Table 3 shows the performance Table 3. the Vt of access transistor is decreased by applying a FBB.33 mV 303. From the plot we can observe that as we gradually increase the FBB of access transistor. 11.R. the read stability decreases. 10. Vc ¼ þV . Thus. This is because Vt variation of the driver transistor has the largest impact on the shape of voltage transfer characteristic as explained in Ref.60% Proposed design Vc ¼ 0:2 V Vc ¼ 0:4 V Vc ¼ 0:8 V Fig. stability is little degraded during read operation when Vc gradually changes. 12. so there is no body bias for driver transistor. Lorenzo & S.41 mV 165. The results of read SNM are shown in the plot of Fig. Butter°y curve of conventional-6T and proposed SRAM during standby operation.58 mV 325. Chaudhury the SRAM cell. in order to avoid degradation in read SNM during active mode.44 mV 8.64% 16.91 mV 179. Vt of driver transistor is kept unaltered. Whereas.25 mV — 185. Of course.58 mv — 271. Therefore. Consequently. SRAM 6T RSNM % penalty WSNM % improvement 193. Read and write SNM of proposed and conventional 6T-SRAM cell. the body of driver transistor is tied to Vss (ground).40% 10. the read and write performance of the SRAM cell depends on the Vt of access transistor.48 mV 3:90% 7:28% 10:50% 296.

8 V 8  16 array (27  C) 8.29% in hold SNM at Va ¼ 1:1 V and Vb ¼ 0:19 V as compared to conventional 6T-SRAM cell. Table 5. 4.60% at Vc ¼ 0:8 V. Hold SNM of proposed and conventional 6T-SRAM cell. each row of SRAM cell is connected to the control circuit. From the table. Butter°y curve of hold static noise margin (HSNM) of conventional 6T and proposed SRAM cell is shown in Fig.29% comparison of conventional 6T and proposed SRAM cell in terms of read and write SNM.4 V 0. As the body bias voltage Va and Vb of proposed cell increases. Writing in SRAM cell takes place. Table 5 shows the comparison of 6T and proposed SRAM cell. Vt of all transistors are high. so SNM is improved.4. when the bitline pairs are set with VDD and 0 V.091 mV 18.13E-04 8. In standby mode. SRAM 6T HSNM % improvement 326.31E-04 1650096-13 13:03% 13:78% 14:92% . when access device and write driver win the ¯ght with the PMOS pull-up transistor inside the cell. voltage transfer characteristic curve is expanded and the size of the butter°y lobe increases which means a better HSNM. The bulk of each transistor of SRAM cell is connected to the control circuit. Dynamic power dissipation (Active mode at WL ¼ 1).Optimal Body Bias to Control Stability. 11.079 mV 443. The write operation can be carried out successfully.98% 26.2 V 0. In the proposed SRAM cell architecture. Table 4 shows an improvement of 26. Dynamic power dissipation Dynamic power is calculated during active mode. Table 5 shows the dynamic power dissipation of 8  16 SRAM array.20E-04 8.07E-04 Proposed design Vc 0. so due to charging/discharging of capacitance and variation of Vt with the proposed control circuit leads to increase in dynamic power dissipation of proposed cell as compared to conventional 6T SRAM cell. An improved noise margin is achieved in the proposed SRAM cell because Vt of accessed transistor is decreased. SRAM 6T Dynamic power % penalty 7. so the access transistors are switched ON for both conventional and proposed cell. From Table 3 we can observe that the improvement in write margin is about 16. Leakage and Speed in SRAM Cell Table 4.569 mV Proposed design Va ¼ 1:12 V & Vb ¼ 0:12 V Va ¼ 1:19 V & Vb ¼ 0:19 V 403.

2%. S. and the read and write performance is enhanced by 68. Design techniques and architectures for low-leakage SRAMs. which can be considered to be in acceptable range. IEEE Trans. Today. and CNTFET devices.14 Using 65 nm technology. In standby mode. 59 (2012) 1992–2007. 5. under various process. Macii and M. A. Layout Photo of 8  16 SRAM with proposed controller circuit. the amount of dynamic power penalty of 14% for 8  16 array and read stability penalty of 10%. static power consumption of 8  16 array is reduced by about 62. Furthermore. In this paper. The cell also exhibits 26. IEEE Trans. Conclusion Leakage power. speed and stability are critical issues in SRAM design. Poncino. Calimera. we can conclude that increase in dynamic power is negligibly small with the proposed design even for large arrays as compared to conventional SRAM array. The layout of proposed SRAM cell is done using L-EDIT environment in Tanner EDA tool. A. the extra area overhead due to controller circuit can be further minimized by using common controller for multiple bit SRAM cells.6% higher HSNM and WSNM.29% and 16. 4. Nanotechnol. 1650096-14 . a novel control circuit is introduced which is based on word line signal. The proposed technique is not able to provide the desired leakage reduction at nanoscale level but it will certainly provide desired speed and stability up to 45 nm. It is clear that the body bias controller is causing some area overhead. transistor size has reached to a level of deep nanometer. References 1. so the area is not a major concern. Chaudhury. This control circuit minimizes the leakage power. Macii.-I. Circuits Syst.5%. nanowire FET. Layout Figure 12 shows the layout of 8  16 SRAM array architecture. we have seen the e®ectiveness of the proposed SRAM cell.5. voltage and temperature variations. 2. by the variation of threshold voltages.5% and 89.Controller R. Sinha and S. Moreover. E. Chaudhury 128 Cells Fig. Lorenzo & S. 12 (2013) 958–965. delay and improves the stability by controlling the threshold voltage of all the transistors of SRAM cell. Impact of oxide thickness on gate capacitance — A comprehensive analysis on MOSFET. 12.

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