IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 62, NO.

8, AUGUST 2014

1705

Design and Analysis of Broadband Darlington

Amplifiers With Bandwidth Enhancement
in GaAs pHEMT Technology
Gholamreza Nikandish, Student Member, IEEE, and Ali Medi, Senior Member, IEEE

AbstractThis paper presents a bandwidth enhancement technique for broadband Darlington amplifiers. A detailed analysis
of the high-frequency performance of the Darlington amplifier
and the effect of bandwidth enhancement is provided. A design
procedure is also given for broadband feedback Darlington
amplifiers with bandwidth enhancement and gain flattening. A
single- and a three-stage feedback amplifier with the proposed
improvements are designed and implemented in a 0.25- m AlGaAsInGaAs pHEMT technology. The single-stage amplifier
provides 6 0.4 dB of small-signal gain in the frequency band
of 130 GHz. The three-stage amplifier features 17.8
0.8 dB of
small-signal gain in the frequency band of 229 GHz. It provides
a gain-bandwidth product of 217 GHz, which is 3.3 times larger
than the unity gain frequency
of the process.
Index TermsBandwidth enhancement, broadband amplifiers,
Darlington amplifier, feedback amplifiers, monolithic microwave
integrated circuit (MMIC).

I. INTRODUCTION

ROADBAND amplifiers are important building blocks

of high-speed communication systems, imaging systems,
and wideband instrumentation. Several architectures are widely
used for implementation of broadband amplifiers including distributed amplifiers, feedback amplifiers, and multi-stage amplifiers with reactive impedance matching [1]. Traditionally, a
single transistor in the common-source configuration is used
as the transconductance stage in broadband amplifiers. Other
gain stage topologies including the cascode amplifier, commonsource with capacitive degeneration, emitter follower, the Darlington amplifier, and the CherryHooper amplifier are also employed as the transconductance stage to improve the amplifier
performance [2][21]. A Darlington amplifier is attractive in
broadband amplifiers as it can provide broad bandwidth performance up to microwave frequencies.
The Darlington amplifier was first introduced to improve the
low-frequency current gain of bipolar transistors [3]. Since then
it has been widely used in implementation of broadband amplifiers, such as distributed amplifiers [4][6], low-noise ampliManuscript received March 11, 2014; revised May 29, 2014; accepted May
31, 2014. Date of publication June 19, 2014; date of current version August 04,
2014.
The authors are with the Department of Electrical Engineering, Sharif University of Technology, Tehran, Iran (e-mail: nikandish@ee.sharif.edu).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TMTT.2014.2328972

Fig. 1. (a) Darlington amplifier and (b) circuit model used for calculation of
unity current gain frequency of the amplifier.

fiers [7], [9], transimpedance amplifiers [10], and power amplifiers [11]. Several circuit techniques have been proposed to improve the performance of the Darlington amplifier. In [2], a Darlington cascode amplifier with active self-bias and a linearizing
circuit has been proposed to improve the linearity-bandwidth
performance. In [12], a mirror-doubler has been used to extend
bandwidth of the amplifier. The inductive peaking techniques
have also been used to improve bandwidth [14]. Moreover, the
triple Darlington amplifier has been proposed to improve the
gain-bandwidth product (GBW) of the amplifier [17].
In this paper, a bandwidth enhancement technique is proposed for the Darlington amplifier. A detailed analysis of
high-frequency performance of the Darlington amplifier is
given in Section II. In Section III, the proposed technique to
improve bandwidth of the Darlington amplifier is presented.
In Section IV, a design procedure is given for the feedback
Darlington amplifier employing the bandwidth enhancement
and gain flattening techniques. Measurement results of the
implemented monolithic microwave integrated circuit (MMIC)
broadband amplifiers are presented in Section V.
II. HIGH-FREQUENCY ANALYSIS OF DARLINGTON AMPLIFIER
The Darlington amplifier can be considered as a transconductance stage. Here, its high-frequency parameters including unity
current gain frequency
, transconductance transfer function
, input/output admittances, as well as the feedback admittance between the input and output terminals of the amplifier are
derived and compared with that of a single transistor.
The schematic of a Darlington amplifier is shown in Fig. 1(a).
The current gain of the amplifier, using the equivalent circuit
shown in Fig. 1(b), is derived as

0018-9480 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

(1)

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IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 62, NO. 8, AUGUST 2014

Fig. 2. Triple Darlington amplifier.

where
is the unity current gain frequency of the
transistors. Here, drainsource capacitance, gatedrain capacitance, and output resistance of the transistors are neglected. The
transistors are conventionally biased at the gatesource voltage
that maximizes their transconductance. If the two transistors
are biased at the same gatesource voltages, then
, where
denotes the width of transistors. Thus,
of the two devices are identical.
Applying the condition
to (1) leads to the
following equation:
(2)
where
denotes the unity gain frequency of the Darlington
amplifier. The above equation can be solved to derive the unity
current gain frequency as
(3)
Therefore,
of the Darlington amplifier is about twice of the
unity current gain frequency of a single transistor. The presented
analysis provides a proof for the commonly known fact that the
Darlington structure can be regarded as a single transistor with
twice [9].
The triple Darlington amplifier, shown in Fig. 2, is also employed in design of broadband amplifiers [17]. The current gain
of the amplifier is derived as

(4)
Assuming identical
dition

for transistors and applying the conto (4) leads to

Fig. 3. (a) Darlington amplifier with main parasitic capacitances. (b) Two-port
equivalent model.

High-frequency behavior of the amplifier cannot be completely described by its unity current gain frequency. Thus,
the admittance parameters of the Darlington amplifier are
derived. The schematic of the Darlington amplifier with main
parasitic capacitances is shown in Fig. 3(a), where the resistor
provides the bias current path for
. It also affects the
high-frequency performance of the amplifier. The gatedrain
capacitance and output resistance of the transistors are neglected to simplify the analysis. The amplifier can be modeled
by a two-port network shown in Fig. 3(b). The main advantage of using this model is that the amplifier behavior can
be easily compared with that of a single transistor, which is
mostly used as the transconductance block. Using the circuit
model of Fig. 3(b) for a single transistor, it is found that the
transconductance is given by
(7)
where

is the low-frequency transconductance and

is the gate transit time, which is a process-dependent parameter and is almost independent of the transistor
width and bias.
By equating admittance parameters of the two circuits, it can
be shown that the four parameters
,
,
, and
are derived in terms of admittance parameters of the circuit in Fig. 3(a)
as follows:
(8)
(9)

(5)

(10)
(11)

By solving (5), the unity current gain frequency is derived to

be

Using (8)(11), it can be shown that

(6)

Therefore, the triple Darlington amplifier provides the unity

current gain frequency, which is three times that of a single transistor.

(12)
(13)

NIKANDISH AND MEDI: DESIGN AND ANALYSIS OF BROADBAND DARLINGTON AMPLIFIERS

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(14)
(15)
where

It can be shown that the second-order polynomial common in

denominators of (12)(15) includes two far apart real roots.
Thus, it can be approximated by
to simplify the results. The behavior of each parameter will be investigated in
the following.
1) Transconductance: The transconductance of the amplifier
at low frequencies, using (12), is derived as
(16)
is chosen large enough such that
If the resistance
, then
. Thus, the low-frequency transconductance is determined by the transistor
. However, the resistor
cannot be arbitrarily large as it limits the output voltage
swing. Also, as will be shown later, large
values degrade
stability of the amplifier. From (16), it is found that
should
be chosen larger than
to achieve higher transconductance
for a given total bias current. In Fig. 4(a), transconductance of
the amplifier extracted from circuit simulations is plotted for
different transistor width ratios
. The circuit simulations are performed using a 0.25- m GaAs pseudomorphic
HEMT (pHEMT) process with
GHz and
ps.
The transistor
has the width of
m and
main elements of its small-signal model are
mS,
fF, and
fF. The transistor
has the
same number of fingers, but the width of each finger is scaled
according the ratio
. Both of the transistors are biased at
the gatesource voltage of 0.8 V to maximize their transconductance. The supply voltage is 8 V. The resistance
is assumed to be 50 . While the low-frequency transconductance
improves by using larger
, the bandwidth is reduced.
The theory and circuit simulation results for the low-frequency
transconductance are compared in Fig. 4(b).
Moreover, (12) indicates that the transconductance frequency
response includes a dominant pole that is given by
(17)

Fig. 4. Effect of the width ratio of transistors on transconductance of the Darlington amplifier. (a) Frequency response of the transconductance transfer function. (b) Low-frequency transconductance. (c) Locations of the poles and zero
of the transconductance transfer function. (d) Ratio of bandwidth of the Darlington amplifier to bandwidth of a single transistor.

Also, it has a second pole at

, which is much higher than

, a third pole at
, and a zero at
(18)

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The pole and zero frequencies normalized by

are plotted
in terms of the transistor width ratio in Fig. 4(c). The third pole
is at least ten times higher than other poles, thus it is not shown
here. As
increases, the first pole frequency, and hence,
overall bandwidth, are reduced while the second pole and the
zero remain almost constant. By approximating bandwidth of
transconductance of the Darlington amplifier
with the
first pole frequency,
, it can be shown that compared to a single transistor with bandwidth of
,
bandwidth of the Darlington amplifier is reduced by a factor of
(19)
,
, and
. It
where
is assumed that both transistors have the same
. In Fig. 4(d),
the ratio
derived using (19) is compared with circuit simulation results. The discrepancy between the theory and
simulation results in Fig. 4(d) is mainly due to neglecting other
parasitic components of transistors, e.g., series resistance and
inductance in each terminal of the device. For
,
the simulation results exhibit higher bandwidth compared to the
theoretical result given by (19). This is due to the zero located
near the first pole [see Fig. 4(c)] that partially cancels out its effect and improves the bandwidth.
2) Input Admittance: The input admittance of the amplifier
at high frequencies, using (13), can be approximated by a capacitance given by
(20)
which is smaller than the gatesource capacitance of each one
of the transistors. If
is neglected, the input capacitance is
the series combination of the gatesource capacitances of the
two transistors.
Investigation of (13) indicates that the input admittance of the
Darlington amplifier includes a real part. It can be shown that
there is a maximum
value that ensures the real part of the
input admittance is positive at all frequencies. Thus, resistor
cannot have an arbitrarily large value. The amplifier can intentionally be designed such that it exhibits a negative resistance at
its input to be used to compensate other losses in the circuit and
improve the bandwidth. However, stability of the overall amplifier should be carefully examined.
3) Output Admittance: The output admittance of the amplifier at high frequencies can be approximated by a capacitance
that its value, using (14), is derived to be
(21)
is much greater than the width
If width of the transistor
of
, the output capacitance is dominated by
, while (20)
indicates that the input capacitance is dominated by
. Similar to the input admittance, the output admittance also includes
a real part. Using (14), it can be shown that the resistance
should be smaller than a maximum value to ensure that real part
of the output admittance is positive at all frequencies.
4) Feedback Admittance: The capacitances
and
generate a path from the output to the input of the amplifier that

Fig. 5. Effect of resistance

on stability of the Darlington amplifier.

Fig. 6. Triple Darlington amplifier with resistors

and

degrades its reverse isolation and stability. Equation (15) also

indicates that the real part of this admittance is always negative.
This admittance can be made smaller by using larger width for
transistor
.
The analysis presented above indicates that the resistance
has a significant effect on the stability of the Darlington amplifier. In Fig. 5, the stability factor is depicted for a single transistor and Darlington amplifier with different
values. The
width of all transistors is 2 75 m. Stability can be improved
by using smaller
, but the low-frequency transconductance
of the amplifier is reduced.
The same analysis can be performed for the triple Darlington
amplifier circuit shown in Fig. 6. However, analytical results
are complicated and cannot provide useful insight about the circuit performance. In Fig. 7, transconductance of the amplifier is
shown in terms of frequency for different transistor width ratios.
In the case that all transistors have the same width, the transconductance exhibits the lowest roll-off with frequency. The lowfrequency transconductance can be increased by using longer
widths for transistors
and
. However, bandwidth of the
transconductance is reduced. Assuming that the total width of
and
is four times the width of
, i.e.,
, three cases are shown in Fig. 7. It can be observed that
in the given frequency band, the case
provides a good compromise between low-frequency value of the
transconductance and its bandwidth.
III. BANDWIDTH-ENHANCED DARLINGTON AMPLIFIER
The proposed method to improve bandwidth of the Darlington amplifier is shown in Fig. 8. The inductance
is
inserted between the drain terminals of the two transistors. This
inductance separates the two parasitic capacitances
and
at the output node of the amplifier. It also separates
from
, which leads to improvement in reverse isolation

NIKANDISH AND MEDI: DESIGN AND ANALYSIS OF BROADBAND DARLINGTON AMPLIFIERS

1709

Fig. 7. Effect of the width ratio of transistors on transconductance of the triple

m,
V, and
V.
Darlington amplifier.
fF,
fF,
mS, and
mS.

Fig. 9. Effect of different parameters on frequency response of the Darlington

. (b)
.
amplifier. (a)
Fig. 8. Darlington amplifier with the proposed bandwidth enhancement.

between the drain and gate of the transistor

. The transconductance of the Darlington amplifier with this inductance is
derived to be
(22)
where

Here,
,
, and
are parameters that can be set by the designer, while
and
are process-dependent parameters. The third-order polynomial in the denominator
of (22) has the same form as the series peaking bandwidth

enhancement technique conventionally used in broadband amplifiers [18], [19]. Thus, it is expected that frequency response
of the amplifier have some common properties with the series
peaking technique. Simulations indicate that the parameters
and have an insignificant effect on the frequency response.
The effect of other parameters is illustrated in Fig. 9.
For the 0.25- m pHEMT process that is used for implementation of amplifiers,
and
. Fig. 9(a) indicates
that there is a dip and a peak in the frequency response. The frequency and magnitude of these points can be controlled by the
parameter
. This behavior is also observed in
the series peaking technique [18], [19]. Using a larger
ratio, as shown in Fig. 9(b), reduces the bandwidth when inductance
is not used
. However, in the presence of
,
the peak frequency is almost unchanged while gain variations in
the frequency band are increased. It should be noted that losses
present in the circuit suppress magnitudes of the dip and peak
in the frequency response. It is also possible to derive other admittance parameters of the amplifier. However, the results are
complicated and cannot provide useful insights about the amplifier performance.
The effect of different values of
on the transconductance
is illustrated in Fig. 10. These results are derived using circuit
simulations. There is an optimum value of
that the transconductance exhibits the lowest roll-off with frequency. If
is
excessively large, the transconductance exhibits large peaking
and sharply falls at the end of frequency band. In Fig. 11, 3-dB
bandwidth of the transconductance is depicted in terms of the
inductance
. The bandwidth is improved by a factor of 1.58
for
with
nH, and 1.91 for

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IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 62, NO. 8, AUGUST 2014

Fig. 12. Triple Darlington amplifier with the proposed bandwidth enhancement
method.

Fig. 10. Effect of different values of

fF,
lington amplifier.
mS.

on the transconductance of the DarfF,

mS, and

Fig. 13. Effect of different values of

the triple Darlington amplifier.
mS.
and
Fig. 11. Effect of different values of
ductance.

and
fF,

on the transconductance of
fF,
mS,

on 3-dB bandwidth of the transcon-

with
nH. For the case
, the bandwidth
is improved by a factor of 1.48 (with
nH), which is
lower than the previous cases (not shown). Therefore, the inductance
should be optimized based on the width ratio of the
two transistors, parasitic capacitances, and the frequency band
of interest.
The proposed bandwidth enhancement can also be adopted
in the triple Darlington amplifier, as shown in Fig. 12. The
two inductances
and
separate the drain terminals of
the transistors. Their values should be optimized to minimize
the transconductance roll-off with frequency. In Fig. 13, the
transconductance of the triple Darlington amplifier is plotted

for different transistor width ratios and inductance values. The

transconductance is shown for four pairs of the inductance
values: both inductances are zero, one of the inductances
is zero and the other is optimized for the lowest roll-off of
the transconductance, and both inductances are optimized to
minimize the transconductance roll-off. It is observed that the
minimum roll-off of the transconductance is obtained when
both inductances are used and all transistors have the same
width.
IV. DESIGN OF BROADBAND DARLINGTON AMPLIFIER
The Darlington amplifier is employed in design of a shuntfeedback amplifier shown in Fig. 14. The input and output impedances of the amplifier are matched to 50 . The amplifier is

NIKANDISH AND MEDI: DESIGN AND ANALYSIS OF BROADBAND DARLINGTON AMPLIFIERS

Fig. 14. Shunt-feedback amplifier with input and output impedance matching
networks.

expected to operate in the frequency band of 130 GHz. A design procedure for the amplifier is provided in Sections IV-AE.
A. Feedback Network
The amplifier low-frequency transconductance
and the
feedback resistance
are determined based on
the closed-loop voltage gain and the input/output impedance
matching conditions of the feedback amplifier. Using the circuit
shown in Fig. 14 and neglecting output resistance of the transistors and loss of the input/output matching networks, it can be
shown that the voltage gain and input/output impedances at low
frequencies are given by
(23)
(24)
(25)
where

and

denote the source and load resistances. For

, using (23)(25) with
, it can be shown that
(26)
(27)

The parameter is chosen according to the tolerable input/

output reflection coefficient . Using
, it
can be shown that to achieve
, the value of should be
chosen in the range of
to
.
For example, to achieve the reflection coefficient lower than
dB , should be chosen between 0.67 and 1.5.
In this design, the feedback amplifier is designed to provide a
voltage gain of
. Thus, for
,
mS
and
, while for
,
mS and
are obtained. Choosing a small
value reduces power consumption of the amplifier, but also degrades its
linearity. Moreover, using a large
values degrades stability
of the amplifier. Therefore, the first option is chosen in this design.
B. Device Selection
Selection of the size and bias of transistors is dependent on
gain, bandwidth, noise, and linearity of the amplifier. If no constraint exists on the noise and linearity of the amplifier and

1711

only the gain and bandwidth should satisfy a set of given conditions, the two transistors should be biased at a current density that maximizes their transconductance. Thus, a small width
can be chosen for
. This improves bandwidth and lowers
power consumption of the amplifier. The width of
is determined from the ratio
optimized based on the gain-bandwidth tradeoff addressed in Section II. However, if noise or linearity of the amplifier should satisfy given constraints, the width
of
should be determined based on these considerations. In
this design, there is no limitation on noise of the amplifier, but
the output 1-dB compression point (
) of the amplifiers
should be better than 10 dBm. The width of transistors are
selected as
m and
m. Both
are biased at
V, leading to bias currents of 16
and 34 mA, respectively. The resulting transconductances are
mS and
mS. The resistance
is determined based on bias current of the transistor
and stability
condition for the Darlington amplifier. It is derived to be 50
in this design. The total transconductance, using (16), is derived
to be
mS.
C. Impedance-Matching Networks
The conditions given by (26) and (27) ensure impedance
matching only at low frequencies. However, the parasitic capacitances of the transistors degrade the impedance matching
at high frequencies. In the Darlington amplifier, the impedance
matching is commonly achieved in narrower bandwidth
compared to gain [20]. To provide input/output impedance
matching at high frequencies, ladder-type networks are used at
the input and output of the amplifier. The parasitic capacitances
of the transistors are absorbed in these matching networks
to achieve impedance matching in the desired bandwidth.
A circuit simulation tool such as Agilent Technologies Advanced Design System (ADS) can be used for synthesis of the
impedance-matching networks.
D. Gain Flattening
The feedback impedance
can be designed to extend
bandwidth and improve flatness of the gain response. An inductor
can be used in the feedback path to further improve bandwidth [1]. This inductance can also represent the
unwanted parasitic inductance of the line connecting the feedback network between the input and output of the amplifier. The
feedback amplifier employing a Darlington amplifier with bandwidth enhancement and gain flattening is shown in Fig. 15. The
inductance
can be determined by the method described in
Section III to improve bandwidth while maintaining gain flatness. Both
and
introduce peaking in the gain response at
high frequencies. The feedback resistance can be partially bypassed at high frequencies using capacitance
to compensate the peaking introduced by the inductances and flatten the
gain response. The gain of the feedback amplifier is depicted in
Fig. 15 for three cases. In the conventional case, the Darlington
amplifier is adopted with the purely resistive shunt feedback.
The bandwidth-enhanced case refers to the circuit with inductances
and
, where the bandwidth is improved compared

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Fig. 15. Feedback amplifier employing a Darlington amplifier with bandwidth

enhancement and gain flattening.

gain of 8. Using identical stages does not necessarily lead to

the best amplifier performance. The width of transistors can
be up-scaled toward the last stage to improve linearity of the
amplifier. However, using identical stages facilitates the design
and layout of the amplifier. The output impedance of each amplifier stage can also be directly matched to the input impedance
of the next stage. However, the gain flatness and stability of the
amplifier can be improved when all stages are matched to 50impedance. Therefore, the three-stage amplifier is implemented
using identical stages with 50- impedance matching at all
interfaces.
The amplifiers are implemented in a 0.25- m GaAs pHEMT
process and optimized using the ADS simulator to improve gain,
bandwidth, and gain flatness. The layouts of the amplifiers are
designed and simulated in the ADS Momentum environment.
Electromagnetic (EM) simulations are performed to consider
the effects of discontinuities and coupling between the passive
structures in the layouts.
V. MEASUREMENT RESULTS

Fig. 16. Schematic of the single-stage amplifier.

to the conventional amplifier, but large peak and dip are also introduced in the gain frequency response. In the bandwidth-enhanced/gain-flattened case, the peak is suppressed by partial bypassing of the feedback resistance and a flat gain response is
achieved. This would lead to a small degradation in the bandwidth due to the added capacitance
.
E. Complete Amplifier Design
The complete schematic of the designed single-stage amplifier is shown in Fig. 16. The inductors are implemented using
microstrip transmission lines. The capacitors

provide
dc block. The resistor
is used to decrease the amplifier gain
at very low frequencies and improve its stability. The capacitor
is inserted in parallel with
to reduce its equivalent
impedance at high frequencies and avoid unnecessary degradation of gain at these frequencies. The resistors
are used
to provide the gate bias for the transistors. The inductor
is used to enable operation of the amplifier at low frequencies.
It is implemented using a bond-wire with 10-mm length to provide about 10-nH inductance. The resistor
is used to improve stability. It is noteworthy that the total feedback resistance
is close to the calculated value of
200 in Section IV-A.
In the three-stage amplifier, three identical stages similar to
the single-stage amplifier are cascaded to achieve a voltage

The designed amplifiers are implemented in an AlGaAsInGaAs pHEMT technology with 0.25- m gate length on a
100- m-thick substrate. The unity gain frequency
and
the maximum oscillation frequency of the process are 65
and 190 GHz, respectively. The peak transconductance of
transistors is 340 mS/mm, obtained at the bias voltages of
V and
V(110-mA/mm current density).
The process offers two metal layers with 1- and 4- m thickness, air bridges, and ground back-vias. Moreover, metalinsulatormetal (MIM) SiN capacitors with 650-pF mm density,
thin film and mesa resistors with 50- and 160sheet resistances are available in the process. The MMIC chips and test
boards are assembled in aluminum housing. The backside of the
chip is attached to the housing using a conductive epoxy. The
chips are connected to the external board using gold bond wires
with 18- m diameter. The test board provides adjustable bias
voltages and RF input/output access through 50- microstrip
lines. Effects of the test board parasitic components have been
de-embedded from the measurement results.
In Fig. 17, the die microphotographs of the two amplifiers and
the three-stage amplifier mounted on the test board are shown.
The RF choke
is realized using bond wires. The input
and output of the amplifier are connected to the test board using
four bond wires in parallel to reduce their inductance (
and
). The external elements
and
are inserted in the gate
bias paths to improve the amplifier stability. The amplifiers are
biased at
V,
V, and
V.
The small-signal -parameters of the two amplifiers are
shown in Figs. 18 and 19. The single-stage amplifier provides
6-dB average small-signal gain with 0.4-dB variation in the
frequency band of 130 GHz. The 3-dB bandwidth of the
amplifier spans from 0.8 to 32.7 GHz. The three-stage amplifier
provides 17.8-dB average small-signal gain with 0.8-dB variation in the frequency band of 229 GHz. The 3-dB bandwidth
ranges from 1.5 to 29.5 GHz.
of the amplifiers is shown in Fig. 20. Its value measured at the frequency of 5 GHz is 15.5 dBm for the single-stage
and 15.3 dBm for the three-stage amplifier. It is noticed that

NIKANDISH AND MEDI: DESIGN AND ANALYSIS OF BROADBAND DARLINGTON AMPLIFIERS

1713

Fig. 19. -parameters of the three-stage amplifier (solid lines: measurement,

dashed lines: simulation).

Fig. 17. (top) Die microphotograph of the single-stage amplifier. (middle) Die
microphotograph of the three-stage amplifier. (bottom) Three-stage amplifier
mounted on the test board.

Fig. 20.

Fig. 18. -parameters of the single-stage amplifier (solid lines: measurement,

dashed lines: simulation).

degrades at higher frequencies. This is a typical behavior of the Darlington amplifier that originates from departure
of the phase at the output of the amplifier from 180 as frequency
increases [2].

of the: (a) single-stage and (b) three-stage amplifiers.

In Table I, performance of the designed amplifiers is compared with the state-of-the-art broadband Darlington amplifiers.
The three-stage amplifier provides the highest GBW compared
to the listed designs. This higher GBW can be partially due
to using more amplifier stages compared to other designs.
However, it should be noted that although higher GBW can be
achieved using more amplifier stages, the gain flatness over the
frequency band cannot be easily maintained. The gain flattening
technique described before helps to improve the gain flatness
of the amplifier. The ratios
and
have
been used as figure-of-merits to compare GBW performance of
the amplifiers implemented in different technologies.
It should be noted that the broadband amplifiers should not
be compared merely based on their GBW performance. Using
smaller transistors leads to higher GBW at high frequencies, at

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TABLE I
PERFORMANCE COMPARISON OF THE DESIGNED AMPLIFIERS WITH STATE-OF-THE-ART BROADBAND DARLINGTON AMPLIFIERS

the cost of degraded linearity of the amplifier. As indicated in

Table I,
of the designed amplifiers is higher than other
designs, except that [2], which adopts a linearization technique
for the Darlington amplifier. It should be noted that there is a
tradeoff between linearity and power consumption
of the
amplifier. It is always possible to lower the power consumption
by reducing the supply voltage if no constraint is put on linearity of the amplifier. However, if there are some constraints
on linearity, the supply voltage and size of transistors should be
high enough, both leading to higher power consumption. Thus,
the ratio
, which is efficiency of the amplifier at the
1-dB compression point, is used to compare performance of the
amplifiers considering the tradeoff between linearity and power
consumption.
VI. CONCLUSION
In this paper, a bandwidth enhancement technique is proposed for broadband Darlington amplifiers. The bandwidth
enhancement reduces roll-off of the transconductance with
frequency. Detailed high-frequency analysis of the Darlington
amplifier is provided. A design procedure is given for determination of size and bias of transistors, bandwidth enhancing
inductance, feedback resistance, and input/output impedance
matching networks in broadband Darlington amplifiers with
shunt feedback. A single-stage amplifier with 6
0.4 dB
small-signal gain in 130 GHz and a three-stage amplifier with
17.8
0.8 dB small-signal gain in 229 GHz are designed
using the proposed techniques and implemented in a 0.25- m
AlGaAs-InGaAs pHEMT technology.

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1715

Gholamreza Nikandish (S11) received the B.Sc.

degree (with highest honor) from Shahid Chamran
University, Ahvaz, Iran, in 2004, the M.Sc. degree in
electrical engineering from the Sharif University of
Technology, Tehran, Iran, in 2006, and is currently
working toward the Ph.D. degree at the Sharif
University of Technology.
His research interests include RF and microwave
integrated circuits.
Mr. Nikandish was the recipient of the Second
Place Award of the National Electrical Engineering
Olympiad and the Third Place Award of the National Universities Exam
for M.Sc. Program in 2004. He was also the recipient of the National Elite
Foundation Fellowship in 20102014.

Ali Medi (S98M08SM13) received the B.Sc.

degree from the Sharif University of Technology,
Tehran, Iran, in 2001, and the M.Sc. and Ph.D.
degrees in electrical engineering from the University
of Southern California, Los Angeles, CA, USA, in
2003 and 2007, respectively.
He is currently an Assistant Professor with the
Electrical Engineering Department, Sharif University of Technology, Tehran, Iran. He was a Research
Assistant with the UltRaLab, where he was involved
with the field of analog and RF circuit design for
ultra-wideband systems. He was with the Broadcom Corporation, where
he developed RF blocks for GSM cellular phone transceivers. His research
interests are RF and microwave integrated circuits, as well as wideband analog
circuit design.