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InternationalJournalofEnergyScience(IJES)Volume3Issue5,October2013

DOI:10.14355/ijes.2013.0305.06

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ReliabilityDesignofSource/DrainAdaptive
LayersinanHVPowernLDMOS
ShenLiChen*,TzungShianWu
Dept.ofElectronicEngineering,NationalUnitedUniversity
1,LienDaRoad,MiaoLiCity36003,Taiwan
jackchen@nuu.edu.tw

recently. Many efforts prevent the Kirk effect and


avoids reliability problems. Techniques in our work
with a higher dosage can improve the reliability of
LDMOS transistors. In addtion, the source/drainside
engineeringcansuppresssubstratenoiseandprevent
LU effect. Its a great method to ensure the HV
nLDMOS reliability in many kinds of applications.
Therefore, in this paper, our experimental data will
demonstrate a novel weak snapback characteristic in
theHVnLDMOSdevice.

Abstract
Reliabilityissuesareveryimportantespeciallyforthehigh
voltage (HV) devices. Unfortunately, an HV nLDMOS is
oftendamagedbyalatchup(LU)problemwhenittriggered
by a transient noise and a bias condition VDDmax is greater
than that of the device holdingvoltage (Vh). The snapback
phenomena of the new adding adaptive layers in the
source/drain ends of an nLDMOS are investigated in this
paper. It is a novel method to reduce the surface field,
control the trigger voltage and holding voltage.
Experimentally, the rightshifting characteristic of snapback
IV curves depends on new adding Pad, LPad, Nad, and LNad
parameters, respectively. Eventually, these source/drain
adaptive layers of an nLDMOS can effectively improve the
LUimmunityunderanHVoperation.
Keywords
Electrostatic Discharge (ESD); Holding Voltage (Vh); Latchup
(LU);nLDMOS;Snapback;TriggerVoltage(Vt1)

Introduction

FIG.1.CONVENTIONALSTRUCTUREOFANNLDMOS

HV integrated circuits have been implemented in


manyapplications,suchasautomotive,aircraft,LCD
drivers, and industrial robotics. The electrostatic
discharge(ESD)andLUreliabilitiesaretwoimportant
issuesinmanykindsofapplications.And,itisalways
found that an nchannel lateraldiffused MOSFET
(nLDMOS) shown in Fig. 1 always has a very low
holdingvoltage(Vh),whichcouldsufferthetransient
induced LU failure during normal circuit operating
condition and inherently weak with respect to ESD
stress, especially when such HV nMOSFETs are used
in onchip I/O circuits or power to ground protection
cellsofanintegratedcircuit.

FIG.2.SOURCESIDEPadLAYERINANNLDMOSSTRUCTURE

ThispaperdiscussesthestudyofannLDMOSusinga
systematicapproach.DUTsaredesignedaccordingto
a0.6m80V/5V(VDS/VGS)BCDprocess,thechannel
length (L) is kept to be 3 m; channel width (W) is
keptaconstancy,50m.Variationsofspecificprofiles,
inFigs2and3,thatleadtohigherVhinthenLDMOS
are described. The source/drainside engineering are
attracted much attention to research HV devices

FIG.3.DRAINSIDENadLAYERINANNLDMOSSTRUCTURE

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DOI:10.14355/ijes.2013.0305.06

Device Engineering and I-V Characteristics

higher implant doping of Pad layer will affect the


channelprofileasaPadpositionnearbythechannel
region. In Figs 5 and 6, a higher Pad implant
improves LU immunity, however, the Ron
resistance and threshold voltage raised as well.
Eventually,anoptimizedconditionwillbetraded
off among the holding voltage, Ron resistance, and
threshold voltage. Furthermore, according to a 0.6
m 80 V/5 V (VDS/Vg) BCD process, if an implant
dosage of sourceside Pad is greater than 4.51015
atoms/cm2, then its threshold voltage of an
nLDMOS will be greater over 5 V on the normal
condition.So,inthiswork,thebestdosecondition
ofPadlayeris4.51015atoms/cm2asshowninFigs5
and6.

SourcesideEngineeringofannLDMOS
1)

EffectofthePadImplantDose

As a current flows through N+/Pbase junction when


this nLDMOS is triggered by an ESD event that
willeasilyleadtoLUhappeningasshowninFig.4.
A parasitic BJT turned on by an ESD event is
appliedonthedrainsideregionanditssnapbackI
V curve describes this phenomenon. A gate bias
inducedinversionlayerappearsonchannelsurface
toturnonMOStodischargeESDcurrentthatwill
be more faster than the internal equivalent BJT
structure (gategrounded type) triggered on.
Extended current flow lines pass through the
Nepi/Psub space to source region that causes Kirk
effect.APadlayerstructurecanreduceelectronslife
time when an ESD event appears and a damaged
degradation is excluded in the source region. The
electronlifetimedegradationwillbeagreatbenefit
against Kirk effect. Such that a Pad layer can be
addedtoagainstgroundnoiseandpreventtheLU
effect. Increasing the Pad implant dose of source
side can raise the recombination rate and the
occurrence of punchtrough current is more
difficult. A holding voltage was raised to improve
LU problem significantly by a Pad implant dose
increasing as shown in Fig. 5. But the channel
resistance (Rch) was increased by raising the Pad
implant dosage; meanwhile, the threshold voltage
wasincreasedtoo.

FIG.5.CHARACTERISTICSOFPadIMPLANTDOSEVS.
THRESHOLDVOLTAGEANDHOLDINGVOLTAGE(ASTHE
LPadBEEQUALTO10.8UM)

FIG.6.CHARACTERISTICSOFPadIMPLANTDOSEVS.
THRESHOLDVOLTAGEANDRONRESISTANCE(ASTHELPadBE
EQUALTO10.8UM)

FIG.4.CURRENTFLOWLINESOFAGATEGROUNDED
NLDMOSASANESDEVENTOCCURREDINTHEDRAINSIDE

2)

The triggeron factor of a parasitic BJT structure


is determined by the concentration and length of
base region. Adding a base region concentration
impliestherecombinationrateincreased.Further,a

350

EffectoftheLPadLength

InFigs7and8,byincreasinganLPadlength,i.e.the
lengths of the P+/N+ regions are kept the same,
changing LPad varies the P buffer layer extension
length under the channel, which canraise holding

InternationalJournalofEnergyScience(IJES)Volume3Issue5,October2013
DOI:10.14355/ijes.2013.0305.06

voltage. However, the threshold voltage and Ron


resistancewerevariedwiththePadmasklengthtoo.
The P+/N+ contacts were all wrapped in the Pad
layer in which the length will be equal to 12 m.
Additionally, the threshold voltage will be
increased significantly as the LPad is equal to 10.9
m, which is due to the status of channel region
influenced by a higher Pad dosage. The longer Pad
affectsthechannelregionstatussignificantly.Itcan
be concluded that the Pad structure at the N+/Pbase
junctioncanpreventtheLUeffect,meanwhile,the
Ronresistanceandthresholdvoltagewillbehigher
with a longer Pad mask in the source end. So that
thebestconditioninthissituation,theLPadlengthis
equalto10.8m.

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holdingvoltage(Vh)ofannLDMOSisraisedbyan
Nadimplantdose.ARESURF(ReduceSurfaceField)
method is used to reduce the drainside electric
field.ThejunctionconcentrationgradientofN+/Nepi
in the drain side is extremely high as for a
conventionalnLDMOS,sothattheN+/Nepijunction
becomes breakdown easily under an ESD event.
Therefore, a new Nad layer was created to reduce
the drain side high electric field. Such that this
N+/Nad/Nepi structure will be with two parasitic
junctions. It may be regarded as two parasitic
diodesthatincreasehighvoltageendurancebythis
structure used to avoid the Kirk effect as an Nad
layer was created too. If the N+/Nepi junction
breakdownoccurs,ahighcurrentwillbeproduced
to turn on a parasitic bipolarjunctiontransistor
(BJT),andwhichmayleadtoalatchupfailure.Itis
obvious that the holding voltage of an nLDMOS
canbeincreasedbyincreasinganNadimplantdose
asshowninFig.9.AsthedoseofNadimplantwas
muchlower,suchastheNaddosagebelow1.71015
atoms/cm2, a double snapback characteristic is
foundinthisstructure.Duetotheverticaljunction
depthXjthatwasshallow,ahighelectricfieldwill
approachN+/NadandNad/Nepijunctions,eventually.
Then, a higher Nad dosage will be with no double
snapback behavior. But, the trigger voltage is also
increased with the rising of Nad implant dose as
well. Finally, the best condition of this Nad was
equalto5.51015atoms/cm2whiletheLadwasfixed
at 5 m. Meanwhile, the holding voltage and
trigger voltage are 97 V and 156 V, respectively.
Therefore, it was a novel effective method to
increase holding voltage and avoid latchup effect
in an HV nLDMOS. And, the ESD protection
windowisseemtobeshiftedtorighthandinthis
experiment. These data can demonstrate that the
holdingvoltagewasincreasedbyincreemntofNad
implantdosesignificantlyasshowninFig.9.

FIG.7.CHARACTERISTICSOFPadMASKLENGTHVS.
THRESHOLDVOLTAGEANDRONRESISTANCE(ASTHEDOSE
OFPadIMPLANTBEEQUALTO4.51015ATOMS/CM2)

FIG.8.CHARACTERISTICSOFPadMASKLENGTHVS.HOLDING
VOLTAGEANDRonRESISTANCE(ASTHEPadDOSEOF
IMPLANTBEEQUALTO4.51015ATOMS/CM2)

DrainsideEngineeringofannLDMOS
1)

EffectoftheNadImplantDose

Furthermore,anNadimplantdoseandalengthLad
of adaptive layer in the drain side are added. The

FIG.9.EFFECTOFTHENadIMPLANTDOSE(ASLad=5UM)

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DOI:10.14355/ijes.2013.0305.06

2)

Results and Discussion

EffectoftheLNadLength

According to experiment results of the previous


Nad implant dose, a trigger voltage was also
increasedbyanNadimplantdose.Atthesametime,
it can lead to internal circuits damage before this
nLDMOS device turned on under an ESD event.
FromFig.10,thetriggervoltagecanbereducedby
increasingthemasklengthofLNad,i.e.thelengthof
theN+regioniskeptthesame,changingLNadvaries
the N buffer layer extension length under the
LOCOS.WhenanLNadwasfixedat5m,thehigh
electric field was found near to the N+ region of
drainside.

SourcesideEngineeringofannLDMOS
From Figs 12 and 13, the current flow lines of an
nLDMOSindifferentPadimplantdosages,thechannel
surface with a crowding current density when it is
withalightenedPadimplantdosage,butannLDMOS
structurewillbenotturnedonasaPadimplantwitha
heavily dosage such as 51015 cm2. However, the Pad
layer will be reduced to be a surface electricfield
distribution especially for some peak values at the
source region as shown in Figs 14~16. A higher
electricfieldpeakappears while the gradient of dope
concentration is larger, meaning that N+/Pad and
Pad/Pbase junction diodes have a higher capability
againstapunchthroughphenomenonandsharingthe
potential drops. Such that a Pad layer in the source
ends has some advantages in the high voltage
operation.

FIG.10.EFFECTOFTHEMASKLENGTHLNad(ASNad=5.51015
ATOMS/CM2)

WhentheLNadwasincreasedfrom5mto10.5m,
ahighelectricfieldwasreducedinthedrainside.
The trigger voltage can be reduced by increasing
the LNad parameter. Then, the Ron resistance is
decreasedaswell,seeFig.11.Thebestconditionof
LNadisequalto9.4mwhiletheNadimplantdose
is set to be 5.51015 atoms/cm2 in the experiment,
andthetriggervoltageandholdingvoltageare124
Vand93V,respectively.

FIG.12.ONSTATECURRENTFLOWLINESOFANNLDMOS
UNDERVg=5V,VDS=30V(ASPadIMPLANT=4.51015
ATOMS/CM2,LPad=10.8UM)

FIG.13.ONSTATECURRENTFLOWLINESOFANNLDMOS
UNDERVg=5V,VDS=30V(ASPadIMPLANT=51015ATOMS/CM2,
LPad=10.8UM)

FIG.11.RONRESISTANCEVS.MASKLENGTHOFLNad(ASNad=
5.51015ATOMS/CM2)

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InternationalJournalofEnergyScience(IJES)Volume3Issue5,October2013
DOI:10.14355/ijes.2013.0305.06

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observed due to the drain side; however, the double


snapbackbehaviourwasobviousonthesefourcurves
in Fig. 17. Moreover, the double snapback IV curves
are right shifted with a Pad implant too. In addition,
latchup key parameters are listed in Table. 1, and a
conventionalnLDMOS has asmaller holding voltage.
Therefore, from Table 1, the best condition of Vt1 and
Vhare125Vand70V,respectively.

FIG.14.SURFACEELECTRICFIELDDISTRIBUTIONOFA
CONVENTIONALNLDMOSSTRUCTURE

FIG.17.RIGHTSHIFTINGCHARACTERISTICSOFSNAPBACKI
VCURVESINDIFFERENTPadIMPLANTDOSAGES
TABLE1.THECOMPARISONOFSNAPBACKPARAMETERSDURING
DIFFERENTPADIMPLANTDOSAGES

FIG.15.SURFACEELECTRICFIELDDISTRIBUTIONOFAN
NLDMOSWITHLIGHTENEDDOPINGPadSTRUCTURE

Vt1(Volt)

Vh(Volt)

Conventional

135

58

Padimplant=2.71015
atoms/cm2,LPad=10.8m

135

65

Padimplant=3.71015
atoms/cm2,LPad=10.8m

160

67

Padimplant=4.51015
atoms/cm2,LPad=10.8m

125

70

DrainsideEngineeringofannLDMOS
Figs 18~20 show the surface electricfield distribution
of an nLDMOS as the bias condition was stressed
under Vg= 5 V and VDS= 40 V. In Fig. 18, the electric
field of none with Nad structure in the drain side has
reachedabout104V/cm,therefore,theN+/Nepijunction
was easy breakdown under this high electric field.
Fortunately, from Fig. 19, an Nad structure can share
thehighelectricfieldofdrainsideanddecreasemore
significantly one order magnitude. If we enlarge the
length of LNad, the high electric field near the drain
sidewillbereducedasshowninFig.20.Therefore,by
this technique, the surface field at the drain side is
successfullylowered.ItcanbeconcludedthattheNad
structure can avoid a parasitic junctiondiode

FIG.16.SURFACEELECTRICFIELDDISTRIBUTIONOFAN
NLDMOSWITHHEAVILYDOPINGPadSTRUCTURE

RightshiftingcharacteristicsofsnapbackIVcurvesin
different Pad implant dosages as a length of LPad fixed
at 10.8 m are shown in Fig. 17. Obviously, the
holding voltage is increased with the Pad implant.
Previously the double snapback characteristic was

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DOI:10.14355/ijes.2013.0305.06

breakdownofN+/Nad/NepiandsuppresstheKirkeffect
efficaciously.

From Fig. 21, the snapback IV curve is right shifted


while increasing the Nad implant dosage. As the
concentration gradient of Nad/Nepi junction becomes
large,thenitleadstoahighelectricfieldmovedfrom
N+/Nad to Nad/Nepi. Two junction diodes can sustain a
highervoltagestress,suchthattheholdingvoltageof
an nLDMOS is increased by raising the Nad implant
dosage. It can be observed that the trigger voltage is
also increased by raising the Nad implant dosage as
well. Therefore, the latchup reliability issue of an
nLDMOS can be easily overcome with an Nad doping
techniqueinthedrainside.

FIG.18.SURFACEELECTRICFIELDDISTRIBUTIONWITHA
NONENadSTRUCTURE

FIG.21.RIGHTSHIFTINGCHARACTERISTICSOFSNAPBACKI
VCURVESINDIFFERENTNadIMPLANTDOSAGES(ASTHE
LNad=5UM)

Furthermore, snapback IV curves of three different


structuresareshowninFig.22,inwhichtheblackdot
line is a conventional structure of nLDMOS. Its
apparent that it has the lowest holding voltage and
holding current as compared with the other two. The
blue dash line is an effective method to increase the
holding voltage and the snapback IV curve is right
shifted significantly. Finally, the red solid line is an
optimizationresultinthiswork,anditiswithamuch
higher Vh and the lowest Vt1 values. This work
succeeds to realize a weak snapback characteristic of
nLDMOS.Suchthatthismethodologyhasanexcellent
LU capability to avoid latchup disaster and with a
much higher robustness to protect internal circuits
under an ESD event. Consequently, from Table 2, the
best condition of Vt1 and Vh are 124V and 93V,
respectively.Accordingly,bothgoodforthereliability
designwindowbythisdrainsideengineeringaredue
toadecrement7V(5.3%)oftheVt1andanincrement
21V(29.2%)oftheVh.

FIG.19.SURFACEELECTRICFIELDDISTRIBUTIONWITHAN
NadSTRUCTURE(ASNad=5.51015ATOMS/CM2,LNad=5UM)

FIG.20.SURFACEELECTRICFIELDDISTRIBUTIONWITHAN
NadSTRUCTURE(ASNad=5.51015ATOMS/CM2,LNad=9.4UM)

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InternationalJournalofEnergyScience(IJES)Volume3Issue5,October2013
DOI:10.14355/ijes.2013.0305.06

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moreeffectivetoensurereliabilitycapabilityinmany
kinds of applications. Thus, it is very easy to fine
tuning the trigger voltageand the holding voltage by
usingtheseadaptivelayersvariations.
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JianHsing Lee, S.H. Chen, Y.T. Tsai, D.B. Lee, F.H. Chen,

In this work, a weak snapback of an nLDMOS has


been presented. The source/drain engineering can
suppress substrate noise and prevent latchup effect.
Thepeakvalueofsurfaceelectricfieldcanbereduced
by these two junction diodes N+/Pad and Pad/Pbase or
N+/Nad and Nad/Nepi successfully. And, the latchup
issuecanbeeasilysolvedbythesemethodologiesina
high voltage operation. So, its a novel method to
reducethesurfacefield,controlthetriggervoltageand
holding voltage. Obviously, the holding voltage is
increasedandanimprovementofLUreliabilitycanbe
achieved.Therightshiftingcharacteristicofsnapback
IV curves depends on Pad, LPad, Nad, and LNad,
respectively. Eventually, it is found that a more
robustness characteristic of LU reliability can be
obtainedbyinsertingthesenewaddingPad/Nadlayers
in the source/drain sides. It can be concluded that a
novel source/drain engineering to achieve weak
snapback nLDMOS by the adaptive layer for HV
power applications in which both the suitable trigger
voltage and holding voltage can be realized easily.
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ShenLi Chen was born in 1958, joined the ERSO, ITRI,


Taiwan in 1987, and worked at the R&D department
responsible for reliability analysisin submicron circuits. He
received Ph.D. degree from National TsingHua University,
Taiwan,in1992.Afterthen,healsoactedandirectorofAX
Electronics Corporation in R&D division, focused on I/O
ESD/Latchup cells design especially used in HV processes
andtheDCDCanalogcircuitdesign.In2001,hejoinedthe
department of Electronic Engineering of National United
University,Taiwan,asanassociateprofessor.

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New Protection Structures for Smart Power Technology
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measured by transmissionlinepulsing (TLP). IEEE
ElectronDeviceLetters29(2008):762764.

In2003,hewasthechairmanofdept.electronicengineering
ofNationalUnitedUniversity,Taiwan.In2013,healsowas
an adjunct professor of Software and Microelectronics
School at Wuxi of Peking University, China. Recently, he
continues to pursue his research interests in the modeling
andcharacterizationofHVpowerdevices,andhighESD/LU
immunitydesignsinVLSIandpowerelectronics.

W.Y.Chen,M.D.Ker,Y.J.Huang,Y.N.JouandG.L.Lin.
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