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DOI:10.14355/ijes.2013.0305.06
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ReliabilityDesignofSource/DrainAdaptive
LayersinanHVPowernLDMOS
ShenLiChen*,TzungShianWu
Dept.ofElectronicEngineering,NationalUnitedUniversity
1,LienDaRoad,MiaoLiCity36003,Taiwan
jackchen@nuu.edu.tw
Abstract
Reliabilityissuesareveryimportantespeciallyforthehigh
voltage (HV) devices. Unfortunately, an HV nLDMOS is
oftendamagedbyalatchup(LU)problemwhenittriggered
by a transient noise and a bias condition VDDmax is greater
than that of the device holdingvoltage (Vh). The snapback
phenomena of the new adding adaptive layers in the
source/drain ends of an nLDMOS are investigated in this
paper. It is a novel method to reduce the surface field,
control the trigger voltage and holding voltage.
Experimentally, the rightshifting characteristic of snapback
IV curves depends on new adding Pad, LPad, Nad, and LNad
parameters, respectively. Eventually, these source/drain
adaptive layers of an nLDMOS can effectively improve the
LUimmunityunderanHVoperation.
Keywords
Electrostatic Discharge (ESD); Holding Voltage (Vh); Latchup
(LU);nLDMOS;Snapback;TriggerVoltage(Vt1)
Introduction
FIG.1.CONVENTIONALSTRUCTUREOFANNLDMOS
FIG.2.SOURCESIDEPadLAYERINANNLDMOSSTRUCTURE
ThispaperdiscussesthestudyofannLDMOSusinga
systematicapproach.DUTsaredesignedaccordingto
a0.6m80V/5V(VDS/VGS)BCDprocess,thechannel
length (L) is kept to be 3 m; channel width (W) is
keptaconstancy,50m.Variationsofspecificprofiles,
inFigs2and3,thatleadtohigherVhinthenLDMOS
are described. The source/drainside engineering are
attracted much attention to research HV devices
FIG.3.DRAINSIDENadLAYERINANNLDMOSSTRUCTURE
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DOI:10.14355/ijes.2013.0305.06
SourcesideEngineeringofannLDMOS
1)
EffectofthePadImplantDose
FIG.5.CHARACTERISTICSOFPadIMPLANTDOSEVS.
THRESHOLDVOLTAGEANDHOLDINGVOLTAGE(ASTHE
LPadBEEQUALTO10.8UM)
FIG.6.CHARACTERISTICSOFPadIMPLANTDOSEVS.
THRESHOLDVOLTAGEANDRONRESISTANCE(ASTHELPadBE
EQUALTO10.8UM)
FIG.4.CURRENTFLOWLINESOFAGATEGROUNDED
NLDMOSASANESDEVENTOCCURREDINTHEDRAINSIDE
2)
350
EffectoftheLPadLength
InFigs7and8,byincreasinganLPadlength,i.e.the
lengths of the P+/N+ regions are kept the same,
changing LPad varies the P buffer layer extension
length under the channel, which canraise holding
InternationalJournalofEnergyScience(IJES)Volume3Issue5,October2013
DOI:10.14355/ijes.2013.0305.06
www.ijesci.org
holdingvoltage(Vh)ofannLDMOSisraisedbyan
Nadimplantdose.ARESURF(ReduceSurfaceField)
method is used to reduce the drainside electric
field.ThejunctionconcentrationgradientofN+/Nepi
in the drain side is extremely high as for a
conventionalnLDMOS,sothattheN+/Nepijunction
becomes breakdown easily under an ESD event.
Therefore, a new Nad layer was created to reduce
the drain side high electric field. Such that this
N+/Nad/Nepi structure will be with two parasitic
junctions. It may be regarded as two parasitic
diodesthatincreasehighvoltageendurancebythis
structure used to avoid the Kirk effect as an Nad
layer was created too. If the N+/Nepi junction
breakdownoccurs,ahighcurrentwillbeproduced
to turn on a parasitic bipolarjunctiontransistor
(BJT),andwhichmayleadtoalatchupfailure.Itis
obvious that the holding voltage of an nLDMOS
canbeincreasedbyincreasinganNadimplantdose
asshowninFig.9.AsthedoseofNadimplantwas
muchlower,suchastheNaddosagebelow1.71015
atoms/cm2, a double snapback characteristic is
foundinthisstructure.Duetotheverticaljunction
depthXjthatwasshallow,ahighelectricfieldwill
approachN+/NadandNad/Nepijunctions,eventually.
Then, a higher Nad dosage will be with no double
snapback behavior. But, the trigger voltage is also
increased with the rising of Nad implant dose as
well. Finally, the best condition of this Nad was
equalto5.51015atoms/cm2whiletheLadwasfixed
at 5 m. Meanwhile, the holding voltage and
trigger voltage are 97 V and 156 V, respectively.
Therefore, it was a novel effective method to
increase holding voltage and avoid latchup effect
in an HV nLDMOS. And, the ESD protection
windowisseemtobeshiftedtorighthandinthis
experiment. These data can demonstrate that the
holdingvoltagewasincreasedbyincreemntofNad
implantdosesignificantlyasshowninFig.9.
FIG.7.CHARACTERISTICSOFPadMASKLENGTHVS.
THRESHOLDVOLTAGEANDRONRESISTANCE(ASTHEDOSE
OFPadIMPLANTBEEQUALTO4.51015ATOMS/CM2)
FIG.8.CHARACTERISTICSOFPadMASKLENGTHVS.HOLDING
VOLTAGEANDRonRESISTANCE(ASTHEPadDOSEOF
IMPLANTBEEQUALTO4.51015ATOMS/CM2)
DrainsideEngineeringofannLDMOS
1)
EffectoftheNadImplantDose
Furthermore,anNadimplantdoseandalengthLad
of adaptive layer in the drain side are added. The
FIG.9.EFFECTOFTHENadIMPLANTDOSE(ASLad=5UM)
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DOI:10.14355/ijes.2013.0305.06
2)
EffectoftheLNadLength
SourcesideEngineeringofannLDMOS
From Figs 12 and 13, the current flow lines of an
nLDMOSindifferentPadimplantdosages,thechannel
surface with a crowding current density when it is
withalightenedPadimplantdosage,butannLDMOS
structurewillbenotturnedonasaPadimplantwitha
heavily dosage such as 51015 cm2. However, the Pad
layer will be reduced to be a surface electricfield
distribution especially for some peak values at the
source region as shown in Figs 14~16. A higher
electricfieldpeakappears while the gradient of dope
concentration is larger, meaning that N+/Pad and
Pad/Pbase junction diodes have a higher capability
againstapunchthroughphenomenonandsharingthe
potential drops. Such that a Pad layer in the source
ends has some advantages in the high voltage
operation.
FIG.10.EFFECTOFTHEMASKLENGTHLNad(ASNad=5.51015
ATOMS/CM2)
WhentheLNadwasincreasedfrom5mto10.5m,
ahighelectricfieldwasreducedinthedrainside.
The trigger voltage can be reduced by increasing
the LNad parameter. Then, the Ron resistance is
decreasedaswell,seeFig.11.Thebestconditionof
LNadisequalto9.4mwhiletheNadimplantdose
is set to be 5.51015 atoms/cm2 in the experiment,
andthetriggervoltageandholdingvoltageare124
Vand93V,respectively.
FIG.12.ONSTATECURRENTFLOWLINESOFANNLDMOS
UNDERVg=5V,VDS=30V(ASPadIMPLANT=4.51015
ATOMS/CM2,LPad=10.8UM)
FIG.13.ONSTATECURRENTFLOWLINESOFANNLDMOS
UNDERVg=5V,VDS=30V(ASPadIMPLANT=51015ATOMS/CM2,
LPad=10.8UM)
FIG.11.RONRESISTANCEVS.MASKLENGTHOFLNad(ASNad=
5.51015ATOMS/CM2)
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InternationalJournalofEnergyScience(IJES)Volume3Issue5,October2013
DOI:10.14355/ijes.2013.0305.06
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FIG.14.SURFACEELECTRICFIELDDISTRIBUTIONOFA
CONVENTIONALNLDMOSSTRUCTURE
FIG.17.RIGHTSHIFTINGCHARACTERISTICSOFSNAPBACKI
VCURVESINDIFFERENTPadIMPLANTDOSAGES
TABLE1.THECOMPARISONOFSNAPBACKPARAMETERSDURING
DIFFERENTPADIMPLANTDOSAGES
FIG.15.SURFACEELECTRICFIELDDISTRIBUTIONOFAN
NLDMOSWITHLIGHTENEDDOPINGPadSTRUCTURE
Vt1(Volt)
Vh(Volt)
Conventional
135
58
Padimplant=2.71015
atoms/cm2,LPad=10.8m
135
65
Padimplant=3.71015
atoms/cm2,LPad=10.8m
160
67
Padimplant=4.51015
atoms/cm2,LPad=10.8m
125
70
DrainsideEngineeringofannLDMOS
Figs 18~20 show the surface electricfield distribution
of an nLDMOS as the bias condition was stressed
under Vg= 5 V and VDS= 40 V. In Fig. 18, the electric
field of none with Nad structure in the drain side has
reachedabout104V/cm,therefore,theN+/Nepijunction
was easy breakdown under this high electric field.
Fortunately, from Fig. 19, an Nad structure can share
thehighelectricfieldofdrainsideanddecreasemore
significantly one order magnitude. If we enlarge the
length of LNad, the high electric field near the drain
sidewillbereducedasshowninFig.20.Therefore,by
this technique, the surface field at the drain side is
successfullylowered.ItcanbeconcludedthattheNad
structure can avoid a parasitic junctiondiode
FIG.16.SURFACEELECTRICFIELDDISTRIBUTIONOFAN
NLDMOSWITHHEAVILYDOPINGPadSTRUCTURE
RightshiftingcharacteristicsofsnapbackIVcurvesin
different Pad implant dosages as a length of LPad fixed
at 10.8 m are shown in Fig. 17. Obviously, the
holding voltage is increased with the Pad implant.
Previously the double snapback characteristic was
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DOI:10.14355/ijes.2013.0305.06
breakdownofN+/Nad/NepiandsuppresstheKirkeffect
efficaciously.
FIG.18.SURFACEELECTRICFIELDDISTRIBUTIONWITHA
NONENadSTRUCTURE
FIG.21.RIGHTSHIFTINGCHARACTERISTICSOFSNAPBACKI
VCURVESINDIFFERENTNadIMPLANTDOSAGES(ASTHE
LNad=5UM)
FIG.19.SURFACEELECTRICFIELDDISTRIBUTIONWITHAN
NadSTRUCTURE(ASNad=5.51015ATOMS/CM2,LNad=5UM)
FIG.20.SURFACEELECTRICFIELDDISTRIBUTIONWITHAN
NadSTRUCTURE(ASNad=5.51015ATOMS/CM2,LNad=9.4UM)
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DOI:10.14355/ijes.2013.0305.06
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moreeffectivetoensurereliabilitycapabilityinmany
kinds of applications. Thus, it is very easy to fine
tuning the trigger voltageand the holding voltage by
usingtheseadaptivelayersvariations.
REFERENCES
SemiconductorDevices&ICs(1994):249252.
FIG.22.RIGHTSHIFTINGCHARACTERISTICSOFSNAPBACKI
VCURVESINDIFFERENTLNadWIDTHS(ASTHENad=5.51015
ATOMS/CM2)
E.Y.Hapsari,A.Kumar,V.N.VasanthaKumar,ShaoMing
Yang, Gene Sheu. Optimization of ESD protection
deviceusingSCRstructureofanovelSTIsidedLDMOS
TABLE2.THECOMPARISONOFSNAPBACKPARAMETERSDURING
DIFFERENTLNADWIDTHS
withPtoplayerfor5Voperatingvoltage.International
Conference on Optoelectronics and Microelectronics
Vt1(Volt)
Vh(Volt)
NoNad
131
73
Nad=5.5x1015atoms/cm2
LNad=5m
156
97
Nad=5.5x1015atoms/cm2
LNad=9.4m
124
93
(ICOM2012):524528.
Conclusion
JianHsing Lee, S.H. Chen, Y.T. Tsai, D.B. Lee, F.H. Chen,
W.C.Liu,C.M.Chung,S.L.Hsu,J.R.Shih,A.Y.Liang,K.
Wu.TheInfluenceofNBLLayoutandLOCOSSpaceon
Component ESD and System Level ESD for HV
LDMOS. 19th International Symposium on Power
SemiconductorDevicesandICs(2007):173176.
M.D.Ker,andK.H.Lin.DoubleSnapbackCharacteristics
in HighVoltage nMOSFETs and the Impact to OnChip
ESDProtectionDesign.IEEEElectronDeviceLetters25
(2004):640642.
P.Hower,J.Lin,S.Pendharkar,B.Hu,J.Arch,J.Smithand
T. Efland. A Rugged LDMOS for LBC5 Technology.
The
17th
International
Symposium
on
Power
SemiconductorDevicesandICs(2005):327330.
S. Dong, X. Du, Y. Han, M. Huo, Q. Cui, D. Huang.
Analysisof65nmtechnologygroundedgateNMOSfor
onchipESDprotectionapplications.ElectronicsLetters
44(2008):11291130.
ShenLi Chen, TzungShian Wu, HungWei Chen, Chun
Hsing Shih, and PoYing Chen. Optimized latchup
355
www.ijesci.orgInternationalJournalofEnergyScience(IJES)Volume3Issue5,October2013
DOI:10.14355/ijes.2013.0305.06
design of a high voltage nLDMOSFET. IEEE
LDMOSina0.5m16VBCDtechnologytoavoidlatch
CircuitTechnology,ShangHai(2010):16891691.
SiYangLiu,WeiFengSun,HongWeiPan,HaoWang,Qin
(IPFA2009):4144.
YoungChung,HongzhongXu,R.Ida,WonGiMin,B.Baird.
IntegratedCircuitTechnology(ICSICT2012):13.
PowerSemiconductorDevicesandICs(2005):351354.
In2003,hewasthechairmanofdept.electronicengineering
ofNationalUnitedUniversity,Taiwan.In2013,healsowas
an adjunct professor of Software and Microelectronics
School at Wuxi of Peking University, China. Recently, he
continues to pursue his research interests in the modeling
andcharacterizationofHVpowerdevices,andhighESD/LU
immunitydesignsinVLSIandpowerelectronics.
W.Y.Chen,M.D.Ker,Y.J.Huang,Y.N.JouandG.L.Lin.
Measurement on snapback holding voltage of high
voltage LDMOS for latchup consideration. IEEE
Proceedings of Asia Pacific Conference on Circuits and
Systems(2008):6164.
W.Y.Chen,M.D.Ker,Y.N.Jou,Y.J.HuangandG.L.Lin.
356