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ECET 1200 LABORATORY EXERCISE 8

BINARY TO HEX SEVEN SEGMENT DISPLAY USING AN ispM4A5 CPLD

http://facultyweb.kennesaw.edu/swils156/1200/labs/

Name: _____________________

Objective:
To entice the student to use CPLDs in future digital designs.
Introduction:
In this exercise, the student will individually design a CPLD circuit that will display the hexadecimal equivalent of
the binary number of activated switches onto a seven segment display using an ispM4A5 CPLD. The ispM4A5 is
embedded in a development board custom designed in a joint venture between SPSU and HS Harz University in
Wernigerode, Germany. The board is shown in Figure 1. The four switches shown at the bottom of the board will
be used as the inputs. The corresponding HEX number will be displayed on the right hand side, seven segment
display.

Figure 1. ispM4A5 lab board with Silkscreen

Once the student successfully compiles the VHDL program, the student will download the JEDEC file to the
development board prior to the scheduled lab meeting and demonstrate the functioning design to the instructor.
Procedure:
Binary to Hexadecimal Converter with Seven Segment Display Circuit
1.

VHDL Software
The VHDL software design package used in this lab will be the current version of ispLEVER obtained from the
Lattice Semiconductor website. A current link is provided on the same web page where this lab was found.
Follow the instructions provided by Lattice. If the software will not install correctly on your home computer,
ispLEVER 1.0 is installed on the computers in G215 and in the lab. There the student can compile and
download the code to the CPLD.

2.

VHDL Circuit Design


Use the provided VHDL template located at the end of this lab to write and compile a VHDL program to
implement the binary to hex circuit with seven segment display. All LEDs of the seven segment display are
active LOW which means that a logic 0 must be sent to the pin for the LED segment to turn on. Use all four
switches available on the development board as the inputs. Complete the truth table for the seven segment
display before writing any code.

DRW 10/20/10

ECET 1200 LABORATORY EXERCISE 8


BINARY TO HEX SEVEN SEGMENT DISPLAY USING AN ispM4A5 CPLD
Name: _____________________
SW1 SW2 SW3 SW4
B
C
D
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

segments
c d e

0
1
0
__
__
__
__
__
__
__
__
__
__
__
__
__

0
0
0
__
__
__
__
__
__
__
__
__
__
__
__
__

0
0
1
__
__
__
__
__
__
__
__
__
__
__
__
__

0
1
0
__
__
__
__
__
__
__
__
__
__
__
__
__

0
1
0
__
__
__
__
__
__
__
__
__
__
__
__
__

0
1
1
__
__
__
__
__
__
__
__
__
__
__
__
__

1
1
0
__
__
__
__
__
__
__
__
__
__
__
__
__

display
0
1
2
3
4
5
6
7
8
9
A
b
c
d
E
F

Figure 2. Seven Segment Truth Table (incomplete)


3.

VHDL RTL Synthesis


Use the available template to complete the truth table entry method for the binary to seven segment display.
(DO NOT CUT AND PASTE FROM ADOBE ACROBAT. Doing so will cause many problems.)
Steps to Start ispLEVER:
In the main Microsoft Windows panel, go to the Start ->All Programs -> Lattice Semiconductor -> ispLEVER
and launch the ispLEVER software. When the software starts, a project window will appear. If a project is
already active, close the project by File -> Close Project. After doing so, the window should be blank. Now go
File -> New Project to start a new project. In the Save In: pull down box, go to the local C: drive and create a
folder with a filename of your choice. DO NOT USE SPACES. For example, MyFilename should be one word
with out spaces. Give the project a name without blank spaces. Select the Schematic/VHLD file type. After
saving the project in the newly created file folder, the following IC part number shows up: ispLSI5256VE165LF256. This is the wrong part. To select the correct part, double click on the part number and select the
device Family: -> ispMACH 4A5 then Device: M4A5-64/32. The Package box should automatically show
44PLCC. Select OK then Yes then Yes then OK. Now the template VHDL file is ready to be imported into the
project.
If not already done, download the example VHDL code to the same file folder created above. The example
code will have an extension of *.VHD. To import the code into the project, place the mouse in the white space
below the M4A5-64/32 part number and left click the mouse. Of the two choices, New.. and Import.., select
Import. Then select the example file with the *.VHD extension. The next window asks for the Type of Source,
select the VHDL Module. Now the code is ready to be altered. Double click the mouse on the *.VHD in the
project window. The ispLEVER text editor window launches. Make your alterations to this code and save it.
To compile the code using the RTL synthesis engine, click the mouse on the part number M4A5-64/32. In the
subwindow on the right, the JEDEC File selection appears. Double click the mouse on the JEDEC File. Doing
so will cause the ispLEVER to start compiling the code. As each step is automatically completed, a green
check mark will appear. Once the JEDEC File has a green check mark, a file with the extension *.JED will
resided in the same folder as the project with the same name as the project. If a window appears that asks to
override the pin assignment, answer yes. Use the new *.JED file to download in the next step.

DRW 10/20/10

ECET 1200 LABORATORY EXERCISE 8


BINARY TO HEX SEVEN SEGMENT DISPLAY USING AN ispM4A5 CPLD
Name: _____________________
4.

VHDL Download
Non-Lattice Download Cable:
The development board is powered through the USB port of the local computer. If the boards USB cable is not
connected, please do so. The JEDEC file is downloaded to the development board via the JTAG programming
cable. The JTAG programming cable is connected to a parallel port adapter which should be connected to the
parallel port of the computer. If it is not, please do so. As stated in the previous instructions, launch the
ispLEVER software and load your project into the ispLEVER Project Navigator window. Compile the VHDL
program by doubling clicking on the JEDEC label. If a window appears that asks to override the pin
assignment, answer yes. Outside of the ispLEVER software in the Windows environment, select Start -> All
Programs -> Lattice Semiconductor -> Accessories -> ispVM System. Doing so will launch the ispVM System
window. When the ispVM System is launched for the first time, it will be necessary to install the parallel port
driver software. To do this, select ispTools ->Install..XP Parallel Port Drive as shown in Figure 3. Now that
the driver is installed, select Edit -> Add Device. In the Device: Select .. box, click on the pulldown tab of the
Device Family and select MACH4A, iM4A5-64/32 in the 44-pin PLCC package configuration. Select OK
which will take you back to the Device Information window. There, select Browse *.JED to point to your
compiled JEDEC file (filename.jed) then click on Open. On the main window task bar, select Project -> Project
Settings. Check the box Continue Download Even on Error. Make sure the security option does not appear
on in the ispVM System window. Finally, select the green GO button. An error message ! Download cable
not connected .. will pop up, select OK. A Processing Please wait message will appear and in about 7
seconds or so, the ispM4A5 will be programmed.

Figure 3. Screen Shot of Parallel Port Driver Installation

5.

Board Testing
As soon as the code meets specifications, request the instructor to sign the attached grading sheet. Attach a
copy of the VHDL code to the end of this lab when submitting the report to the instructor.

DRW 10/20/10

ECET 1200 LABORATORY EXERCISE 8


BINARY TO HEX SEVEN SEGMENT DISPLAY USING AN ispM4A5 CPLD
Name: _____________________
VHDL Programming Example Using the Data Flow Approach Method
library ieee;
use ieee.std_logic_1164.all;
entity Binary2Hex is
port(SWES:in bit_vector (3 downto 0);
SevenSeg:out bit_vector
attribute LOC: string;
attribute LOC of SWES: signal is P09 P21
attribute LOC of SevenSeg: signal is P36
P40
end entity Binary2Hex;
-- where
-------

-- a -|
|
f
b
|--g--|
e
c
|
|
-- d --

SevenSeg(0),
SevenSeg(1),
SevenSeg(2),
SevenSeg(3),
SevenSeg(4),
SevenSeg(5),
SevenSeg(6),

segment
segment
segment
segment
segment
segment
segment

a,
b,
c,
d,
e,
f,
g,

(0 to 6));
P31 P43;
P37 P38 P39
P41 P42;

maps
maps
maps
maps
maps
maps
maps

to
to
to
to
to
to
to

Pin
Pin
Pin
Pin
Pin
Pin
Pin

36
37
38
39
40
41
42

-- attribute LOC is a method of setting the Pins on the chip


-- remember active low outputs will turn on the LED segments
-- remember active low push buttons are low only when pushed
architecture DisplayBehavior of Binary2Hex is
begin
process (SWES)
begin
if
(SWES="0000") then SevenSeg<="0000001";
elsif (SWES="0001") then SevenSeg<="1001111";
.
.
else SevenSeg<=_ _ _ _ _ _ _;
end if;
end process;

-- continue code completing remaining values


end architecture DisplayBehavior;
The above VHDL code may have syntax errors. It is also incomplete.

Verification ____________________

Date:______________

DRW 10/20/10