8/12/2015
Review: Design Abstraction Levels
SYSTEM
EE370 Digital Electronics
The Inverter!
MODULE
+
GATE
Yogesh S. Chauhan
Department of Electrical Engineering
IIT Kanpur
Email: chauhan@iitk.ac.in
Office: WL125, Phone: 7244
CIRCUIT
Vin
Vout
G
S
n+
DEVICE
D
n+
Y. S. Chauhan, IITK
Review: The MOS Transistor
Switch
vi
Normal switch
Gate oxide
W
ON (Signal applied) = Low resistance (Ideal 0)
OFF = High resistance (Ideal )
Polysilicon
Gate
Source
n+
Drain
n+
L
FieldOxide
(SiO2)
Inverted switch
ON (Signal applied) = High resistance
OFF = Low resistance
p substrate
p+ stopper
Bulk (Body)
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Y. S. Chauhan, IITK
8/12/2015
Inverter using switch
Voltage Swing
Inverters are implemented using switches.
Vswing= VOHVOL
1
RL
RL
Swing should be maximized.
RL
RSL
RSH
Ideally VOH = VDD and VOL=0
Thus RSH as high as possible and RSL as low as
possible.
SimplestInverter
Y. S. Chauhan, IITK
Y. S. Chauhan, IITK
Performance Delay
/
V DD
V DD
RL
CL discharging to VOL.
RL
V out
Req
R SH
Propagation Delay
0.69
CL charging to VOH.
(a) Lowtohigh
Vin goes from VDD to ground.
2
Asymmetric delays are undesirable.
To solve this (asymmetric delays),
CL
0.69
1
1
(b) Hightolow
Vin goes
Y. S. Chauhan, IITK
V out
R SL
0.69
0.69
As RSH>> RSL, tpLH>>tpHL
Req
CL
Decrease RSH and Increase RSL
But there is a tradeoff
RSH VOH and RSL VOL
Noise margin and swing suffer.
from ground to VDD.
7
Y. S. Chauhan, IITK
8/12/2015
Power
NMOS Inverter
MOSFET can be operated as a switch.
Ptotal = Pdyn + Pstat
Low to high transition (
and
Capacitor is charging from supply
Energy transferred by source
High to Low transition (
Capacitor is discharging
Energy transferred by source
and
VOH=VDD
To reduce power, reduce swing!
Y. S. Chauhan, IITK
NMOS Inverter
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10
NMOS Inverter
Visually, we can plot VTC of this inverter.
Lets find VIL,
For VIL, NMOS is in saturation.
1,
Differentiating and using
1
Where
Lets find VM, vO=vin=VM
Its not sufficient, Lets do calculation of VTC
critical points (VOH, VOL, VIH, VIL and VM).
Y. S. Chauhan, IITK
2
11
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8/12/2015
NMOS Inverter
NMOS Inverter
Boundary of saturation (C)
Using
,
Lets find VOL.
2
Assuming v0 is small, ignore v02
Beyond C, NMOS is in linear region.
To find VIH, use
1 and linear current equation.
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NMOS Inverter
NMOS Inverter Power dissipation
Power dissipation
Dynamic power in one complete cycle (T)
All NMOS inverter parameters are functions of
VDD, VT and VX only.
VDD and VT are determined by the process technology
Only design parameter available is
Static power dissipation (only when vI is low)
To place VM at VDD/2,
14
Total Power dissipation

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8/12/2015
NMOS Inverter Delay
NMOS Inverter
Output going low to high
MOSFET is in cutoff
tpLH=0.69RLCL
Using VDD=1.8V and VT=0.5V,
Output going high to low
Capacitor discharges through MOSFET
Req=(Rdis(0%) + Rdis(50%))/2
and
To determine RL, use
kn = 300 A V2 and W/L = 1.5
Average v0,
RL=25k
Inverter dissipates static power only when output is low.
=121W
Average power = PD/2=60.5W
tpHL=0.69ReqCL
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Key observations
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Saturated NMOSLoad Inverter
Lets replace passive resistance with an NMOS transistor.
Output signal swing, though not equal to the VDD, is reasonably
good:
VOH = 1.8 V, VOL = 0.12 V
Noise margins are far from the optimum value of
NML = VIL VOL = 0.47 V
NMH = VOH VIH = 0.74 V
Most seriously, the gate dissipates a relatively large amount of
power.
Million inverters in an IC (a very small number) will dissipate 61 W!
This is too large, especially given that this is static power, unrelated
to the switching activity of the gates.
Each inverter requires a load resistance of 25 k
This kind of value needs large chip area
Unsuitable for IC fabrication
tpLH>> tpHL
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8/12/2015
Saturated NMOSLoad Inverter
Saturated NMOSLoad Inverter
VOH = VDD VT
Q2 is always in saturation
1
2
As vI exceeds VT1, Q1 operates in saturation,
1
2
Using VT1=VT2=VT and equating,
1
All inverter parameters are function of VDD,
VT and kr.
Only design parameters is kr.
Output is linear function of input with slope =  kr
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Saturated NMOSLoad Inverter
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Key observations
Using VDD=1.8V and VT=0.5V
(W L)1 = 5, (W L)2 = 1/5
Body of Q2 is connected to ground, thus
,
2
2
VT2 will increase with increase in vo (i.e. during charging CL)
VOH is lower than VDD by VT2 and VT2 increases with vo.
Swing & NM decrease.
Body effect imposes a major disadvantage on this NMOSload
inverter.
Noise margins are much lower than the ideal values of VDD/2.
Inverter dissipates static power only when output is low.
Average power = PD/2=42.9W
Y. S. Chauhan, IITK
=85.7W
VM is far from VDD/2.
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8/12/2015
Improvements1
Depletion load NMOS Inverter
Key observations
Like the resistivelyloaded MOS inverter, the NMOSloaded inverter dissipates a large amount of static power.
Advantages
VOH=VDD
The sharpness of the transition of the VTC increases with
the value of Increasing kr.
VT2=0V
However, kr has the effect of increasing the silicon area.
Disadvantages
Since the circuit utilizes NMOS transistors exclusively, it is
certainly suitable for implementation in IC form.
AllNMOS technology was at one time (1970s) the
technology of choice for the implementation of
microprocessor chips (e.g. Intel 4004).
Y. S. Chauhan, IITK
Body effect
Others similar to NMOS
load
DepletionloadNMOSInverter
25
Improvements2
PseudoNMOS Inverter
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PseudoNMOS Inverter
Ratio r
1
1
2
3
1
1
1
Avoids body effect problem seen in NMOS
loaded inverter
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1
1
>0
1
1
2
3
Designparameter=r
Ratioed Logic
tpLH isr timeslargerthantpHL
VOL0
Standbypower
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The CMOS Inverter: A First Glance
CMOS Inverter
N Well
Design Metrics:
V DD
V in
VDD
Cost=Complexity and
area
Integrity and
robustness Static (or
steadystate) behavior
Performance
Dynamic (or transient)
response
Energy efficiency
Energy and power
consumption
V out
CL
Y. S. Chauhan, IITK
Reference:Rabaey book
In
Vin = 0
Out
Metal 1
Polysilicon
NMOS
GND
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30
Full railtorail swing high noise margins
VOL = 0
VOH = VDD
VM = f(Rn, Rp)
Vin = V DD
Y. S. Chauhan, IITK
Out
CMOS Properties
Rp
Rn
Contacts
NMOS
Vout = 0
In
29
VDD
Vout = 1
PMOS
PMOS
CMOS Inverter:
Steady State Response
VDD
VDD
31
Logic levels not dependent upon the relative device sizes transistors
can be minimum size ratioless
Always a path to Vdd or GND in steady state low output
impedance (output resistance in k range) large fanout
(albeit with degraded performance)
Extremely high input resistance (gate of MOS transistor is
near perfect insulator) nearly zero steadystate input current
No direct path steadystate between power and ground no
static power dissipation
Propagation delay function of load capacitance and resistance
of transistors
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8/12/2015
Review: Short Channel IV Plot (NMOS)
Review: Short Channel IV Plot (PMOS)
X 104
2.5
All polarities of all voltages and currents are reversed
VGS = 2.5V
VDS (V)
2
1
0
0
VGS = 2.0V
1.5
1
VGS = 1.5V
0.5
VGS = 1.0V
VGS = 1.0V
0.2
VGS = 1.5V
0.4
0.6
VGS = 2.0V
0.8
0
0.5
1.5
VDS (V)
2.5
VGS = 2.5V
NMOS transistor, 0.25um, Ld = 0.25um, W/L = 1.5, VDD = 2.5V, VT = 0.4V
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1 X 104
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34
PMOS transistor, 0.25um, Ld = 0.25um, W/L = 1.5, VDD = 2.5V, VT = 0.4V
CMOS
Inverter Load Lines
CurrentthroughNMOSandPMOSaresame.
Want common coordinate set Vin, Vout, and IDn
IDSp = IDSn
VGSn = Vin ; VGSp = Vin  VDD
VDSn = Vout ; VDSp = Vout  VDD
PMOS
IDn
2.5
NMOS
X 104
Vin = 2.5V
Vin = 0V
2
Vin = 0.5V1.5
Vin = 2.0V
Vout
Vin = 0
Vin = 0
Vin = 1.5
Vin = 1.5
Vin = 1.0V 1
Vin = 2V
0.5
Vin = 1V
Vin = 1.5V
Vin = 0.5V
Vin = 1.0V
Vin = 1.5V
Vin = 2.0V
VGSp = 1
VGSp = 2.5
Mirror around xaxis
Horiz. shift over VDD
Vout = VDD + VDSp
Vin = VDD + VGSp
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IDn = IDp
35
Vin = 0.5V
Vin = 2.5V 0
Vin = 1.5V
0.5
1.5
Vout (V)
Y. S. Chauhan, IITK
2.5 Vin = 0V
0.25um, W/Ln = 1.5, W/Lp = 4.5, VDD = 2.5V, VTn = 0.4V, VTp = 0.4V
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CMOS Inverter Load Lines
CMOS Inverter VTC
All operating points are located
either at the high or low output
levels.
The VTC of the inverter hence
exhibits a very narrow transition
zone.
NMOS sat
PMOS res
Vout (V)
This results from the high gain
during the switching transient,
when both NMOS and PMOS are
simultaneously on, and in
saturation.
In that operation region, a small
change in the input voltage results
in a large output variation.
PMOS
1.5
In
NMOS sat
PMOS sat
NMOS
NMOS res
PMOS sat
NMOS res
PMOS off
0
0
37
CMOS Inverter:
Switch Model of Dynamic Behavior
VDD
Vout
CL
Rn
1.5
Vin (V)
2.5
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38
When designing static CMOS circuits, balance
the driving strengths of the transistors by
making the PMOS section wider than the
VDD
NMOS section to
Rp
Vout
0.5
Relative Transistor Sizing
VDD
Maximize the noise margins and
Obtain symmetrical characteristics
In
Vin = 0
Out
1
0.5
Y. S. Chauhan, IITK
CL
VDD
NMOS off
PMOS res
2.5
PMOS
Out
Vin = V DD
Gate response time is determined by the time to
Charge CL through Rp
DecreaseCL
Discharge CL through Rn
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NMOS
and/orR
39
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8/12/2015
Static behavior Switching Threshold
VM where Vin = Vout (both PMOS and NMOS in saturation
since VDS = VGS)
2
VM where Vin = Vout (both PMOS and NMOS are velocity
saturated since VDS = VGS)
VM rVDD/(1 + r) where r = kpVDSATp/knVDSATn
Using VTn=VTp=VT, and
1
Switching threshold set by the ratio r, which compares the
relative driving strengths of the PMOS and NMOS transistors
Switching Threshold
(short channel)
Want VM = VDD/2 (to have comparable high and low noise
margins) So r = 1 for long channel.
Switching threshold set by the ratio r, which compares the
relative driving strengths of the PMOS and NMOS transistors
Want VM = VDD/2 (to have comparable high and low noise
margins), so want r 1
(W/L)p
knVDSATn(VMVTnVDSATn/2)
(W/L)n kpVDSATp(VDDVM+VTp+VDSATp/2)
Thus
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0.25mCMOS,VDD=2.5V
VM is relatively insensitive to
variations in device ratio
1.4
Vmb
Vma
ChangingWp/Wn ratio
shiftsthetransientregion
oftheVTC.
Thiscanbeveryuseful, as
asymmetricaltransfer
characteristicsareactually
desirableinsomedesigns.
setting the ratio to 3, 2.5 and 2
gives VMs of 1.22V, 1.18V, and
1.13V
1.3
1.2
1.1
42
Making VM asymmetric
Simulated Inverter VM
1.5
Y. S. Chauhan, IITK
Increasing the width of the
PMOS moves VM towards VDD
1
0.9
Increasing the width of the
NMOS moves VM toward GND
0.8
0.1
(W/L)p/(W/L)n
Note: xaxis is semilog
~3.4
10
TomovetheVM to1.5Vrequiresatransistorratioof
11,andfurtherincreasesareprohibitivelyexpensive.
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The incoming signal Vin has a very noisy zero value.
Passing this signal through a symmetrical inverter would lead to erroneous
values.
This can be addressed by raising the threshold of the inverter, which results in a
correct response.
Changing the switching threshold by a considerable amount is however not
easy, especially when the ratio of VDD/VM is relatively small.
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Determining VIH and VIL
Noise Margins Determining VIH and VIL
By definition, VIH and VIL are
where dVout/dVin = 1 (= gain)
Vout
V OH
VOH = VDD
NMH = VDD  VIH
NML = VIL  GND
VM
VM
V in
VOL = GND0
V OL
Vin VIH
A piecewise linear
approximation of VTC
V IL
VIL
A simplified approach
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45
Y. S. Chauhan, IITK
2.5
Vout (V)
2
1.5
0.25um, (W/L)p/(W/L)n = 3.4
(W/L)n = 1.5 (min size)
VDD = 2.5V
VM 1.25V, g = 27.5
VIL = 1.2V, VIH = 1.3V
NML = NMH = 1.2
(actual values are
VIL = 1.03V, VIH = 1.45V
NML = 1.03V & NMH = 1.05V)
0.5
0
0.5
Vin (V)
1.5
2.5
Output resistance
lowoutput = 2.4k
Y. S. Chauhan, IITK
highoutput = 3.3k
46
Gain calculation in Long channel
CMOS Inverter VTC from Simulation
So high gain in the transition
region is very desirable
V IH
For NML and NMH, we need to find gain.
Gain is a strong function of the slopes of the currents in the saturation region. The
CLM factor hence cannot be ignored in this analysis doing so would lead to an
infinite gain.
1
2
2
Gain is dVout/dVin, Using VTn=VTp=VT,
2
Ignoring CLM and for Vin=VM,
This gives,
and using it in above equation
1
47
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Gain Determinates
Vin
0.5
1.5
2.5
Gain is a strong function of the
slopes of the currents in the
saturation region, for Vin = VM
0
2
4
(1+r)
g (VMVTnVDSATn/2)(n  p )
6
8
10
Determined by technology
parameters, especially channel
length modulation (). Only
designer influence through supply
voltage and VM (transistor sizing).
14
16
18
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49
PVT
Nominal
Bad PMOS
Good NMOS
0
0
0.5
1.5
2.5
Vin (V)
CMOS Inverter Propagation Delay
0.2
VDD
tpHL = f(Ron.CL)
Vout (V)
0.15
Vout (V)
2.5
Process variations (mostly) cause a shift in the switching threshold.
Operation of the gate is notY.affected.
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50
Forfixedr,VM isproportionaltoVDD.
GainincreaseswithdecreaseinVDD ( areconstant)!
1.5
1
= 0.69 RonCL
0.1
Vout
0.05
0.5
CL
Ron
Gain=1
0
0
0.5
Scaling the Supply Voltage
Corners:
SlowFast
FastFast
FastSlow
SlowSlow
1.5
0.5
12
PVT
Good PMOS
Bad NMOS
Vout (V)
Impact of Process Variation on VTC Curve
1.5
2.5
ln(0.5)
Vout
1
VDD
0.5
Vin (V)
Device threshold voltages are
kept (virtually) constant Y. S. Chauhan, IITK
0.05
0.1
0.15
Vin (V)
Device threshold voltages are
kept (virtually) constant 51
0.2
0.36
Vin = V DD
RonCL
Y. S. Chauhan, IITK
t
52
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Computing the Capacitances
GateDrain Capacitance
Gatedrain
capacitances
Diffusion
capacitances
Wire
capacitances
Y. S. Chauhan, IITK
The gatedrain overlap capacitance of M1, Cgd1, can be replaced by
an equivalent capacitance between the output node and ground of
2Cgd1.
The factor 2 arises because of the Miller effect. As vI goes high and
vO goes low by the same amount, the change in voltage across Cgd1
is twice that amount.
Total Capacitance
53
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54
Inadigitalinverter,thelargescalegainbetweeninputandoutputalwaysequals1.
CMOS Inverter Layout
Out
CMOS Inverters
In
VDD
metal1poly via
metal1
PMOS
polysilicon
metal2
VDD
pdiff
1.2m
=2
Out
In
PMOS (4/.24 = 16/1)
NMOS (2/.24 = 8/1)
Metal1
Polysilicon
metal1diff via
ndiff
NMOS
GND
GND
metal2metal1 via
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Transient Response
3
2.5
Propagation delay
tp = 0.69 CL (Reqn+Reqp)/2
ln 2
2
Very often, it is desirable for a gate to have identical
propagation delays for both rising and falling inputs.
Use
out
(V)
1.5
tpHL
tpLH
ln 2
and
0.5
0
0.5
0.5
1.5
t (sec)
This condition is identical to the requirement for a
symmetrical VTC.
2.5
x 10
10
OvershootscausedbytheCgd oftheinvertertransistors,whichcouplethesteepvoltagestepat
theinputnodedirectlytotheoutputbeforethetransistorscanevenstarttoreacttothe
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57
changesattheinput.
Design for Performance
Minimizing propagation delay
Y. S. Chauhan, IITK
Delay as a function of VDD
DelayofagatecanbemodulatedbymodifyingVDD.Thisflexibilityallowsthedesignerto
tradeoffenergydissipationforperformance.
Keep capacitances small
5.5
Internal diffusion capacitance, Interconnect
capacitance, and the fanout.
Careful layout helps to reduce the diffusion and
interconnect capacitances. Good design practice
requires keeping the drain diffusion areas as small as
possible.
5
4.5
t (normalized)
Increase VDD Next slides
Increase transistor sizes
3.5
3
ForVDD>>VTn +VDSATn/2,delayisindependentofVDD.
2.5
2
1.5
Watch out for selfloading!
1
0.8
1.2
1.4
1.6
V
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59
DD
1.8
2.2
(V)
SharpincreasearoundVDD2VTn.
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2.4
LargeVDD
reliabilityconcerns(oxide
breakdown,hotelectroneffects)
60
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Minimizing propagation delay
Device Sizing
Increase the W/L ratio of the transistors.
3.8
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61
Revisiting Propagation Delay
Design tradeoffs
(for fixed load)
3.4
3.2
0.69
2.8
tp0 Intrinsic delay
of the gate (no
extrinsic load = 0).
S>> is not useful.
2.6
2.4
2.2
2
8
S
10
12
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1
Widening both
NMOS and PMOS of
the driving inverter
with a factor S,
14
Selfloading effect:
Intrinsic capacitances
dominate
62
NMOS/PMOS ratio
Impact of Fanout:
Reqp=Reqn Symmetrical VTC and tpHL=tpLH
1
Extrinsic capacitance is a function of the fanout of the gate: the
larger the fanout, the larger the external load.
Assuming that each fanout gate presents an identical load, and that
the wiring capacitance is proportional to the fanout, we can rewrite
the delay equation as a function of the fanout N.
1
This gives Wp=3*Wn
This does not imply that this ratio also yields
the minimum overall propagation delay!
If symmetry and reduced noise margins are not
of prime concern, we speed up the inverter by
reducing the width of the PMOS device!
Large fanout factors should hence be avoided if performance is an
issue.
Increasing the sizing factor S of the driving inverter is appropriate
and recommendable in the presence of fanout.
Y. S. Chauhan, IITK
Total Capacitance
11
3.6
t (sec)
This is the most powerful and effective performance
optimization tool in the hands of the designer.
Increasing the transistor size also raises the diffusion
capacitance and hence CL.
Once the intrinsic capacitance (i.e. the diffusion
capacitance) starts to dominate the extrinsic load formed by
wiring and fanout, increasing the gate size does not longer
help in reducing the delay, and only makes the gate larger
in area. This effect is called selfloading.
In addition, wide transistors have a larger gate capacitance,
which increases the fanout factor of the driving gate and
adversely affects its speed.
x 10
63
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NMOS/PMOS ratio
x 10
11
0.35
tpHL
0.3
= Wp/Wn
tp
t (sec)
tpLH
4.5
tpH L(nsec)
Impact of Rise Time on Delay
0.25
0.2
3.5
0.15
3
1.5
2.5
3.5
4.5
0.2
0.4
0.6
trise (nsec)
0.8
Homework Determineoptimalvalueof tominimizetp.
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Inverter Sizing
Sizing up an inverter reduces its delay it also increases
its input capacitance.
Inverter Sizing
Gate sizing in an isolated fashion without taking into account its
impact on the delay of the preceding gates is a purely academic
exercise.
Lets determine the optimum sizing of a gate when
embedded in a real environment.
A simple chain of inverters is a good first case to study.
Relation between input gate capacitance Cg and the intrinsic
output capacitance both are proportional to the gate sizing.
Cint=Cg
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67
is technology dependent and close to 1.
Y. S. Chauhan, IITK
Cint=Cgd1+Cgd2+Cdb1+Cdb2=3fF
Cg=Cg3+Cg4=3.04fF
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Inverter Chain
In
Inverter Delay
Minimum length devices, L=0.25m
Assume that for WP = 2WN =2W
same pullup and pulldown currents
approx. equal resistances RN = RP
approx. equal rise tpLH and fall tpHL delays
Analyze as an RC network
Out
CL
If CL is given:
 How many stages are needed to minimize the delay?
 How to size the inverters?
W
RP Runit P
Wunit
W
Runit N
Wunit
Delay (D): tpHL = (ln 2) RNCL
May need some additional constraints.
Load for the next stage:
Y. S. Chauhan, IITK
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RN RW
tpLH = (ln 2) RPCL
C gin 3
Y. S. Chauhan, IITK
Inverter with Load
2W
W
Cunit
Wunit
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Inverter with Load
CP = 2Cunit
Delay
Delay
2W
RW
W
Cext
RW
Load (CL)
tp = k RWCext
Y. S. Chauhan, IITK
Cext
Load
CN = Cunit
Delay = kRW(Cint + Cext) = kRW Cint(1+ Cext /Cint)
= Delay (Internal) + Delay (Load)
k is a constant, equal to 0.69
Assumptions: no load > zero delay
Wunit = 1
Cint
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Delay Formula
Apply to Inverter Chain
Delay ~
In
Out
1
CL
Cint = Cgin with 1
f = CL/Cgin  effective fanout
R = Runit/W ; Cint =WCunit
tp0 = 0.69RunitCunit
Y. S. Chauhan, IITK
Note that Cg,N+1=CL
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Y. S. Chauhan, IITK
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Optimal Tapering for Given N
Optimum Delay and Number of Stages
Delay equation has N  1 unknowns, Cg,2 Cg,N
To minimize the delay, find N  1 partial derivatives and
equate them to zero.
When each stage is sized by f and has same effective fanout
f:
f N F C /C
Effective fanout of each stage:
Result: Cg,j+1/Cg,j = Cg,j/Cg,j1
Size of each stage is the geometric mean of two neighbors
,
gin ,1
F represents overall effective fanout = CL/Cg,1.
Minimum path delay:
Each stage has the same effective fanout (Cout/Cin)
Each stage has the same delay
Relation between tp and F is strongly nonlinear.
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It is linear only when N=1.
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Example
Optimum Number of Stages
For a given load, CL and given input capacitance Cin
In
C1
Find optimal sizing f (
Out
1
f2
C L F Cin f N Cin with N
C L= 8 C 1
ln F
ln f
t p 0 ln F f
ln f ln f
t p t p 0 ln F ln f 1 f
0
f exp1 f
f
ln 2 f
t p Nt p 0 F 1/ N / 1
CL/C1 has to be evenly distributed across N = 3 stages:
f 38 2
For = 0, f = e, N = lnF
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Optimum Effective Fanout f
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Impact of SelfLoading on tp
Optimum f for given process defined by
WithSelfLoading=1
f exp1 f
fopt = 3.6
for =1
Y. S. Chauhan, IITK
=0 means no self loading. This design scales consecutive
Y. S. Chauhan, IITK
stages in an exponential fashion.
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For the typical case of 1, the
optimum scaler factor turns out to be
close to 3.6.
Choosing values of the fanout that are
higher than the optimum does not
impact the delay that much, and
reduces the required number of buffer
stages and the implementation area.
A common practice is to select an
optimum fanout of 4.
The use of too many stages (f < fopt),
on the other hand, has a substantial
negative impact on the delay, and
should be avoided.
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