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ABSTRACT

With microprocessors getting faster every year, memory architectures also must be
improved to enhance the overall system performance. As rapid development in
technology, speed and store capacity are the major concern of the processors. For fast
memory access architectures data has to be transferred faster than processor speed and
transferring should be synchronized with the processor. Modern real-time embedded
system must support multiple concurrently running applications. Double Data Rate
Synchronous DRAM (DDR SDRAM) became mainstream choice in designing memories
due to its burst access, speed and pipeline features. Synchronous dynamic access memory
is designed to support DDR transferring. To achieve the correctness of different
applications and system work as to be intended, the memory controller must be configured
with pipelined design for multiple operations without delay. The main function of DDR
SDRAM is to double the bandwidth of the memory by transferring data (either read
operation or write operation) twice per cycle on both the falling and raising edges of the
clock signal. The designed DDR Controller generates the control signals as synchronous
command interface between the DRAM Memory and other modules. The DDR SDRAM
controller supports data width of 64 bits and Burst Length of 4 and CAS (Column Address
Strobe) latency of 2 and in this pipelined SRAM controller design,
In the present work, Double data rate synchronous dynamic (DDR SDRAM)
accessing of memory and controller are designed in such a way that it supports double
data transfer rate. A fully functional controller is designed to perform Read and Write
operations on both rising and falling edge of clock from the memory by using data path
module with double data transfer throughput and bandwidth of the memory. The memory
has been designed to access the data by using the CAS and RAS signals in an easy way
and controller also has been implemented with double data rate. For a single row different
column data can be read so that the improvement of 28.57% is achieved in the
performance of memory accessing. The architecture is designed in Modelsim ALTERA
STARTER EDITION 6.5b and Cadence (RTL complier and encounter).
Keywords double data rate, column address strobe, data path and address latch.