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FAULT MODELS

Samiha Mourad and Edward J. McCluskey
CENTER FOR RELIABLE COMPUTING
Computer Systems Laboratory
Departments of Electrical Engineering and Computer Science
Stanford University, Stanford, CA 94305-4055, USA
1. INTRODUCI10N

A key requirement for obtaining reliable electronic systems is the ability to control the
effects of failures in such systems. Failures in integrated circuits can be characterized
according to their duration: temporary or permanent. Techniques for handling failures in digital
systems use fault models to represent the logical effects of the failures. Fault models have the
advantage of being a more tractable representation than physical failure modes, but risk the
omission of vital effects on system operations. For example, the most common fault model
assumes single-stuck faults even though it is clear that this model does not accurately represent
all actual physical failures. The rationale for continuing to use the single-stuck fault model is
that it has been satisfactory in the past. The argu~nts against the single stuck model are that it
is not adequate for present VLSI or ULSI technologies.
Fault control involves frrst detecting the presence of a fault and then acting to eliminate its
effects. There are two distinct environments in which fault detection is important: production
testing and concurrent error checking. The critical issues for production testing are the cost of
the test, the number and types of undetected failures, and whether faulty parts are repaired or
discarded. Concurrent checking schemes differ in their cost, effect on system reliability, class
of failures detected, and repair strategy. Fault models are used in developing methods for
concurrent checking as well as for production test. The choice of a fault model has a dominant
effect on the characteristics of the resulting technique.
This paper presents various fault models (for temporary as well as permanent failures) for
VLSI and ULSI parts. It also evaluates the effectiveness of various testing and checking
schemes for systems constructed of such parts. In Section 2, the relationship between faults,
failure modes and failure mechanisms is established. In Section 3, processes for screening
failures are described. Sections 4 through 6 examine different fault models used to represent
permanent failures, the stuck-at model, MOS faults and bridging faults. In Section 7 the
effectiveness of test sets generated for the single stuck-at fault model to detect multiple and
bridging faults are evaluated. Delay faults are the topic of Section 8. Topics related to
temporary faults will be covered in Sections 9 to 11.
2. FAULTS, FAILURE MODES, AND MECHANISMS
The underlying cause of digital system malfunctions is always some type of failure. These
failures can be due to incorrect design, defects in the material or in the production, physical
interference from the environment, or human error. The following classifications of failures
are generally accepted in the testing community [78]:
Permanent Failures are usually caused by breaks due to mechanical rupture or some wearout
phenomenon. They do not occur as frequently as temporary failures which are either transient
or intermittent. Transient failures are induced by some external perturbation such as power
supply fluctuations or radiation. Intermittent failures are usually due to some degradation of
the component parameters. Permanent failures are sometimes referred to as hardfailures and
temporary failures as soft failures.
49

F. Lombardi and M. Sami (eds.), Testing and Diagnosis ofVLSI and ULSI,49-68.
© 1988 by Kluwer Academic Publishers.

50

The most common failure mechanisms are listed in Table 1. These mechanisms
manifest themselves on the circuit level as failure modes. The most common failure modes are
open or short interconnections, or parameter degradation. Failure mechanisms are largely
dependent on the technology and even the layout of the circuit
Table 1. Failure Mechanisms.
Basic chemical or physical failure causes
Surface and bulk: effect
Passivation pits or cracks
Gate oxide breakdown
Pinholes or thin spots in oxide
Electrical overstress
Surface Potential instability
Metalization and metal semiconductor
Open metal at oxide steps
Wire bonding failure
Intermetalic compound formation
Electromigration
Package related
Mass transport of metal atoms
Momentum exchange with electrons
Passivation pits and cracks are usually spotted during visual inspection They affect the yield
rather the reliability of the product. Localized effects such as pinholes and thin spots in oxide
may be partly eliminated by electrical screening.
These different modes cause the component to fail at different stages of its lifetime. The
failure rate over the lifetime is given by the well known bathtub curve shown in Fig. 1.

INFANT
MORTALITY
PERIOD

WEAROUT
PERIOD

NORMAL
LIFETIME

....LIJ
<C

a::

SLIGHTLY DECREASING
FAILURE RATE

LIJ

a::

:;)

...J

<C

LL

1 - 20 WEEKS

.1.

10 - 20 YEARS

Figure 1. Failure Rate versus Lifetime.

~I

TIME

An attempt to map physical defects to the circuit and logical level is reported in [72]. Th~ usefulness of a fault model is determined by its accuracy in representing the effect of the failure as well as its tractability as a design tool. An example is given in Fig. show that of a total of 743 simulated physical defects. Afault model is the representation of the effect of a failure by means of the change that is produced in the system signal [78]. Stuck-Open (SOP) Faults A failure in a pull-up or pull-down transistor in a CMOS logic device causes it to behave like a memory element under certain input conditions. to illustrate the interpretation of physical defects as failure modes and their manifestation on the circuit and gate level. due to excessive use of the components. The different failure modes are manifested on the logical level as incorrect signal values. a fulladder. Includes both internal and external sources as well as particle impact. . Transient Faults Incorrect signal values caused by coupled disturbance.51 Failures that escape visual and optical scanning cause many chips to fail within one to twenty weeks of their operation (infant mortality). taken from [4]. Table 2. At the end of this period. Fault Model Description Single Stuck-at (SSA) Faults One line has a fixed value 0 or 1 Multiple Stuck-at Faults Two or more lines have fixed values. but the circuit remains combinational. not necessarily the same value. Eventually. the failure rate tends to stabilize for 10 to 20 years (normal lifetime period). Degradation is progressive until permanent failure occurs. 2. Results of applying of this method to one circuit. become connected when faulty. Intermittent Faults Caused by internal parameter degradation. Bridging Faults Two or more lines that are normally independent. Delay faults A fault caused by incorrect delays in one or more paths in the circuit. there is an exponential increase in failure rate (wearout period). Coupling can be via power bus capacitive or inductive coupling. Incorrect signal values occur for some but not all states of the circuit. Most Commonly Used Fault Models. 93 resulted in circuit level faults. Stuck-on (SON) Faults A transistor is always conducting. Table 2 lists the most common fault categories. The severity of the different physical defects is measured by their manifestation on the logical level. Combinational Faults Any change in the function realized by a combinational circuit can be caused by the fault.

temperature and humidity. The fIrst stage consists of an internal visual (optical) test. DC parametric testing insures that the device will operate within the specifIed voltage and current levels. 3. they have not been given as much attention. Here we will group them in four major stages. the defect level DL of the components is determined as function of the yield and the test fault coverage. FAILURE SCREENING The first principle in developing reliable systems is to avoid building them with faulty components [82]. Interpretation of failure modes on the electrical and logical model. the processes used to screen failures in digital components will be presented. AC parametric testing is a general name for timing measurement tests which measure speed and propagation delay. Also. the ratio of undetected faults to the total number of faults in the circuit. The next stage consists of parametric tests. that is. For example. The logic aspects of a design are typically checked by applying a set of input signals to assert that the circuit is performing its proper function. vibration. It is the basis of many test pattern generators and fault simulators (software programs). patterns to guarantee that the circuit is fault free. A Boolean test is defined as a test in which only logical signal values are considered. [79]. and Y is the yield. This is sometimes called functional testing. The single stuck-at fault is the most widely used fault model. There are several steps followed in screening failed components [82]. Before describing the different fault models. Hence a new term Boolean testing was coined by [79]. It has been proven that such a test does not necessarily guarantee that the circuit is fault free [78]. Parametric tests are technology dependent [lOS]. The function. The third and fourth stages are functional and stress testing. although temporary failures occur more often than hard failures. in addition. The single most important issue in eliminating . [45]. The latter is performed in order to eliminate marginal components (infant mortality) using stresses such as. The purpose of such a test is to detect some of those defects listed in Table 1. it has become evident that other fault models are needed to represent more accurately the failure modes in this technology. it is more effective to decrease M in order to reduce the defect level. {80]. After this test has been performed. The issue then is how to screen the defective components.52 Failure Mechanism: Particle on Mask A' A B-C Failure Mode Shorted: Metal Lines F = A'eB' B' Electrical Fault Model Logical Fault Model Figure 2. DL = 1-yM [115] was simplifIed by [83] to DL = M In (lIY). for values ofDL:S 1000 DPM (Defects Per Million). Here M is the fault uncoverage. With the advent of MOS technology. The relation is linear in M and logarithmic in Y. the fraction of die on a wafer that are free of defects. ECL technology is current driven and voltage requirements are different than for high input impedance TTL. It usually includes the functional test and. Thus.

4 [85]. In the bridge nMOS circuit shown in Fig. Exhaustive testing has been used in VLSI testing by two major microprocessors manufacturers. the output function. Motorola [64] and Intel [40]. On the other hand.53 defective components is the development of Boolean test sets that guarantee a high fault coverage. When the number of inputs is very large. the test conditions imposed by the routine should be devised at the level of the components themselves. to represent the failure mode by a logical value. stuck-at-1 (sal). this will be equivalent to C sal. IfC is shorted to Vdd (held high). it is then important to characterize the defects in the circuit as logical or electrical values on the nodes connecting the different components of the circuit. The stuck-at fault model is one such representation. more than 20 primary inputs.1 Sinl:le Stuck-at Fault. exhaustive testing is not practical [78].111'--4__---1 (b) VGND (a) Figure 3. The same effect is obtained if transistor C is always on (stuck on). This fault model can successfully represent some of the failure modes. 3 is connected to Vem it is stuck at O. The single stuck-at fault model assumes that a node in the logical diagram of a circuit is always fixed at 0 or at 1. rather than at the level of programmed orders. A short in resistance R2 can also be modeled by the input 'A' stuck at O. Such test sets are very largely dependent on the fault model used. The opening sentence of this paper is: "In order for the successful operation of a test routine to guarantee that a computing system has no faulty components. For example. if the line ab is . To make testing more manageable. is given by (A + q(B + D)." In order to confirm or deny the presence of a failure in an n-input circuit representing a logical function. If the input 'A' of the XOR gate shown in Fig. TIffiSTUCK-ATFAULTMODEL Early techniques of testing digital circuits were mostly concerned with functional design verification which could not necessarily guarantee that the circuit was fault free. Bipolar Circuit: (a) Circuit level. That is. it is considered stuck-at-O (saO) and the latter. Z. 4. B A --. In the former case. Eldred at the August 1958 meeting of the ACM [33]. (b) Logical level. one can apply all 2n input combinations and check if the output response is correct or faulty. 4. as will be shown in the remainder of this paper. The switch to a testing method that takes into consideration the structure of the circuit was suggested in a paper presented by R.

r) is the number of all combinations of r out of m things. The major problem involved with the generation of test sets for multiple faults is the large number of possible faults. The number of SSA faults is 2m.2 Multiple Stuck-at Faults With increased device density and decreased geometry. Two faults are equivalent if they have the same detecting test sets [74]. Fanout stem stuck faults dominate fanout branch faults unless the fanout branches reconverge with odd inversion parity [82]. diffusion of poly. the number of r simultaneous faults in an m-node circuit is 2r C(m. [102] found that the stuck-at model can represent one of several causes: extra metal. In general. . In his study.r). A fault fl is said to dominate another fault f2 if the test set of fl includes the test set of f2. A A--1 C b B~ + &. The SSA faults can thus be grouped in equivalence classes and it is thus sufficient to consider one fault from each class in generating test sets. where m is the number of signal lines in the circuit. The results suggest that up to 6 simultaneous multiple faults should be tested to guarantee that a circuit is fault free. There are different strategies for developing test sets for SSA faults. Goldstein translated the probability distributions of physical defect size and location into probabilities of occurrence of single and multiple faults. nMOS Circuit. missing diffusion or missing poly. double and triple SA faults are listed in Table 3.54 open. The attractiveness of the SSA fault model is its simplicity. B 0 z + Figure 4. the likelihood that more than one SSA fault can occur simultaneously is greater [43]. It is the widely used model in software packages developed for digital testing. By grouping faults according to their effect on the circuit. test patterns that detect f2 also detect fl. 4. where C(m. The numbers of single. the fault set can be collapsed to a minimal number.circuit is reduced to AB + CD and the failure mode cannot be modeled by the stuck-at model. The SSA fault model has proven to be successful in detecting permanent failures. The number of faults can be further reduced usingfault dominance. the number of faults to be considered during test set generation can be reduced. the . In a simulation study on MOS technology circuits. These will be discussed in Section 7. Consequently. Using fault equivalence and fault dominance.

[111]. an open at sites 1 and 5 is equivalent to a saO fault on A. the fault is equivalent to A saO. fault collapsing is used. depending on the site of the open in the circuit. For A = 1 the output is pulled down to 0. 3x 1()6 l. drain. e. Detection of the open at site 6 requires the application of the pattern pair (0. The nMOS implementations of an inverter shown in Fig. a) the sites of the failure modes. or source contacts. [108]. 2) shorts between gate and drain or gate and source. The are several failure modes in MOS technology circuits [9]. Opens on the interconnecting lines may be represented by a stuck-at model or may cause the circuit to store its previous logical value. b) Circuit responses. SSA test sets are often used to detect multiple faults as will be discussed in Section 7.. 5 will be used to illustrate the interpretation of the failures modes on the logical level. FAULT MODELS FOR MOS DEVICES The SSA fault model cannot represent all failure modes in MOS technology [9]. and for A = 0 the transistor is not conducting and it retains its previous value. Number of Faults Single Double Number of nodes 180 19800 l. The numbers indicated on the circuits refer to a certain failure mode.998x1()6 20 200 10 100 2000 1000 Triple 960 I. .3x109 In order to reduce the number of multiple stuck-at faults. 5. If the transistor is stuck on. and site 3 is gate contact open. The frrst and second categories of the failure modes can be represented by a stuck-at fault. [39].1) V dd OUtpU13 in presense of fau113 at the indicated sites 6 5 A 3 Z A 0 1 Z 1 2 3 4 0 0 5 6 Q 0 Q previous charge I intemUdiate value (a) (b) Figure 5. On the other hand.g. etc. In Fig.55 Table 3. Numbers of Possible Stuck-At Faults. site 2 is a short between gate emitter. site 1 is open on the interconnecting line. and 4) open on gate. nMOS Inverter. the circuit behaves as if input A is sal. while an open at site 6 will cause the output to depend on the input signal. Also. [39]: 1) transistors shorts and opens. 5. 3) opens and shorts on interconnecting lines. The main reason for this is that MOS combinational circuits do not remain combinational under all faulty conditions. if the gate is shorted to the source (site 2).

a pair of test patterns is needed to detect the fault. a 3-pattern test scheme is used to detect both SOP and SON faults [68).56 For CMOS circuits. 17) or as a connector-switch-attenuator (CSA) multi-component [49). The other important fault model in CMOS is the Stuck-On type (SON) in which a transistor is always on. Hayes [51) presents a general class of CSA and its underlying algebraic structure (pseudo Boolean). [92). [50). Jain [58) suggested a modification of the D-Algorithm to represent the failures by the stuck-at model. [111). Simulators based on gate level fault models are not suitable to represent all faulty conditions of MOS circuits. [42). They describe a layout method for gate-arrays chips in which any SOP fault is forced to appear as a SA fault. A survey of switch level algorithms used for logic and fault simulators is given in [18). The output will then be charged or discharged to a faulty value. failures in pull-up or pull-down transistors can cause the transistor to function as a memory element Here again. depending on the value of the connector. The electrical representation of the model is by a voltage source and a finite series of non-zero resistors Rj. Special simulators were developed. [26). The advantage of this technique is that the patterns can be generated by a gate level SSA fault automatic test pattern generator. Chiang et. opens at the indicated sites (1 through 6) are represented by stuckopen faults. Other design for testability techniques have been developed for CMOS circuits [19). For the inverter in Fig. Here. It has been investigated extensively by [20). [61). [58). [25). [70). In the CSA model each ideal transistor is represented as a switch and a connector. [66). In references [61) and [118) it has been demonstrated that Stuck-Open faults can be avoided by proper design practices. [34). This type of failure is called Stuck-Open (SOP). and [118). b) Responses of the circuit. al. [26) have developed a graph and an approach to test pattern generation for stuck-open faults and short in complex gates. In order to allow for intermediate values between open and closed. a transistor is represented as a switch [16. the current is given by Ij=VjIRj and represent the faulty values other than logical 0 or 1. Test generation for multiple SOP and SON faults has been attempted by EI-Ziq[35) for some special functions. Test generation algorithms for MOS technology have been reported [23). an attenuator is added.Using Ohm's law. 6. 6 Outputs in 1he presence of faults at 1he iIldica1ed si1eS 4 A 3 0 A Z 1 0 2 3 1 1 I Q Q Q 4 5 6 Q 0 Q 0 Q 0 Q previous charge I In1ennidiA1e value (a) (b) Figure 6. [25). [67). CMOS Inverter a) Sites of failure modes represented by Stuck-Open faults. For CMOS combinational circuits. Such a fault may cause a short between Vm and ground. Ij). [26). Each transistor is then represented by the pair (Vj . . It includes an extensive bibliography on switch level representation and application in test pattern generation and simulation. The switch is open or closed.

OR AND 00 00 AND (c) Figure 7. otherwise. Among these are 1) manufacturing defects. Bridging faults are becoming more important because of high device density and decreasing geometry. (b) Equivalent electrical circuit. When the fault involve r lines with r ~ 2. BRIDGING FAULTS Bridging faults occur when two or more lines in a circuit are shorted together and create wired logic [84].p ~< R. the simple SSA model is not adequate. ~- C RCp A C RCn - ~ Inj2uts A=B A = 0. Thus the number of possible faults is smaller and depends largely on the circuit layout. and has resulted in the practice of monitoring the power supply current [3]. it is a simple bridging fault.':. in CMOS. This wired logic depends on the types of gates driving the bridged lines. The voting model for bridging faults: (a) Bridged signal lines. and 3) intercomponent (chips or boards) connections. (c) Possible output of the faulty circuit. It is very unlikely for some pairs of the signal lines to be shorted. Chiang [26] states that the relative strengths of the pull-up and pulldown of the driving gates determines the voltage of the shorts and that voltage may lie between the defined logic voltages. which has become the dominant VLSI technology. However. Bridging faults in TTL and nMOS circuits can be modeled by wired logic. B=O D D B (b) (a) -- !Relative Drivel Out~ut any ratio > R{)J C = D = A' = B' C=D=O C=D=1 Ren >RQJ C=D=1 C=D=O 'j. [118]. Fig. 7 illustrates the different types of bridging faults. There are several causes that produce bridging faults.57 6. Multiple bridging faults are more likely to occur at the primary inputs of the chip. 2) packaging.' < Rlh Value ! Wired LogiC! AND.' [If}.2). They are classified as feedback (tb) and non-feedback faults (nfb) [84].. B=1 A = 1. A logic model proposed by Timoc [108] uses "asymmetrical wired . The lack of an effective logic model for bridging faults severely complicated the test pattern generation for CMOS circuits. The total number of simple bridging faults for a circuit of m nodes is C(m. the fault is said to be of multiplicity r.

7. However. The most common approach to testing is design verification. and [103] in which simulated annealing was used. The theoretical results were confirmed with simulation studies on multiplexers of different complexities and implementation [69]. Specific circuits have been identified for which a complete SSA fault test set is guaranteed to detect all multiple stuck-at faults. [76] guarantee 100% detection of all SSA faults. One such class is single output. and increase the number of states in a sequential circuit. In this section. A fortiori this is also true for toggle and pin test sets. the effectiveness of SSA fault model in detecting multiple SA faults and bridging faults will be reported. [84]. This is particularly troublesome since pseudorandom test sets tend to be longer than algorithmic test sets. random or pseudorandom patterns are computed when needed using a LinearFeedback-Shift-Register (LFSR). [28]. For this type of testing. [81]. Their results together with a simulation experiment [86] are discussed in the next section. [53]. McCluskey [81] shows that for an n-input circuit. Even when a model is assumed. The disadvantage is that fault simulation is needed for fault grading. the logical value of the bridged lines can be represented by wired-OR or wired-AND. Sin~le Stuck-at Faults McCluskey [80] compares several strategies for generating test patterns for SSA faults. The probabilistic model [36] indicates that in the absence of information about the driving gates. The voting model [3] is illustrated in Fig. a wired-AND model is most appropriate. many effort and resources were invested in developing tests for it. Although the multiple fault testability of restricted connected sets is a useful property. and they are not suited for Built-In Self-Testing (BIST). The increased number of states causes an increase in the test length [1]. we will consider different types of test generation for the SSA fault model. passing this test does not guarantee that the circuit is fault free. Exhaustive and pseudoexhaustive testing [75]. Among these are the D-algorithm [96]. the method of test generation affects the fault coverage. [95]. Here. However. EFFECTIVENESS OF SINGLE-STUCK FAULT TEST SETS Because the stuck-at fault model has been used for a long time. the escape probability of a fault of detectability k is given by Qk = e -kLlN.1.2. 7. depending on the input signals on these driving gates and their pull-up and pull-down values as shown in Fig. These approaches to testing do not assume a fault model. these circuits are actually a special class of circuits known as restricted connected sets [99]. [70]. Simulation studies on CMOS circuits carried out by [3] and [36] showed that the bridged lines remain at logic 0 or 1 depending on the driving gates and the input on these gates. 7. and the detectability is the number of test patterns that detect the fault. . 7. However. [113]. Current research is aimed at discovering some way to accurately estimate the fault coverage without detailed simulation [27]. Multiple Stuck-at Faults Several studies have been conducted to examine the detection of multiple stuck-at faults using single stuck-at test patterns. Techniques to partition a circuit were developed [90]. These methods are computationally expensive. L is the length of the test set. [100]. Feedback bridging faults transform a combinational circuit into a sequential circuit. and many others studied the detection of bridging faults using SSA fault test sets. It is only natural that these tests are used to detect other fault models. for the same driving gates. exhaustive testing is not realistic when the number of inputs exceeds 20 and pseudoexhaustive testing requires efficient segmentation of the circuit. First. where N=2n . The optimal circuit segmentation for pseudoexhaustive testing has been shown to be NP-complete [6]. few practical circuits correspond to the required structure. [98].58 logic" where one signal line retains its value and the other assumes the logical function of both shorted lines. 7(c). FAN [38] and PODEM [41]. There is a number of techniques for generating test sets that are shorter than exhaustive test sets. two level circuits with primary input fanout allowed.

Brid~in~ Faults SSA fault test sets have been proposed for the detection of bridging faults by [1]. In order to gain more insight in bridging fault testing.9% coverage was obtained for double stuck-at faults. n-input balanced parity trees (2~ n ~ 32) [87]. This coverage increased to 96% when an exhaustive codeword test was applied. then no fault simulation or other circuit analysis is required for the evaluation of the multiple fault coverage of specific single fault test sets. 2) the length of the test set model seems not to be a significant factor. The use of test structures becomes more difficult as device density increases. Agarwal [2] shows that the inclusion of one internal reconvergent fanout reduces the bound on the fault coverage by approximately 5%. [84] and [116]. But the bound on the coverage decreases rapidly as the amount of reconvergent internal fanout increases. as well as algorithmic test sets generated for SSA faults. pseudoexhaustive and pseudorandom test sets. If the guaranteed coverage is sufficient.3. This can be explained by the highly reconverging paths nature of the circuit that caused fault masking. [Abromivici 83] alters the SSA test set to meet constraints imposed by bridging faults. [56]. ten SSA fault test sets were used. and a two-rail code checker [88]. 85. For VLSI. [37]. Here. these methods are not efficient. 7. [12]. The second circuit is a C-testable circuit that requires no more than 4 test patterns for 100% detection of all SSA faults. Millman [86] carried out several simulations on the ALU 181. 8. The inclusion of a second and a third fanout reduces the bound by 3% in each case. In order to assess the multiple fault coverage by SSA fault test sets for commercial circuits.5%. The last circuit uses only codeword test patterns. The results of these experiments (bridging fault coverage) showed that 1) there was no significant difference between the two types of wired logic. reorders it and augments it to detect all bridging faults. However. Both wired-AND and wired-OR models were used. simulation studies were performed on the three types of circuits: the 74LS18l 4-bit ALU [55]. the main conclusion of the analysis that the multiple fault coverage of a single stuck-at fault test set is generally close to 100% for circuits without reconvergent fanout. a 4 codeword test set that detects all SSA faults yields a double fault coverage of 84. For the 2-rail checker circuit.33%. Algorithms based only on the circuit structure and not the specific test set have been developed for computing a lower bound on the multiple fault coverage of single fault test sets [2]. Some test structures can be used to provide a measure of device switching speed. Many of the undetectable faults were self masking. Delay testing of a circuit determines if it contains signal paths that are too slow or too fast in propagating input transitions. Mei [84] starts with an existing SSA fault test set. The algorithm shows only lower bounds. Careful analysis shows that the simulation results and the assumptions of the theoretical results suggest that much of the difference is due to test set size and multiple primary outputs. That is. and 3) the patterns in a pseudoexhaustive test set can be rearranged in such a way as to increase the coverage to 100%. They included algorithmic as well as pseudorandom and pseudoexhaustive test sets. . The fault coverage determined by simulation is much higher than would be anticipated based on the results of Schertz and Agarwal. The first benchmark circuit was selected because it is one of the most complex combinational circuits. The parity tree study yielded a much lower fault coverage. [57]. DELAY FAULTS It is possible for a circuit to be structurally correct but to have signal paths with delays that exceed the bounds required for correct operation. balanced parity trees and multiplexers. They yield 100% fault detection for some special circuits. two faults which are observable at the same primary output are detected by the same test patterns. can be applied. Better than 99. Delay faults may not be provoked if the operating frequency is low. Other approaches to ensure correct timing include external scan [117] and I/O scan path [78].59 It is not always practical to use exhaustive testing to detect multiple faults for the same reasons mentioned in previous sections. Almost all the undetected faults involved reconverging paths through exclusive OR gates. For the ALU.

9. Atmospheric discharges Electrostatic discharges Intermittent Parameter degradation Timing Metal related (open/short) . is tested. [71]. microprocessors. etc. In addition to algorithmic delay test generation. Temporary failures are much harder to track because when a component. They are not as thoroughly studied as permanent failures. Temporary Failures. The inputs a and c sensitize a path for any transition on b to appear on the output ~ X . The latter is more suitable for BIST environment Simulation issues in delay testing are discussed in [60] and [114]. it is not usually possible to reproduce the fault. Test generation techniques for delay faults are proposed in [15].RAMs. Sensitization and detection of a delay fault. and [101]. ~ Transient ~ Power supply disturbances Electromagnetic interferences Charged particles . Delay testing consists of applying a pair of input vectors at the desired operational speed and observing the outputs for early or late transition. chip or board. Temporary failures are encountered in different digital components . 00 1)..::.60 Delay faults model the effect of physical defects on circuit response time. [65].00=-_ _ _ _--1 1x1 10 Oxxxxx1 Oxxx1 DI'A'\'!!II!4!"""'---t X3 ~11':""""_ _~'=U~_--1 & 1xxxxO ® Figure 8. These faults may be made more complex by taking into account the direction of the signal transition as well as the condition of other gate inputs. testing [112] is also used. [104]. The first type is usually due to some temporary external condition. The application of a vector pair to sensitize and propagate the fault is illustrated in Fig. Physical causes for delay faults are discussed in [54] and [60]. There are two major types of temporary failures: transient and intermittent (recurring).parameter degradation or improper timing. soft or temporary failures are more frequent [7]. while the second is due to varying hardware states . [54]. Table 4. Table 4 lists the different types of temporary failures and some of their main causes. The test coverage is improved when a self-test method is used [10]. The delay in the inverter is propagated to the output by the pair of vectors (011. pseudorandom. TEMPORARYFAILURES Although hard failures result in a need to change a component or repair it causing a long mean-time-to-repair. 8.

Vdd (V) 4.5 1.2 Metastability Another form of transient faults is caused by metastability in latches and flip flops. Metastability occurs when a latch is given only enough energy to switch its state halfway to another stable state. The circuit used in the experiment was proposed by [75]. For this.0 . Power SuwJy Disturbances Power supply disturbances are known to cause errors in the operation of digital systems. It was found that the susceptibility of the circuits to power supply voltage disturbances is related to the operating frequency. CMOS Breadboard.5 5.0 2. Transient failure may be caused by fluctuations in the power supply. No method eliminating all metastability is known [78]. [30] on circuits implemented in different technologies: CMOS Gate Array. The experimental results were confirmed with simulation on the Daisy Megalogician. is 5 volts. Errors are more likely to occur as the operating frequency increases. the experiment was carried out under a more realistic assumption. metastability . metastability or cosmic radiation. Later experimentation was carried out by Cortes [29].5 0. however. logic signal changing with time.1. These experiments related the disturbances to the noise immunity of the circuits. Tolerance of disturbances versus clock frequency.61 10. It is important. 9 [29]. The dependency of disturbance (llYdd) on clock frequency for the three types of technologies are shown in Fig. The results show that propagation delay variation is the dominant effect and that noise immunity plays a smaller role in error occurrence. The latch will remain in this metastable state for some indeterminate amount of time. 10.5 3.!l. and LSTTL breadboard.0 1.0 4.0 2.0 1. Allen [5] and Chesney [24] characterized the susceptibility of circuits to power supply disturbances by measuring the change in the outputs of gates whose inputs are kept at constant signals.0 3. It was then concluded that failures due to power supply disturbances can be modeled by delay faults. or metastable state which exists somewhere between the two stable states.5 3. 10.0 CMOS Gate Array LSTTL Breadboard 0 2 4 6 8 10 12 14 Frequency (MHz) Figure 9.5 4.5 2.0 0. to determine with a certain degree of certainty the probability of metastability occurrences. Vdd. and when the latch enters a semi-stable. Such a fault is difficult to diagnose and correct It is thus important to minimize the noise in the circuit and increase the noise immunity of the circuit.5 2. but will eventually leave it for one of the stable states. Vdd 1.0 3. Here the nominal supply voltage. TRANSIENT FAULTS A transient fault occurs when a logic signal has its value temporarily altered by noise signals and the resulting signal may be interpreted incorrectly by the rest of the circuit [78]. Here.

[63]. and the low and high values of the voltage at the driver's output as stress. The pattern sensitivity is particularly strong for light intermittent faults. [47]. artificially induced intermittent failures can be easily produced. temperature and loading. [110]. Cortes [31] believes that these failures are better described by delay faults than by pattern sensitivity. in a first reference to pattern sensitivity in nonmemory circuits. low probability of activity. Radiation Induced Faults Studies on the effect of radiation have examined alpha particles as well as cosmic rays disturbances in static and dynamic RAMs [11]. [97]. and [107]. 10. controlled and observed. [93]. Hackmeister produced shmoo plots (supply voltage versus speed) that have different shapes for different instruction streams. An interesting discussion on the causes of pattern sensitivity is presented in [94]. catalog parts are forced into intermittent faulty behavior by stressing supply voltage. 11. The temperature stress changes the voltage transfer characteristics. and [109] have addressed the problem of testing for intermittent failures. Two classes of failure mechanisms are listed as responsible for this type of failure: 1) metal-related open and short circuits.. A stress-strength model was developed to explain the experimental results [31]. INTERMITTENTFAULTS Intermittent failures are recognized to be an important cause of field failures in computer systems. The intermittent fault models presented in these papers assume signalindependent faults. Hard failures (field data) that are believed to have appeared earlier as intermittent failures are analyzed. An attempt to collect data on intermittent failures on Sperry-Univac computers is reported by O'Neil [89]. . Pattern Sensitivity was first encountered in memory testing [46]. There is a general consensus that radiation hardening and proper packaging of integrated circuits are sufficient to decrease the occurrence of radiation induced transient faults [32]. 2) marginal operation of violations of operating margins. The latter class of failures has been investigated further by Cortes [31]. Using standard microprocessor characterization techniques. This assumption has turned out to be inappropriate after the experimental evidence of pattern-sensitive intermittent failures. The voltage stress affects the noise immunity. [36]. [73]. The loading stress reduces the driving capability. Other authors referred to Hackmeister results as pattern sensitivity due to "charge-leakage possibilities" [13] or "presence of moderately large RAMs on chip" [48]. Radiations cause ionization that may alter the content of the RAM cells. 10 form a driver-receiver pair. [59]. Both bipolar [91] and MaS [62] technologies are susceptible to such disturbances. as described in [52]. Hackmeister [44] reports instruction sensitivity in microprocessor chips.62 sensors have been developed [21]. Several papers [14]. However. In this study. [119]. thereby causing the circuit under stress to exhibit a similar behavior to that of a marginal circuit under normal operating conditions as described in [83]. The low and high values of the voltage at the input of the receiver can be related to strength. This is known as a single-event fault. The experiments reveal the existence of pattern-sensitive intermittent faults for both sequential and combinational circuits. Le. Very little is known about the failure mechanisms because spontaneous intermittents are difficult to observe and control. The two gates in Fig. It is reasonable to conjecture that different instruction streams exercise different portions of the chip and failures are caused by delay faults due to supply voltage reductions as described in [30]. All stresses used in the experiments have some impact on the logic interfacing between two gates. [106]. The mean time between metastability (MTBM) can be predicted in terms of latch parameters [22].3. Despite the lack of a detailed description of the experimental procedure in [44].

These types of faults need more attention since they occur more frequently than hard faults. Then we indicated the need to depart from this model for two main reasons. the driver-receiver pair. On the other hand. It was indicated that the functional test is not sufficient to guarantee that the circuit is fault free. First. SUMMARY This paper presented a survey of fault models and some of their implications on the development of test pattern generators and simulators. 11. The stress-strength relation is shown in Fig. .visual. Then the screening of failures was outlined . Stress/Strength model of intermittent faults. Two categories of temporary faults were also presented . A failure occurs when stress is larger than strength. the relationship between physical defects. the increased chip density and circuit complexity have increased the probability of occu::rence of multiple and bridging faults. parametric. Strength Stress Fault Fault Input Vectors Figure 11.transient and intermittent faults. we started with the single stuck-at fault. ID presenting fault models. The Stress-Strength model. Cortes further conjectures that his results can be extended to LSTfL and HCMOS catalog parts. failure modes and fault models was established. 12. the use of MOS technology VLSI requires the development of a fault model on the switch level rather than the gate level. functional and stress testing.63 z{ Receiver Driver W Figure 10. failure mechanisms. On one hand.

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