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Digital System Design

with Verilog

Adapted from Z. Navabi


Portions Copyright Z. Navabi, 2006

CSE 467

Verilog Digital System Design

Digital System Design


Automation with Verilog
Digital Design Flow
Design entry
Testbench in Verilog
Design validation
Compilation and synthesis
Postsynthesis simulation
Timing analysis
Hardware generation
Verilog HDL
Verilog evolution
Verilog attributes
The verilog language

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Verilog Digital System Design

Digital System Design


Automation with Verilog

As the size and complexity of digital systems increase, more computer


aided design (CAD) tools are introduced into the hardware design
process.
Early simulation and primitive hardware generation tools have given
way to sophisticated design entry, verification, high-level synthesis,
formal verification, and automatic hardware generation and device
programming tools.
Growth of design automation tools is largely due to hardware
description languages (HDLs
(HDLs)) and design methodologies that are
based on these languages.
Based on HDLs,
HDLs, new digital system CAD tools have been developed
and are now widely used by hardware designers.
One of the most widely used HDLs is the Verilog HDL.
Because of its wide acceptance in digital design industry, Verilog has
become a must-know for design engineers and students in computerhardware-related fields.
Verilog Digital System Design

CSE 467

Digital Design Flow


Design Entry in Verilog

Testbench in Verilog
module testbench ();
generate data ;
process data ;
endmodule

module design (. . .) ;
assign . . .
always . . .
compi (. . .)
endmodule

Behavioral Simulation

Comp1 U1 (. . .) ;
Comp2 U2 (. . .) ;
...
Compn Un (. . .) ;

always (posedge clk )


begin . . . end
if () bus = w;
else . . .

Assertion Verification

Formal Verification

Violation Report;
Time of Violation;
Monitor Coverage

Pass / Fail Report


Property Coverage
Counter Examples

Compilation and Synthesis


Analysis

Synthesis

C++ Classes,
Language Representation

Routing and placement

Y=a &d&w
w =a &b| c

Timing Analysis

1.6 ns

2 ns

Post-synthesis Simulation

Device Programming

FPGA Design Flow


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1010 ...

ASIC Netlist

Custom IC Layout

EDIF
or other netlists

Verilog Digital System Design

Digital Design Flow


Design Entry
Phase
Design Entry in Verilog

Testbench in Verilog
module testbench ();
generate data ;
process data ;
endmodule

module design (. . .) ;
assign . . .
always . . .
compi (. . .)
endmodule

Behavioral Simulation

Comp1 U1 (. . .) ;
Comp2 U2 (. . .) ;
...
Compn Un (. . .) ;

always (posedge clk )


begin . . . end
if () bus = w;
else . . .

Assertion Verification

Formal Verification

Violation Report;
Time of Violation;
Monitor Coverage

Pass / Fail Report


Property Coverage
Counter Examples

FPGA Design Flow

CSE 467

Verilog Digital System Design

Digital Design Flow

Digital Design Flow begins with specification of the design at various


levels of abstraction.

Design entry phase: Specification of design as a mixture of behavioral


Verilog code, instantiation of Verilog modules, and bus and wire
assignments

CSE 467

Verilog Digital System Design

Digital Design Flow


Behavioral Simulation

Assertion Verification

Formal Verification

Violation Report;
Time of Violation;
Monitor Coverage

Pass / Fail Report


Property Coverage
Counter Examples

Compilation and Synthesis


Analysis

Synthesis

C++ Classes,
Language Representation

Routing and placement

Y=a& d&w
w =a& b|c

Timing Analysis

FPGA Design Flow


(Continued)
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2 ns

Presynthesis
Verification
1.6 ns

Verilog Digital System Design

Digital Design Flow

Presynthesis verification: Generating testbenches for verification of the


design and later for verifying the synthesis output

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Verilog Digital System Design

Digital Design Flow


Behavioral Simulation

Assertion Verification

Formal Verification

Violation Report;
Time of Violation;
Monitor Coverage

Pass / Fail Report


Property Coverage
Counter Examples

Compilation and Synthesis


Analysis

Synthesis

C++ Classes,
Language Representation

Routing and placement

Y=a& d&w
w =a& b|c

Timing Analysis

Synthesis Process

FPGA Design Flow


(Continued)
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2 ns

1.6 ns

Verilog Digital System Design

Digital Design Flow

Synthesis process: Translating the design into actual hardware of a


target device (FPGA, ASIC or custom IC)

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Verilog Digital System Design

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Digital Design Flow


Testbench in Verilog

Timing Analysis

module testbench ();


generate data ;
process data ;
endmodule

1.6 ns

2 ns

Post-synthesis Simulation

Postsynthesis
Verification

Device Programming

ASIC Netlist

Custom IC Layout

EDIF
or other netlists

1010 ...

FPGA Design Flow (Continued)


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Verilog Digital System Design

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Digital Design Flow

Postsynthesis simulation: Testing the behavioral model of the design


and its hardware model by using presynthesis test data

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Verilog Digital System Design

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Digital Design Flow


Testbench in Verilog

Timing Analysis

module testbench ();


generate data ;
process data ;
endmodule

1.6 ns

2 ns

Post-synthesis Simulation

Device Programming

ASIC Netlist

Custom IC Layout

EDIF
or other netlists

1010 ...

FPGA Design Flow (Continued)


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Digital Design Flow

Digital Design Flow ends with generating netlist for an application


specific integrated circuits (ASIC), layout for a custom IC, or a program
for a programmable logic devices (PLD)

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Digital Design Flow


Digital Design
Flow
Design Entry

Testbench in Verilog

Design Validation

Compilation
and Synthesis

Postsynthesis
Simulation

Timing
Analysis
Hardware
Generation
Verilog Digital System Design

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Design Entry
Digital Design
Flow
Design
Design Entry
Entry

Testbench in Verilog

Design Validation

Compilation
and Synthesis

Postsynthesis
Simulation

Timing
Analysis
Hardware
Generation

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Verilog Digital System Design

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Design Entry
The first step in the design of a digital system
Describing the design in Verilog in a top-down hierarchical fashion
Register Transfer Level (RTL): High-level Verilog designs usually
described at this level
Verilog constructs used in RT level design:
procedural statements for high-level behavioral description
continuous assignments for representing logic blocks, bus assignments,
and bus and input/output interconnect specifications
instantiation statements for using lower-level components in an upperlevel design

Verilog Digital System Design

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Testbench in Verilog
Digital Design
Flow
Design Entry

Testbench
Testbench in
in Verilog
Verilog

Design Validation

Compilation
and Synthesis

Postsynthesis
Simulation

Timing
Analysis
Hardware
Generation

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Testbench in Verilog

Simulation and Test of a designed system functionality before


Hardware generation
Detection of design errors and incompatibility of components used
in the design
By generation of a test data and observation of simulation results
Testbench: A Verilog module
Use of high-level constructs of Verilog for:
Data Generation
Response Monitoring
Handshaking with the design
Inside the Testbench: Instantiation of the design module
Forms a simulation model together with the design, used by a
Verilog simulation engine

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Design Validation
Digital Design
Flow
Design Entry

Testbench in Verilog

Design
Design Validation
Validation

Compilation
and Synthesis

Postsynthesis
Simulation

Timing
Analysis
Hardware
Generation

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Design Validation

An important task in any digital system design


The process to check the design for any design flaws

A design flaw due to:


Ambiguous Problem Specifications
Designer Errors
Incorrect Use of Parts in the Design

Can be done by:


Simulation
Assertion Verification
Formal Verification

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Design Validation
Design
Validation

Simulation

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Assertion
Verification

Verilog Digital System Design

Formal
Verification

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Simulation
Design
Validation

Simulation

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Assertion
Verification

Verilog Digital System Design

Formal
Verification

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Simulation

Simulation for design validation, done before a design is synthesized


Also Referred to as RT level, or Pre-synthesis Simulation
Simulation at RTL level is accurate to the clock level
The advantage: its speed compared with simulations at the gate or
transistor levels
The Required Test data: generated graphically using waveform editors,
or through a testbench
Outputs of simulators:
Waveforms (for visual inspection)
Text for large designs for machine processing

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Simulation
Inputs

Hierachical
Design
Description

Simulator

Text,
VCD...

...

Testbench

Two
alternatives
for defining
test input
data for a
simulation
engine

Outputs

Waveform

Simulation Model

Other forms
Waveform

Simulation Model
Hierachical
Design
Description

Simulator

Text,
VCD...

...
Other forms

Waveform
Stimuli

Using a Testbench or a Waveform Editor for Simulation


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Testbench
for the
Counter
Circuit

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Simulation
`timescale 1 ns / 100 ps
module Chap1CounterTester ();
reg Clk=0, Reset=0;
wire [3:0] Count;
initial begin
Reset = 0; #5 Reset = 1; #115 Reset = 0;
# 760 $stop;
end
always #26.5 Clk = ~ Clk;
Chap1Counter U1 (Clk, Reset, Count);
endmodule

Simulator

module Chap1Counter (Clk, Reset, Count);


input Clk, Reset;
output [3:0] Count;
reg [3:0] Count;
always @(posedge Clk) begin
if (Reset) Count = 0;
else Count = Count + 1;
end
endmodule

Testbench

Verilog Code
of a Counter
Circuit

Design to Simulate

The simulation
results in form
of a waveform

Verilog Simulation with a Testbench


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SimulationThe testbench instantiates


the design under test, and as
part of the code of the
testbench it applies test data
to the instantiated circuit.
`timescale 1 ns / 100 ps
module Chap1CounterTester ();
reg Clk=0, Reset=0;
wire [3:0] Count;
initial begin
Reset = 0; #5 Reset = 1; #115 Reset = 0;
# 760 $stop;
end
always #26.5 Clk = ~ Clk;
Chap1Counter U1 (Clk, Reset, Count);
endmodule

module Chap1Counter (Clk, Reset, Count);


input Clk, Reset;
output [3:0] Count;
reg [3:0] Count;
always @(posedge Clk) begin
if (Reset) Count = 0;
else Count = Count + 1;
end
endmodule

Verilog Simulation with a Testbench (Continued)

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Verilog Digital System Design

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Simulation
Simulator

Validates the
functionality of the
counter circuit being
tested, Regardless of
clock frequency

Verilog Simulation with a Testbench (Continued)


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Simulation

Obviously, an actual hardware component behaves differently.


Based on the timing and delays of the parts used, there will be a
nonzero delay between the active edge of the clock and the counter
output.
Furthermore, if the clock frequency applied to an actual part is too fast
for propagation of values within the gates and transistors of a design,
the output of the design becomes unpredictable.
The simulation shown here is not provided with the details of the
timing of the hardware being simulated.
Therefore, potential timing problems of the hardware that are due to
gate delays cannot be detected.
This is typical of a presynthesis or high-level behavioral simulation.

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Assertion Verification
Design
Validation

Simulation

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Assertion
Verification

Verilog Digital System Design

Formal
Verification

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Assertion Verification

Assertion Monitors:
Monitors: Used to continuously check for design properties
during simulation
Instead of having to inspect simulation results manually or by
developing sophisticated testbenches
Design Properties: Certain conditions have to be met for the design to
function correctly
Assertion Monitors developed to
to assert that the Design Properties are
not violated
Firing of an assertion verification: alerts
alerts the malfunctioning
malfunctioning of design
according to the designer
designers expectation
Open verification library (OVL): provides a set of assertion monitors for
monitoring common design properties

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Formal Verification
Design
Validation

Simulation

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Assertion
Verification

Verilog Digital System Design

Formal
Verification

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Formal Verification

Formal verification: The process of checking a design against certain


properties
Examining the design to make sure that the described properties by the
designer to reflect correct behavior of the design hold under all
conditions
Property
ropertys Counter Examples:
xamples: Input
Input conditions making a property to
fail
Property coverage indicates how much of the complete design is
exercised by the property

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Compilation and Synthesis


Digital Design
Flow
Design Entry

Testbench in Verilog

Design Validation

Compilation
Compilation
AndSynthesis
Synthesis
and

Postsynthesis
Simulation

Timing
Analysis
Hardware
Generation

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Compilation and Synthesis

Synthesis: The process of automatic hardware generation from a design


description that has an unambiguous hardware correspondence.
A Verilog description for synthesis:
Cannot include signal and gate level timing specifications, file
handling, and other language constructs that do not translate to
sequential or combinational logic equations
Must follow certain styles of coding for combinational and
sequential circuits
Compilation process has three phases:
Analysis Phase
Synthesis Phase
Routing and Placement Phase

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Compilation and Synthesis


The compilation

Input: Hardware
description
consisting of
various levels of
Verilog

Design Specification
Intermediate Format
module design (. . .);
assign . . .
always . . .
compi (. . .)
endmodule
Comp1 U1 (. . .) ;
Comp2 U2 (. . .) ;
...
Compn Un (. . .) ;

Analysis

always (posedge clk )


begin . . . end
if () bus = w;
else . . .

process and a
graphical
representation for
each of the
compilation phase
outputs

Target Hardware
Specification

Generic
Hardware
Generation

Logic
Optimization

Binding

Synthesis
TP d= ; TS u= ...

Routing
and
Placement

Timing
Analysis

Operating
Condition

Chip
Manufacturing
or
Device
Programming

Compilation and Synthesis Process


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Verilog Digital System Design

Output:
A detailed
hardware for
programming
an FPGA or
manufacturing
an ASIC
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Compilation and Synthesis


Analysis Phase: Translates
various parts of the design to
an intermediate format.

Design Specification
Intermediate Format
module design (. . .) ;
assign . . .
always . . .
compi (. . .)
endmodule
Comp1 U1 (. . .) ;
Comp2 U2 (. . .) ;
...
Compn Un (. . .) ;

always (posedge clk )


begin . . . end

Analysis

if () bus = w;
else . . .

Compilation and Synthesis Process (Continued)

Verilog Digital System Design

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Compilation and Synthesis


Synthesis Phase: Links all
parts together and generates
the corresponding logic.

Target Hardware
Specification

Generic
Hardware
Generation

Logic
Optimization

Binding

Synthesis
Has three different phases.

Compilation and Synthesis Process (Continued)

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Compilation and Synthesis


Routing and Placement Phase:
Places and routes components
of the target hardware, and
generates timing details.

TP d= ; TS u= ...

Routing
and
Placement

Timing
Analysis

Chip
Manufacturing
or
Device
Programming

Operating
Condition

Compilation and Synthesis Process (Continued)

Verilog Digital System Design

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Compilation and Synthesis


Compilation
and Synthesis
Analysis

Generic Hardware
Generation

Logic
Optimization

Binding

Routing and
Placement
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Analysis
Compilation
and Synthesis
Analysis

Generic Hardware
Generation

Logic
Optimization

Binding

Routing and
Placement
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Analysis

Before the complete design is turned into hardware


Analyzing the design and generating a uniform format for all parts of it
Also checks the syntax and semantics of the input Verilog code

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Generic Hardware Generation


Compilation
and Synthesis
Analysis

Generic Hardware
Generation

Logic
Optimization

Binding

Routing and
Placement
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Generic Hardware Generation

Generic Hardware Generation: Turning the design into a generic


hardware format such as a set of Boolean expressions or a netlist of
basic gates

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Logic Optimization
Compilation
and Synthesis
Analysis

Generic Hardware
Generation

Logic
Optimization

Binding

Routing and
Placement
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Logic Optimization

Logic Optimization:
Reducing expressions with constant input
Removing redundant logic expressions
Two-level minimization
Multilevel minimization that include logic sharing
Output:
Boolean expressions
Tabular logic representations
Primitive gate netlists

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Binding
Compilation
and Synthesis
Analysis

Generic Hardware
Generation

Logic
Optimization

Binding

Routing and
Placement
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Binding

Binding:
Decide exactly what logic elements and cells are needed for the
realization of the circuit using information from target hardware
Output is specific to the FPGA, ASIC, or custom IC being used

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Routing and Placement


Compilation
and Synthesis
Analysis

Generic Hardware
Generation

Logic
Optimization

Binding

Routing and
Placement
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Routing and Placement

Decides on the placement of cells of the target hardware


Determines wiring of inputs and outputs of the cells through wiring
channels and switching areas of the target hardware
The output is specific to the hardware being used and can be used for
programming an FPGA or manufacturing an ASIC.

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Routing and Placement


module Chap1Counter (Clk, Reset, Count );
input Clk, Reset;
output [3:0] Count ;
reg [3:0] Count ;
always @(posedge Clk) begin
if (Reset) Count = 0;
else Count = Count + 1;
end
endmodule

Design to Synthesize

An example of
a synthesis run:
The counter
circuit is being
synthesized

Target hardware specification

Synthesis Tool

List of primitive components


- Flip-flops
- Logic elements
Timing specifications
- Pin-to-pin timing

An Example Synthesis Run


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Routing and Placement


module Chap1Counter (Clk, Reset, Count );
input Clk, Reset;
output [3:0] Count ;
reg [3:0] Count ;
always @(posedge Clk) begin
if (Reset) Count = 0;
else Count = Count + 1;
end
endmodule

Verilog Description
of the Design

Design to Synthesize
Specification
of the Target
Hardware
Target hardware specification

Synthesis Tool

List of primitive components


- Flip-flops
- Logic elements
Timing specifications
- Pin-to-pin timing

An Example Synthesis Run (Continued)


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Routing and Placement


The output of
synthesis tool

Synthesis Tool

An Example Synthesis Run (Continued)

A list of gates and flipflops available in the


target hardware and
their interconnections

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Postsynthesis Simulation
Digital Design
Flow
Design Entry

Testbench in Verilog

Design Validation

Compilation
and Synthesis

Postsynthesis
Postsynthesis
Simulation
Simulation

Timing
Analysis
Hardware
Generation

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Post-synthesis Simulation

After the Synthesis Phase a complete netlist of target hardware


components and their timings is generated.
The generated netlist includes:
The details of gates used for the implementation of the design
Wiring delays and load effects on gates used in the postsynthesis
design
The netlist output is made available in various netlist formats including
Verilog
A Postsynthesis
Postsynthesis simulation checks:
Timing issues
Determination of a proper clock frequency
Determination of race, and hazard considerations
The behavior of a design as intended by the designer and its behavior
after postsynthesis simulation may be different due
due to delays of wires
and gates.
gates.

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Timing Analysis
Digital Design
Flow
Design Entry

Testbench in Verilog

Design Validation

Compilation
and Synthesis

Postsynthesis
Simulation

Timing
Timing
Analysis
Analysis
Hardware
Generation

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Timing Analysis

A part of the compilation process, or in some tools after the compilation


process
Timing Analysis Phase generates:
Worst-case
Worst-case delays
Clocking speed
Delays from one gate to another
Required setup and hold times
Results of timing analysis appear in Tables and/or Graphs
The results is used by designers to decide on speed of their circuits.

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Hardware Generation
Digital Design
Flow
Design Entry

Testbench in Verilog

Design Validation

Compilation
and Synthesis

Postsynthesis
Simulation

Timing
Analysis
Hardware
Generation

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Hardware Generation

Last stage in an automated Verilog-based design


Generates a netlist for ASIC manufacturing, a program for programming
FPGAs,
FPGAs, or layout of custom IC cells

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Verilog HDL
Verilog
HDL

Verilog
Evolution

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Verilog
Attributes

Verilog Digital System Design

The Verilog
Language

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Verilog HDL

A language that can be understood by:


System Designers
RT Level Designers,
Test Engineers
Simulators
Synthesis Tools
Machines
Has become an IEEE standard

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Verilog Evolution
Verilog
HDL

Verilog
Verilog
Evolution
Evolution

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Verilog
Attributes

Verilog Digital System Design

The Verilog
Language

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Verilog Evolution

Designed in early 1984 by Gateway Design Automation


Originally used as a simulation and verification tool
After the initial acceptance of this language by electronic industry, a
fault simulator, a timing analyzer, and later in 1987, a synthesis tool was
developed based on this language.
Since acquiring Gateway Design Automation and its Verilog-based
tools by Cadence Design System, Cadence has been a strong force
behind popularizing the Verilog hardware description language.
In 1987 VHDL became an IEEE standard hardware description
language.
VHDL was adapted by the U.S. government for related projects and
contracts.
In an effort for popularizing Verilog, in 1990, OVI (Open Verilog
International) was formed and Verilog was placed in public domain.
In 1993, efforts for standardization of this language started. Verilog
became the IEEE standard, IEEE Std. 1364-1995,
1364-1995, in 1995.

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Verilog Evolution

Verilog-2001: A new version of Verilog approved by IEEE in 2001


Additional Features of Verilog-2001:
New features for external file access for read and write
Library management
Constructs for design Configuration
Higher abstraction level constructs
Constructs for specification of iterative structures

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Verilog Attributes
Verilog
HDL

Verilog
Evolution

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Verilog
Attributes

The Verilog
Language

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Verilog Attributes

Verilog is a hardware description language for describing hardware


from transistor level to behavioral.
Supports timing constructs for switch level timing simulation and at the
same time, has features for describing hardware at the abstract
algorithmic level.
A Verilog description may consist of a mix of modules at various
abstraction levels with different degrees of detail.

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Verilog Attributes
Verilog Attributes
Switch Level

Gate Level

Pin-To-Pin Delay

Bussing
Specifications

Behavioral
Level

System Utilities
PLI
Verilog Digital System Design

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Switch Level
Verilog Attributes
Switch
Switch Level
Level

Gate Level

Pin-To-Pin Delay

Bussing
Specifications

Behavioral
Level

System Utilities
PLI

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Switch Level

Features of the language for switch level modeling and simulation:


Primitive unidirectional and bidirectional switches with parameters
for delay and charge storage

Circuit delays may be modeled as propagation delay, rise and fall delay,
and line delays.
The charge storage feature for describing dynamic complimentary
metal oxide semicondutor (CMOS) and metal oxide semiconductor
(MOS) circuits.

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Gate Level
Verilog Attributes
Switch Level

Gate
Gate Level
Level

Pin-To-Pin Delay

Bussing
Specifications

Behavioral
Level

System Utilities
PLI

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Gate Level

Gate level primitives with predefined parameters provide a convenient


platform for:
netlist representation
gate level simulation.
For more detailed and special purpose gate simulations:
Gate components defined at the behavioral level.
Verilog provides utilities for defining primitives with special
functionalities:
A simple 4-value logic system used for signal values
16 levels of strength in addition to the four values for more accurate
logic modeling

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Pin-To-Pin Delay
Verilog Attributes
Switch Level

Gate Level

Pin-To-Pin
Pin-To-Pin Delay
Delay

Bussing
Specifications

Behavioral
Level

System Utilities
PLI

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Pin-To-Pin Delay

Verilog provides a utility for timing specification of components at the


input/output level:
Can be used for back annotation of timing information in original
predesigned descriptions
Enables modelers to finetune timing behavior of their models based
on physical implementations

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Bussing Specifications
Verilog Attributes
Switch Level

Gate Level

Pin-To-Pin Delay

Bussing
Specifications

Behavioral
Level

System Utilities
PLI

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Bussing Specifications

Verilog provides:
Bus and register modeling utilities
For various bus structures, predefined wire and bus resolution
functions using the 4-value logic value system.

Combination of bus logic and resolution-functions enable modeling of


most physical bus types.

For register modeling, high-level clock representation and timingcontrol constructs can be used for representation of registers with
various clocking and resetting schemes.

Verilog Digital System Design

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Behavioral Level
Verilog Attributes
Switch Level

Gate Level

Pin-To-Pin Delay

Bussing
Specifications

Behavioral
Behavioral
Level
Level

System Utilities
PLI

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Behavioral Level

Procedural blocks in Verilog enable algorithmic representations of


hardware structures.
Constructs similar to those in software programming languages are
provided for describing hardware at this level.

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System Utilities
Verilog Attributes
Switch Level

Gate Level

Pin-To-Pin Delay

Bussing
Specifications

Behavioral
Level

System Utilities
PLI

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System Utilities

System tasks in Verilog provide designers with tools for :


Testbench generation
File access for read and write
Data handling
Data generation
Special hardware modeling.

System utilities for reading memory and programmable logic array


(PLA) images provide convenient ways of modeling these components.
Verilog display and I/O tasks can be used to handle all inputs and
outputs for data application and simulation.
Verilog allows random access to files for read and write operations.

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Program Language Interface


Verilog Attributes
Switch Level

Gate Level

Pin-To-Pin Delay

Bussing
Specifications

Behavioral
Level

System Utilities
PLI

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Program Language Interface

The Programming Language Interface (PLI) for Verilog is a


mechanism to interface Verilog programs with programs written in the
C language. It also provides mechanisms to access internal databases
of the simulator from C programs.

PLI is used for implementing system calls which would be hard to do


otherwise (or impossible) using Verilog syntax. Or, in other words, you
can take advantage of both paradigms - the parallel and hardware
related features of Verilog and the sequential flow of C - using the PLI.

Some of the most common applications of PLI are delay back


annotation, writing delay calculators and developing user interface.

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The Verilog Language


Verilog
HDL

Verilog
Evolution

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Verilog
Attributes

Verilog Digital System Design

The Verilog
Verilog
The
Language
Language

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The Verilog Language

The Verilog HDL satisfies all requirements for design and synthesis of
digital systems:

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Supports hierarchical description of hardware from system to gate


or even switch level.
Has strong support at all levels for timing specification and
violation detection.
Timing and concurrency required for hardware modeling are
specially emphasized in it.
A hardware component is described by the module_declaration
language construct in it.

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The Verilog Language

The Verilog HDL satisfies all requirements for design and synthesis of
digital systems (Continued):

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Description of a module specifies a component


components input and output
list as well as internal component busses and registers within a
module,
module, concurrent assignments, component instantiations, and
procedural blocks can be used to describe a hardware component.
Several modules can hierarchically be instantiated to form other
hardware structures.
Many Verilog tools and environments exist that provide simulation,
fault simulation, formal verification, and synthesis.
Simulation environments provide graphical front-end programs and
waveform editing and display tools.
Synthesis tools are based on a subset of Verilog.

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