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Chennai Institute of Technology

Sarathy Nagar, Pudupedu, Kundrathur, Chennai-600069

Department of Electronics and Communication Engineering


Ex. No. 6
Date:

CARRY SELECT ADDER

Aim:
To simulate and synthesis Carry Select Adder using Verilog HDL
Software tools Required:
Synthesis tool: Xilinx ISE.
Simulation tool: Project navigator Simulator
Theory:
Carry-select adders use multiple narrow adders to create fast wide
adders. A carry-select adder provides two separate adders for the upper
words, one for each possibility. A MUX is then used to select the valid
result. Consider an 8-bit adder that is split into two 4-bit groups. The lowerorder bits and are fed into the 4_bit adder l to produce the sum bits and a
carry-out bit .the higher order bits and are used as input to one 4_bit adder
and and
are used as input of the another 4_bit adder. Adder U0
calculates the sum with a carry-in of C3=0.while U1 does the same only it
has a carry-in value of C3=1.both sets of results are used as inputs to an
array of 2:1 MUXes .the carry bit from the adder L is used as the MUX
select signal. If =0 then the results U0 are sent to the output, while a value
of =1 selects the results of U1 for
. The carry-out bit is also
selected by the MUX array.
BLOCK DIAGRAM

y11 x11 y10 x10 y9 x9 y8 x8

y7 x7

C3=1

4-bit ADDER U1
s11

s10

s9

c7

s8

m5

MUX

MUX

MUX

s7

m4

m3

m2

MUX

m1

y5 x5 y4 x4

4-bit ADDER U0

y3

MUX

y6 x6

s6

x3

s5

y2 x2

C3

s4

y1 x1

4-bit ADDER

s3

s2

s1

s0

y0 x0

Chennai Institute of Technology


Sarathy Nagar, Pudupedu, Kundrathur, Chennai-600069

Department of Electronics and Communication Engineering


Verilog module:
module project2(s, m, x, y, z);
output [0:3]s;
output [1:5]m;
input [0:11]x;
input [0:11]y;
input z;
wire c0,c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,s4,s5,s6,s7,s8,s9,s10,s11;
fulladder f1(s[0],c0,x[0],y[0],z);
fulladder f2(s[1],c1,x[1],y[1],c0);
fulladder f3(s[2],c2,x[2],y[2],c1);
fulladder f4(s[3],c3,x[3],y[3],c2);
fulladder f5(s4,c4,x[4],y[4],c3);
fulladder f6(s5,c5,x[5],y[5],c4);
fulladder f7(s6,c6,x[6],y[6],c5);
fulladder f8(s7,c7,x[7],y[7],c6);
fulladder f9(s8,c8,x[8],y[8],~c3);
fulladder f10(s9,c9,x[9],y[9],c8);
fulladder f11(s10,c10,x[10],y[10],c9);
fulladder f12(s11,c11,x[11],y[11],c10);
muxer mu1(m[1],s4,s8,c3);
muxer mu2(m[2],s5,s9,c3);
muxer mu3(m[3],s6,s10,c3);
muxer mu4(m[4],s7,s11,c3);
muxer mu5(m[5],c7,c11,c3);
endmodule
module fulladder (s,c,x,y,z);
output s,c;
input x,y,z;
xor (s,x,y,z);
assign c = ((x & y) | (y & z) | (z & x));
endmodule
module muxer (m,s1,s2,c);
output m;
input s1,s2,c;
wire f,g,h;
not (f,c);
and (g,s1,c);
and (h,s2,f);
or (m,g,h);
2

Chennai Institute of Technology


Sarathy Nagar, Pudupedu, Kundrathur, Chennai-600069

Department of Electronics and Communication Engineering


endmodule

Test bench waveform of carry-select adder:

Result:
Thus Ripple carry adder was designed, simulated and synthesized using verilog HDL.

Chennai Institute of Technology


Sarathy Nagar, Pudupedu, Kundrathur, Chennai-600069

Department of Electronics and Communication Engineering

Ex. No.7
Date:

4 BIT MULTIPLIER

Aim:
To simulate and synthesis 4 Bit multiplier using Verilog HDL.

Software tools requiredr:


Synthesis tool: Xilinx ISE.
Simulation tool: Project navigator Simulator

Theory:
Binary multiplication can be accomplished by several approaches. The approach
presented here is realized entirely with combinational circuits. Such a circuit is called an array
multiplier.
The term array is used to describe the multiplier because the multiplier is organized
as an array structure. Each row, called a partial product, is formed by a bit-by-bit multiplication
of each operand.
For example, a partial product is formed when each bit of operand a is multiplied
by b0, resulting in a3b0, a2b0,a1b0, a0b0. The binary multiplication table is identical to the AND
truth table.
Each product bit {o(x)}, is formed by adding partial product columns. The product
equations, including the carry-in {c(x)}, from column c(x-1), are (the plus sign indicates addition
not OR).
Each product term, p(x), is formed by AND gates and collection of product terms
needed for the multiplier. By adding appropriate p term outputs, the multiplier output equations
are realized, as shown in figure.
4 Bit Multiplier:

a3b3

a3
a2
a1
b3
b2
b1
a3b0 a2b0 a1b0
a3b1 a2b1 a1b1 a0b1
a3b2 a2b2 a1b2 a0b2
a2b3 a1b3 a0b3

a0
b0
a0b0

Chennai Institute of Technology


Sarathy Nagar, Pudupedu, Kundrathur, Chennai-600069

Department of Electronics and Communication Engineering


o7
o6
a0b0 = p0
a1b0 = p1
a0b1 = p2
a2b0 = p3
a1b1 = p4
a0b2 = p5
a3b0 = p6
a2b1 = p7

o5

o4
o3
a1b2 = p8
a0b3 = p9
a3b1 = p10
a2b2 = p11
a1b3 = p12
a3b2 = p13
a2b3 = p14
a3b3 = p15

o2

o1

4 bit multiplier using verilog code


module multiplier (prod, multiplicand, multiplier);
output [7:0] prod;
input [3:0] multiplicand;
input [3:0] multiplier;
wire [7:0] shift1, shift2, shift3, shift4;
wire [7:0] add1,add2,add3,add4;
assign shift1 = {4b0, multiplicand};
assign shift2 = {3b0, multiplicand, 1b0};
assign shift3 = {2b0, multiplicand, 2b0};
assign shift4 = {1b0, multiplicand, 3b0};
assign add1 = (multiplier[0] = = 1b1)? Shift1: 8b0;
assign add2 = (multiplier[1] = = 1b1)? Shift2: 8b0;
assign add3 = (multiplier[2] = = 1b1)? Shift3: 8b0;
assign add4 = (multiplier[3] = = 1b1)? Shift4: 8b0;
assign prod = add1+add2+add3+add4;
endmodule
module testbench( );
wire [7:0] prod;
reg [3:0] multiplicand, multiplier;
multiplier test (prod, multiplicand, multiplier);
initial
begin
multiplicand = 4b0010;
multiplier = 4b0001;
#20 $finish;
end
endmodule
Result:
Thus 4 bit multiplier was simulated and synthesized using verilog HDL.
5

Chennai Institute of Technology


Sarathy Nagar, Pudupedu, Kundrathur, Chennai-600069

Department of Electronics and Communication Engineering

Ex No.8:
Date:

ADDRESS DECODER

Aim:
To simulate and synthesis 2:4 Decoder using Verilog HDL
Software tools required:
Synthesis tool: Xilinx ISE.
Simulation tool: Project navigator Simulator.

Theory:
A decoder is a combinational circuit that converts binary information from n input lines
to a maximum of 2n unique output lines. It performs the reverse operation of the encoder. If the
n-bit decoded information has unused or dont-care combinations, the decoder output will have
fewer than 2n outputs. The decoders are represented as n-to-m line decoders, where m 2n. Their
purpose is to generate the 2n (or fewer) minterms of n input variables. The name decoder is also
used in conjunction with some code converters such as BCD-to-seven-segment decoders. Most,
if not all, IC decoders include one or more enable inputs to control the circuit operation. A
decoder with an enable input can function as a de-multiplexer.
Logic diagram:

Chennai Institute of Technology


Sarathy Nagar, Pudupedu, Kundrathur, Chennai-600069

Department of Electronics and Communication Engineering

Truth table:
INPUTS

OUTPUTS

D0

D1

D2

D3

Decoder using verilog code


module decoder(d,x);
output [7:0] d;
input [2:0] x;
wire [2:0] temp;
not n1(temp[0],x[0]);
not n2(temp[1],x[1]);
not n3(temp[2],x[2]);
and a0(d[0],temp[0],temp[1],temp[2]);
and a1(d[1],temp[0],temp[1],x[2]);
and a2(d[2],temp[0],x[1],temp[2]);
and a3(d[3],temp[0],x[1],x[2]);
and a4(d[4],x[0],temp[1],temp[2]);
and a5(d[5],x[0],temp[1],x[2]);
and a6(d[6],x[0],x[1],temp[2]);
and a7(d[7],x[0],x[1],x[2]);
endmodule
module testbench( );
reg [2:0] x;
wire [7:0] d;
decoder test(d,x);
initial
begin
x=3b000;
#10 x=3b010;
#50 $finish;
end
endmodule
7

Chennai Institute of Technology


Sarathy Nagar, Pudupedu, Kundrathur, Chennai-600069

Department of Electronics and Communication Engineering


Waveform:

Result:
Thus 2 to 4 decoder was simulated and synthesized using Verilog HDL.

Chennai Institute of Technology


Sarathy Nagar, Pudupedu, Kundrathur, Chennai-600069

Department of Electronics and Communication Engineering


Ex. No.9
Date:

MULTIPLEXERS

Aim:
To simulate and synthesis 4 to 1 multiplexer using verilog HDL.
Software tools requiredr:
Synthesis tool: Xilinx ISE.
Simulation tool: Project navigator Simulator
Theory:
A digital multiplexer is a combinational circuit that selects binary information from one
of many input lines and directs it to a single output line. Multiplexing means transmitting a large
number of information units over a smaller number of channels or lines. The selection of a
particular input line is controlled by a set of selection lines. Normally, there are 2n input lines and
n selection lines whose bit combinations determine which input is selected. A multiplexer is also
called a data selector, since it selects one of many inputs and steers the binary information to the
output lines. The size of the multiplexer is specified by the number 2n of its input lines and the
single output line. In general, a 2n to 1 line multiplexer is constructed from an n to 2n
decoder by adding to it 2n input lines, one to each AND gate. The outputs of the AND gates are
applied to a single OR gate to provide the 1 line output.
Logic diagram:

Chennai Institute of Technology


Sarathy Nagar, Pudupedu, Kundrathur, Chennai-600069

Department of Electronics and Communication Engineering


Truth table:
INPUT

OUTPUT

s[1]

s[0]

D[0]
D[1]

D[2]

D[3]

Multiplexer using verilog code:


Structural modeling:
module multiplexer(y,d,s);
output y;
input [3:0] d;
input [1:0] s;
wire a,b,c,e,f,g,h,i;
//Instantiate Primitive gates
not (a,s[0]);
not (b,s[1]);
and (c,d[0],b,a);
and (e,d[1],s[0],a);
and (f,d[2],b,s[1]);
and (g,d[3],s[0],s[1]);
or (h,c,e);
or (i,f,g);
or (y,h,i);
endmodule
Data flow modeling:
module multiplexer(y,d,s);
output y;
input [3:0] d;
input [1:0] s;
wire a,b,c,e,f,g,h,i;
assign a= ~ s[0];
assign b= ~ s[1];
assign c = d[0]&c&b&a;
assign e = d[1]&e&s[0]&a;
10

Chennai Institute of Technology


Sarathy Nagar, Pudupedu, Kundrathur, Chennai-600069

Department of Electronics and Communication Engineering


assign f = d[2]&f&b&s[1];;
assign g = d[3]&g&s[0]&s[1];
assign h = c/e;
assign i= f/g;
assign y= h/i;
endmodule
Behavioural modeling:
module multiplexer (y,a,b,c,e,f,g,h,i,d,s);
output y,a,b,c,e,f,g,h,i;
input [3:0] d;
input [1:0] s;
reg y,a,b,c,e,f,g,h,i;
always@ (d ors)
begin
a=~s[0];
b=~s[1];
c=d[0]&c&b&a;
e=d[1]&s[0]&s;
f=d[2]&b&s[1];
g=d[3]&s[0]&s[1];
h=c/e;
i=f/g;
y=h/i;
end
endmodule
Program using Case statement:
module multiplexer (y,d,s);
output y;
input [3:0] d;
input [1:0] s;
always@(d or s)
begin
case (s)
2b00: y=d[0];
2b01: y=d[1];
2b10: y=d[2];
2b11: y=d[3];
endcase
end
endmodule

11

Chennai Institute of Technology


Sarathy Nagar, Pudupedu, Kundrathur, Chennai-600069

Department of Electronics and Communication Engineering


//Stimulus for testing 4 to 1 Multiplexer
module simulation;
reg [3:0]d;
reg [1:0]s;
wire y;
//Instantiate 4 to 1 Multiplexer
multiplexer mux_t(y,d,s);
initial
begin
s=2'b00;d=4b0001;
#100
s=2'b01;d=4b0010;
end
endmodule
Test bench waveform of multiplexers:

Result:
Thus 4:1 multiplexer was designed, simulated and synthesized using Verilog HDL
12

Chennai Institute of Technology


Sarathy Nagar, Pudupedu, Kundrathur, Chennai-600069

Department of Electronics and Communication Engineering

Ex No.10:
Date:

COUNTERS

Aim:
To simulate and synthesis Counter using Verilog HDL.
Software tools required:
Synthesis tool: Xilinx ISE.
Simulation tool: Project navigator Simulator

LOGIC DIAGRAM:
MOD-10 Ripple Counter:

TRUTH TABLE:

COUNT

A0

A1

A2

A3

13

Chennai Institute of Technology


Sarathy Nagar, Pudupedu, Kundrathur, Chennai-600069

Department of Electronics and Communication Engineering


4

10

Verilog code:
module FF( q,clk,reset);
output q;
input clk,reset;
reg q=1b0;
always@ ( negedge clk or negedge reset)
if ( ~ reset)
q = 1b0;
else
q=(~q);
endmodule
module MOD10 (A0,A1,A2,A3,count);
output A0,A1,A2,A3;
input count;
wire reset;
FF F0 ( A0,count, reset);
FF F1 ( A1,A0, reset);
FF F2 ( A2,A1, reset);
FF F3 ( A3,A2, reset);
nand n1(reset,A1,A3);
endmodule
module tesetbench ( );
reg count;
wire A0,A1,A2,A3;
MOD10 test(A0,A1,A2,A3,count);
always
#10 count = ~count;
initial
begin
count = 1b0;
14

Chennai Institute of Technology


Sarathy Nagar, Pudupedu, Kundrathur, Chennai-600069

Department of Electronics and Communication Engineering


end
endmodule

Waveform:

RESULT:
Thus the mod 10 counter was simulated and synthesized using Verilog HDL and the
output was verified.

15

Chennai Institute of Technology


Sarathy Nagar, Pudupedu, Kundrathur, Chennai-600069

Department of Electronics and Communication Engineering


Ex No.11:
Date:

PSEUDO RANDOM BINARY SEQUENCE GENERATOR

Aim:
To Simulate and Synthesis PRBS using Verilog HDL
Software tools required:
Synthesis tool: Xilinx ISE.
Simulation tool: Project navigator Simulator
Theory:
Random numbers for polynomial equations are generated by using the shift register
circuit. The random number generator is nothing but the Linear Feedback Shift Register (LFSR).
The shift registers are very helpful and versatile modules that facilitate the design of many
sequential circuits whose design may otherwise appear very complex. In its simplest form, a shift
register consists of a series of flip-flops having identical interconnection between two adjacent
flip-flops. Two such registers are shift right registers and the shift left registers. In the shift right
register, the bits stored in the flip-flops shift to the right when shift pulse is active. Like that, for
a shift left register, the bits stored in the flip-flops shift left when shift pulse is active. In the shift
registers, specific patterns are shifted through the register. There are applications where instead
of specific patterns, random patterns are more important. Shift registers can also build to
generate such patterns, which are pseudorandom in nature. Called Linear Feedback Shift
Registers (LFSRs), these are very useful for encoding and decoding the error control codes.
LFSRs used as generators of pseudo random sequences have proved externally useful in the area
of testing of VLSI chips.
Logical diagram:

q [1]

q [0]

q [2]
q2
q1

16

q0

Chennai Institute of Technology


Sarathy Nagar, Pudupedu, Kundrathur, Chennai-600069

Department of Electronics and Communication Engineering


Verilog code
module prbs(d,clk,load,reset,q);
input [2:0] d;
input clk,load,reset;
output [2:0] q;
reg [2:0] q;
always@(posedge clk)
begin
if (reset)
q<=3b000;
else if (load)
q<=d;
else
begin
q[0]<=q[1];
q[1]<=q[2];
q[2]<=q[0]^q[1];
end
end
endmodule
module testbench();
reg [2:0] d;
reg clk,load,reset;
wire [2:0] q;
prbs test(d,clk,load,reset,q);
initial
begin
clk = 1b1;
forever #100 clk = ~clk;
end
initial
begin
load = 1b1;
reset = 1b0;
d = 3b101;
#100 load = 1b0;
end
endmodule
Result:
Thus PRBS generator was designed simulated and synthesized using Verilog HDL.
17

Chennai Institute of Technology


Sarathy Nagar, Pudupedu, Kundrathur, Chennai-600069

Department of Electronics and Communication Engineering


Ex No.12:
Date:

ACCUMULATORS

Aim:
To simulate and synthesis accumulators in Verilog HDL
Software tools required:
Synthesis tool: Xilinx ISE.
Simulation tool: Project navigator Simulator
Theory:
An accumulator differs from a counter in the nature of the operands of the add and
subtract operation:
In a counter, the destination and first operand is a signal or variable and the other
operand is a constant equal to 1: A <= A + 1.
In an accumulator, the destination and first operand is a signal or variable, and the
second operand is either:
A signal or variable: A <= A + B
A constant not equal to 1: A <= A + Constant
An inferred accumulator can be up, down or up down. For an up down accumulator, the
accumulated data may differ between the up and down mode:
...
if updown = '1' then
a <= a + b;
else
a <= a - c;
Block diagram:

18

Chennai Institute of Technology


Sarathy Nagar, Pudupedu, Kundrathur, Chennai-600069

Department of Electronics and Communication Engineering

Program:
module acc (clk,clr,d,y);
input clk,clr,d;
output y;
reg y;
always@ (posedge clk)
begin
case (clr)
1b0 : y=d;
1b1 : y=1b0;
endcase
end
endmodule
module testbench();
reg clk,clr,d;
wire y;
acc test (clk,clr,d,y);
initial
begin
d=1b0;
#10 d=1b1;
#10 d=1b0;
end
initial
begin
clk = 1b0;
forever #10 clk = ~clk;
end
initial
begin
clr=1b0;
forever #30 clr=~clr;
#100 $finish;
end
endmodule

19

Chennai Institute of Technology


Sarathy Nagar, Pudupedu, Kundrathur, Chennai-600069

Department of Electronics and Communication Engineering


Test bench waveform of accumulator:

Result :
Thus Accumulator was simulated and synthesized using Verilog HDL.

20

Chennai Institute of Technology


Sarathy Nagar, Pudupedu, Kundrathur, Chennai-600069

Department of Electronics and Communication Engineering

Ex. No.13
Date

AUTOMATIC LAYOUT GENERATION AND SIMULATION OF


BASIC GATES

Aim:
To generate layout and simulate basic logic gates using Microwind and DSCH V3.5
Software tools required:
Microwind and DSCH V3.5
Procedure:
1. Click on start and go to program. Then go to microwind 3.5 and open DSCH 3.5.
2. Draw the circuit diagram on the screen by dragging the symbol which is present at right hand
side.
3. Use button as input, LED as output and wire is used to connect the input and output.
4. Save the circuit in desktop with .sch as extension.
5. Check the circuit for any floating line and run the circuit to check the output.
6. Convert the circuit to verilog file by clicking make verilog file in file.
7. Open microwind 3.5 in desktop and then compile the verilog file and click on editor to get the
layout.
8. Click on circuit layout to get the node properties and then note down the corresponding
voltage versus time graph.
Schematic diagram and layout for all logic gates:
The Nand Gate
The truth-table and logic symbol of the NAND gate with 2 inputs are shown below. In
DSCH3, select the NAND symbol in the palette, add two buttons and one lamp as shown above.
Add interconnects if necessary to link the button and lamps to the cell pins. Verify the logic
behavior of the cell.

21

Chennai Institute of Technology


Sarathy Nagar, Pudupedu, Kundrathur, Chennai-600069

Department of Electronics and Communication Engineering

In CMOS design, the NAND gate consists of two nMOS in series connected to two
pMOS in parallel. The schematic diagram of the NAND cell is reported below. The nMOS in
series tie the output to the ground for one single combination A=1, B=1.
For the three other combinations, the nMOS path is cut, but a least one pMOS ties the
output to the supply VDD. Notice that both nMOS and pMOS devices are used in their best
regime: the nMOS devices pass 0, the pMOS pass 1.

We may load the NAND gate design using the command File ReadNAND.MSK.
You may also draw the NAND gate manually as for the inverter gate. An alternative solution is
to compile directly the NAND gate into layout with MICROWIND3. In this case, complete the
following procedure:
22

Chennai Institute of Technology


Sarathy Nagar, Pudupedu, Kundrathur, Chennai-600069

Department of Electronics and Communication Engineering

In MICROWIND3.5, click on CompileCompile


One Line. Select the line corresponding to the 2-input NAND description as shown above. The
input and output names can be by the user modified.

Click Compile. The result is reported above.


The compiler has fixed the position of VDD power supply and the ground VSS. The texts A, B,
and S have also been fixed to the layout. Default clocks are assigned to inputs A and B.

The cell architecture has been optimized for easy supply and input/output routing. The
supply bars have the property to connect naturally to the neighboring cells, so that specific effort
for supply routing is not required. The input/output nodes are routed on the top and the bottom of
the active parts, with a regular spacing to ease automatic channel routing between cells.

23

Chennai Institute of Technology


Sarathy Nagar, Pudupedu, Kundrathur, Chennai-600069

Department of Electronics and Communication Engineering


The AND gate
As can be seen in the schematic diagram and in the compiled results, the AND gate is the sum of
a NAND2 gate and an inverter. The layout ready to simulate can be found in the file
AND2.MSK. In CMOS, the negative gates (NAND, NOR, INV) are faster and simpler than the
non-negative gates (AND, OR, Buffer).
The XOR Gate
The truth-table and the schematic diagram of the CMOS XOR gate are shown above. There exist
many possibilities for implementing the XOR function into CMOS. The least efficient design,
but the most forward, consists in building the XOR logic circuit from its Boolean equation.

The proposed solution consists of a transmission-gate implementation of the XOR


operator. The truth table of the XOR can be read as follow: IF B=0, OUT=A, IF B=1, OUT =
Inv(A). The principle of the circuit presented below is to enable the A signal to flow to node N1
if B=1 and to enable the Inv(A) signal to flow to node N1 if B=0.

We may use DSCH3 to create the cell, generate the Verilog description and compile the
resulting text. In MICROWIND3.5, the Verilog compiler is able to construct the XOR cell We
may add a visible property to the intermediate node which serves as an input of the second
inverter. See how the signal, called internal, is altered by Vtn (when the nMOS is ON) and Vtp
(when the pMOS is ON).
24

Chennai Institute of Technology


Sarathy Nagar, Pudupedu, Kundrathur, Chennai-600069

Department of Electronics and Communication Engineering

Result:
Thus layouts of Logic gates were generated and simulated using Microwind and DSCH.

25

Chennai Institute of Technology


Sarathy Nagar, Pudupedu, Kundrathur, Chennai-600069

Department of Electronics and Communication Engineering


Ex. No.14
Date

AUTOMATIC LAYOUT GENERATION AND SIMULATION OF


ADDERS

Aim:
To generate layout and simulate Adders using Microwind and DSCH V3.5
Software tools required:
Microwind and DSCH V3.5
Procedure:
1. Click on start and go to program. Then go to microwind 3.5 and open DSCH 3.5.
2. Draw the circuit diagram on the screen by dragging the symbol which is present at right hand
side.
3. Use button as input, LED as output and wire is used to connect the input and output.
4. Save the circuit in desktop with .sch as extension.
5. Check the circuit for any floating line and run the circuit to check the output.
6. Convert the circuit to verilog file by clicking make verilog file in file.
7. Open microwind 3.5 in desktop and then compile on make verilog file in file and click on
editor to get the layout.
8. Click on circuit to get the node properties and then note down the corresponding voltage
versus time graph.

Schematic diagram and layout for Adders:


Half-Adder
The Half-Adder gate truth-table and schematic diagram are shown in Figure. The SUM
function is made with an XOR gate, the Carry function is a simple AND gate.

26

Chennai Institute of Technology


Sarathy Nagar, Pudupedu, Kundrathur, Chennai-600069

Department of Electronics and Communication Engineering

Verilog compiling:
Use DSCH3 to create the schematic diagram of the half-adder. Verify the circuit with
buttons and lamps. Save the design under the name hadd.sch using the command File Save
As.
Generate the Verilog text by using the command File Make Verilog File. In MICROWIND3,
click on the command Compile Compile Verilog File. Select the text file hadd.txt.

Compiling and Simulation of half adder


Click Compile. When the compiling is complete, the resulting layout appears shown below. The
XOR gate is routed on the left and the AND gate is routed on the right. Now, click on Simulate
Start Simulation.

27

Chennai Institute of Technology


Sarathy Nagar, Pudupedu, Kundrathur, Chennai-600069

Department of Electronics and Communication Engineering

Full-Adder
The truth table and schematic diagram for the full-adder are shown in Figure 5-4. The
SUM is made with two XOR gates and the CARRY is a combination of NAND gates, as shown
below. The most straightforward implementation of the CARRY cell is AB+BC+AC. The
weakness of such a circuit is the use of positive logic gates, leading to multiple stages. A more
efficient circuit consists in the same function but with inverting gates.

Truth table and Schematic diagram of Full Adder

Full-Adder Symbol in DSCH3


When invoking File Schema to new symbol, the screen of figure 6-5 appears. Simply
click OK. The symbol of the full-adder is created, with the name FullAdder.sym in the current
directory. Meanwhile, the Verilog file fullAdder.txt is generated, which contents is reported in
the left part of the window (Item Verilog).
We see that the XOR gates are declared as primitives while the complex gate is declared
using the Assign command, as a combination of AND (&)and OR (|) operators. If we used AND
and OR primitives instead, the layout compiler would implement the function in a series of AND
and OR CMOS gates, loosing the benefits of complex gate approach in terms of cell density and
switching speed.

28

Chennai Institute of Technology


Sarathy Nagar, Pudupedu, Kundrathur, Chennai-600069

Department of Electronics and Communication Engineering

Verilog description of Full Adder

Result:
Thus layouts of Adders were generated and simulated using Microwind and DSCH.

29

Chennai Institute of Technology


Sarathy Nagar, Pudupedu, Kundrathur, Chennai-600069

Department of Electronics and Communication Engineering

Ex. No.15
Date

CMOS INVERTER

Aim:
To generate layout and parasitic extraction of CMOS inverter and to simulate it using
Microwind and DSCH V3.5
Software tools required:
Microwind and DSCH V3.5
Procedure:
1. Click on start and go to program. Then go to microwind 3.5 and open DSCH 3.5.
2. Draw the circuit diagram on the screen by dragging the symbol which is present at right hand
side.
3. Use button as input, LED as output and wire is used to connect the input and output.
4. Save the circuit in desktop with .sch as extension.
5. Check the circuit for any floating line and run the circuit to check the output.
6. Convert the circuit to verilog file by clicking make verilog file in file.
7. Open microwind 3.5 in desktop and then compile on make verilog file in file and click on
editor to get the layout.
8. Click on circuit to get the node properties and then note down the corresponding voltage
versus time graph.

Schematic diagram and layout for CMOS Inverters:


The CMOS inverter
The CMOS inverter design is detailed in the figure below. Here the p-channel MOS and
the n-channel MOS transistors function as switches. When the input signal is logic 0 (Fig. 3-4
left), the nMOS is switched off while PMOS passes VDD through the output. When the input
signal is logic 1 Fig. the pMOS is switched off while the nMOS passes VSS to the output.

30

Chennai Institute of Technology


Sarathy Nagar, Pudupedu, Kundrathur, Chennai-600069

Department of Electronics and Communication Engineering

CMOS Inverter
The fan out corresponds to the number of gates connected to the inverter output. Physically, a
large fan out means a large number of connections that is a large load capacitance. If we simulate
an inverter loaded with one single output, the switching delay is small. Now, if we load the
inverter by several outputs, the delay and the power consumption are increased. The power
consumption linearly increases with the load capacitance.
This is mainly due to the current needed to charge and discharge that capacitance.
Manual layout of the inverter
Click the icon MOS generator on the palette. The following window appears. By default
the proposed length is the minimum length available in the technology (2 lambda), and the width
is 10 lambda. In 0.12m technology, where lambda is 0.06m, the corresponding size is 0.12m
for the length and 0.6m for the width. Simply click Generate Device, and click on the middle
of the screen to fix the MOS device.
Click again the icon MOS generator on the palette. Change the type of device by a tick on pchannel, and click Generate Device. Click on the top of the nMOS to fix the pMOS device.

31

Chennai Institute of Technology


Sarathy Nagar, Pudupedu, Kundrathur, Chennai-600069

Department of Electronics and Communication Engineering

Selecting the n- MOS device


Connection between Devices

Connections required building the inverter


Within CMOS cells, metal and polysilicon are used as interconnects for signals. Metal is
a much better conductor than polysilicon. Consequently, polysilicon is only used to interconnect
gates, such as the bridge (1) between pMOS and nMOS gates, as described in the schematic
diagram of figure. Polysilicon is rarely used for long interconnects, except if a huge resistance
value is expected.
32

Chennai Institute of Technology


Sarathy Nagar, Pudupedu, Kundrathur, Chennai-600069

Department of Electronics and Communication Engineering


In the layout shown in figure, the Polysilicon Bridge links the gate of the n-channel MOS
with the gate of the p-channel MOS device. The polysilicon serves as the gate control and the
bridge between MOS gates.

Polysilicon Bridge between pMOS and nMOS devices


Metal-to-poly
As polysilicon is a poor conductor, metal is preferred to interconnect signals and
supplies. Consequently, the input connection of the inverter is made with metal. Metal and
polysilicon are separated by an oxide which prevents electrical connections. Therefore, a box of
metal drawn across a box of polysilicon does not allow an electrical connection (Figure). To
build an electrical connection, a physical contact is needed. The corresponding layer is called
"contact". We may insert a metal-to-polysilicon contact in the layout using a direct macro
situated in the palette.

Physical contact between metal and polysilicon

33

Chennai Institute of Technology


Sarathy Nagar, Pudupedu, Kundrathur, Chennai-600069

Department of Electronics and Communication Engineering

Adding a poly contact, poly and metal bridges to construct the CMOS inverter
(InvSteps.MSK)
The Process Simulator shows the vertical aspect of the layout, as when fabrication has
been completed. This feature is a significant aid to understand the circuit structure and the way
layers are stacked on top of each other. A click of the mouse on the left side of the n-channel
device layout and the release of the mouse at the right side give the cross-section reported in
figure.

The 2D process section of the inverter circuit near the nMOS device (InvSteps.MSK)
34

Chennai Institute of Technology


Sarathy Nagar, Pudupedu, Kundrathur, Chennai-600069

Department of Electronics and Communication Engineering

Supply Connections
The next design step consists in adding supply connections, that is the positive supply
VDD and the ground supply VSS. We use the metal2 layer (Second level of metallization) to
create horizontal supply connections. Enlarging the supply metal lines reduces the resistance and
avoids electrical overstress. The simplest way to build the physical connection is to add a
metal/Metal2 contact that may be found in the palette. The connection is created by a plug called
"via" between metal2 and metal layers.
The final layout design step consists in adding polarization contacts. These contacts
convey the VSS and VDD voltage supply close to the bulk regions of the device. Remember that
the n-well region should always be polarized to a high voltage to avoid short-circuit between
VDD and VSS. Adding the VDD polarization in the n-well region is a very strict rule.

Adding polarization contacts


Inverter Simulation
The inverter simulation is conducted as follows. Firstly, a VDD supply source (1.2V) is
fixed to the upper metal2 supply line, and a VSS supply source (0.0V) is fixed to the lower
metal2 supply line. The properties are located in the palette menu. Simply click the desired
property, and click on the desired location in the layout. Add a clock on the inverter input node

35

Chennai Institute of Technology


Sarathy Nagar, Pudupedu, Kundrathur, Chennai-600069

Department of Electronics and Communication Engineering

Adding simulation properties (InvSteps.MSK)


The command Simulate Run Simulation gives access to the analog simulation.
Select the simulation mode Voltage vs. Time. The analog simulation of the circuit is performed.
The time domain waveform, proposed by default, details the evolution of the voltages in1 and
out1 versus time. This mode is also called transient simulation, as shown in figure .

Transient simulation of the CMOS inverter (InvSteps.MSK)


The truth-table is verified as follows. A logic zero corresponds to a zero voltage and a
logic 1 to a 1.20V.When the input rises to 1, the output falls to 0, with a 6 Pico-second delay
(6.10-12 second).
Result:
Thus layout and parasitic extraction of CMOS inverter was generated and simulated
using Microwind and DSCH V3.5

36

Chennai Institute of Technology


Sarathy Nagar, Pudupedu, Kundrathur, Chennai-600069

Department of Electronics and Communication Engineering


Ex. No.16
Date:

SCHEMATIC ENTRY AND SPICE SIMULATION OF


MOS DIFFERENTIAL AMPLIFIER

Aim:
To generate schematic entry of MOS differential amplifier and to perform SPICE
simulation of it using Microwind and DSCH V3.5
Software tools required:
Microwind and DSCH V3.5
Procedure:
1. Click on start and go to program. Then go to microwind 3.5 and open DSCH 3.5.
2. Draw the circuit diagram on the screen by dragging the symbol which is present at right hand
side.
3. Use button as input, LED as output and wire is used to connect the input and output.
4. Save the circuit in desktop with .sch as extension.
5. Check the circuit for any floating line and run the circuit to check the output.
6. Convert the circuit to verilog file by clicking make verilog file in file.
7. Open microwind 3.5 in desktop and then compile on make verilog file in file and click on
editor to get the layout.
8. Click on circuit to get the node properties and then note down the corresponding voltage
versus time graph.

Schematic diagram and layout for CMOS Inverters:


The goal of the differential amplifier is to compare two analog signals, and to amplify
their difference. The differential amplifier formulation is reported below (Equation 8-3). Usually,
the gain K is high, ranging from 10 to 1000. The consequence is that the differential amplifier
output saturates very rapidly, because of the supply voltage limits.
Vout = K(Vp Vm)
The schematic diagram of a basic differential amplifier is proposed in figure 9-26. An
nMOS device has been inserted between the differential pair and the ground to improve the gain.
The gate voltage Vbias controls the amount of current that can flow on the two branches. This

37

Chennai Institute of Technology


Sarathy Nagar, Pudupedu, Kundrathur, Chennai-600069

Department of Electronics and Communication Engineering


pass transistor permits the differential pair to operate at lower Vds, which means better analog
performances and less saturation effects.

An improved differential amplifier


The best way to measure the input range is to connect the differential amplifier as a follower, that
is Vout connect to Vm. The Vm property is simply removed, and a contact poly/metal is added at
the appropriate
Place to build the bridge between Vout and Vm. A slow ramp is applied on the input Vin and the
result is observed on the output. We use again the Voltage vs. Voltage to draw the static
characteristics of the follower. The BSIM4 model is forced for simulation by a label "BSIM4" on
the layout.

38

Chennai Institute of Technology


Sarathy Nagar, Pudupedu, Kundrathur, Chennai-600069

Department of Electronics and Communication Engineering

The layout corresponding to the improved differential amplifier


As can be seen from the resulting simulation reported in figure 8-19, a low Vbias features
a larger voltage range, specifically at high voltage values. The follower works properly starting
0.4V, independently of the Vbias value. A high Vbias leads to a slightly faster response, but
reduces the input range and consumes more power as the associated nMOS transistor drives an
important current. The voltage Vbias is often fixed to a value a little higher than the threshold
voltage Vtn. This corresponds to a good compromise between switching speed and input range.

Effect of Vbias on the differential amplifier performance

39

Chennai Institute of Technology


Sarathy Nagar, Pudupedu, Kundrathur, Chennai-600069

Department of Electronics and Communication Engineering


SPICE Simulation
* MOS Diff Amp with Current Mirror Load
*DC Transfer Characteristics vs VID
VID 7 0 DC 0V AC 1V
E+ 1 10 7 0 0.5
E- 2 10 7 0 -0.5
VIC 10 0 DC 0.65V
VDD 3 0 DC 2.5VOLT
VSS 4 0 DC -2.5VOLT
M1 5 1 8 8 NMOS1 W=9.6U L=5.4U
M2 6 2 8 8 NMOS1 W=9.6U L=5.4U
M3 5 5 3 3 PMOS1 W=25.8U L=5.4U
M4 6 5 3 3 PMOS1 W=25.8U L=5.4U
M5 8 9 4 4 NMOS1 W=21.6U L=1.2U
M6 9 9 4 4 NMOS1 W=21.6U L=1.2U
IB 3 9 220UA
.MODEL NMOS1 NMOS VTO=1 KP=40U
+ GAMMA=1.0 LAMBDA=0.02 PHI=0.6
+ TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10
+ U0=550 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9
.MODEL PMOS1 PMOS VTO=-1 KP=15U
+ GAMMA=0.6 LAMBDA=0.02 PHI=0.6
+ TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10
+ U0=200 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9
.DC VID -2.5 2.5 0.05V
.TF V(6) VID
.PROBE
.END

Result:
Thus schematic entry of MOS differential amplifier was generated and SPICE simulation
was done using Microwind and DSCH V3.5.

40

Chennai Institute of Technology


Sarathy Nagar, Pudupedu, Kundrathur, Chennai-600069

Department of Electronics and Communication Engineering


Ex. No.17
Date:

SIMULATION OF VOLTAGE CONTROLLED OSCILLATOR

Aim:
To Simulate voltage controlled oscillator using Microwind and DSCH V3.5
Software tool required:
Microwind and DSCH V3.5
Schematic diagram and layout of Controlled Oscillator:

Voltage Controlled Oscillator


The voltage controlled oscillator is able to produce a square wave with a frequency varying
depending on an analog control Vc. Ideally, the frequency dependence with Vc should be linear.
One example of voltage controlled oscillator is given in figure 8-16. It consists of a ring
oscillator with three stages. Vc acts on the resistance of the supply path, which acts on the speed
response of the inverters.

Schematic diagram of a voltage controlled oscillator

41

Chennai Institute of Technology


Sarathy Nagar, Pudupedu, Kundrathur, Chennai-600069

Department of Electronics and Communication Engineering

Implementation of a voltage controlled oscillator based on a 5-stage ring


Oscillator

42

Chennai Institute of Technology


Sarathy Nagar, Pudupedu, Kundrathur, Chennai-600069

Department of Electronics and Communication Engineering

Simulation of the voltage controlled oscillator


In the simulation of figure, we use the specific mode "Frequency and Voltages" to plot
the frequency variation with Vc. The VCO output is a frequency-varying square wave. Its
dependence with Vc is not linear.

Result:
Thus Voltage Controlled Oscillator was simulated using Microwind and DSCH V3.5

43