Vijayamangalam – 638 056

Subject code/Title: EC6302/ Digital Electronics
Minimization Techniques: Boolean postulates and laws – De-Morgan‟s Theorem –
Principle of Duality - Boolean expression - Minimization of Boolean expressions –– Minterm
– Maxterm - Sum of Products (SOP) – Product of Sums (POS) – Karnaugh map
Minimization – Don‟t care conditions – Quine - Mc Cluskey method of minimization.
Logic Gates: AND, OR, NOT, NAND, NOR, Exclusive–OR and Exclusive–NOR
Implementations of Logic Functions using gates, NAND–NOR implementations – Multi
level gate implementations- Multi output gate implementations. TTL and CMOS Logic and
their Characteristics – Tristate gates
1. Prove the Boolean theorems X+X=X, X+XY=X ? [may/june 2016]
Proof: x + x = (x + x) • 1
1 is the identity for AND
= (x + x) • (x + x')
Complement, x + x' = 1
= x + (x • x')
OR distributes over AND
Complement, x • x' = 0
0 is the identity for OR (P2)
Proof: x+xy =(x.1)+xy
2. Define Noise margin? [may/June 2016]
Noise margin is the maximum external noise voltage added to an input signal that does not cause
an undesirable change in the circuit output.
3. State the advantages of CMOS logic? [April/may 2015]
 High input impedance. ...
 The outputs actively drive both ways.
 The outputs are pretty much rail-to-rail.
 CMOS logic takes very little power when held in a fixed state. ...
 CMOS gates are very simple.
4. State De Morgan’s theorems? [May 2012] [April 2010]
De Morgan has suggested two theorems which are extremely useful in Boolean Algebra. The two
theorems are discussed below.
Theorem 1

The left hand side (LHS) of this theorem represents a NAND gate with inputs A and B,
whereas the right hand side (RHS) of the theorem represents an OR gate with inverted inputs.

This OR gate is called as Bubbled OR.

Vijayamangalam – 638 056

Table showing verification of the De Morgan's first theorem −

Theorem 2

The LHS of this theorem represents a NOR gate with inputs A and B, whereas the RHS
represents an AND gate with inverted inputs.

This AND gate is called as Bubbled AND.

Table showing verification of the De Morgan's second theorem −


Vijayamangalam – 638 056

5. Application of Gray code? May 2012
1.glitch free circuit
2.asynchronous fifo pointer
3.high speed decode circuit
6. Draw the logic diagram of OR gate using universal gates? Nov 2011

7. What is the complement of F = (A+ BC+ AB) ? (Nov / Dec – 08)
F = (A+ BC+ AB)
F‟ = (A+ BC+ AB)' = A'. (BC)'. (AB)'
F = A'. (B'+ C'). (A'+ B')
8. Simplify: Z= X + X'Y [Apr. /May – 10]
Z= X + X'Y = X + XY + X‟Y
since X + XY = X
Z= X + Y (X + X')
since X + X' = 1
9. State the two canonical forms of Boolean algebra. [Apr. / May – 07]
The two canonical forms of Boolean algebra are:
i. Sum of products
ii. Products of Sum
10. Define noise margin?
It is the maximum noise voltage added to an input signal of a digital circuit that does not cause an
undesirable change in the output. It is expressed in milli volts(mV).
11. What is propagation delay?
Propagation delay is the average transition delay time for the signal to propagate from input to
output when the signals change in value. It is expressed in nano seconds(ns).
12. Show that a positive logic NAND gate is a negative logic NOR gate.
Logic expression for NAND gate is F=(X.Y)‟
F= (X.Y)‟= X' + Y' …DeMorgan‟s theorem
F= X' + Y' is the logic expression for negative logic NOR gate

2. The advantages are: 1. to the time that the output of that logic gate is table and valid. Reducing gate delays in digital circuits allows them to process data at a faster rate and improve overall performance. Minimum number of IC‟s required. Draw the TTL Inverter (NOT) Circuit. Power supply requirements 15. OR.Vijayamangalam – 638 056 13. Reduces the printed board size. 17. 4. reduction in costs. Propagation Delay 5. 16. is the length of time which starts when the input to a logic gate becomes stable and valid. or gate delay. 4 . It is specifically designed to reduce the propagation delay in the circuit and to provide sufficient output power for high fan-out. These gates are used to perform all logic operations. As number of IC‟s reduced the probability of occurrence of troubles becomes less. NOT. These output levels are indicated by „X‟ or „d‟ in the truth tables and are called don‟t care conditions or incompletely specified functions. Operating temperature 7. Noise Margin 6. [April/May-2010] Enable 0 1 1 19. EX-OR & EX – NOR etc operations. Input X 0 1 Output Z 0 1 What is a totem pole output? [April/May-2011] Totem pole output is a standard output of a TTL gate.e. Often this refers to the time required for the output to reach from 10% to 90% of its final output level when the input changes. 18. Power dissipation 4. In such cases the output level is not defined. therefore the corresponding output never appears. (i. Mention the important characteristics of digital IC’s? The important characteristics of digital IC‟s are 1. Only one type of gate is required to implement the functions. Draw an active-high tri-state buffer and write its truth table. it can be either high or low. Which gates are called as universal gates? What are its advantages? The NAND and NOR gates are called as the universal gates. What is meant by propagation delay? [Apr /May – 09] The propagation delay. 3. What are called don’t care conditions? In some logic circuits certain input conditions never occur. Fan out 2. AND. Fan In 3. [April/May-2012] 14.

7.0. 4.7. 13.3) D′=(A′+B′)(B+C) 2. = A′B′(C+C′)+(A+A′)BC = A′B′C+ A′B′C′+ABC+A′BC D(A.C)= Σ m(1. 1.B.7.0.[April/May2010] (12) 5 . Express the Boolean function as 1) POS form 2) SOP form D=(A′+B)(B′+C)[April/May-2010] POS form: Given D=(A′+B)(B′+C) =A′B′+A′C+BB′+BC = A′B′+A′C+BC = A′+B′+ A′C+BC = A′(1+C)+B′+BC = A′+B′+BC D= A′B′+BC Using missed terms formulae. 11.Vijayamangalam – 638 056 PART-B 1. 15) + πd (5.3) (4) D= A′B′+BC SOP form: D(A. Minimize the given terms πM (0. 8) using QuineMcClusky methods and verify the results using K-map methods.B.C)= πM(1.

000 0–01 010-101 01-1 1-11 -111 Prime Implicant 0.15 D7.4.d13.15 Binary representation 0000-00 .d5 0.15 D5.4.1.d5 d5.1.7.4 0. d7 Binary Representation 0-00-0-1-1 Step:2 Step:3 Step:4 6 .d5 4.d5 D5.Vijayamangalam – 638 056 Step:1 MINTERM M0 M1 M4 M11 M13 M15 MD5 MD7 MD8 BINARY NUMBER 0000 0001 0100 1011 1101 1111 0101 0111 1000 MINTERM 0 1 4 D8 D5 11 13 D7 15 BINARY REPRESENTATION 0000 0001 0100 1000 0101 1011 1101 0111 1111 Prime Implicant 0.d7 11.15 13.1 0.d8 1.

4) = 0 when the inputs are Σ m(5. Given F=Σ m(0.2.Vijayamangalam – 638 056 Step:5 Y=A′C′+BC′D+AB′CD+ABCD′ 3.2.7) . [April/May-2010] Output = 1 when the inputs are Σ m(0.4) Y=AC+AB 7 (8) . Y=A′+B′C′ Given F′=Σ m(0. Implement the following function using NOR gates.6.2.

2 mw in 74 LS and 4mw in 74 ALS. F (w.17 mw in silicon gate and 0. Discuss the general characteristic of TTL and CMOS logic families. 6.  The power per gate 10mw in 74.  Unique of merit is 1. 5.4 PJ in silicon gate and 10.  The propagation delay is ions 74 and 74LS. z ) = Σ(0.Vijayamangalam – 638 056 4.5 PJ in metal gate. Simplify the Boolean function using K-map.1mw in metal gate.  The propagation delay is 8ns in silicon gate and 105 min metal gate. [April/May2010] (8) Characteristic of TTL:  In the input can be left open.  Iron out of TTL is 10. 12.  The power per gate is 0. 4. It has to be connected to 0 or to VDD or to the another input.  Very less. 13. but increase with increase in switching speed. 1. 2. x .  Less susceptible to noise. 5. 14 ) [April/May-2011] (10) F=Y′+W′Z′+XZ′ 8 . Characteristic of TTL:  Input cannot be left open.  Speed power product of figure of fact is 1 in 74 ALS. Express the Boolean function F=A+B′C in sum of min terms[April/May-2011] (6) Given F=A+B′C =A(B+ B′)(C+C′)+ B′C(A+A′) =(AB+A B′)(C+C′)+B′C(A+A′) =ABC+ABC′+AB′C+AB′C′+AB′C+A′B′C = ABC+ABC′+AB′C+AB′C+A′B′C F=m1+m4+m5+m6+m7 6. y.  More susceptible to voice. 8. 9. It is constant. does not depend on switching speed. It is treated as high input.

 The P-channel device is off and the n-channel device is on. State and verify DeMorgan’s Law.  The result is that the P-channel device is turned on and n-channel is turned off. (A + B)' = A'B' 9 . Draw the schematic and explain the operation of a CMOS inverter. They are. 8. [April/May-2012] (3) De Morgan suggested two theorems that form important part of Boolean algebra. (AB)' = A' + B' A 0 0 1 1 A‟B‟ 1 1 1 0 B 0 1 0 1 A‟+B‟ 1 1 1 0 2) The complement of a sum term is equal to the product of the complements.impedance path from output to sound.Vijayamangalam – 638 056 7.  Under these conditions.  the result is that the output approaches the low level of 0v. there is a low impedance path from VDD to the output and a very high. 1) The complement of a product is equal to the sum of the complements. [April/May-2011] (8)  When the input is low.  When the input is high both the gates are at VDD and the situation is reversed. the output voltage approaches the high level VDD under normal learning conditions.  Therefore. Also explain its characteristics. both gates are at zero potential.  The input is at VDD Relative to the source of the P-channel device and at 0v relative to the source of the n-channel device.

1. F using Quine Mcclusky Method.14.15) [April/May-2012.8. F= Σ(0.B‟ 1 0 0 0 9.10.2013] Step:1 Group 0 1 2 3 4 Minterm 0 1 2 8 10 11 15 Step:2 10 (5) (8) A 0 0 0 1 1 1 1 B 0 0 0 0 0 0 1 C 0 0 1 0 1 1 1 D 0 1 0 0 0 1 1 .2.11. Minimize the Function. Simplify the Boolean expression F=x′y′z′+x′yz+xy′z′+xyz′[April/May-2012] Given F=x′y′z′+x′yz+xy′z′+xyz′ =x′y′z′+x′yz+xz′(y′+y) =x′y′z′+x′yz+xz′ =x′yz+ z′(x′y′+x) = x′yz+z′(x′+x)(y′+x) F=x′yz+xz′+z′y′ 10.Vijayamangalam – 638 056 A 0 0 1 1 A‟+B‟ 1 0 0 0 B 0 1 1 1 A‟.

2.B.[April/May-2012] (4)  A product term containing all the variables of the function in either complemented or uncomplemented form is called a min term.5) 11 .4. Y=ABC+BD  A sum term containing all the variables of the function in either complemented or uncomplemented form is called a max term. Using Karnaugh map simplify the following expressions and implement using basic gates.4.3.7. [April/May-2012] (12) 1) F= Σ(1.3.5) Given F= Σ(1.D)=A′B′C′+B′D′+AC 11. Differentiate between Min Term and Max Term. F=AC′+A′C Given F= Σ(1.Vijayamangalam – 638 056 Step:3 Step:4 F(A.15)+d(0.C.7.6) 2) F= Σ(1. Y=(A+B+C)(B+D) 12.11.15)+d(0.

12 (8) (8) .D)= Σ( (i) Sum of product form.Vijayamangalam – 638 056 F=A′B′+CD 13. Simplify the Boolean function into[April/May-2013] (i) Sum of product form.2.5.10) Given F(A.B.B.C. F=A′B′C′+A′C′D+A′BC′+B′CD′ (ii) Product of sum form.8.1. (ii) Product of sum form.D)= Σ( F(A.

8. B. 7. 12. [Nov/Dec-2009] F(A. D) = Σm(0.D)= π(0. 6.12. 2.5) F=(X+Y+Z)(X+Y′+Z)(X′+Y+Z)(X′+Y+Z′) 15. 10.C.12.D)=D(A+C′) 16.7.Vijayamangalam – 638 056 F=(A′+B′)(C′+D′)(B′+D) 14. Reduce the following function using K-map technique.B.6) Given F(A.B.4.14)+d(2.D)= π(0.4.1) = Πm(0.10.4. C.8.10. 13 ) [Nov/Dec-2009] (16) 13 .7.C.3. 3.C.B. Simplify the following Boolean function by using a Quine-McCluskey method. 8. Express the Boolean function F=XY+X′Z in product of Maxterm.2.[Nov/Dec-2009] Given (6) F=XY+X′Z =XY(Z+Z′)+X′Z(X+X′) =XYZ+XYZ′+X′YZ+X′Y′Z = Σm(7.6.6) (10) F(A.14)+d(2. F (A.3.3.

Vijayamangalam – 638 056 Step:1 Step:2 Step:3 Step:4 14 .

z) = Σ( 2.2. Draw a NAND logic diagram that implements the complement of the following function.8.z) = Σ( 2.D)=ABC′+B′D′+A′C 17.11.y.12) [Nov/Dec-2010] (8) Given F (A.x. C.15) F(w. 13. C. D) = Σ(0.9. 3. B.1.12) F=A′B′+B′C′+C′D′ 15 .12. 3.Vijayamangalam – 638 056 F(A. Simplify the following Boolean function using 4-variable map F (w.11. 3.B. 10.x.4.8.C.1. 10. 13. F (A. 3.14.14.z)=wx+x′y 18.9.x.15) [Nov/Dec-2010] (8) Given F (w.4.y.12. D) = Σ(0. B.y.2.

When the base-emitter junction is forward biased with a voltage greater than 0.  We have assumed positive directions for the currents as indicated.  Collector and base currents are positive when they flow into the transistor. the transistor conducts and Ie starts rising very fast where a s VBE changes very little.  The current marked Ie flows through resistor Rc and the collector of the transistor. Draw and explain Tri-state TTL inverter circuit diagram and explain its operation. the transistor is said to be cut off and no base current flows. The circuit is a simple inverter with two resistors and a transistor. The input is between V. VB£ is the voltage drop across the base-to-emitter junction. Correspondingly.8V.Vijayamangalam – 638 056 19. as indicated by the arrow in the emitter terminal. and the output is between Vo and ground. and ground. shown in Fig.6 Y.   The base-emitter graphical characteristic is shown in Fig (b). Emitter current IE is positive when it flows out of the transistor. Which is a plot of VBE versus lB' If the base-emitter voltage is less than 0.The supply voltage is between Vee and ground.6 V. and its current 1£ = Ie + te. Current Is flows through resistor RB and the base of the transistor. This junction is forward biased when VB£ is positive and reverse biased when Vs£ is negative. 16 . [Nov/Dec-2014] (12)  The basic data needed in the analysis of digital circuits may be obtained by inspection of the typical characteristic curves of a common-emitter npn silicon transistor. The voltage VBE across a conducting transistor seldom exceeds 0.  The emitter is connected to ground. These are the directions in which the currents normally flow in an npn transistor.  The symbol Ve£ stands for the voltage drop from collector to emitter and is always positive.

[May/June-2012.encoder – parity checker – parity generators – code converters Magnitude Comparator. [April/May-2011] 4 What is an encoder?[May/June-2012] An encoder has 2n input lines and n output lines.Vijayamangalam – 638 056 UNIT-II COMBINATIONAL CIRCUITS Design procedure – Half adder – Full Adder – Half subtractor – Full subtractor – Parallel binary adder.  Time multiplexing systems  Frequency multiplexing systems.  Implement combinational logic circuit. 5 List few applications of multiplexer.[April/May-2010] 3 Design a single bit magnitude comparator to compare two words A and B. [April/May-2010] Difference=A′B+AB′=A⊕B Borrow=A′B 2 Draw the circuits diagram for 4-bit odd parity generator. 17 . PART-A 1 Write an expression for borrow and difference in a full subtractor circuit. In encoder the output lines generate the binary code corresponding to the input value. parallel binary Subtractor – Fast Adder .BCD adder – Binary Multiplier – Binary Divider .Multiplexer/ Demultiplexer – decoder .  D/A and A/D converter  Data acquisition systems. Nov/Dec-2013]  Data Selector.Carry Look Ahead adder – Serial Adder/Subtractor .

Vijayamangalam – 638 056 6 Design a half subtractor using basic gates.[May/June-2013. In priority encoder. Nov/Dec-2010] Difference=A′B+AB′=A⊕B Borrow=A′B 7 Draw the logic diagram of a 4 line to 1 line multiplexer. the input having the highest priority will take precedence. if 2 or more inputs are equal to 1 at the same time. 18 . [May/June-2013] 8 What is priority Encoder?[May/June-2014] A priority encoder is an encoder circuit that includes the priority function.

Demultiplexers v. Decoders 12 Draw the logic circuit of a 2-bit comparator.Vijayamangalam – 638 056 9 Write down the difference between demultiplexer and decoder. Encoders vi.2014] 19 .[April/May-2015. Adders ii.[April/May-2015] Definition Demultiplexer 1 data input 2^n outputs Decoder It has n inputs 2^n outputs It has n control inputs Characteristic Connects the data input to Selects one of the 2^n outputs by the data output decoding the binary value on the basis of n inputs Reverse of Multiplexer Encoder 10 Give the logic expression for sum and carry in full adder circuit. Multiplexers iv. Nov/Dec-2013] i.[April/May2015] Sum= (A⊕B)⊕Cin Carry=AB+BCin+A Cin 11 Give examples for combinational circuit. Subtractors iii.[April/May-2015.

Vijayamangalam – 638 056 13 Suggest a solution to overcome the limitation on the speed of an adder.C)= Σ (0. 14 Relate carry generate. the parallel adder is a purely combinational circuit 20 . Carry propagate.1. This method utilizes logic gates to look at the lower-order bits of the augend and addend to see if a higher-order carry is to be generated.[Nov/Dec-2010] 15 Realize the Boolean function using appropriate multiplexer F(A. Sum and Carry-out of a Carry look a head adder.[Nov/Dec2009] It is possible to increase speed of adder by eliminating inter-stage carry delay.7) [Nov/Dec-2010] 16 Compare the performance of binary serial and parallel adders.3.B.[Nov/Dec-2011]          Serial Adder: Serial adder uses shift registers The serial adder requires only one full adder circuit The serial adder is a sequential circuit Time required for addition depends on the number of bits It is slower parallel adder: Parallel adder uses registers with parallel load capacity It is faster Time required for addition does not depend on number of bits Excluding the registers.

Vijayamangalam – 638 056 17 Design of three bit parity generator.[Nov/Dec-2012] Odd parity generator: Even Parity generator: 18 Draw the logic diagram of serial adder.[Nov/Dec-2012] 21 .

The carry-lookahead system is obtained by unwinding the recurrence relation for ci+1: ci = gi−1 + ci−1 pi−1 = gi−1 + (gi−2 + ci−2pi−2) pi−1 = gi−1 + gi−2pi−1 + ci−2pi−2pi−1 .[April/May2010.Vijayamangalam – 638 056 19 Construct a two-4-bit parallel adder/subtractor using Full Adders and XOR gates.e.[Nov/Dec-2014] PART-B 1. Derive the equation for a 4-bit look ahead carry adder circuit. until we reach 22 . Although we will use the signal ti in practice.2010] Simplest Carry-Lookahead System Recall the following equations from the section on Adder Circuits: gi = xiyi pi = xi ⊕ yi ti = ai = xi + yi The transfer signal ti can be used in preference to pi since it is easier and quicker to generate.2014. i...2015. we shall use pi in the following since it makes the derivation easier to understand. Nov/Dec-2009. [Nov/Dec-2014] 20 Convert a two-to-four line decoder with enable input to 1X4 Demultiplexer. = gi−1 + gi−2pi−1 + gi−3pi−2pi−1 + gi−4pi−3pi−2pi−1 + ci−4pi−4pi−3pi−2pi−1 We could continue unrolling until the entire adder length is covered.

then the 2 levels of the CLA become 4 levels or more in order to preserve the fain-in of 4. t and sum signals. Fan-in much greater than 4 is impractical for single CMOS gates because of poor noise immunity. The carries C1. we stop at carry-lookahead blocks of size 4. poor rise and fall times. and 5. and therefore poor delay.4. Fortunately we don‟t need the carry-out signal c4. ti can be used in place of pi. but the fan-in of the gates grows linearly with the number of stages covered by them. C2. and there are OR gates with fan-ins of 2. Each lower block combines the ci signal with ti and gi to give the sum output. the delay through the carry-lookahead block will be just 2D. 23 . Each HEX digit can generate or propagate a carry G = g3 + g2p3 + g1p2p3 + g0p1p2p3 P = p3p2p1p0 These block propagate and generate signals can be combined in groups of four by using a second level CLA-4 block. but note that the AND gate in two of the equations has a fan-in of 4. in the following. and C3 can be expressed in SOP form as functions of C0 and the different (Pi) and (Gi) as follows: complete 4-bit CLA adder. zi = xi ⊕ yi ⊕ ci = pi ⊕ ci = giti ⊕ ci x1 y1 z1 t 1 g1 x0 y0 z0 t 0 g0 x2 y2 z2 t 2 g2 x3 y3 z3 t 3 g3 cin c0 = cin c1 c2 c3 cout = c4 CLA-4 If implemented strictly as implied. c4 = g3 + g2p3 + g1p2p3 + g0p1p2p3 + c0p0p1p2p3 c3 = g2 + g1p2 + g0p1p2 + c0p0p1p2 c2 = g1 + g0p1 + c0p0p1 c1 = g0 + c0p0 The carry propagate (Pi) and carry generate (Gi) variables are shown on the full adder logic circuit. We shall need two additional signals.3.Vijayamangalam – 638 056 cin. If CLA blocks larger than size 4 are needed. Recall. On the right of the drawing are the logic diagrams of the two blocks that generate the p. Think of these as the result of combining 4 neighboring bits of the adder into one HEX digit. For most implementations. the block propagate signal P and the block generate signal G.

Furthermore. and so on. carry is not one of the inputs being added. Notice that in the operation A1 + B1 + carry = S1. 24 . A3A2A1A0 and B3B2B1B0. [April/May-2010]      A and B are the two different digit which is added with carry Cin.Vijayamangalam – 638 056 2. namely. the inputs being added are A1 and B1. where the S figures represent the sum: A + B = S. Draw and explain the block diagram of a 4-bit serial adder to add the contents of two registers. we do A1 + B1 + carry = S1. the consequence of something that happened in the past. First. Carry is simply a given condition. the value of carry does not depend on the inputs A1 and B1. we do A0 + B0 = S0. and so on. A0 + B0. Second. we add two figures at a time starting with the least significant pair.

Multiply(1011)2 by (1101)2 using addition and shifting operation also draw the block diagram of the 4-bit by 4-bit parallel multiplier. 3. Then the shifted and added values are given to the next input as C1. This addition method is shifting and adding with the values. [April/May-2010] 2BINARY MULTIPLIER: Multiplication of binary numbers is performed in the same way as in decimal numbers – partial product: the multiplicand is multiplied by each bit of the multiplier starting from the least significant bit Multiplication of two bits = A * B (AND) 0*0=00*1=01*0=01*1=1 2-BIT BY 2-BIT BINARY MULTIPLIER: 25 .Vijayamangalam – 638 056   The sum is given by S and carry is given by c.

Vijayamangalam – 638 056 4-BIT BY 3-BIT BINARY MULTIPLIER: 1 0 1 1 1 1 0 1 1 0 1 1 0 0 0 1 0 1 1 1 0 1 1 10 0 0 1 1 11 26 .

 Since there are 10 different combinations of BCD.Vijayamangalam – 638 056 4. we need at least a 4-bit Gray Code to create sufficient number of these combinations. 27 .2015]  Binary Coded Decimal (BCD) is a way to store the decimal numbers in binary form. Design and implement the conversion circuits for binary code to gray code.2014. [April/May-2010. The number representation requires 4 bits to store every decimal digit (from 0 to 9).

In case of BCD theBINARY number 28 . Nov/Dec-2012] BCD or BINARYCoded Decimal is that number system or code which has theBINARY numbers or digits to represent a decimal number.2015. [April/May-2011] Sum= A⊕B⊕C Carry= A′B+B′C+C′A 6. A decimal number contains 10 digits (0-9).2013.2012. Now the equivalentBINARY numbers can be found out of these 10 decimal numbers. [April/May-2011.Vijayamangalam – 638 056 5. Design a full adder using two half adders and an OR gate. Explain the operation of a BCD adder.

will be the equivalent code for the given decimal digits. For 0 to 9 decimal numbers both binary and BCD is equal but when decimal number is more than one bit BCD differs from binary. which are the decimal equivalent from 0-9 respectively. Four bits from L. In BCD we can use the binary number from 0000-1001 only. It may be cleared from an example. Suppose if a number have single decimal digit then it‟s equivalent Binary Coded Decimal will be the respective four binary digits of that decimal number and if the number contains two decimal digits then it‟s equivalent BCD will be the respective eight binary of the given decimal number. Table given below shows the binary and BCD codes for the decimal numbers 0 to 15. From the table below.B is binary equivalent of 2 and next four is the binary equivalent of 1.S. Let. Decimal number BINARYnumber BINARYCoded Decimal(BCD) 0 0000 0000 1 0001 0001 2 0010 0010 3 0011 0011 4 0100 0100 29 . Four for the first decimal digit and next four for the second decimal digit. (12)10 be the decimal number whose equivalent Binary coded decimal will be 00010010.Vijayamangalam – 638 056 formed by fourBINARY digits. we can conclude that after 9 the decimal equivalent binary number is of four bit but in case of BCD it is an eight bit number. This is the main difference between Binary number and binary coded decimal.

30 . a) At first the given number are to be added using the rule ofBINARY. BCD is a numerical code which has several rules for addition. For example. The rules are given below in three steps with an example to make the idea of BCD Addition clear.Vijayamangalam – 638 056 5 0101 0101 6 0110 0110 7 0111 0111 8 1000 1000 9 1001 1001 10 1010 0001 0000 11 1011 0001 0001 12 1100 0001 0010 13 1101 0001 0011 14 1110 0001 0100 15 1111 0001 0101 BCD Addition Like other number system in BCD arithmetical operation may be required.

Draw the logic diagram of a 2-bit by 2-bit binary multiplier and explain its operation.e from 10 to 15 and again return to the BCD codes. As you can see the result is valid in BCD. which is not valid for BCD number. Here two cases are shown to describe the rules of BCD Addition.But in case 2 the result was already valid BCD. Now the idea of BCD Addition can be cleared from two more examples. Example:1 Let 0101 is added with 0110. Now a question may arrive that why 6 is being added to the addition result in case BCD Addition instead of any other numbers. which is greater than 9 so we have to add 6 or (0110)2 to it. 7. It is done to skip the six invalid states ofBINARY coded decimal i. which is valid for BCD numbers.(1111)2 + (0110)2 = 0001 0101 = 15. so there is no need to add 6. Then the resultant that we would get will be a validBINARY coded number.Nov/Dec-2010] 2-BIT BY 2-BIT BINARY MULTIPLIER: 31 . In case 1 the result of addition of twoBINARY number is greater than 9.Vijayamangalam – 638 056 b) In second step we have to judge the result of addition. This is how BCD Addition could be. c) If the four bit result of addition is greater than 9 and if a carry bit is present in the result then it is invalid and we have to add 6 whoseBINARY equivalent is (0110)2 to the result of addition. [April/May-2011. But the result of addition in case 2 is less than 9. In case 1 the result was (1111)2.

2015] F(A.2015.D)= Σ (1.4. Implement the following function using suitable multiplexer.12. 8. [April/May2011. so that the output follows the table 1.14. Design a 4-bit word comparator. [April/May-2011. Nov/Dec-2011.C.Vijayamangalam – 638 056 2BINARY MULTIPLIER: Multiplication of binary numbers is performed in the same way as in decimal numbers – partial product: the multiplicand is multiplied by each bit of the multiplier starting from the least significant bit.15) 9.13.2013.2013] Table 1 Word Output A=B 100 A>B 010 A<B 001 32 .3.B.11.

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10. Design a 3:8 decoder using basic gates. [April/May-2014, Nov/Dec-2011]

11. Design a full subtractor using demultiplexer. [April/May-2014,Nov/Dec-2009]

12. Implement the given Boolean function using 8:1 multiplexer
F(A,B,C)= Σ (1,3,5,6)


VIL (max) required for a LOW input is called Low-state noise margin.[Nov/Dec-2011] 37 . VOL (max) and the maximum voltage.  The voltage difference between the largest possible LOW output. VIH (min) required for a HIGH input is called High-state noise margin. Fan-out and Noise margin. For example: 2 input NOR has Fan-in of 2. the fan-out of the inverter is 10. VOH (min) and the minimum input voltage. For example: If an inverters output can drive maximum 10 inputs of any logic gates from same family. Fan-out of a gate It is the maximum number of inputs of the same family that the gate can drive maintaining its output levels within the specified limits. Fan-in of a gate Fan-in of a gate is said to be the number of inputs in a digital logic gate. The voltage difference between the lowest possible HIGH output. Define Fan-in.Vijayamangalam – 638 056 13. 14.  The noise margin allows the digital circuit to function properly if noise voltages are within the noise margin. Design 4:1 Encoder using basic gates.[Nov/Dec-2010] Noise Margin.

2) It is not-sensitive to Glitches.  Decades. D. Edge Triggering: 1) The input signal is sampled at the RISING EDGE or FALLING EDGE of the clock signal.Nov/Dec-2010.Universal shift registers – Shift register counters – Ring counter – Shift counters . 2. input change can cause output change as soon as logic is done – a big problem when two machines are interconnected asynchronous feedback.2011] 1)Mealy Machines tend to have less states a) Different outputs on arcs (n^2) rather than states (n). PART-A 1. [April/May-2011. [April/May2011.  Street light controller. [April/May-2010]  A counter that divides an input frequency by a number which can be programmed into de cades of synchronous down counters. Registers – shift registers .SR. b) In Mealy machines. Example: Latch. What is meant by programmable counter? Mention its application. 2) It is sensitive to Glitches. 3) Mealy Machines react faster to inputs b) React in same cycle – don't need to wait for clock.Vijayamangalam – 638 056 UNIT-III SEQUENTIAL CIRCUITS Latches. Nov/Dec-2009] The characteristic equation of a JK flip-flop is given by Q(next) = JQ' + K'Q 4. 3. Flip-flops . where N can be made equal to any number. 2) Moore Machines are safer to use a) Outputs change at clock edge (always one cycle later). Write the characteristic equation of a JK flip-flop. give the equivalent of a divide-by N counter system. Mention any two differences between the edge triggering and level triggering. [April/May-2010] Level Triggering: 1) The input signal is sampled when the clock signal is either HIGH or LOW. Example: Flipflop. Appication:  Microprocessor. c) In Moore machines.Sequence generators. more logic may be necessary to decode state into outputs – more gate delays after. 38 . T.Asynchronous Ripple or serial counter Asynchronous Up/Down counter .Synchronous counters – Synchronous Up/Down counters – Programmable counters – Design of Synchronous counters: state diagram.State table – State minimization –State assignment – Excitation table and maps-Circuit implementation Modulo–n counter.  Traffic light controller. State the differences between Moore and mealy state machine. JK. with additional decoding and control logic. and Master-Slave – Characteristic table and equation – Application table – Edge triggering – Level Triggering – Realization of one flip flop using other flip flops – serial adder/subtractor.

2012] 7. then 2n-1=1023 n=10 since 210=1024 8. 3. Realise T-FF from JK-FF. 2. 39 . [April/May-2014. Convert JK flip-flop to T flip-flop.Vijayamangalam – 638 056 5. [April/May-2012] 6. Design involves complex logic circuit as number of states increases. [April/May-2013. Nov/Dec-2009] Asynchronous counter: 1. Compare the logics of synchronous counter and ripple counter. 3. All the flip-flop are clocked simultaneously. synchronous counter: 1. In this type of counter flipflop are connected in such a way that output of first flip-flop drives the clock for next flip-flop. 2. All the flip-flop are not clocked simultaneously. Logic circuit is very simple even for more number of states. In this type there is no connection between output of first flip-flop and clock input of the next flip-flop. How many flip-flops are required to build a binary counter that counts from 0 to 1023? [April/May-2013] If the number of flip-flops required is n.

the race around condition occurs.Vijayamangalam – 638 056 4. If it toggles even number of times the output is same but if it toggles odd number of times then the output is complimented. Sketch the logic diagram of a clocked SR flip-flop. [Nov/Dec-2011] 40 . Realize JK flip-flop using D flip-flop.e it occurs when the time period of the clock pulse is greater than the propagation delay of the flip flop. 9. 13. Positive or negative edge triggering 11.  the output changes or toggles in a single clock period. To avoid race around condition we cant make the clock pulse smaller than the propagation delay so we use 1. What is the output frequency of its third Flip flop? [Nov/Dec-2011] The output frequency of third flip-flop is: ½3=1/8KHz. [Nov/Dec-2010] 12. Draw the state table and excitation table of T flip-flop. How do you eliminate the race around condition in a JK flip-flop?[Nov/Dec2010]  When the input to the JK flip-flop is j=1 and k=1. i. Master slave JK flip flop 2. [April/May-2014] 10. A 4-bit binary ripple counter is operated with clock frequency of 1KHz.

Nov/Dec-2013] 41 . which permits a single bit to be stored. [Nov/Dec2012] 15. Design a 3-bit ring counter and find the mod of the designed counter.Vijayamangalam – 638 056 14. First. Define latches. which consists of a pair of logic gates with their inputs and outputs inter connected in a feedback arrangement. [Nov/Dec-2013] A digital clock is a simplified logic diagram of a digital clock that displays seconds. Write short notes on Digital Clock. minutes. [Nov/Dec-2013] Latch is a simple memory element. PART-B 1. 16. Construct a clocked JK flip-flop which is triggered at the positive edge of the clock pulse from a clocked SR flip-flop consisting of NOR gates. a 60 Hz sinusoidal ac voltage is converted to a 60 Hz pulse waveform and divided own to a 1Hz pulse waveform by a divide-by-60 counter formed by a divide-by-10 counter allowed by a divide-by-6 counter. and hours.[April/May-2010. Both the seconds and minutes counts are also produced by divide-by-60 counters.

Whereas the register that is capable of transferring data in both left and right direction is called a „bidirectional shift register. [April/May-2010] 3. Write down the characteristic table for the JK flip-flop with NOR gates. [April/May-2011] A unidirectional shift register is a register that can capable of transferring data in only one direction. It has both serial and parallel input and output capability.Vijayamangalam – 638 056 2.‟ 4-Bit Bidirectional Universal Shift Registers (74HC194): The 74HC194 is a universal bi-directional shift register. along with the necessary input and output terminals for parallel transfer. then it is called a shift register with parallel load or „universal shift register. Operating Mode S1 S0 Locked 0 0 Shift-Right 0 1 Shift-Left 1 0 Parallel Loading 1 1 42 . What is meant by universal counter? Explain the principles of operation of 4-bit universal shift register.‟ Now let we have a register which can capable to transfer data in both the shift-right and shift-left.

from a digital system perspective when we say computer memory we mean registers. on a particular job a universal register can load data in series (e. division. it must first select the mode. the universal shift register can combine the capabilities of both parallel and shift registers to accomplish tasks that neither basic type of register can perform on its own. Like a parallel register it can load and transmit data in parallel. Although other types of memory devices are used for the efficient storage of very large volume of data. each permutation of the switches corresponds to a loading/input mode. In order for the universal shift register to operate in a specific mode.Vijayamangalam – 638 056     A universal shift register is an integrated logic circuit that can transfer data in three different modes. S1 and S0. In fact. Examples of such operations include multiplication. To accomplish mode selection the universal register uses a set of two selector switches. as all other types of registers. through a sequence of left shifts) and then transmit/output data in parallel. and data transfer. are used in computers as memory elements.g. through left shifts or right shifts. In addition. As shown in Table 1. For instance. Universal shift registers. all the operations in a digital system are performed on registers. Like shift registers it can load and transmit data in serial fashions. 43 .

lowest to highest. one per clock cycle. The carry-in signal is the previously calculated carry-out signal.Vijayamangalam – 638 056 4. [April/May-2011]  The serial binary adder or bit-serial adder is a digital circuit that performs binary addition bit by bit. The serial full adder has three single-bit inputs for the numbers to be added and the carry in.  It has X and Y two digits binary values.  If speed is not of great importance. [April/May-2011] 5. It produces sum and Cout as output. a cost-effective option is to use a serial adder  Serial adder: bits are added a pair at a time (in one clock cycle) A=an-1an-2…a0. 44 . Design serial binary adder.  The addition is performed by adding each bit. Convert D flip-flop to T flip-flop. A two bit serial binary adder is shown in figure.  There are two single-bit outputs for the sum and carry out. B=bn-1bn-2…b0 In serial binary adder shifting and adding is the main operation for adding two binary numbers.

•The count starts with binary 0 and increments by one with each count pulse input •After the count 15 the counter goes back to binary 0 to repeat the count For positive edge triggered flip-flops the counter count down: • e. – Ripple counter is asynchronous – Binary ripple (up) counter – Binary ripple down counter BCD Ripple Counter • Verify the following circuit is a BCD Ripple counter triggered by negative edge.g start from15 to 14 to 13 to…….Vijayamangalam – 638 056 6. So. Explain the operation of a BCD ripple counter with JK flip-flops. Consist of a series of connection of negative edge triggering complementing flip-flops with the output of each flip-flop connected to the C input of the next high order flip flop. • The diagram is same as the count up binary counter except that the flip-flop trigger on the positive edge of the clock. • Ripple counter: the CP of some flip-flops are from other flip-flops. the complement will go from 1 to o and complement the next flip flop as required.Nov/Dec-2009] Synchronous counter: The CP signals of all flipflops are from the common clock. The flip flop holding the LSB receives the input pulses. • If negative edge triggered flip-flops are used then the C input of each flip-flop must be connected to the complement output of the previous flip-flop. [April/May2011. 45 .2012. when the true output goes from 0 to 1.April/May-2013.

a ring counter results. The most generally useful pattern is a single 1. All 0„s or all 1„s doesn‟t count. 46 . We make provisions for loading data into the parallel-in/ serial-out shift register configured as a ring counter below. Any random pattern may be loaded. the data pattern will repeat every four clock pulses in the figure below. we must load a data pattern. Both outputs Q A and Q D are now equal to logic "1" and the output from the NAND gate changes state from logic "1" to a logic "0" level when the clock goes to level one and whose output is also connected to the CLEAR (CLR) inputs of all the J-K Flip-flops. 7. [April/May-2012] If the output of a shift register is fed back to the input. For example. However. The data pattern contained within the shift register will recirculate as long as clock pulses are applied.Vijayamangalam – 638 056 This counter counts upwards on each negative edge of the input clock signal starting from "0000" until it reaches an output "1001“. Explain the operation of shift and ring counters.

shows a frequency ratio of 4:1. initialization should never be required again. destroying the data pattern. above. like a conventional synchronous BINARY counter would be more reliable. The circuit above is a divide by 4 counter. 47 . repeating every fourth clock pulse. The requirement for initialization is a disadvantage of the ring counter over a conventional counter. In theory. The data pattern for a single stage repeats every four clock pulses in our 4-stage example.Vijayamangalam – 638 056 LoadingBINARY 1000 into the ring counter. prior to shifting yields a viewable pattern. The waveforms for all four stages look the same. the flip-flops could eventually be corrupted by noise. An alternate method of initializing the ring counter to 1000 is shown above. Comparing the clock input to any one of the outputs. At a minimum. A “self correcting” counter. How may stages would we need for a divide by 10 ring counter? Ten stages would recirculate the 1 every 10 clock pulses. except for the one clock time delay from one stage to the next. See figure below. In actual practice. it must be initialized at power-up since there is no way to predict what state flip-flops will power up in. The shift waveforms are identical to those above.

if most of the logic is in a single shift register package. The waveforms decoded from the synchronous binary counter are identical to the previous ring counter waveforms. Draw the Schematic diagram of up/down counter and explain its operations.Vijayamangalam – 638 056 The above BINARY synchronous counter needs only two stages. the ring counter looks attractive. The ring counter had more stages. If not. 48 . in particular. but was self decoding. 8. The counter sequence is (QA QB) = (00 01 10 11). saving the decode gates above. Similar to an asynchronous up-down counter. If we need the decoded outputs. a synchronous up-down counter also has an updown control input. Another disadvantage of the ring counter is that it is not “self starting”. but requires decoder gates. It is used to control the direction of the counter through a certain sequence. [April/May-2013] A circuit of a 3-bit synchronous up-down counter and a table of its sequence. the conventional BINARY counter is less complex without the decoder.

Q2 changes state on the next clock pulse when Q0=Q1=0 49 . • for the UP sequence. • for the DOWN sequence. Q2 changes state on the next clock pulse when Q0=Q1=1. Q0 toggles on each clock pulse. • for the DOWN sequence. • for the UP sequence. Q1 changes state on the next clock pulse when Q0=0.Vijayamangalam – 638 056 An examination of the sequence table shows: • for both the UP and DOWN sequences. Q1 changes state on the next clock pulse when Q0=1.

Limitations: 1.  When an input (or address) is presented. Compare Dynamic RAM with Static RAM.  Dynamic Ram is used in system RAM.Vijayamangalam – 638 056 UNIT-IV MEMORY DEVICES PART-A 1. 2. [April/May-2010] The memory expansion can be achieved in two ways: by expanding word size and expanding memory capacity. 50 .  Static Ram contains Transistors. 3.  Static Ram is used in L1 and L2 cache.  Each data output represents the correct value for its logic function 5. 2. Dynamic Ram  It consumes less power.  Data outputs are the logic functions and the address lines are the logic function inputs.  Cost is low. Implement the exclusive or function using ROM. [April/May-2011]  Can implement multi-input/multi-output logic functions inside of ROM. [April/May-2012]  Static Ram is very costly.  We create a ROM Table to store the logic functions. What are the advantages of static RAM and Dynamic Ram? [April/May2010. 24 address lines and 16 data lines.  Dynamic Ram is cheaper. Nov/Dec2010] PLA:  Both AND and OR arrays are programmable and Complex  Costlier than PAL PAL:  AND arrays are programmable OR arrays are fixed  Cheaper and Simpler 4.Nov/Dec-2009] Static RAM:  Access time is less.  Dynamic Ram contains Capacitors. Memory capacity upto 16Mbytes. the value stored in the specified memory location appears at the data outputs.  Fast operation. What is meant by memory Expansion? Mention its limit. 2013. What is difference between PAL and PLA? [April/May-2011.

51 .  simple. Draw the structure of a static RAM cell. Nov/Dec-2010]  low and fixed (two gate) propagation delays (typically down to 5 ns). Mention few applications of PLA and PAL. 10. What is PAL? [Nov/Dec-2009] PAL is programmable array logic. [April/May-2014] 9.Vijayamangalam – 638 056 6. List the advantages of PLDs. [April/May-2012]  Implement combinational circuits  Implement sequential circuits  Code converters  Microprocessor based systems 7. What are the different types of programmable logic devices? [April/May-2013]  PROM  PLA  PAL  GAL 8.  design tools. [April/May-2014. What is access time and cycle time of a memory? [Nov/Dec-2010] Access time is the maximum specified time within which a valid new data is put on the data bus after an address is applied. 11.  low-cost (free). PAL consists of a programmable AND array and a fixed OR array with output logic. Cycle time is the minimum time for which an address must be held stable on the address bus in read cycle.

[Nov/Dec-2010] 13. Draw the logic diagram of a static RAM cell and Bipolar cell. Implement a 2-bit multiplier using ROM.Vijayamangalam – 638 056 12. How the memories are classified? It is classified into two types:  volatile  non-volatile memory 14. [Nov/Dec-2012] 52 .

PART-B 1. Give the advantages of RAM. CMOS SRAM Cell  A low power SRAM cell may be designed by using cross-coupled CMOS inverters. without any need for periodic refresh operation. essentially. [April/May-2010]  SRAM Basics The memory circuit is said to be static if the stored data can be retained indefinitely. i. Explain the principle of operation of bipolar SRAM cell. we need atleast one switch.  The data storage cell. it is limited by small leakage current. The memory which can hold the data when power is turned off is known as nonvolatile memory 16. the data being held in the memory cell will be interpreted either as logic '0' or as logic '1'. invariably consists of a simple latch circuit with two stable operating points. The most important advantage of this circuit topology is that the static power dissipation is very small.e. which is controlled by the corresponding word line.. as long as the power supply is on.  Higher speed. 53 .Vijayamangalam – 638 056 15.  To access the data contained in the memory cell via a bit line. the one-bit memory cell in the static RAM arrays. [Nov/Dec-2013]  Read and write the data. What is volatile and non-volatile memory? [Nov/Dec-2013] The memory which cannot hold the data when power is turned off is known as volatile memory.  Depending on the preserved state of the two inverter latch circuit.  Data is accessed by using address of the memory location.

[April/May-2010]  Static memory is the most widely used method of configuring FPGAs. Thus internal node voltages are V1 = 0 and V2 = VDD before the cell access transistors are turned on.6 they don‟t use the same circuits as are used in commodity SRAMs).  The memory cell consists of simple CMOS inverters connected back to back. In this section we will look at the elements of an FPGA: logic. interconnect. and two access transistors. while M2 and M5 are operating in the linear mode. SRAM-based FPGAs are the generally accepted choice for system prototyping.  Thus the internal node voltage V1 = VDD and V2 = 0 before the access transistors are turned on. 2. we expect the nodal voltage V2 to remain below the threshold voltage of M1.  The transistors M2 and M5 are turned off. Write a note on SRAM based FPGA. and the ability to operate at lower power supply voltage. 54 . The transistors M1 and M6 are turned off.Vijayamangalam – 638 056  Other advantages of this design are high noise immunity due to larger noise margins.  In doing so we will consider both general principles and specific commercial FPGAs. Once M3 and M4 are turned on. The column voltage Vb is forced to '0' by the write circuitry. assuming that logic '0' is stored in the cell.  SRAM-based FPGAs hold their configurations in static memory (though as we will see in Section 3.  Using static memory has several advantages: • The FPGA can be easily reprogrammed.  The output of the memory cell is directly connected to another circuit and the state of the memory cell continuously controls the circuit being configured.  The voltage levels in the CMOS SRAM cell at the beginning of the data write operation. and I/O. The access transistors are turned on whenever a word line is activated for read or write operation. Because the chips can be reused. and generally reprogrammed without removing them from the circuit. connecting the cell to the complementary bit line columns. WRITE Operation:  Consider the write '0' operation assuming that logic '1' is stored in the SRAM cell initially. while the transistors M1 and M6 operate in linear mode. The major disadvantage of this topology is larger cell size. READ Operation:  Consider a data read operation.

SRAM-based FPGAs also have some disadvantages: • The SRAM configuration memory burns a noticeable amount of power. [April/May-2011] 3. 3. The circuit accepts a 3-bit number and generates an output binary number equal to the square of the input number. 55 . [April/May-2011]  An EEPROM or EPROM transistor is used as a programmable switch for CPLDs (and also for many SPLDs) by placing the transistor between two wires in a way that facilitates implementation of wired-AND functions.  This is illustrated in Figure 4. needs to be refreshed. although more dense. which shows EPROM transistors as they might be connected in an AND-plane of a CPLD. which would make the configuration circuitry much more cumbersome. • Dynamic RAM. even when the program is not changed. A large number of bits must be set in order to program an FPGA. if that input is part of the corresponding product term. Design a combinational circuit using a ROM. Briefly explain the EPROM and EEPROM technology.  An input to the AND-plane can drive a product wire to logic level „0‟ through an EPROM transistor. Although there is no technical reason why EPROM or EEPROM could not be applied to FPGAs. • The bits in the SRAM configuration are susceptible to theft. • The circuits used in the FPGA can be fabricated with standard VLSI processes. providing dynamically reconfigurable systems. current commercial FPGA products are based either on SRAM or anti-fuse technologies.  A diagram for an EEPROM based device would look similar. For inputs that are not involved for a product term. the appropriate EPROM transistors are programmed to be permanently turned off. Each combinational logic element requires many programming bits and each programmable interconnection point requires its own bit.Vijayamangalam – 638 056 • The FPGA can be reprogrammed during system operation. as discussed below.

 The figures gives an example of the connection of one logic block (represented by the AND-gate in the upper left corner) to another through two pass-transistor switches. all controlled by SRAM cells. showing two applications of SRAM cells: for controlling the gate nodes of pass-transistor switches and to control the select lines of multiplexers that drive logic block inputs. and then a multiplexer.  Whether an FPGA uses pass-transistors or multiplexers or both depends on the particular product..Vijayamangalam – 638 056  An example of usage of SRAM-controlled switches is illustrated in Figure 5. known as PLICE [Ham88].  Antifuses are suitable for FPGAs because they can be built using modified CMOS technology. The figure shows that an antifuse is positioned between two interconnect wires and physically consists of three sandwiched layers: 56 . Antifuses are originally open-circuits and take on low resistance only when programmed. Actel‟s antifuse structure. As an example. The other type of programmable switch used in FPGAs is the antifuse.

 The technology that preceded EPROM did not allow the data to be changed. registers. Essentially. once bugs are found they can erase the EPROM then load a modified version for further testing. the insulator isolates the top and bottom layers. EPROMS allow them to fully deploy their program on the chip then test it. However this style is often a viable approach for low production volumes. but when programmed the insulator changes to become a low-resistance link.  A standard cell library is sometimes called a "macrocell library". and the like. 57 .  These problems led to the development of a version of EPROM that is much easier to use. [April/May-2012]  A macrocell array is an approach to the design and manufacture of ASICs. These logic functions are simply placed at regular predefined positions and manufactured on a wafer.  EPROM (Erasable Programmable Read Only Memory) was a great invention that allowed hardware programmers to make changes to their code without buying new chips. usually called master slice.  Erasure of data is done by exposing the little window on its top side to ultraviolet light. Creation of a circuit with a specified function is accomplished by adding metal interconnects to the chips on the master slice late in the manufacturing process.  Although EPROM was a great advancement in technology. but rather than being a prefabricated array of simple logic gates. With the logic diagram explain the basic macrocell. the macrocell array is a prefabricated array of higher-level logic functions such as flip-flops.  Each section of an SPLD is called a macrocell. the erasure method still left some people wanting more. allowing the function of the chip to be customised as desired.  Exposing the window to light for a period of time meant that you would have to remove the chip and it would not be usable until the data is fully erased. The fabrication according to the individual customer specifications may be finished in a shorter time compared with standard cell or full custom design. 4. The macrocell array approach reduces themask costs since fewer custom masks need to be produced. and the middle layer is an insulator. A macrocell is a circuit that contains a sum-ofproducts combinational logic function and an optional flip-flop.  Drawbacks are somewhat low density and performance than other approaches to ASIC design. There is also no possibility of having the data replaced by the end user.Vijayamangalam – 638 056  The top and bottom layers are conductors. In addition manufacturing test tooling lead time and costs are reduced since the same test fixtures may be used for all macrocell array products manufactured on the same die size. When unprogrammed. it is a small step up from the otherwise similargate array. ALU functions.  Macrocell array master slices are usually prefabricated and stockpiled in large quantities regardless of customer orders.

Discuss the classification of memories.2012.2015] Random Access Memory (RAM) Read Only Memory (ROM) Random Access Memory (RAM)  Can be written to or read from.  Access time to read from any memory location is the same.  As compared to serial access memory.2013.  Static Random Access Memory (SRAM)  Based on the Flip-Flop  Requires a large number of transistors  Fast  Dynamic Random Access Memory (DRAM)  Uses a single transistor to store charge  Requires very few transistors  Must be periodically refreshed  Slow(er) 58 . [April/May-. Design 32X8 ROM.  Read/Write memory  Reading from RAM is non-destructive.Vijayamangalam – 638 056 5. [April/May-2013] 6.  Volatile  Information is lost when power is removed.

Memory is written (or “programmed”) once Reading from ROM is non-destructive. Programmable Read Only Memory (PROM)  Can be “programmed” Erasable PROM (EPROM)  Can be “programmed” and erased Electrically Erasable PROM (EEPROM)  Can be erased using an electrical signal UV Erasable PROM (UVEPROM) Can be erased using Ultraviolet light Address  Location in memory of the binary information  Must be decoded to select the appropriate location and read/write the associated data  k-bit address → 2k memory locations Data  Binary information of interest  Stored in a specific location in the memory  Typically organized into words  Each word has n bits  Read  Indicates that the memory is to be read  Write Indicates that the memory is to be written 59 . Non-Volatile  Information is retained even after power is removed.  As compared to serial access memory.Vijayamangalam – 638 056            Read Only Memory (ROM) Can only be read from. Access time to read from any memory location is the same.

2015] 60 .Vijayamangalam – 638 056  Rather than use the Read and Write signals. most commercially available RAM chips use Enable and Read/Write'  Enable  Used to enable the selected RAM chip  Aka. Discuss in detail about the FPGA with suitable diagrams. [April/May-2013. “chip select”  Read/Write'  RAM is read when Read/Write' = 1  RAM is written when Read/Write' = 0 7.

Number of segments used for interconnection typically is a trade-offs between density of logic blocks used and amount of area used up for routing. Density of logic block used in an FPGA depends on length and number of wire segments used for routing. FPGA provides its user a way to configure: 1. Routing in FPGAs consists of wire segments of varying lengths which can be interconnected via electrically programmable switches. combinational gates like basic NAND gates or XOR gates 3. Logic blocks of an FPGA can be implemented by any of the following: 1. Wide fan-in And-OR structure. Logic block of an FPGA can be configured in such a way that it can provide functionality as simple as that of transistor or as complex as that of a microprocessor. The intersection between the logic blocks and 2. Transistor pairs 2. Multiplexers 5. 61 . which gives it a more compact design compared to an implementation with two-level AND-OR logic. The function of each logic block. n-input Lookup tables 4. It can used to implement different combinations of combinational and sequential logic functions.Vijayamangalam – 638 056 In an FPGA logic blocks are implemented using multiple level low fan-in gates.

2012] 2. next state and output. 6. What is state table? [April/May-2012] The state table representation of a sequential circuit consists of three sections labelled present state. [April/May-2010. 62 . Draw the block diagram for Moore model. Nov/Dec-2009] The unwanted switching transients (glitches) that may appear at the output of a circuit are called Hazards. What are hazard free digital circuits? [April/May-2010] A circuit which has no hazard like static-0-hazard and static-1-hazard is called hazard free digital circuit. What are Hazards? [April/May-2013. What are the basic building blocks of a algorithmic state machine chart? [April/May-2011] 4. 3. What are the two types of asynchronous sequential circuits? [April/May-2011]  Fundamental mode circuit  Pulse mode circuit 5.Vijayamangalam – 638 056 UNIT-V SYNCHRONOUS AND ASYNCHRONOUS SEQUENTIAL CIRCUITS PART-A 1. and the output section lists the value of the output variables during the present state. The next state shows the states of flip-flops after the clock pulse. The present state designates the state of flip-flops before the occurrence of a clock pulse.

input c .c . C <= A and B. while at other times this is a reasonable abstraction. Under what circumstances asynchronous circuits are prepared. assign diff = a ^ b ^ c. output diff . -Architecture Architecture struct of HALFADD is begin S <= A xor B. Write the VHDL code for a half adder. sometimes. 9. input b .C : out bit ). Nov/Dec2009]  A conventional flow chart describes the square of procedural steps and decision paths for an algorithm without concern for their time relationship. Many forms of state diagrams exist. 10. [Nov/Dec-2011] (i) Fundamental mode asynchronous circuits (ii) Pulse mode asynchronous circuits 12. assign borrow = ((~a) & b) | (b & c) | (c & (~a)). this is indeed the case.borrow ). 8. S. end struct. [Nov/Dec-2010] module full_subtractor ( a .B : in bit. What is a state diagram? Give an example. [April/May-2014] HALF ADDER – Entity entity HALFADD is port ( A.Vijayamangalam – 638 056 7. [April/May-2013. 63 . (i)Memory elements are clocked flip-flops (i) Memory elements are either unlocked flip flops or time delay elements. State diagrams require that the system described is composed of a finite number of states. Differentiate fundamental mode and pulse mode asynchronous sequential circuits. [Nov/Dec-2012] Fundamental mode sequential circuits Pulse mode sequential circuits.  The ASM chart describes the sequence of event as well as timing relationship between the states of a sequential controller and the events that occur while going from one state to the next.b . output borrow . input a . Write a verilog model of a full subtractor circuit. [April/May-2014] A state diagram is a type of diagram used in computer science and related fields to describe the behaviour of systems. endmodule 11. end HALFADD. Distinguish between a flowchart and an ASM chart.diff . which differ slightly and have different semantics.

[Nov/Dec-2013] The unwanted switching transients (glitches) that may appear at the output of a circuit are called Hazards. input a . Design a 3 input AND gate using verilog. [Nov/Dec-2012] module and ( a . What is synchronous sequential circuit? [Nov/Dec-2013]  In synchronous circuits the input are pulses (or levels and pulses) with certain restrictions on pulse width and circuit propagation delay.  Static-0-Hazard  Static-1-Hazard PART-B 1.2013]  Unwanted switching appears at the output of a circuit „  Due to different propagation delay in different paths „  May cause the circuit to mal-function „  Cause temporary false-output values in combinational circuits „  Cause a transition to a wrong state in asynchronous circuits „  Not a concern to synchronous sequential circuits „  Three types of hazards: 64 .b . Therefore synchronous circuits can be divided into clockedsequential circuits and uncklocked or pulsed sequential circuits. to synchronize all internal changes of state 15. output diff .  In a clocked sequential circuit which has flip-flops or.2012. gated latches. assign f = a &b & c. Write short notes on Hazards. for its memory elements there is a (synchronizing) periodic clock connected to the clock inputs of all the memory elements of the circuit.2011. in some instances.Vijayamangalam – 638 056 (ii)Easier to design (ii)More difficult to design 13.f). input c . Nov/Dec-2012. What are called as essential hazards? How does the hazard occur in sequential circuits? How can the same be eliminated using SR latches? Give an example. input b . endmodule 14. [April/May-2010.c .

2013] Hazard-Free Circuit „  Hazard can be detected by inspecting the map „  The change of input results in a change of covered product term-> Hazard exists „ Ex: 111-> 101 in (a) „  To eliminate the hazard. enclose the two minterms in another product term „ Results in redundant gates 65 . use complemented inputs  S‟ = (AB + CD)‟ = (AB)‟(CD)‟ „ R‟ = (A‟C)‟ „ Q = (Q‟S)‟ = [Q‟(AB)‟(CD)‟]‟ >Two-level circuits 2.2012.Vijayamangalam – 638 056 Circuits with Hazards „     Static hazard: a momentary output change when no output change should occur „ If implemented in sum of products: „ no static 1-hazard-> no static 0-hazard or dynamic hazard „ Two examples for static 1-hazard: Implementation with SR Latches  Given: S = AB + CD R = A‟C „  For NAND latch. Write short notes on Hazard free switching circuits. [April/May-2010.

With an example. and etc and output the results. shift register. explain the use of algorithmic state machines.  Partition of digital system Data processor is a hardware required for data manipulation that may consist of adder. [April/May2012.2013]  Algorithmic State Machine An approach of digital design is to partition the system into a controller and a controlled architecture also called data processor.Vijayamangalam – 638 056 Remove Hazard with Latches:  Implement the asynchronous circuit with SR latches can also remove static hazards „ A momentary 0 has no effects to the S and R inputs of a NOR latch „  A momentary 1 has no effects to the S and R inputs of a NAND latch 3. subtractor. 66 .

 The controller. the decision box. It is called ASM because it consists of well defined finite number of step to the solution of a process. whilst state output function block is similar to that of a Moore machine. The input data is used in the manipulation.  Algorithmic State Machine . 67 .  Algorithmic State Machine Chart The algorithmic state machine SM chart can be divided into three blocks namely the state box.148 . Conditional output function block is similar to that of a Mealy machine. and the conditional output box.  Next state and memory blocks are similar for both Mealy and Moore machines.Vijayamangalam – 638 056  In addition to this function.  The external input is used to provide the task required to be carried out by the controller. The machine is viewed as the combination of Mealy and Moore machines. the data processor also provides status of the data manipulation to the controller.The model of algorithmic state machine. provides sequence of command to data processor. which is also termed as ASM.

Vijayamangalam – 638 056  The state box contains an output list.  The conditional output box contains conditional output list. The decision box is a usual diamond shaped symbol with true and false evaluate to decide the branches. The conditional outputs depend on both the state of system and the inputs. state name. and optional state code. 68 .

and at the end of state time the machine goes to the next state via exit path 1. [April/May-2013. the output Y5 is “1” and exit to the next state will occur via exit path  If X1 = “1” and X3 = “1”. Y3 and Y4 are also “1”.  If inputs X1 = “0” and X2 = “1”.Vijayamangalam – 638 056  When state S1 entered.  On the other hand. the exit to the next state will occur via path 4. the exit to next state is via path. if X1 = “1” and X3 = “0”. output Y1 and Y2 become “1”. Design a full adder using two half adders by writing Verilog program. If inputs X1 and X2 are both equal to 0. 4.2015] 69 . Y3 and Y4 are “1”.

[April/May-2015]  An algorithmic state machine (ASM) is a Finite State Machine that uses a sequential circuit (the Controller) to coordinates a series of operations among other functional units such as counters.out_sum(w_sum1). to the Data path.  The series of operations implement an algorithm. adders etc. output sum_out. carry_out). .in_y(carry_in).  Both the Controller and the Data path may each have external inputs and outputs and are clocked simultaneously as shown in the following figure: 70 . input carry_in. wire w_sum1.out_carry(w_carry2) ). registers. sum_out.out_carry(w_carry1) ). . Derive the ASM chart for binary multiplier.in_x(w_sum1).in_y(in_y). input in_y. wire w_carry2. . half_adder u2_half_adder ( .Vijayamangalam – 638 056 // Full Adder rtl module full_adder (in_x.out_sum(sum_out). assign carry_out = w_carry1 | w_carry2 half_adder u1_half_adder ( . in_y. . wire w_carry1. carry_in. endmodule 5. output carry_out. (the Data path). . . input in_x.in_x(in_x). The Controller passes “control” signals which can be Moore or Mealy outputs from the Controller.  The Data path returns information to the Controller in the form of “status” information that can then be used to determine the sequence of states in the Controller.

In state MUL0. it indicates that multiplication is completed 71 . Reg A and Reg Q are treated as a (1 + n + n)-bit register and shifted one position to the right. the Carry flipflop is cleared . C< The process is achieved with 3 states (IDLE. This is indicated with the notation C|A|Q << shr (C|A|Q) in the ASM chart. The counter is also decremented (P << P – 1). for example. Remember that Z=1 means that the counter has counted down from n-1 to 0 and therefore n iterations have been completed. for the case Q0=1. the Cout from the adder is stored in the carry flipflop. the ASM remains in state IDLE. together. The process is started with an input G. the Carry flipflop. the carry flip flop is cleared (C<<<< n-1) and Register Q is loaded with the Multiplier. Each state will provide control signals to the Data path to perform the multiplication sequence. In MUL1. the value of each bit of the multiplier (available on Q0) determines if the multiplicand is added (Q0 = 1) or not (Q0=0). Note that << indicates an assignment. the multiplication process is started. The value of Z then determines whether to: return to state MUL0 (Z=0) to continue iteration OR return to state IDLE (Z=1) thus completing the process. For the case Q0=0. As long as G remains LO. MUL0 and MUL1).Vijayamangalam – 638 056        Design of the Binary Multiplier Controller An ASM chart that implements the binary multiply algorithm is given below. When G=1. State IDLE=0 therefore indicates that the Multiplier is “currently multiplying” and when the ASM returns to state IDLE (IDLE=1). The next state is always MUL1. As the ASM moves to state MUL0.

one square for each combination of states taken two at a time  Square labeled Si. Sj. if outputs differ then the square gets an 'X'. [Nov/Dec-2010]  A critical race occurs when the order in which internal variables are changed determines the eventual state that the state machine will end up in. [Nov/Dec-2010]  Construct implication chart.  A non-critical race occurs when the order in which internal variables are changed does not alter the eventual state. write down implied state pairs for all input combinations. 72 . Explain the steps involved in the reduction of state table.Vijayamangalam – 638 056 6. Otherwise. Differentiate critical races from non-critical races. In other words. the resultant state will be the same. 7. a non-critical race occurs when moving to a desired state means that more than one internal state variable must be changed at once. but no matter in what order these internal state variables change.

 For each remaining unmarked square Si.c). Sj contains next state pair Sm.k. Sj.Vijayamangalam – 638 056  Advance through chart top-to-bottom and left-to-right. If square Si.q1.  Continue executing Step 3 until no new squares are marked with 'X'. 73 . then Si and Sj are equivalent. Design a JK flip-flop by writing Verilog program. [April/May-2015] module jk(q. 8.j. Sj is labeled 'X' . Sn and that pair labels a square already labeled 'X' then Si.

c. q1=q1.1'b0}:begin q=q. end always @ (posedge c) begin case({j.Vijayamangalam – 638 056 output q.1'b1}: begin q=~q. initial begin q=1'b0. end {1'b0. end endcase end endmodule 74 .k. input j.q1.q1. q1=~q1. q1=1'b1.1'b0}:begin q=1'b1. reg q. q1=1'b0.k}) {1'b0. end {1'b1. end {1'b1. q1=1'b1.1'b1}: begin q=1'b0.