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Method of Data transfer

Interrupt Structure in 8085

Data Transfer Mechanism

Data Transfer can take place between
processor-memory, processor-I/O devices ,
and memory-I/O devices
The mechanism differs based on
characteristics such as:
Addressing of the device
Amount of data transferred
Method of data transfer
Interaction among devices

Based on Addressing of the device

I/O Mapped data transfer

Memory Mapped data transfer

Based on program and hardware involved

Programmed Data Transfer
Polled mode

Interrupt driven

Direct Memory Access

Burst mode

Cycle stealing mode

Based on Method of data transfer and access

Parallel data transfer
Simple mode Handshake mode

Serial Data Transfer



I/O mapped and Memory mapped

Data transfer
In I/O mapped data transfer method, I/O devices
and memory are handled separately.
A separate address range is assigned for I/O
devices and separate control signals are used for
memory access and I/O device read/write
Separate instructions are used for input and
output device access (IN and OUT instructions)
A single address can be assigned to both I/O and
memory location

In memory mapped data transfer, each I/o

device is treated like a memory location.
The same separate control signals are used for
memory access and I/O device read/write
Each input or output device is identified by a
unique address in the memory address range.
Maximum memory addressing capacity is

Programmed Data Transfer

The instructions for programmed data transfer
is written and controlled by programmer
The transfer between processor and I/O
devices (vice versa) takes place by executing
the corresponding instruction.
Based on time of execution, it is divided in to
Polled mode
Interrupt driven

In Polled mode data transfer, data is read from an

input device when the processor is ready.
If the input device is not ready, the processor waits
till the device is ready with data
Similarly, data is written in to output device by the
processor, when it executes the write instruction
corresponding to that output device.
Considerable wastage of processor time in waiting.

In interrupt driven data transfer, data is read

from an input device only when it is ready
with data.
When the device is ready, it gives an interrupt
signal to the processor.
In the Interrupt service routine (ISR), a
program is executed to read the data from the
corresponding input device

The data transfer is done only when the

device is ready. The processor need not wait,
can execute other main routines
Suitable for slow I/O devices

Programmed I/O and interrupt I/O provide

data transfer between the Microprocessor and
external devices. However, there are various
instances when data must be moved between
memory and external devices.

Direct Memory Access (DMA)

DMA is an input output technique used for
high speed data transfer
Large block of data transfer between system
memory and I/O
It introduces two new signals that are

DMA performs data transfer memory and an

external device without involving the CPU.
The interface or controller chip must be
perform memory read and write operations in
similar way as microprocessor.
DMA data transfer can be of 2 types:
Burst or block transfer mode
Cycle stealing or interleaved mode

In bust mode of DMA data transfer, a

complete block of data is transferred in a
single DMA cycle
The system bus is released by the DMA
controller when the required bytes of data are

In cycle stealing mode of DMA data transfer, a

bock of data is transferred in many DMA
The system bus is released to the processor
after a set of bytes are transferred in one DMA
The processor is not halted for a long time.

Parallel Data Transfer

In Parallel mode of data transfer, all the bits in
a word are simultaneously transmitted.
Not suitable for long distance transfers
Can be of two types
Simple or synchronous mode
Handshake mode

In simple mode of data transfer, data is read

from an input device by the processor
irrespective of the status of the device.
Similarly, data is written in to an output device
irrespective of the status of the device.

In handshake mode, the processor checks the

status of I/O device before transmission.

Serial data transfer

Only one bit is transferred at a time
Is a low cost way to send data over long
All the bits in a data word can be transmitted
by using a shift register and transferring the
data bit by bit.
Can be done in 2 ways

In Synchronous data transfer, the sending and

receiving device are synchronized with a common
Data transfer takes place with a fixed and known
time frame

In asynchronous data transfer, the data words

are transmitted with a random time frame
between them.

Interrupt Structure of 8085

Interrupt is a process where an external device
can get the attention of the microprocessor.
An interrupt is considered to be an emergency
signal that may be serviced.
The Microprocessor may respond to it as soon as

Interrupts are useful when interfacing I/O devices

with low data-transfer rates, like a keyboard or a
mouse, in which case polling the device wastes
valuable processing time

The peripheral interrupts the normal

application execution, requesting to send or
receive data.
The processor jumps to a special program
called Interrupt Service Routine (ISR)to service
the peripheral
After the processor services the peripheral,
the execution of the interrupted program

Main Program

Main Program
Printer Interrupt

Main Program
Modem Interrupt

Main Program
Modem Interrupt

Classification of Interrupts
Interrupts can be classified into two types:
Maskable Interrupts (Can be delayed or Rejected)
Masking can be done by software or
hardware means.
Non-Maskable Interrupts (Can not be delayed or
Non-maskable interrupts are interrupts that are
always recognized; the corresponding ISRs are executed.

Interrupts can also be classified into two types:

Vectored (the address of the service routine is hardwired)
Vectored interrupts require the Interrupt Vector Address
(IVA) to be supplied by the external device that gives
the interrupt signal. This technique is vectoring, is
implemented in number of ways.

Non-vectored interrupts have fixed Interrupt Vector
Address for ISRs of different interrupt signals.

Interrupts can also be classified into two types:

Software Interrupts :
Software interrupts are special instructions, after
execution transfer the control to predefined ISR.

Hardware interrupts:
are signals given to the processor, for recognition
as an interrupt and execution of the
corresponding ISR

What happens when MP is interrupted ?

When the Microprocessor receives an interrupt
signal, it suspends the currently executing program
and jumps to an Interrupt Service Routine (ISR) to
respond to the incoming interrupt.
Each interrupt will most probably have its own ISR.

Responding to an interrupt may be immediate

or delayed depending on whether the
interrupt is maskable or non-maskable and

There are two ways of redirecting the

execution to the ISR depending on whether
the interrupt is vectored or non-vectored.
Vectored: The address of the subroutine is
already known to the Microprocessor
Non Vectored: The device will have to supply the
address of the subroutine to the Microprocessor

Interrupt Handling Procedure

The following sequence of operations takes
place when an interrupt signal is recognized
Save the PC content and information about
current state (flags, registers etc) in the stack.
Load PC with the beginning address of an ISR and
start to execute it.
Finish ISR when the return instruction is executed.
Return to the point in the interrupted program
where execution was interrupted.

Interrupt Sources and Vector

Addresses in 8085
Software Interrupts:
8085 instruction set includes eight software
interrupt instructions called Restart (RST)

Software interrupts and their vector


Hardware Interrupts
8085 have five hardware interrupts INTR,
RST 5.5, RST 6.5, RST 7.5 and TRAP.

Hardware interrupts of 8085

The INTR input.

The INTR input is the only non-vectored interrupt.
INTR is maskable using the EI/DI instruction pair.

RST 5.5, RST 6.5, RST 7.5 are all automatically

RST 5.5, RST 6.5, and RST 7.5 are all maskable.

TRAP is the only non-maskable interrupt in the

TRAP is also automatically vectored

Organization of hardware interrupts in

the 8085

The maskable interrupts are by default masked by
the Reset signal. So no interrupt is recognized by
the hardware reset.
The interrupts can be enabled by the EI
The three RST interrupts can be selectively
masked by loading the appropriate word in the
accumulator and executing SIM instruction. This
is called software masking.

All maskable interrupts are disabled whenever

an interrupt is recognized.
All maskable interrupts can be disabled by
executing the DI instruction.

Interrupt Vectors and the Vector Table

An interrupt vector is a pointer to where the
ISR is stored in memory.
All interrupts (vectored or otherwise) are
mapped onto a memory area called the
Interrupt Vector Table (IVT).
The purpose of the IVT is to hold the vectors that
redirect the microprocessor to the right place when
an interrupt arrives.

The 8085 Non-Vectored Interrupt

1. The interrupt process should be enabled
using the EI instruction.
2. The 8085 checks for an interrupt during the
execution of every instruction.
3. If INTR is high, MP completes current
instruction, disables the interrupt and sends
INTA (Interrupt acknowledge) signal to the
device that interrupted

4. INTA allows the I/O device to send a RST

instruction through data bus.
5. Upon receiving the INTA signal, MP saves the
memory location of the next instruction on
the stack and the program is transferred to
call location (ISR Call) specified by the RST

6. Microprocessor Performs the ISR.

7. ISR must include the EI instruction to enable
the further interrupt within the program.
8. RET instruction at the end of the ISR allows
the MP to retrieve the return address from
the stack and the program is transferred back
to where the program was interrupted.

The 8085 Maskable/Vectored Interrupt

1. The interrupt process should be enabled
using the EI instruction.
2. The 8085 checks for an interrupt during the
execution of every instruction.
3. If there is an interrupt, and if the interrupt is
enabled using the interrupt mask, the
microprocessor will complete the executing
instruction, and reset the interrupt flip flop.

4. The microprocessor then executes a call

instruction that sends the execution to the
appropriate location in the interrupt vector
5. When the microprocessor executes the call
instruction, it saves the address of the next
instruction on the stack.
6. The microprocessor jumps to the specific
service routine.

7. The service routine must include the

instruction EI to re-enable the interrupt
8. At the end of the service routine, the RET
instruction returns the execution to where
the program was interrupted.

Manipulating the Masks

The Interrupt Enable flip flop is manipulated
using the EI/DI instructions.
The individual masks for RST 5.5, RST 6.5 and
RST 7.5 are manipulated using the SIM
This instruction takes the bit pattern in the
Accumulator and applies it to the interrupt mask
enabling and disabling the specific interrupts.

SIM Instruction
The SIM instruction is used to mask or unmask
RST hardware interrupts.
When executed, the SIM instruction reads the
content of accumulator and accordingly mask
or unmask the interrupts.

Accumulator bit pattern for SIM


Bit 0 is the mask for RST 5.5

Bit 1 is the mask for RST 6.5
Bit 2 is the mask for RST 7.5.
If the mask bit is 0, the interrupt is available.
If the mask bit is 1, the interrupt is masked.

Bit 3 (Mask Set Enable - MSE) is an enable for

setting the mask.
If it is set to 0 the mask is ignored and the old
settings remain.
If it is set to 1, the new setting are applied.
The SIM instruction is used for multiple
purposes and not only for setting interrupt
It is also used to control functionality such as Serial
Data Transmission.

The RST 7.5 interrupt is the only 8085 interrupt that has
If a signal on RST7.5 arrives while it is masked, a flip flop
will remember the signal.
When RST7.5 is unmasked, the microprocessor will be
interrupted even if the device has removed the interrupt
This flip flop will be automatically reset when the
microprocessor responds to an RST 7.5 interrupt.

Bit 4 of the accumulator in the SIM instruction

allows explicitly resetting the RST 7.5 memory
even if the microprocessor did not respond to
Bit 5 is not used by the SIM instruction

In addition to masking interrupts, SIM

instruction can be used to send serial data on
the SOD line of the processor.
The data to be send is placed in the MSB bit of
the accumulator and the serial data output is
enabled by making D6 bit to 1.

RIM Instruction
RIM instruction is used to read the status of
the interrupt mask bits.
When RIM instruction is executed, the
accumulator is loaded with the current status
of the interrupt masks and the pending

Accumulator bit pattern after

execution of RIM instruction

Bits 0-2 show the current setting of the mask

for each of RST 7.5, RST 6.5 and RST 5.5
They return the contents of the three mask flip flops.
They can be used by a program to read the mask
settings in order to modify only the right mask.

Bit 3 shows whether the maskable interrupt

process is enabled or not.
It returns the contents of the Interrupt Enable Flip Flop.
It can be used by a program to determine whether or
not interrupts are enabled.

Bits 4-6 show whether or not there are

pending interrupts on RST 7.5, RST 6.5, and
RST 5.5
Bits 4 and 5 return the current value of the RST5.5 and
RST6.5 pins.
Bit 6 returns the current value of the RST7.5 memory
flip flop.

Bit 7 is used for Serial Data Input.

The RIM instruction reads the value of the SID pin on
the microprocessor and returns it in this bit.

RIM instruction is also used to read the serial

data on the SID pin of the processor.
The data on the SID pin is stored in the MSB of
the accumulator after the execution of the
RIM instruction.

Triggering Levels
RST 7.5 is positive edge sensitive.
When a positive edge appears on the RST7.5 line, a
logic 1 is stored in the flip-flop as a pending interrupt.
Since the value has been stored in the flip flop, the line
does not have to be high when the microprocessor
checks for the interrupt to be recognized.
The line must go to zero and back to one before a new
interrupt is recognized.

RST 6.5 and RST 5.5 are level sensitive.

The interrupting signal must remain present until the
microprocessor checks for interrupts.

Pending Interrupts
Since the 8085 has five interrupt lines,
interrupts may occur during an ISR and remain
Using the RIM instruction, it is possible to can
read the status of the interrupt lines and find if
there are any pending interrupts

TRAP is the only non-maskable interrupt.
It does not need to be enabled because it cannot be

It has the highest priority amongst interrupts.

It is edge and level sensitive.
It needs to be high and stay high to be recognized.
Once it is recognized, it wont be recognized again
until it goes low, then high again.

TRAP is usually used for power failure and

emergency shutoff.

Issues in Implementing INTR Interrupts

How long must INTR remain high?
The microprocessor checks the INTR line one clock
cycle before the last T-state of each instruction.
The INTR must remain active long enough to allow for
the longest instruction.
The longest instruction for the 8085 is the conditional
CALL instruction which requires 18 T-states.
Therefore, the INTR must remain active for 17.5 Tstates.
If f= 3MHZ then T=1/f and so, INTR must remain active
for [ (1/3MHZ) * 17.5 5.8 micro seconds].

The INTR line must be deactivated before the EI is

executed. Otherwise, the microprocessor will be
interrupted again.
Once the microprocessor starts to respond to an
INTR interrupt, INTA becomes active (=0).

Therefore, INTR should be turned off as soon

as the INTA signal is received.

The 8085 Interrupts