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Mentor ModelSim
Guide for the usage of Mentor ModelSim hardware description language editing and simulation environment.

Site:
Turun yliopiston Moodle-oppimisymprist
Course:
Guides for the usage of EDA tools
Book:
Mentor ModelSim
Printed by: Amir-Mohammad Rahmanisane
Date:
Thursday, 12 September 2013, 02:33 PM

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Table of Contents
General
Typing and editing HDL source code
Compiling source code
Simulating and viewing results using ModelSim
Code coverage analysis
Simulating with SDF (Standard-Delay-Format) timing data (post-synthesis simulation)
ModelSim project features

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General
Mentor ModelSim is an HDL (Hardware Description Language) editing and simulation environment which can be used to simulate
hardware modeled for instance with VHDL, Verilog or SystemC. This guide focuses to the simulation of the VHDL but can be applied
also to editing and simulation of the other languages.
The ModelSim software can be used on the departments Linux and Sun Solaris workstations (in the workstation classroom). Navigate to
your own work directory (in terminal window) and start ModelSim by typing commands
> use modelsim 65f
and
> vsim
You can also use ModelSim with your Microsoft Windows workstation by requesting and downloading the ModelSim Student Edition.

The original ModelSim tutorial can be found from location /soft/mentor/modeltech/docs/pdf/se_tutor.pdf on the department's
Linux/Solaris workstations.

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Typing and editing HDL source code


The ModelSim has its own text editor to be used to write and edit the HDL source code. However, it is strongly recommended to use
some other text editor (for instance Emacs) to compose the source code files.
To create a new or open an existing VHDL file with Emacs navigate to your work directory with terminal and type
> emacs your_file_name.vhd
Emacs text editor has its own templates to create known VHDL structures. At first these templates can appear annoying
but the usage of them is worth learning and doing.

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Compiling source code


Start Modelsim on your working directory where you have your .vhd-files, or if you have Modelsim already up and running move to
your working directory by selecting File -> Change Directory.
Create a working library. All the compiled HDL design files will be stored to this library called work.
Choose File -> New -> Library, Create a new library... and name it as work.

Compile your .vhd-files to your work-library.


Choose Compile -> Compile... , choose your files which you want to compile, and press Compile.

Now you can see the feedback (errors or no errors) of the compilation on the Transcript window on the bottom of the ModelSim. Correct
the potential errors on your source codes and repeat the compile process as long as your design is compiled without errors.
If you have hierarchical components on your design you have to compile the files starting from the components on the bottom level of
the hierarchy.

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Simulating and viewing results using ModelSim


When you have successfully compiled all your source code files you have to simulate your design.
The compiled design files can be found on the Modelsim Workspace window under the work-library.

Start the simulation by double clicking the entity you want to simulate (typically the testbench entity).
Alternative way to start the simulation is to choose Simulate -> Start Simulation..., choosing the entity to be simulated and clicking OK.

After successful simulation the simulated design units can be seen on the Workspace window.

The xxxx_testbench is simulated here. To analyze the simulation results the ports and signals of the design can be viewed as timing
diagrams (waves).
To open the signals to the wave window click the simulated entity with the secondary mouse button and choose Add -> Add to Wave or
Add -> Add All Signals to Wave.

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Now when you have the signals on the wave window you can run the simulation. Choose an eligible Run Length and press Run.

You can find other run options, for instance Run -All, Restart and Break, under the Simulate menu and among the menu buttons.
Now you can analyze the functionality of your design on the Wave window. From top panel you can found the zooming tools and from
bottom left corner the green and red buttons to add and remove cursors which make the wave analysis easier.

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Code coverage analysis


The code coverage analysis gives you graphical and report file feedback on which executable statements, branches, conditions, and
expressions in your source code have been executed. It also measures bits of logic that have been executed during execution. The code
coverage analysis is carried out before synthesis.
Example code coverage analysis (command line only):
Create working library
vlib work
Compile the design files (VHDL):
vcom -cover -bcsxf file1.vhd file2.vhd test_bench.vhd
Load the design:
vsim -voptargs="+acc" -coverage test_bench.vhd
Note: Verilog files are compiled using command: vlog -cover -bcsxf.
The argument -cover -bcsxf collects information on branch, condition, statement, extended toggle, and finite state
machine statistics.
Run the simulation by typing in the VSIM> prompt for example:
run 1ms
Several code coverage panels appear after running the simulation. The workspace windows the results of the coverage analysis. Roll the
workspace window to right to get more information on different coverages.

Detailed coverage information can be obtained for instance from: missed coverage, instance coverage, or detailed window.
Missed coverage displays the selected file's un-executed statements, branches, conditions, expressions, and signals that have not toggled.
It also includes missed states and transitions in finite state machines.
Missed coverage window is opened/closed from:
view -> coverage -> missed coverage

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Instance coverage displays statement, branch, condition, expression and toggle coverage statistics for each instance in a non-hierarchical
view.
Instance coverage window is opened/closed:
view -> coverage -> instance coverage

Details pane shows the coverage details for the item selected in Missed Coverage pane.
Details pane is opened/closed from:
view -> coverage -> details

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Simulating with SDF (Standard-Delay-Format) timing data


(post-synthesis simulation)
The compilation and simulation phases (presented earlier) ensures that both the syntax of VHDL code and the functionality of design are
correct.
At this point, the design is already synthesized, for instance using Cadence PKS. Basically the synthesis process converts HDL code into
netlist that describes various logic gates in the design and how they are interconnected. To verify design work after synthesis, a
post-synthesis simulation is performed.
The post synthesis simulation follows the simulation guidelines presented earlier. The biggest exceptions are: mapping of technology
library and including SDF-File (Standard Delay Format). The timing information is generated by the synthesis tool, and it is technology
specific. The guidelines given here are also applicable to a post-layout simulation in which layout of design is generated by synthesis
tool after which the design is simulated. (In fact the example screen captures refer to the post-layout simulation.)
The netlist and the SDF (after synthesis or after layout) are written from the synthesis tool. The netlist of the design is written in verilog
(how this happens is explained in the Cadence PKS manual). The verilog output is selected because it just works better especially in
post-layout simulation (There is not exact reason for this behavior). Write theses file into the same working directory that was used
before synthesis (If you want to put these files into separate directory, create the working directory first using the guidelines given
earlier). The command line procedure of post-synthesis simulation is presented at the end of this file.
Including the technology file to an existing work library:

For instance, by adopting the UMC Faraday 90 nm technology:


Library name: fsd0a_a_generic_core
Library maps to:/tech/umc/faraday/Core/fsd0a_a/2007Q1v1.7/GENERIC_CORE_1D2V/FrontEnd/modelsim/SunOS
/fsd0a_a_generic_core
Note: the technology libraries are (usually) platform depended! That is if you are running Modelsim on a Linux platform you should use
different libraries. With this technology, the Linux translation of the technology library can be accessed simply by replacing the SunOS
with Linux in the path. After the library mapping, the technology library can be seen from the workspace in the upper left corner of the
Modelsim.

Compile the netlist and your testbench (usually one is able to use the same testbench that was used in pre-synthesis simulation).

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You can select the necessary files for compilation using the control-button. Observe that the simulator chooses the appropriate compiler
for verilog- and VHDL-files.

The simulation is carried out using the actual delay information generated by the synthesis tool (SDF-file). The simulator is started by
selecting:
Design -> Start Simulator
A pop window appears. Define the design unit(s): work.name_of_testbench.
For instance, in the example counter design, one selects work.tcounter

Do not close the pop-up window. In other words, do not press the OK button yet. Next select libraries from the start simulator window.

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Add the technology library to the search libraries (-L) using the Add-button. Next select the SDF from the Start Simulation window.

Define the path to the SDF-file using the Add-button. The dut is the name of the toplevel process in the testbench. Press the OK-button
and if everything is correct the simulator should start.

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Select the signals using the right mouse button. Select the eligible simulation time and press Run.

The result of the simulation appears into the waveform window:

The above presented waveform is post-layout simulation of a simple counter structure. The cursors highlight the delay from rising clock
edge to the output. Furthermore, one is able to see that the signal values ripple before stabilizing meaning that the design has potential
timing problems. However with the selected clock period, the unstable phase do not disturb the design.

Command line procedure:

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The post-synthesis or post-layout simulation can be done using command line procedure:
Create work library (if not already created in pre-synthesis simulation):
vlib work work
Map technology library into an existing library (example UMC Faraday 90 nm) (one long command):
vmap fsd0a_a_generic_core
/tech/umc/faraday/Core/fsd0a_a/2007Q1v1.7/GENERIC_CORE_1D2V/FrontEnd/modelsim/SunOS
/fsd0a_a_generic_core
Compile:
vcom file.vhd
vlog file.v
Start simulator (one long command):
vsim -sdftyp /dut=/path_to_file/name_of_the_sdf_file.sdf -t ps -L
fsd0a_a_generic_core -sdfnoerror work.your_testbench
Again if your are using Linux platform instead of the SunOS, correct the path of the technology library.

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ModelSim project features


The ModelSim has features to handle your designs as projects. However, the usage of these features cannot be recommended.

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