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LIST OF EXPERIMENTS

**1. Verification of basic Logic Gates.
**

2. Implementing all individual gates with universal gates NAND &

NOR.

3. Design a circuit for the given canonical form, draw the circuit

diagram and verify the demorgan laws.

4. Design a combinational logic circuit for 4x1 MUX and verify the

truth table.

5. Design a combinational logic circuit for 1x4 De-MUX and verify the

truth table.

6. Verify the data read and data write operations for the IC 74189.

7. Design a gray code encoder and interface it to SRAM IC 74189 for

write operation display on seven segment display.

8. Design a gray code decoder and interface it to SRAM IC 74189 for

read operation display on seven segment display.

9. Construct Half Adder and Full Adder using Half Adder and verify

the truth table.

10. Verification

of

truth

tables

of

the

basic

Flip-Flops

with

**Synchronous and Asynchronous modes.
**

11. Implementation of Master-Slave Flip-Flop with JK Flip-Flop and

verify the truth table for race around condition.

12. Design a decade counter and verify the truth table.

13. Design MOD-6 counter using D- Flip-Flop.

14. Construct 4-bit ring counter with T- Flip-Flop and verify the truth

table.

15.Design a 8 – bit right shift register using D- Flip-Flop and verify

the truth table.

.

1.

VERIFICATION OF BASIC LOGIC GATES.

AIM:

To verify the truth tables of AND, OR, NOT, NAND, NOR, EX-OR gates.

APPARATUS:

1. Bread board IC trainer

2. IC 74LS08 (AND)

3. IC 74LS32 (OR)

4. IC 74LS04 (NOT)

5. IC 74LS00 (NAND)

6. IC 74LS02 (NOR)

7. IC 74LS86 (EX-OR)

8. Patch cards.

THEORY:

In digital electronic circuits as two logic levels Logic-I, Logic-O. These are also

known as HIGH and LOW logic levels.

There are two logic circuits.

1. Positive logic: In which 1 corresponding to HIGH, 0 corresponding to LOW.

2. Negative logic: In which 1 corresponding to LOW, 0 corresponding to HIGH.

BASIC’ OPERATIONS:

AND Gate:

IC 74LS08 is quad 2-i/p AND gate. It requires 5V DC. The o/p of AND

gate is HIGH when both the inputs are HIGH otherwise HIGH.

OR Gate:

IC 74LS32 is quad 2-i/p OR gate. It requires 5V DC. The o/p of OR gate is

LOW when both the inputs are LOW otherwise IIIGH.

NOT Gate:

IC 74LS04 is hex NOT gate. The o/p of NOF gate is always

complementing of i/p.

NAND Gate:

**IC 74LS00 is quad 2-i/p NAND gate. It requires 5V DC. The o/p of NAND
**

gate is LOW when both the inputs are HIGH otherwise I 11GII.

NOR Gate:

IC 74LS02 is quad 2-i/p NOR gate. It requires 5v. The O/p of NOR gate is

HIGH when both e inputs are LOW otherwise LOW.

EX-OR Gate:

IC 74LS86 is quad 2-i/p EX-OR gate. It requires 5V DC. The o/p of EX-OR

gate is HIGH when two different inputs are applied otherwise LOW.

CIRCUIT DIAGRAMS:

AND GATE:

DIGRAM

TRUTH TABLES

A

B

Y

0

0

1

1

0

1

0

1

0

0

0

1

A

B

Y

0

0

1

1

0

1

0

1

0

0

0

1

OR GATE:

NOT GATE:

PIN

I/P’s are applied from toggle switches and o/p is observed at o/p indicators. PRECATIONS: . 3.t ground (pin no7). 1/Ps are applied (at pin no’s l&2) and output is taken from (pin no 3).NAND GATE: NOR GATE: EX-OR GATE: PROCEDURE: 1. 2.r.+5V DC is applied at 1cc (pin no 14)of each IC w.

IMPLEMENTATION OF ALL INDIVIDUAL GATES WITH UNIVERSAL GATES NAND & NOR. When all or either of the inputs are high output is low. Take care while make connections with NOT and NOR gates. Bread board IC trainer 2. Thus NAND gate is the inverse of AND gate.1. The output is low when all inputs are high. The output of NOR gate is high only when all inputs are low. Avoid loose connections on bread board. APPARATUS: 1. Patch cards. The output is high for all the remaining combinations. IC 74LS00 (NAND) 3. NOT gates using NAND and NOR gates. Thus NOR gate is the inverse of OR gate. OR. . IC 74LS02 (NOR) 4. RESULT: 2. THEORY: NAND gate: NAND gate is a combination of AND & NOT gates. 2. Logic equation is: Digital IC for NOR: IC 7402. Logic equation is: Digital IC for NAND: IC 7400. AIM: To develop the AND. NOR gate: NOR gate is a combination of OR & NOT gates.

a HIGH (1) output results. It is made using transistors and junction diodes.600 in total for the later versions. AB=A+B.In digital electronics. Digital systems employing certain logic circuits take advantage of NAND's functional completeness Like NAND gates. and thus a NAND gate is equivalent to inverters followed by an OR gate. This property is called functional completeness. Today. For example. CIRCUIT DIAGRAMS: AND GATE: A Y 0 1 1 0 A A 0 00 01 11 1 B B 0 01 10 01 1 Y Y 0 01 01 01 1 . a NAND gate (negative-AND) is a logic gate which produces an output which is false only if all its inputs are true. NOR gates are so-called "universal gates" that can be combined to form any other kind of logic gate. Instead. Apollo Guidance Computer. By De Morgan's theorem. integrated circuits are not constructed exclusively from a single type of gate. the first embedded system. about 5. A LOW (0) output results only if both the inputs to the gate are HIGH (1). EDA tools are used to convert the description of a logical circuit to a netlist of complex gates (standard cells) or transistors (full custom approach). thus its output is complement to that of the AND gate. The NAND gate is significant because any boolean function can be implemented by using a combination of NAND gates. was built exclusively from NOR gates. if one or both inputs are LOW (0).

4.r. Don’t switch ON the kit till all connections are made. Avoid loose connections on bread board. Inputs are applied to toggle switches and outputs are connected to output LEDs. Take care while make connections with VCC and GND. 2. 3. Connect the circuit as shown in circuit diagram 3. PRECATIONS: 1.t ground (pin no7). RESULT: . 2. +5V DC is applied at VCC (pin no 14) of each IC w. Verify the truth tables as shown in the truth tables.A Y 0 1 A 1 0 B Y 0 0 1 1 0 1 0 1 0 0 0 1 A B Y 0 0 1 1 0 1 0 1 0 1 1 1 PROCEDURE: 1.

3.VERIFICATION OF DE-MORGAN LAWS AIM: Design a circuit for the given conical form. The distinction between "canonical" and "normal" . Bread board IC trainer 2. 7408. APPARATUS: 1. normal. THEORY: In mathematics and computer science. Patch cards. 7432 3. IC 7404. or standard form of a mathematical object is a standard way of presenting that object as a mathematical expression. draw the circuit diagram and verify De-Morgan laws. a canonical.

Thus. However canonical forms frequently depend on arbitrary choices (like ordering the variables).In computer science. Putting something into canonical form is canonicalization. normal form is a weaker notion: A normal form is a representation such that zero is uniquely represented.The canonical form of a positive integer in decimal representation is a finite sequence of digits that does not begin with zero. Therefore. in computer algebra.In computer science. data that has more than one possible representation can often be canonicalized into a completely unique representation called its canonical form. there are usually many different ways to represent the same object. while a normal form simply specifies its form. In this context. and this introduces difficulties for testing the equality of two objects resulting on independent computations. when representing mathematical objects in a computer.forms varies by subfield.More generally. a canonical form consists in the choice of a specific object in each class. when one consider as equivalent a matrix and its left product by an invertible matrix. a canonical form is a representation such that every object has a unique representation. CIRCUIT DIAGRAMS: . the equality of two objects can easily be tested by testing the equality of their canonical forms. In most fields. This allows testing for equality by putting the difference of two objects in normal form. Jordan normal form is a canonical form for matrix similarity. without the requirement of uniqueness. for a class of objects on which an equivalence relation is defined. and the row echelon form is a canonical form. a canonical form specifies a unique representation for every object. For example.Canonical form can also mean a differential form that is defined in a natural (canonical) way. and more specifically in computer algebra.

Take care while make connections with VCC and GND. Verify the tables.TRUTH TABLES: A´ A 0 B 0 ´ AB 1 PROCEDURE: 0 1 1 1. Inputs are outputs are 4. + B´ 1 A´ B ´B A+ 1 . +5V DC is 1 0 1 each IC w. B´ 1 0 A 0 0 1 1 0 1 0 0 1 0 0 0 applied at VCC (pin no 14) of ground (pin no7).4×1 MULTIPLEXER AIM: Design a Combinational Logic Circuit for 4×1 MUX and verify the truth table. Don’t switch ON the kit till all connections are made. truth tables as shown in the truth PRECAUTIONS: 1 1 0 0 1. Avoid loose connections on bread board.1 Connect the 1 0 diagram 3. IC 74153 3. 2. RESULT: 4. Bread board IC trainer 2. 3. .r. APPARATUS: 1. circuit as shown in circuit applied to toggle switches and connected to output LEDs.t 2. Patch cards.

A multiplexer is a circuit with many inputs but only one output. Multiplexer means many to one.THEORY: Multiplexers are very useful components in digital systems. n control/select signals and 1 output signal. By using control signals (select lines) we can select any input to the output. CIRCUIT DIAGRAM: PIN DIAGRAM: TRUTH TABLE: . Multiplexer is also called as data selector because the output bit depends on the input data bit that is selected. The general multiplexer circuit has 2n input signals. They transfer a large number of information units over a smaller number of channels. (usually one channel) under the control of selection signals.

Avoid loose connections on bread board. Take care while make connections with VCC and GND. PRECAUTIONS: 1.PROCEDURE: 1. 4. 2. Connect the circuit as shown in circuit diagram 3.t ground (pin no 8).r. +5V DC is applied at VCC (pin no 16) w. RESULT: . 3. Verify the truth tables as shown in the truth tables. Inputs are applied to toggle switches and outputs are connected to output LEDs. 2. Don’t switch ON the kit till all connections are made.

1×4 DE-MULTIPLEXER AIM: Design a combinational circuit for 1×4 De-MUX and verify the truth table. The general demultiplexer circuit has 1 input signal. APPARATUS: 1. THEORY: De-multiplexers perform the opposite function of multiplexers. Bread board IC trainer 2. PIN DIAGRAM: IC 74139 . IC 74156 3. They transfer a small number of information units (usually one unit) over a larger number of channels under the control of selection signals.5. n control/select signals and 2n output signals. De-multiplexer circuit can also be realized using a decoder circuit with enable. Patch cards.

t ground (pin no 8). PRECAUTIONS: 1. RESULT: . +5V DC is applied at VCC (pin no 16) w. Take care while make connections with VCC and GND. 3. 2. Inputs are applied to toggle switches and outputs are connected to output LEDs. Avoid loose connections on bread board. 4.r. Don’t switch ON the kit till all connections are made. Verify the truth tables as shown in the truth tables. Connect the circuit as shown in circuit diagram 3.TRUTH TABLE: PROCEDURE: 1. 2.

Patch cords 5. The outputs are 3-state and are in high impedance state whenever the Memory Enable (ME) input is HIGH. 16X4 SRAM IC 74189 2.SRAM-74189 AIM:To verify the data read and data write operations for the IC74189 APPARATUS 1. Here A0-A3 are the address inputs.6. The outputs are active only in the Read mode and the output data is the complement of the stored data. Digital IC trainer kit 3. 1 No. Connecting wires … … … 1 No.chip. 1 No. O1-O4 are inverted data outputs . D1-D4 are data inputs. THEORY The 74189 is a high speed 64-bit RAM organized as a 16-word by 4-bit array. Address inputs are buffered to minimize loading and are fully decoded on. Bread board 4.

7. Verify the read &write operations as per the truth table. For read operation apply logic 1 to pin-3 & enter the address input to pins 1.Fig. data L output are compliment of the Ram content) Table 6.15. Enter the 4-bit address to pins 1.14. 2.15. 3. 4.9.14.10.1: Logic diagram of SRAM for data read and write operations FUNCTION TABLE OPERATION H X L H L All data outputs are high Read mode )date outputs are compliment of the RAM content) Write mode(data inputs are written on the memory.13 observe the read data from pins 5. Apply logic 0 to the chip select to turn on the IC. Connections are made as per the circuit diagram.12 by applying logic 0 to pin-3 for write operation.6.1: SRAM Function table.11 5. 6.13 & 4-bit data as input to pins 4. PROCEDURE: 1. Truth Table for Write operation: .

Truth Table for read operation: PIN DIAGRAM: .

check your circuit thoroughly. Pulse width and voltage level of pulse generator output is crucial for the operation of the flip-flops. Correct ICs should be properly placed on the IC bases using pin diagrams. 5. 3. 2. In case the logic gate outputs do not make sense. Use multimeter probe tip to gently ease the IC out of breadboard. If the problem is still not resolved. get the IC tested by the technician.Draw the pin configurations of IC74189 (SRAM)from Annexure-A here PRECAUTIONS: 1. 4. The open circuit voltage of the power supply must be stable and close to 5V. Using bare hands might cause IC pins to break. The mid-section groove of the breadboard can be used to gently lift the IC. RESULT: Verified the data read and data write operations for the IC74189 VIVA 1) 2) 3) 4) 5) 6) 7) QUESTIONS: What is the difference between SRAM & DRAM? What is the function of CS & WE in SRAM IC 74189? What is meant by high impedance state? How can you enable the SRAM for read &write operations? What is 7-segment display? Differentiate b/w RAM & ROM? SRAM is volatile or Nonvolatile memory? .

EQUIPMENT REQUIRED: 1. a sum bit and a carry bit. The half adder accepts two binary digits on its inputs and produces two binary digits on its outputs.9. therefore sum is 1 when A and B are different carry is 1 when A and B are 1’s. A Boolean equations for these outputs are Sum(S)= A B C Carry(C)=AB+BC+AC . 2. The half adder accepts two binary digits on its inputs and produces two binary digits on its outputs. ICS 7486. Full adder is a logic circuit that adds two bits. 3.Connecting wires/ patch chords THEORY: Half adder is a logic circuit that adds two bits. a sum bit and a carry bit. A Boolean equations for these outputs are Sum(S)= A B Carry(C) =AB The sum output is A XOR B the carry output is A AND B. IC trainer kit. 7408. 7432. HALF ADDER AND FULL ADDER USING TWO HALF ADDERS AIM: To construct half-adder and full adder using two half adders and verify its truth table.

therefore sum is 1 when A and B are different carry is 1 when A and B are 1’s. LOGIC SYMBOL: CIRCUIT DIAGRAM: HALF ADDER FULL ADDER TRUTH TABLE: 0 SU M 0 CARR Y 0 0 1 1 0 1 0 1 0 1 1 0 1 A B 0 TRUTH TABLE: .The sum output is A XOR B the carry output is A AND B.

Inputs are applied to toggle switches and outputs are connected to output LEDs. 2. 4. Connecting wires/ patch chords. Connect the circuit as shown in circuit diagram 3.r. AIM: Verify the truth tables of the basic flip flops with synchronous and asynchronous modes. Take care while make connections with VCC and GND. Carr y 0 0 0 1 0 1 1 1 PRECATIONS: 1.t ground (pin no7). +5V DC is applied at VCC (pin no 14) of each IC w. 10. IC trainer kit. 1.7402 2. 3. RESULT: The construction of half adder and full adder using half adder and the verification of truth table is done. Don’t switch ON the kit till all connections are made.BASIC FLIP FLOPS WITH SYNCHRONOUS AND ASYNCHRONOUS MODES. THEORY: The Asynchronous RS Flip Flop (Latch): . 2. Verify the truth tables of half adder as shown in the truth tables. ICs 7400. EQUIPMENT REQUIRED: 1.A B C 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Su m 0 1 1 0 1 0 0 1 PROCEDURE: 1. Avoid loose connections on bread board.

CIRCUIT DIAGRAM: S-R FLIP FLOP: QN S CLK QN R TRUTH TABLE: S R 0 0 1 1 0 1 0 1 J-K FLIP FLOP: CL K 1 1 1 1 Q N 0 0 1 1 Q N 1 1 0 1 RESPONSE PRIVIOUS STATE QN ~QN UN DETERMINE . Digital circuits can have a concept of time using a clock signal. This means that this flip flop is concern with time. Rs flip flop is also called synchronous flip flop. The synchronous RS flip flop: Synchronous flip flop means that this flip flop is concerned with time.Latch is a type of bi-stable circuit. The main difference between latches and flip-flops is in the method used for changing their state. Digital circuits can have a concept of time using a clock signal. The clock signal simply goes from low-to-high and high-to-low in a short period time. The clock signal simply goes from low to high and high to low in a short period of time. similar to a flip-flop. which can reside in either of two stable states by virtue of feedback arrangement.

J K QN CLK QN TRUTH TABLE J K 0 0 1 1 0 1 0 1 CL K 1 1 1 1 Q N 0 0 1 1 Q N 1 1 0 1 RESPONSE PRIVIOUS STATE QN ~QN TOGGLE D.FLIP FLOP: QN D CLK QN TRUTH TABLE CL Q Q D K N N 0 1 0 1 1 1 1 0 RESPONSE QN ~QN .

Avoid loose connections on bread board.MASTER SLAVE JK FLIP-FLOP . Inputs are applied to toggle switches and outputs are connected to output LEDs. Take care while make connections with VCC and GND.T. RESULT: 11. Don’t switch ON the kit till all connections are made.t ground (pin no7).r. PRECATIONS: 1. 3.FLIP FLOP: TRUTH TABLE T 0 1 CL K 1 1 Q N 1 0 Q N 0 1 RESPONSE ~QN QN PROCEDURE: 1. Connect the circuit as shown in circuit diagram 3. 4. 2. Verify the truth tables of NAND and NOR Latches as shown in the truth tables. +5V DC is applied at VCC (pin no 14)of each IC w. 2.

THEORY: A master slave flip flop contains two clocked flip flops. 2. IC trainer kit. When the clock is high the master is active. The final output of master slave flip flop is the output of the slave flip flop. The first is called master and the second slave. As the slave is inactive during this period its output remains in the previous state.AIM: Implementations of master slave flip-flop with JK Flip-Flop and verify the truth table for race around condition. So the output of master slave flip flop is available at the end of a clock pulse. EQUIPMENT REQUIRED: 1. ICs 7476 3. Connecting wires/ patch chords. The output of the master is set or reset according to the state of the input. When clock becomes low the output of the slave flips flop changes because it become active during low clock period. PIN DIAGRAM: .

+5V DC is applied at VCC (pin no 5)of each IC w. Connect the NOT gate input to the pin no. 4. Inputs are applied to toggle switches and outputs are connected to output LEDs. 5. 2.t ground (pin no13).Avoid loose connections on bread board.1 6. Apply the clock signal to the pin no. RESULT: . 3. PRECATIONS: 1. Connect the circuit as shown in circuit diagram 3.CONNECTION DIAGRAM: TRUTH TABLE: PROCEDURE: 1. Don’t switch ON the kit till all connections are made. 2. Take care while make connections with VCC and GND.6.r. Verify the truth table and of the JK master slave flip-flop.1 and output to the pin no.

In order to count from 0 through 9.12. all the flip-flops should be reset. With 4 flip-flops one can count from 0 to15 (16 states). In the decade counter. Connecting wires/ patch chords. Thus the outputs Q3 and Q1 are given directly to the inputs of the AND gate and the outputs Q2 and Q0 are given through inverters. a counter with 3 flip-flops is not sufficient. the counter output would be 1010 for a moment. ICs 7490 3.DECADE COUNTER AIM: Design a decade counter and verify the truth table. when the output is 1010(for the 10th clock pulse). This sends the output of the AND gate to HIGH clearing all the flip-flops. PIN DIAGRAM: . for the 10th clock pulse. Therefore. Thus a decade counter has been developed. Out of these 16 states. we should skip any 6 states. EQUIPMENT REQUIRED: 1. IC trainer kit. THEORY: The decade counter (mod-10 counter) is used most often. 2.

4.Feed MR terminal with ‘0’ and MS terminals with ‘0’.now apply clock then the output varies between the values ‘0’ and ‘9’. 3. Pins-12.Feed MR terminal with ‘0’ and MS terminals with ‘1’ then the display shows‘9’. 7. 3 are Master Reset (MR) inputs and pins-6. Pin-12 and pin-1 to be shorted. 6. 10. 9. 2. PRECAUTIONS: 1.11 are outputs. 2. 3. Connect the circuit as shown in the figure. 14 has no connections. Pins-2. The clock pulse is given to pin-14 of IC 7490. Vcc should not exceed +5v. No connections are to be given to pins-13. 8. 3. RESULT: . Pins-2.8. 14. 7 are inputs and is always ‘0’ so that it is connected to ground.TRUTH TABLE: PROCEDURE: 1. 11. 6. Feed MR terminal with ‘1’ and MS terminals with ‘0’ then the display shows‘0’. Pins-13. 7 are Master Set (MS) inputs. 9. 5. The Vcc supply is given to pin-5 of IC 7490. Avoid loose connections on the bread board.

and are manufactured as separate integrated circuits and also incorporated as parts of larger integrated circuits. IC trainer kit.2no’s 3. a counter is a device which stores (and sometimes displays) the number of times a particular event or process has occurred. Each pulse applied to the clock input increments or decrements the number in the counter. often in relationship to a clock signal. A counter circuit is usually constructed of a number of flip-flops connected in cascade. The values on the output lines represent a number in the binary or BCD number system.13. 2. ICs 7474 . CIRCUIT DIAGRAM: . EQUIPMENT REQUIRED: 1. THEORY: In digital logic and computing. MOD-6 Counter AIM: Design a MOD-6 counter with D Flip-Flop and verify the truth table. Connecting wires/ patch chords. Counters are a very widely-used component in digital circuits. The most common type is a sequential digital logic circuit with an input line called the "clock" and multiple output lines.

4.Q1 Q2 Q3 PRESET PR PR D PR D-Q1 D D-Q2 D D-Q3 FF1 FF2 FF3 CLR CLR CLR Q1 Q2 Q3 CLK CLR TRUTH TABLE: Clock Pulse 0 1 2 3 4 5 Q3 0 1 0 1 0 1 Q2 0 0 1 1 0 0 Q1 0 0 0 0 1 1 PROCEDURE: 1. PRECAUTIONS: 1.Apply the clock pulse and observe the out puts. 2.Held the preset at high position. 2. Vcc should not exceed +5v.Apply vcc to pin -14 and gnd to pin-7 for all IC’s. . Connect the circuit as shown in the figure. Avoid loose connections on the bread board. 3.

A counter circuit is usually constructed of a number of flip-flops connected in cascade. The values on the output lines represent a number in the binary or BCD number system. IC trainer kit. THEORY: In digital logic and computing. Counters are a very widely-used component in digital . Each pulse applied to the clock input increments or decrements the number in the counter.RESULT: 14. 2. often in relationship to a clock signal. a counter is a device which stores (and sometimes displays) the number of times a particular event or process has occurred. The most common type is a sequential digital logic circuit with an input line called the "clock" and multiple output lines.2no’s 3. EQUIPMENT REQUIRED: 1. ICs 7474 . Connecting wires/ patch chords. 4-Bit Ring Counter AIM: Design a 4-Bit Ring counter with D Flip-Flop and verify the truth table.

and are manufactured as separate integrated circuits and also incorporated as parts of larger integrated circuits. CIRCUIT DIAGRAM: PRESET Q1 Q2 Q3 Q4 PRESET PR PR PR PR D Q1 D Q2 D Q3 D Q4 DFF1 DFF2 DFF3 DFF4 CLR CLR CLR CLR Q1 Q2 Q3 Q4 CLK CLR TRUTH TABLE: Clock Pulse 0 1 2 3 4 Q4 Q3 1 0 0 0 1 0 1 0 0 0 Q2 0 0 1 0 0 Q1 0 0 0 1 0 PROCEDURE: 1.Short t preset of flip-flop from ff2 to ff4and held it in high position . Typically. A ring counter is a circular shift register which is initiated such that only one of its flip-flops is the state one while others are in their zero states. 4. 2. that is.circuits. 3. Connect the circuit as shown in the figure. in a ring. a pattern consisting of a single bit is circulated so the state repeats every n clock cycles if n flip-flops are used. .apply clock pulses to pin 3&11 for all IC’s simultaneously.Apply vcc to pin -14 and gnd to pin-7 for all IC’s. A ring counter is a Shift Register (a cascade connection of flip-flops) with the output of the last one connected to the input of the first.

each flip-flop is edge triggered. this staggers the serial input in the time domain. Each subsequent flip-flop halves the frequency of its predecessor. sharing the same clock. leading to parallel output.5. in which the output of each flip-flop is connected to the 'data' input of the next flip-flop in the chain. a shift register is a cascade of flip flops. Once the data has been clocked in. PRECAUTIONS: 1. as described in the SISO section above. THEORY: In digital circuits.Apply the clock pulse and observe the out puts. . As a result. such that its 'data in' and stage outputs are themselves bit arrays: this is implemented simply by running several shift registers of the same bit-length in parallel. Data is input serially. 2. or it can be shifted out In this configuration. which doubles its duty cycle. 8-Bit Shift Register AIM: Design a 8-Bit Shift Register using D Flip-Flop and verify the truth table. 'shifting in' the data present at its input and 'shifting out' the last bit in the array. it takes twice as long for the rising/falling edge to trigger each subsequent flip-flop. This configuration allows conversion from serial to parallel format. at each transition of the clock input. The initial flip-flop operates at the given clock frequency. EQUIPMENT REQUIRED: 1. 6. resulting in a circuit that shifts by one position the 'bit array' stored in it. ICs 7474 . Avoid loose connections on the bread board. a shift register may be multidimensional. it may be either read off at each output simultaneously. Vcc should not exceed +5v.4no’s 3. Connecting wires/ patch chords. More generally. RESULT: 15. 7. Short t clear i/p’s and held it in low position to clear the o/p’s. 2.Now the out put of the ff1 held at high using preset at low position. IC trainer kit. And now the position of preset of ff1 is held at high position.

In a latched shift register (such as the 74595) the serial data is first loaded into an internal buffer register. it is desirable to use a latched or buffered output.Q2.Q5.Q6 . In general. CIRCUIT DIAGRAM: D D D D D D D D -Q1 .Q3Q4 .In cases where the parallel outputs should not change during the serial loading process. then upon receipt of a load signal the state of the buffer register is copied into a set of output registers. the practical application of the serial-in/parallel-out shift register is to convert data from serial format on a single wire to parallel format on multiple wires.Q7 -Q8 PRE PRE PR PR PR PR F DQ2 F DF Q3 FQ5 FQ6 FQ7 FQ8 DQ1 DF Q4DPR DPR DPR DPR F F F F F F F F Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CLR CLR 1 CLR 2 CLR 3 CLR 4 5 CLR 6 CLR 7 CLR 8 CLK CLR TRUTH TABLE: Cloc k Puls e 0 1 2 3 4 Q8 Q7 1 0 0 0 0 0 1 0 0 0 Q6 0 0 1 0 0 Q5 Q4 Q3 Q2 Q1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .

without the requirement of uniqueness. 2. Avoid loose connections on the bread board.Now the out put of the ff1 held at high using preset at low position.5 6 7 8 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 PROCEDURE: 1. Patch cards. Bread board IC trainer 2.Apply the clock pulse and observe the out puts. a canonical form specifies a unique representation for every object. PRECAUTIONS: 1. The distinction between "canonical" and "normal" forms varies by subfield. In most fields. THEORY: In mathematics and computer science. 2. And now the position of preset of ff1 is held at high position. draw the circuit diagram and verify De-Morgan laws. 3. Connect the circuit as shown in the figure. or standard form of a mathematical object is a standard way of presenting that object as a mathematical expression.Short t preset of flip-flop from ff2 to ff8and held it in high position . normal. APPARATUS: 1. 7432 3. The canonical form of a positive . 6. Vcc should not exceed +5v.Apply vcc to pin -14 and gnd to pin-7 for all IC’s. 5. a canonical.apply clock pulses to pin 3&11 for all IC’s simultaneously. while a normal form simply specifies its form. 7408. 7.Draw the circuit diagram and verify the Commutative law Design a circuit for the given conical form. Short t clear i/p’s and held it in low position to clear the o/p’s. RESULT: 1. 4. IC 7404.

In this context. there are usually many different ways to represent the same object. for a class of objects on which an equivalence relation is defined. This allows testing for equality by putting the difference of two objects in normal form. and the row echelon form is a canonical form. and more specifically in computer algebra. a canonical form is a representation such that every object has a unique representation. Jordan normal form is a canonical form for matrix similarity. Putting something into canonical form is canonicalization. normal form is a weaker notion: A normal form is a representation such that zero is uniquely represented. when one consider as equivalent a matrix and its left product by an invertible matrix. often data be that has canonicalized more into than a one completely possible unique representation called its canonical form. Thus. Therefore. CIRCUIT DIAGRAMS: . For example. a canonical form consists in the choice of a specific object in each class. when representing mathematical objects in a computer. However canonical forms frequently depend on arbitrary choices (like ordering the variables).Canonical form can also mean a differential form that is defined in a natural (canonical) way.integer in decimal representation is a finite sequence of digits that does not begin with zero. in computer algebra.In computer representation can science. and this introduces difficulties for testing the equality of two objects resulting on independent computations. More generally. the equality of two objects can easily be tested by testing the equality of their canonical forms. In computer science.

RESULT: 2. Don’t switch ON the kit till all connections are made. Construct Half Adder and using NAND gates and verify the truth table AIM: . 2.t 2.r. 3. Avoid loose connections on bread board. truth tables as shown in the truth PRECAUTIONS: 1 1 1. Take care while make connections with VCC and GND. A´ B A 0 0 0 1 1 0 ´B A+ .1 Connect the 1 diagram 3. +5V DC is 1 0 each IC w. circuit as shown in circuit applied to toggle switches and connected to output LEDs. B´ applied at VCC (pin no 14) of ground (pin no7). Inputs are outputs are 4.TRUTH TABLES: A´ A 0 B ´ AB + B´ 0 PROCEDURE: 0 1 1. Verify the tables.

A Boolean equations for these outputs are Sum(S)= A B Carry(C) =AB The sum output is A XOR B the carry output is A AND B. therefore sum is 1 when A and B are different carry is 1 when A and B are 1’s. IC trainer kit. A Boolean equations for these outputs are Sum(S)= A B C Carry(C)=AB+BC+AC The sum output is A XOR B the carry output is A AND B. LOGIC SYMBOL: CIRCUIT DIAGRAM: HALF ADDER TRUTH TABLE: 0 SU M 0 CARR Y 0 0 1 1 0 1 0 1 0 1 1 0 1 A B 0 . a sum bit and a carry bit. a sum bit and a carry bit. 7408. Full adder is a logic circuit that adds two bits. 7432.Connecting wires/ patch chords THEORY: Half adder is a logic circuit that adds two bits. EQUIPMENT REQUIRED: 1.To construct half-adder and full adder using two half adders and verify its truth table. The half adder accepts two binary digits on its inputs and produces two binary digits on its outputs. therefore sum is 1 when A and B are different carry is 1 when A and B are 1’s. 2. The half adder accepts two binary digits on its inputs and produces two binary digits on its outputs. 3. ICS 7486.

Take care while make connections with VCC and GND. +5V DC is applied at VCC (pin no 14) of each IC w.t ground (pin no7).ENCODER . Connect the circuit as shown in circuit diagram 3. 4. Don’t switch ON the kit till all connections are made. 2. 3.r. 3. Inputs are applied to toggle switches and outputs are connected to output LEDs. 2. Avoid loose connections on bread board. RESULT: The construction of half adder and full adder using half adder and the verification of truth table is done. PRECATIONS: 1.Half Adder using NAND Gates: A B SU M CARR Y PROCEDURE: 1. Verify the truth tables of half adder as shown in the truth tables.

2. 1. 2 3 1 1 27 THEORY: ENCODER: An encoder is a digital circuit that performs inverse operation of a decoder. n An encoder has 2 input lines and n output lines.AIM: To design and implement encoder and decoder using logic gates and study of IC 7445 and IC 74147. It has an ambiguila that when all inputs are zero the outputs are zero.No. The zero outputs can also be generated when D0 = 1. 2. In encoder it is assumed that only one input has a value of one at any given time otherwise the circuit is meaningless. APPARATUS REQUIRED: Sl. COMPONENT 3 I/P NAND GATE OR GATE NOT GATE IC TRAINER KIT PATCH CORDS SPECIFICATION IC 7410 IC 7432 IC 7404 - QTY. In octal to binary encoder it has eight inputs. LOGIC DIAGRAM FOR ENCODER Y1 1 0 0 0 0 0 0 Y2 0 1 0 0 0 0 0 PROCEDURE: Y3 0 0 1 0 0 0 0 INPUT Y4 Y5 0 0 0 0 0 0 1 0 0 1 0 0 0 0 Y6 0 0 0 0 0 1 0 Y7 0 0 0 0 0 0 1 A 0 0 0 1 1 1 1 OUTPU T B 0 1 1 0 0 1 1 C 1 0 1 0 1 0 1 . In encoder the output lines generates the binary code corresponding to the input value. 3. 3. one for each octal digit and three output that generate the corresponding binary code.

. (ii) Logical inputs are given as per circuit diagram.(i) Connections are given as per circuit diagram. (iii) Observe the output and verify the truth table. RESULT: Thus the design and implementation of encoder and decoder using logic gates and study of IC 7445 and IC 74147 were done.

Don’t switch ON the kit till all connections are made. 4. PRECATIONS: 1. Bread board IC trainer 2. +5V DC is applied at VCC (pin no 14) of each IC w.Design a logic diagram for Y=(B+C)A using AND gates. Inputs are applied to toggle switches and outputs are connected to output LEDs. 2. Take care while make connections with VCC and GND. Connect the circuit as shown in circuit diagram 3. Patch cards. AIM: To develop the Logic Diagram for Expression. Verify the truth tables as shown in the truth tables. IC 74LS32 (OR) 4. . IC 74LS08 (AND) 3. 2. APPARATUS: 1. Avoid loose connections on bread board.r. 3.4.t ground (pin no7). CIRCUIT DIAGRAMS: B A (B +C )A C TRUTH TABLE: A B C 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Y=A(B +C) 0 0 0 0 0 1 1 1 PROCEDURE: 1.

3. This means that this flip flop is concern with time. ICs 7400. Rs flip flop is also called synchronous flip flop. AIM: Verify the truth tables of the basic flip flops with synchronous and asynchronous modes. Digital circuits can have a concept of time using a clock signal. EQUIPMENT REQUIRED: 2. Digital circuits can have a concept of time using a clock signal. Connecting wires/ patch chords.7402 4. The main difference between latches and flip-flops is in the method used for changing their state. Synchronous flip flop means that this flip flop is concerned with time.Design a Logic diagram for J-k flip flop using AND and NAND Gates. The clock signal simply goes from low to high and high to low in a short period of time. CIRCUIT DIAGRAM: J K QN CLK QN TRUTH TABLE: J K CLK QN QN RESPONSE . which can reside in either of two stable states by virtue of feedback arrangement. THEORY: Latch is a type of bi-stable circuit. The clock signal simply goes from low-to-high and high-to-low in a short period time.RESULT: 5. IC trainer kit. similar to a flip-flop.

Connect the circuit as shown in circuit diagram 3. 2. PRECATIONS: 1.t ground (pin no7). +5V DC is applied at VCC (pin no 14)of each IC w. Verify the truth tables of NAND and NOR Latches as shown in the truth tables. 4.Avoid loose connections on bread board. Take care while make connections with VCC and GND.r. RESULT: . Inputs are applied to toggle switches and outputs are connected to output LEDs. 3. Don’t switch ON the kit till all connections are made. 2.0 0 0 1 1 0 0 1 0 1 0 1 1 1 1 0 0 0 1 1 0 1 1 0 0 PRIVIOUS STATE PRIVIOUS STATE QN ~QN TOGGLE PROCEDURE: 1.

Each input code word produces a different output code word i. 1. 2n output values are from 0 through output 2n-1. 2. 2 3 1 1 27 THEORY: DECODER: A decoder is a multiple input multiple output logic circuit which converts coded input into coded output where input and output codes are different.6.DECODER AIM: To design and implement encoder and decoder using logic gates and study of IC 7445 and IC 74147 APPARATUS REQUIRED: Sl. The input code generally has fewer bits than the output code. COMPONENT 3 I/P NAND GATE OR GATE NOT GATE IC TRAINER KIT PATCH CORDS SPECIFICATION IC 7410 IC 7432 IC 7404 - QTY. In the block diagram of decoder circuit the encoded information is present as n input producing 2n possible outputs. 3. 2.e there is one to one mapping can be expressed in truth table.No. 3. .

. (v) Logical inputs are given as per circuit diagram.TRUTH TABLE: PROCEDURE: (iv) Connections are given as per circuit diagram. RESULT: Thus the design and implementation of encoder and decoder using logic gates and study of IC 7445 and IC 74147 were done. (vi) Observe the output and verify the truth table.

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of Electronics and Communication Engineering .P a g e | 49 Dept.

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