The University of Texas at Dallas

Erik Jonsson School of Engineering and
Computer Science

Sequential Logic and Clocked Circuits
Clock or
Timing
Device
Input
Variables

State or
Memory
Element

Combinational
Logic
Elements
Output

• From combinational logic, we move on to sequential logic.
• Sequential logic differs from combinational logic in several ways:
– Its outputs depend not only on logic inputs but also the internal state of
the logic.
– Sequential logic output does not necessarily change when an input
changes, but is synchronized to some “triggering event.”
– Sequential logic is often synchronized or triggered by a series of regular
pulses on a serial input line, which is referred to as a “clock.” That is, the
outputs normally change as a function of the timing element.
– Sequential logic may (usually will) have combinational parts.
1

Lecture #7: Flip-Flops, The Foundation of Sequential Logic

© N. B. Dodge 9/15

The University of Texas at Dallas

Erik Jonsson School of Engineering and
Computer Science

The Simple R-S Flip-Flop
• The simplest example of a sequential logic
device is the R-S flip-flop (R-S FF).
• This is a non-clocked device that consisting
Q
of two cross-connected 2-input NAND gates S ‒
(may also be made from other gates).
• Inputs are “negative-true” input logic
(inputs are active at logic state 0).
Q
R‒
=
Q 1;=
Q 0 , the R-S FF is “set.”
• When
R-S Flip-Flop
• Likewise, when
=
Q 0;=
Q 1 , the flip-flop is
“reset.”
• Q and Q will always have opposite states.
• The R-S FF is bistable. That is, it is “at rest”
in either of its two states (“set” or “reset”)
until an input forces it to change.
2

Lecture #7: Flip-Flops, The Foundation of Sequential Logic

© N. B. Dodge 9/15

The University of Texas at Dallas

Erik Jonsson School of Engineering and
Computer Science

The Simple R-S Flip-Flop (2)
• If the R-S FF is in the “set” state, it will
not go “reset” until the Reset line goes
“true” (in this case, to 0). Likewise, when
“reset”, it will not go “set” unless the Set
line goes to 0.
• Note also that once “set,” if Set goes to 0
more than once, the FF simply stays “set.”
• Likewise, when “reset,” more Reset’s do
not affect the circuit; it remains “reset.”
• Thus the R-S FF has an output that
depends not only on the inputs but the
current state.
3

S‒

Q

Q
R‒
R-S Flip-Flop

Note: The triggering signal of an
input (Set or Reset) is always
assumed to be momentary. That
is, a “Set” or “Reset” signal is
considered to last a VERY short
time (in the case of real circuits,
this is nanoseconds or less).
Lecture #7: Flip-Flops, The Foundation of Sequential Logic

© N. B. Dodge 9/15

Then both inputs to bottom NAND are 1. 4. Thus Set = 1.= Q 1. Dodge 9/15 . Set goes active (Set → 0).The University of Texas at Dallas Erik Jonsson School of Engineering and Computer Science R-S Flip-Flop Set Cycle • • • Assume the ff is reset (Q = 0). Thus. Also. Reset = 1. since the Set and Reset inputs are not active. then the value of Q remains 0. 2. except that the change is initiated by reset going low. Lecture #7: Flip-Flops. The other input to the upper NAND is now 0. Then the cycle is: 1. The reverse cycle (set-to-reset) occurs in the identical way. since the other input is still 0. both input are at 1. and Q → 0. 6. Then Q must → 1 (output of a NAND = 1 if any input = 0). Q remains at 1. Likewise. since both inputs to the lower NAND are now 1. B. The Foundation of Sequential Logic © N. 3. 4 S‒ Q Q R‒ R-S Flip-Flop 5. when the Set signal goes back high. = Q 0.

The University of Texas at Dallas Erik Jonsson School of Engineering and Computer Science RS FF “Set” Cycle Pictorially =0 5 =1 Lecture #7: Flip-Flops. The Foundation of Sequential Logic © N. B. Dodge 9/15 .

The University of Texas at Dallas Erik Jonsson School of Engineering and Computer Science The Simple Latch or R-S Flip-Flop (4) S‒ Q Q R‒ R-S Flip-Flop • The truth table for the R-S FF is relatively simple. Dodge 9/15 . The Foundation of Sequential Logic © N. as shown below: Inputs Current Outputs New Outputs S R Q Q Q Q 1 1 1 or 0 0 or 1 Same Same 0 1 0 1 1 0 0 1 1 0 Same Same 1 0 1 0 0 1 1 0 0 1 Same Same 0* 0* 1 or 0 0 or 1 1* 1* * This is a race condition and not stable. The S-R input “0-0” is “forbidden.” 6 Lecture #7: Flip-Flops. B.

since the output state is not stable. • Note the race condition that is triggered by R=S=0: – Then Q= Q= 1 . so both other 2-NAND inputs are 1.The University of Texas at Dallas Erik Jonsson School of Engineering and Computer Science “Forbidden” RS FF Inputs S‒ Q R‒ Q • As noted on the truth table. Dodge 9/15 . then all 4 inputs of the two 2-input NAND gates are 1 and both outputs go to 0(!) – The result is a “race” to see which output gets to 0 first. The Foundation of Sequential Logic © N. 0-input to both R and S is forbidden. getting one 2NAND input to 0. 7 Lecture #7: Flip-Flops. The result of the “race” cannot be predicted. and therefore forcing that NAND output to 1. Thus R and S = 0 together is forbidden. – If S and R go to 1 simultaneously. B.

the output stays in that state until the opposite input is triggered. • Groups of flip-flops that store large binary numbers are called registers. • Thus the RS flip-flop or latch has the property of “remembering” a one-bit binary number: It can be set to 1 or 0. Lecture #7: Flip-Flops. 8 S‒ Q R‒ Q Q can be set to 1 or 0. • Thus. we can use flip-flops to store binary numbers in a computer. • If an RS FF has its Q output changed to 1 or 0.The University of Texas at Dallas Erik Jonsson School of Engineering and Computer Science Flip-Flops and “Memory” • Many circuits in the modern computer are either based on or related to the R-S FF. The Foundation of Sequential Logic © N. Thus the output Q can be said to “remember” one bit. B. Dodge 9/15 .

B. although the gates and inputs are not the same. The Foundation of Sequential Logic © N. Q and Q are labeled. Complete the truth table and label R and S (including their polarity). The circuit below is also an RS flipflop.Erik Jonsson School of Engineering and Computer Science The University of Texas at Dallas Exercise 1 • • • This exercise can improve your understanding of RS flip-flops. Dodge 9/15 . 1 2 9 Q Inputs Current Outputs New Outputs Q 1 2 Q Q 0 0 1 or 0 0 or 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 0 1 1 1 1 or 0 1 or 0 Q Q Lecture #7: Flip-Flops.

• We refer to a circuit as a “clocked circuit” when sequential elements in the circuit change states in synchronization to a train of pulses. 10 Lecture #7: Flip-Flops. • The clock pulses change regularly from 0 to 1 and back. (“square wave”). The Foundation of Sequential Logic © N. B. the circuit can only change states on a “tick” of the clock element. • Clocked circuits are circuits that are regulated by a clocking element.The University of Texas at Dallas Erik Jonsson School of Engineering and Computer Science Clocked Circuits (1) Logic 1 Time Logic 0 Stream of Clock Pulses (“Square Wave” or “Pulse Train”) • The majority of all sequential logic circuits are clocked logic circuits. • Such a “pulse train” is shown below. • In a clocked sequential circuit. in general. Dodge 9/15 . which determines when state changes occur.

g. it spends equal time each period in the 1 and 0 states. Dodge 9/15 .The University of Texas at Dallas Erik Jonsson School of Engineering and Computer Science Clocked Circuits (2) • The period T of a sequential logic clock is the distance between identical points on the pulse train. – The clock alternates between the states.. • The clock below has a 50/50 duty cycle. e. The Foundation of Sequential Logic © N. B. 1 T 11 0 T Lecture #7: Flip-Flops. two rising edges or two falling edges. • The amount of time that the clock spends in each of the two states is called the duty cycle. – The clock has only two states: 0 and 1.

In the same way. Thus we say that the clock has a “35/65” duty cycle. It stays in the “1” state about 35% of the time.e. a clock can have a 70/30 cycle time (i. and so forth.. and in the “0” state about 65% of the time. B. it stays in the “1” state 70% of the time). 1 0 T 12 T Lecture #7: Flip-Flops. The Foundation of Sequential Logic © N. Dodge 9/15 .The University of Texas at Dallas Erik Jonsson School of Engineering and Computer Science Clocked Circuits (3) • • • The clock below does not have a 50/50 duty cycle. Note that the period T is defined in the same way as before.

• Thus clocked ff’s do not change states. • The most useful ff’s are not simple asynchronous (non-clocked) ff’s. – “Set” is when Q=1. – Triggered by “set” and “reset” inputs. Dodge 9/15 .The University of Texas at Dallas Erik Jonsson School of Engineering and Computer Science Clocked Flip-Flops • All ff’s have the same basic configuration: – Both true and false outputs (“Q” and “Q-not”). regardless of the set or reset inputs. B.” 13 Lecture #7: Flip-Flops. however. until the “clock ticks. there must also be the presence of a clock signal in its true state (normally 1). • Clocked ff’s are very similar to non-clocked ff’s -.the main difference is that in addition to a “set” or “reset” input to cause the outputs to change. The Foundation of Sequential Logic © N. but synchronous (“clocked”) ff’s.

shown above (NAND version). The Foundation of Sequential Logic © N.Erik Jonsson School of Engineering and Computer Science The University of Texas at Dallas The Clocked R-S Flip-Flop Set+ S‒ Q R‒ Q Clock+ Reset+ Clocked R-S Flip-Flop • • • • • 14 The simplest clocked ff is the clocked R-S FF. neither set or reset input affect the circuit. Having set and reset 1 at the same time is forbidden as for the RS FF. we say that the clock “gates” the set or reset signal to the RS FF. the clock input is present. simultaneous set and reset true causes a race condition when clock is high. Lecture #7: Flip-Flops. B. Dodge 9/15 . In addition to the set and reset inputs. In this case. the set or reset input must be high (1) to set or reset the ff when the clock goes true (0 1). Since when clock is low (0).

B. The Foundation of Sequential Logic © N.Erik Jonsson School of Engineering and Computer Science The University of Texas at Dallas Clocked R-S Flip-Flop Truth Table Set+ S‒ Q R‒ Q Clock+ Reset+ Clocked R-S Flip-Flop Clock 0 1 1 1 1 1 1 Inputs S X 0 1 1 0 0 1* Current Outputs R X 0 0 0 1 1 1* Q 1 or 0 1 or 0 0 1 1 0 1 or 0 Q 0 or 1 0 or 1 1 0 0 1 0 or 1 New Outputs Q Same Same 1 Same 0 Same 1* Q Same Same 0 Same 1 Same 1* * This is a race condition and not stable. Dodge 9/15 . as for the non-clocked RS FF. 15 Lecture #7: Flip-Flops.

then the ff goes into the “reset” state when clock goes high (“set” input=0. “reset”=0). B. When clock = 0. Lecture #7: Flip-Flops.” Clock+ Since the D FF is limited to one R‒ Q input. “reset”=1). When the D input = 0. when the clock is high. There is no “forbidden” state here -.The University of Texas at Dallas Erik Jonsson School of Engineering and Computer Science The D Flip-Flop • • • • • • 16 (S+) The D FF is a bistable circuit with D S‒ Q only one input plus the clock. next page) for ALL inputs. The term “D” refers to “data. we can see that if the D input = 1. there is no chance that a D (R+) Clocked D Flip-Flop race condition will occur. The Foundation of Sequential Logic © N. the ff will go into the “set” state (“set” input=1. The clocked D FF can be created simply by replacing the “reset” input with an inverted “set” input in the clocked RS FF. the ff is idle. Dodge 9/15 .the D FF output is defined (see truth table. In this configuration.

B.Erik Jonsson School of Engineering and Computer Science The University of Texas at Dallas D Flip-Flop Truth Table D (S+) S‒ Q R‒ Q Clock+ D Inputs 17 (R+) Clocked D Flip-Flop Current Outputs New Outputs Clock D Q Q Q Q 0 X 1 or 0 1 or 0 Same Same 1 1 0 1 1 0 1 1 1 0 Same Same 1 0 1 0 0 1 1 0 0 1 Same Same Lecture #7: Flip-Flops. The Foundation of Sequential Logic © N. Dodge 9/15 .

Dodge 9/15 . Time 2. Using the gates shown on the next page.The University of Texas at Dallas Erik Jonsson School of Engineering and Computer Science Exercise 2 1. 18 Lecture #7: Flip-Flops. make a clocked D FF. The Foundation of Sequential Logic © N. to the nearest nsec? What is the duty cycle (nearest %)? 5 nsec Time 3. B. What is the period of the clock shown. Draw a representation of a 7030 duty cycle clock (pulse train). Label inputs and outputs.

Erik Jonsson School of Engineering and Computer Science The University of Texas at Dallas Exercise 2 (continued) Clocked D FF -.Answer D Q Clock+ Q 19 Lecture #7: Flip-Flops. B. Dodge 9/15 . The Foundation of Sequential Logic © N.

and show the input polarities. Q-not.The University of Texas at Dallas Erik Jonsson School of Engineering and Computer Science New Information Quiz • You can also make an RS FF as shown above. Reset. The Foundation of Sequential Logic © N. The input signal labels are different. B. Q. 20 Lecture #7: Flip-Flops. Dodge 9/15 . and the polarities may not be the same (or they might be the same!). • Label the signals Set.

The Foundation of Sequential Logic © N. • In any fundamental timing diagram. unless specifically instructed to do otherwise. 21 Lecture #7: Flip-Flops. • Always assume a “50/50” clock. Dodge 9/15 .of the elements of interest. B. if duty cycle not specified. • This is normally done by plotting the “transitions” -.Erik Jonsson School of Engineering and Computer Science The University of Texas at Dallas Timing Diagrams 1 Clock 0 Time • It is important when designing sequential circuits to understand the timing relationships between circuit elements.the changes between logic “1” and logic “0” -. always start with the clock (it goes best at the diagram bottom). • All event timing is normally related to the clock.

The University of Texas at Dallas Erik Jonsson School of Engineering and Computer Science Timing Diagrams (Continued) Q Output D Input 1 Clock 0 • To illustrate D FF timing by plotting the D FF “Q” output: – Remember that a D FF output is normally triggered when clock = 1. the D FF “Q” changes as D changes. Dodge 9/15 . when the D input is 1. • Principle: Output “Q” of a simple D FF tracks D when the clock ticks! Note: The clock is shown above running continuously. – Assume D FF is originally “reset. In some cases.” Then on the rising edge of the clock. • On successive clock pulses. the clock may “tick” only some times. the D FF output goes to “set” (1). The Foundation of Sequential Logic 22 © N. Lecture #7: Flip-Flops. B.

Q D 1 Clock 0 Time 23 Lecture #7: Flip-Flops. Note that you do not need to see the ff diagram itself to do the plot. The Foundation of Sequential Logic © N. plot the timing of the Q output of the D FF (assume the D FF starts out in the reset condition).The University of Texas at Dallas Erik Jonsson School of Engineering and Computer Science Exercise 3 • The incomplete timing diagram below shows the clock input as the basis for the diagram and a D FF input. Dodge 9/15 . the clock does not run continuously. In this case. but on a sporadic basis. but not the output. B. Based on the discussion so far.

” or Delay Flip-Flops • It is often desirable to have a flip-flop whose output does not change immediately when its internal state is altered from “set” (Q = 1) to “reset” (Q = 0). or vice-versa. or “backside” of a clock pulse. • In this way. • This sort of ff is called a “master-slave” or “delay” ff. The Foundation of Sequential Logic © N. the internal state of the ff changes one-half clock cycle prior to the time in which the changed state appears on the circuit outputs. controlling) ff change states on one edge of a clock pulse (normally the leading edge) and have a second ff connected to the first change to the same state as the “master” on the trailing edge. 24 Lecture #7: Flip-Flops.e. B. • The idea behind the master-slave ff is to have a “master” (i.. Dodge 9/15 .The University of Texas at Dallas Erik Jonsson School of Engineering and Computer Science “Master-Slave.

The Foundation of Sequential Logic © N. 25 Lecture #7: Flip-Flops. B. • The slave circuit changes state 1/2 cycle after the master. Dodge 9/15 . no indeterminate state.The University of Texas at Dallas Erik Jonsson School of Engineering and Computer Science The Master-Slave D Flip-Flop D Q Clock+ Q Master Slave • D FF converted to master-slave type. • The device still operates as a D FF. • The slave (basically a clocked RS FF) always mirrors the state of the master.

The University of Texas at Dallas Erik Jonsson School of Engineering and Computer Science Timing of Master-Slave D Flip-Flop D Q Clock+ Q Master Slave Slave FF (Q) Master FF (Q) D 1 Clock 26 0 Lecture #7: Flip-Flops. Dodge 9/15 . B. The Foundation of Sequential Logic © N.

B. • One symbol for a D FF is shown to the right. • Circles on S and R inputs mean that set and reset are “negative-true” signals (active at level 0). Therefore. D Q C Simple D FF D S Q CR Q – “Q-not” output is also available. output may be indeterminate. • D FF’s with asynchronous set and reset are also available. “1” is the active state (when clock and D = 1.The University of Texas at Dallas Erik Jonsson School of Engineering and Computer Science D Flip-Flop Symbols • Flip-flop detail is not usually shown in diagrams. • Set and reset have the same problems discussed before: If S = R = 0. output will → 1). • There is no small circle on either input. The Foundation of Sequential Logic D FF With Asynchronous S/R © N. Dodge 9/15 . 27 Lecture #7: Flip-Flops.

the J-K inputs are not restricted.The University of Texas at Dallas Erik Jonsson School of Engineering and Computer Science The J-K Master-Slave Flip-Flop • It is often useful to have a FF that will not have indeterminate outputs when S and R inputs are both 1 simultaneously. The Foundation of Sequential Logic © N. The J input corresponds to “Set. B. However. 28 Lecture #7: Flip-Flops.” while K corresponds to “Reset. • The J-K FF. fits those requirements.” • The J-K FF is designed so that the condition of J = K = 1 does not result in an indeterminate output when clocked. • There may still be asynchronous RS inputs with the usual cautions. Dodge 9/15 . shown above.

and the ff will be set. The Foundation of Sequential Logic © N. If Q = 1 (“Set”) and J = K = 1.The University of Texas at Dallas Erik Jonsson School of Engineering and Computer Science Internals of the J-K Flip-Flop J OR Q K Q Clock+ J-K Master-Slave Flip Flop • • • • • • 29 A master-slave J-K FF can be designed as shown above. so the ff will reset. Likewise.) Then for J = K = 1. output of the OR = 0. when the clock ticks Q → the opposite state. Dodge 9/15 . if Q = 0 (“Reset”) and J = K = 1. B. for either output state (set or reset). Lecture #7: Flip-Flops. OR = 1. The key states are J=K=1. (For J=1 and K=0. or J=0 and K=1) normal set or reset occurs.

The Foundation of Sequential Logic © N. Dodge 9/15 . B.Erik Jonsson School of Engineering and Computer Science The University of Texas at Dallas JK Flip Flop Truth Table 1 J K 3 Q 4 Q 2 Clock+ Inputs 30 Outputs AND Outputs OR Outputs New Outputs J K Q Q 1 2 3 4 Q Q 0 0 0 1 0 0 0 1 Same Same 0 0 1 0 0 1 1 0 Same Same 0 1 0 1 0 0 0 1 Same Same 0 1 1 0 0 0 0 1 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Same Same 1 1 0 1 1 0 1 0 1 0 1 1 1 0 0 0 0 1 0 1 Lecture #7: Flip-Flops.

enables the T FF to work properly.” along with the connected J and K inputs. and clock = 1. Note Q tied to the K input and Q-not tied to the J input. the ff does not change state on the clock “tick. Dodge 9/15 .The University of Texas at Dallas Erik Jonsson School of Engineering and Computer Science The Toggle Flip-Flop T J Q K Q Clock+ T Master-Slave Flip-Flop • • • • • • 31 The T FF is like a JK FF with J and K tied together (K input inverted). If T = 0. Lecture #7: Flip-Flops.” The T FF is a master-slave ff. This “feedback. output changes on the back edge of the clock. The Foundation of Sequential Logic © N. Then if T = 1. Set T = 1 permanently. the ff “toggles” to the opposite state. and the T FF toggles on every clock pulse. B.

B. The Foundation of Sequential Logic © N.Erik Jonsson School of Engineering and Computer Science The University of Texas at Dallas Toggle Flip Flop Truth Table T J 1 K 2 3 Q 4 Q Clock+ T Master-Slave Flip-Flop Input T 32 Outputs AND Outputs OR Outputs New Outputs Q Q 1 2 3 4 Q Q 0 0 1 0 0 0 1 Same Same 0 1 0 0 1 1 0 Same Same 1 0 1 1 0 1 0 1 0 1 1 0 0 0 0 1 0 1 Lecture #7: Flip-Flops. Dodge 9/15 .

The University of Texas at Dallas Erik Jonsson School of Engineering and Computer Science Master-Slave T FF as a Frequency Divider 1 f/8 Clock (at frequency f) Reset f/2 f/4 All T FF’s shown are masterslave. Dodge 9/15 . The Foundation of Sequential Logic © N. T FF #3 T FF #2 T FF #1 1 Clock 33 0 Lecture #7: Flip-Flops. B.

Erik Jonsson School of Engineering and Computer Science The University of Texas at Dallas Timing (Continued) f/8 1 f/2 f/4 Pulse Out Clock Reset Clock frequency = f • Suppose that we want to decode a state of the frequency divider circuit seen on the last slide. The Foundation of Sequential Logic © N. Dodge 9/15 . • How do we show the timing on this sequential decoder? 34 Lecture #7: Flip-Flops. • When the “/8” and “/4” and “/2” outputs are high. we want to AND those signals with clock to get a decoded pulse to perform some operation (see diagram above). B.

and #2 clocks #3. FF #2 toggles. The Foundation of Sequential Logic © N. Dodge 9/15 . Lecture #7: Flip-Flops. B. On the first falling edge of the clock. etc.Erik Jonsson School of Engineering and Computer Science The University of Texas at Dallas Timing (Continued) f/8 1 1 Clock (f) f/2 2 f/4 Pulse Out 3 Reset T FF #3 T FF #2 T FF #1 Clock • • 35 1 0 We know that the output of FF #1 clocks FF#2. FF #1 toggles. On the falling edge of the “Q” output of FF #1.

B. The Foundation of Sequential Logic © N.Erik Jonsson School of Engineering and Computer Science The University of Texas at Dallas Timing (Concluded) f/8 1 Clock (f) 1 f/2 2 f/4 3 Pulse Out Reset Pulse T FF #3 T FF #2 T FF #1 1 0 Clock • • 36 On the timing diagram. Dodge 9/15 . Lecture #7: Flip-Flops. We then diagram “Pulse Out” based on the AND of the 3 signals plus clock. we look for the time when the three Q’s are high.

Dodge 9/15 . fast memory. – J-K FF: Control functions and status indicators. 37 Lecture #7: Flip-Flops. – T FF: Frequency division and counter circuits. • We will study more complex ff circuits next. The Foundation of Sequential Logic © N. B. because it is important in modern computer circuitry. • The primary uses for latches are: – D FF: ALU registers.The University of Texas at Dallas Erik Jonsson School of Engineering and Computer Science Flip – Flop Summary • We have devoted a good deal of time to the study of the latch. or flip-flop. shift registers. input/output buffers.